PCF85133U/2DA/1,02 [NXP]
PCF85133 - Universal LCD driver for low multiplex rates DIE 110-Pin;
| 型号： | PCF85133U/2DA/1,02 |
| 厂家： | 
NXP |
| 描述： | PCF85133 - Universal LCD driver for low multiplex rates DIE 110-Pin PC CD |
| 文件： | 总46页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCF85133
Universal LCD driver for low multiplex rates
Rev. 2 — 4 July 2011
Product data sheet
1. General description
The PCF85133 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 80 segments and can easily
be cascaded for larger LCD applications. The PCF85133 is compatible with most
microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication
overheads are minimized by a display RAM with auto-incremental addressing, by
hardware subaddressing and by display memory switching (static and duplex drive
modes).
2. Features and benefits
Single-chip LCD controller and driver
Selectable backplane drive configuration: static or 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Selectable frame frequency: 82 Hz or 110 Hz
Internal LCD bias generation with voltage-follower buffers
80 segment drives:
Up to 40 7-segment numeric characters
Up to 20 14-segment alphanumeric characters
Any graphics of up to 320 elements
80 4 bit RAM for display data storage
Auto-incremental display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
From 2.5 V for low-threshold LCDs
Up to 8.0 V for guest-host LCDs and high-threshold twisted nematic LCDs
Low power consumption
400 kHz I2C-bus interface
May be cascaded for large LCD applications (up to 5120 elements possible)
May be cascaded with PCF8532 to gain more flexibility in the number of addressable
segments
No external components required
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17.
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
Compatible with Chip-On-Glass (COG) technology
Manufactured using silicon gate CMOS process
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Delivery form[1]
Version
PCF85133U/2DA/1
PCF85133 bare die; 110 bumps; 4.16 1.07 0.38 mm
chip with bumps in tray
PCF85133
[1] Bump hardness see Table 24.
4. Marking
Table 2.
Marking codes
Type number
Marking code
PC85133-1
PCF85133U/2DA/1
5. Block diagram
BP0 BP1 BP2 BP3
S0 to S79
80
V
LCD
BACKPLANE
OUTPUTS
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
LCD
VOLTAGE
SELECTOR
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROL
LCD BIAS
GENERATOR
V
SS
DISPLAY
RAM
PCF85133
CLK
BLINKER
CLOCK SELECT
TIMEBASE
AND TIMING
SYNC
OSC
FF
COMMAND
DECODE
DATA POINTER AND
AUTO INCREMENT
WRITE DATA
CONTROL
POWER-ON
RESET
OSCILLATOR
SCL
SDA
2
INPUT
FILTERS
SUBADDRESS
COUNTER
I C-BUS
CONTROLLER
A0 A1 A2
SA0
SDAACK
V
DD
001aaj583
Fig 1. Block diagram of PCF85133
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
2 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
+y
+x
0
0
PCF85133
001aaj559
Viewed from active side. For mechanical details, see Figure 24.
Fig 2. Pin configuration for PCF85133
6.2 Pin description
Table 3.
Symbol
SDAACK
SDA
Pin description overview
Pin
Description
1 to 3
4 to 6
7 to 9
10
I2C-bus acknowledge output
I2C-bus serial data input
I2C-bus serial clock input
clock input/output
SCL
CLK
VDD
11 to 13
14
supply voltage
SYNC
OSC
cascade synchronization input/output
oscillator select
15
FF
16
frame frequency select
A0, A1 and A2
SA0
17 to 19
20
subaddress input
I2C-bus slave address input
ground supply voltage
LCD supply voltage
[1]
VSS
21 to 23
24 to 26
VLCD
BP2, BP0, BP3 and BP1
S0 to S79
27, 28, 109 and 110 LCD backplane output
29 to 108
-
LCD segment output
dummy pads
D1 to D9
[1] The substrate (rear side of the die) is at VSS potential and should be electrically isolated.
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
3 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
7. Functional description
The PCF85133 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It
can directly drive any static or multiplexed LCD containing up to four backplanes and up to
80 segments.
The display configurations possible with the PCF85133 depend on the required number of
active backplane outputs. A selection of display configurations is given in Table 4.
All of the display configurations given in Table 4 can be implemented in a typical system
as shown in Figure 4.
dot matrix
7-segment with dot
14-segment with dot and accent
013aaa312
Fig 3. Example of displays suitable for PCF85133
Table 4.
Selection of possible display configurations
Number of
Backplanes
Icons
Digits/Characters
7-segment[1]
Dot matrix/
Elements
14-segment[2]
4
3
2
1
320
240
160
80
40
30
20
10
20
15
10
5
320 (4 80)
240 (3 80)
160 (2 80)
80 (1 80)
[1] 7 segment display has 8 elements including the decimal point.
[2] 14 segment display has 16 elements including decimal point and accent dot.
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
4 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
V
DD
SDAACK
t
r
R
≤
2C
b
V
V
DD
LCD
SDA
SCL
OSC
FF
80 segment drives
4 backplanes
HOST
MICRO-
PROCESSOR/
MICRO-
LCD PANEL
PCF85133
(up to 320
elements)
CONTROLLER
A0 A1 A2 SA0
V
SS
001aaj582
V
SS
Fig 4. Typical system configuration
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCF85133. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are the power supplies (VDD
,
V
SS, and VLCD) and the LCD panel chosen for the application.
7.1 Power-on reset
At power-on the PCF85133 resets to the following starting conditions:
• All backplane and segment outputs are set to VLCD
• The selected drive mode is 1:4 multiplex with 1⁄3 bias
• Blinking is switched off
• Input and output bank selectors are reset
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared (set to logic 0)
• The display is disabled
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins VLCD and VSS. The center impedance is bypassed
by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is
selected.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
V
LCD and the resulting discrimination ratios (D) are given in Table 5.
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
5 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
Table 5.
Biasing characteristics
Number of:
LCD drive
mode
LCD bias
configuration
VoffRMS VonRMS
------------------------ ----------------------- D = ------------------------
VLCD VLCD VoffRMS
VonRMS
Backplanes Levels
static
1
2
2
3
4
2
3
4
4
4
static
0
1
1
⁄
1:2 multiplex
1:2 multiplex
1:3 multiplex
1:4 multiplex
0.354
0.333
0.333
0.333
0.791
0.745
0.638
0.577
2.236
2.236
1.915
1.732
2
1
⁄
3
1
⁄
3
1
⁄
3
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD > 3Vth(off)
.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------ , where the values for a are
1 + a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
a2 + 2a + n
n 1 + a2
VonRMS
=
-----------------------------
(1)
V
LCD
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
a2 – 2a + n
n 1 + a2
VoffRMS
=
-----------------------------
(2)
(3)
V
LCD
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
a2 + 2a + n
VonRMS
----------------------
D =
=
---------------------------
a2 – 2a + n
VoffRMS
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
6 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄2 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
21
1⁄2 bias is ---------- = 1.528 .
3
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): VLCD
• 1:4 multiplex (1⁄2 bias): VLCD
=
=
6 VoffRMS = 2.449VoffRMS
4 3
---------------------
= 2.309VoffRMS
3
These compare with VLCD = 3VoffRMS when 1⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 5. For a good contrast performance, the following rules should be followed:
V
V
onRMS Vthon
offRMS Vthoff
(4)
(5)
V
on(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
7 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
100 %
90 %
10 %
V
[V]
RMS
V
th(off)
V
th(on)
OFF
SEGMENT
GREY
SEGMENT
ON
SEGMENT
013aaa494
Fig 5. Electro-optical characteristic: relative transmission curve of the liquid
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
8 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 6.
T
fr
LCD segments
V
LCD
BP0
Sn
V
SS
state 1
(on)
state 2
(off)
V
LCD
V
SS
V
LCD
Sn+1
V
SS
(a) Waveforms at driver.
V
LCD
0 V
state 1
−V
LCD
V
LCD
state 2
0 V
−V
LCD
(b) Resultant waveforms
at LCD segment.
013aaa207
Vstate1(t) = VSn(t) VBP0(t).
on(RMS) = VLCD
V
.
Vstate2(t) = V(Sn + 1)(t) VBP0(t).
Voff(RMS) = 0 V.
Fig 6. Static drive mode waveforms
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
9 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF85133 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 7 and
Figure 8.
T
fr
V
LCD
LCD segments
V
V
/2
BP0
BP1
Sn
LCD
SS
state 1
V
LCD
state 2
V
V
/2
LCD
SS
V
LCD
V
V
SS
LCD
Sn+1
V
SS
(a) Waveforms at driver.
V
V
LCD
/2
LCD
0 V
−V
state 1
/2
LCD
−V
LCD
V
V
LCD
/2
LCD
0 V
state 2
−V /2
LCD
−V
LCD
(b) Resultant waveforms
at LCD segment.
013aaa208
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.791VLCD
Vstate2(t) = VSn(t) VBP1(t).
off(RMS) = 0.354VLCD
.
V
.
Fig 7. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
10 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
T
fr
V
LCD
LCD segments
2V
/3
LCD
BP0
BP1
Sn
V
V
/3
LCD
SS
state 1
V
LCD
state 2
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+1
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 1
/3
LCD
−2V
−V
/3
LCD
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 2
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
013aaa209
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.745VLCD
Vstate2(t) = VSn(t) VBP1(t).
off(RMS) = 0.333VLCD
.
V
.
Fig 8. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
11 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 9.
T
fr
V
LCD
LCD segments
2V
/3
LCD
BP0
BP1
BP2
Sn
V
V
/3
LCD
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+1
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+2
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
/3
LCD
V
/3
LCD
state 1
0 V
−V
/3
LCD
−2V
−V
/3
LCD
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
state 2
0 V
−V
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
013aaa210
Vstate1(t) = VSn(t) VBP0(t).
on(RMS) = 0.638VLCD
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD
V
.
.
Fig 9. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
12 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 10.
T
fr
V
LCD
LCD segments
2V
/3
LCD
BP0
BP1
BP2
V
V
/3
LCD
SS
state 1
state 2
V
LCD
2V
LCD
/3
V
V
/3
LCD
SS
V
LCD
2V
LCD
/3
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
BP3
Sn
V
V
/3
LCD
SS
V
LCD
2V
LCD
/3
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+1
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+2
Sn+3
V
V
/3
LCD
SS
V
LCD
2V
LCD
/3
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
LCD
/3
V
/3
LCD
state 1
0 V
-V
/3
LCD
-2V
/3
LCD
-V
LCD
V
LCD
2V
LCD
/3
V
/3
LCD
0 V
-V
state 2
/3
LCD
-2V
/3
LCD
-V
LCD
(b) Resultant waveforms
at LCD segment.
013aaa211
Vstate1(t) = VSn(t) VBP0(t).
on(RMS) = 0.577VLCD
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD
V
.
.
Fig 10. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
13 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF85133 are timed by a frequency fclk
which either is derived from the built-in oscillator frequency fosc
:
fosc
--------
fclk
=
(6)
(7)
64
or equals an external clock frequency fclk(ext)
:
fclk = fclkext
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output
from pin CLK provides the clock signal for cascaded PCF85133s in the system.
7.5.2 External clock
Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing and frame frequency
The clock frequency fclk determines the LCD frame frequency ffr and is calculated as
follows:
fclk
-------
ffr
=
(8)
24
The internal clock frequency fclk can be selected using pin FF. As a result 2 frame
frequencies are available: 82 Hz or 110 Hz (typical), see Table 6.
Table 6.
LCD frame frequencies
Pin FF tied to
Typical clock frequency (Hz)
LCD frame frequency (Hz)
VDD
VSS
1970
2640
82
110
The timing of the PCF85133 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between all the PCF85133s in the system.
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
14 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.8 Segment outputs
The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data residing in the display register. When less
than 80 segment outputs are required the unused segment outputs must be left
open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated in accordance with the selected LCD drive mode.
• In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required the unused outputs can be left
open-circuit.
• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1; therefore, these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode: BP0 and BP2, respectively, BP1 and BP3 carry the same
signals and can also be paired to increase the drive capabilities.
• In static drive mode: The same signal is carried by all four backplane outputs; and
they can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 80 4 bit RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map, Figure 11, shows rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment
outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second,
third and fourth row of the display RAM are time-multiplexed with BP0,
BP1, BP2, and BP3 respectively.
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
15 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
columns
display RAM addresses/segment outputs (S)
0
1
2
3
4
75 76 77 78 79
rows
0
1
2
3
display RAM rows/
backplane outputs
(BP)
013aaa214
The display RAM bitmap shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Fig 11. Display RAM bitmap
When display data is transmitted to the PCF85133, the received display bytes are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and depending on the current multiplex drive mode the bits are stored singularly,
in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment
display showing all drive modes is given in Figure 12; the RAM filling organization
depicted applies equally to other LCD types.
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
columns
display RAM address/segment outputs (s)
byte1
S
S
S
S
S
a
n+2
n+3
n+4
n+5
n+6
b
BP0
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
S
f
n+1
rows
static
display RAM
rows/backplane
outputs (BP)
MSB
LSB
g
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
S
S
n
x
x
x
e
n+7
c
b
a
f
g
e
d
DP
c
x
d
DP
x
columns
display RAM address/segment outputs (s)
byte1 byte2
BP0
a
S
S
n
1:2
b
n
n + 1 n + 2 n + 3
f
n+1
rows
MSB
LSB
DP
display RAM
rows/backplane
outputs (BP)
g
0
1
2
3
a
b
x
x
f
e
c
x
x
d
DP
x
multiplex
g
x
x
BP1
a
b
f
g
e c d
e
S
S
n+2
n+3
c
d
DP
x
columns
display RAM address/segment outputs (s)
BP0
BP1
byte1
byte2
byte3
S
S
n+1
n+2
a
1:3
b
n
n + 1 n + 2
S
f
n
rows
MSB
LSB
e
display RAM
rows/backplane
outputs (BP)
0
1
2
3
b
DP
c
a
d
g
x
f
g
multiplex
b
DP
c
a
d
g
f
e
x
x
BP2
e
c
d
DP
x
columns
display RAM address/segment outputs (s)
byte2 byte3 byte4
byte1
byte5
a
S
S
n
1:4
b
BP2
BP3
n
n + 1
BP0
BP1
f
rows
display RAM
rows/backplane
outputs (BP)
g
0
1
2
3
a
c
f
MSB
LSB
d
multiplex
e
g
d
e
c
b
a
c
b
DP
f
e
g
d
DP
DP
n+1
001aaj646
x = data bit unchanged
Fig 12. Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
The following applies to Figure 12:
• In static drive mode the eight transmitted data bits are placed into row 0 as one byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.10.3).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
7.10.1 Data pointer
The addressing mechanism for the display RAM is realized using a data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 12). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 12. After each byte is stored, the content of the data
pointer is automatically incremented by a value dependent on the selected LCD drive
mode:
• In static drive mode by eight
• In 1:2 multiplex drive mode by four
• In 1:3 multiplex drive mode by three
• In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early then the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten prior to further RAM accesses.
7.10.2 Subaddress counter
The storage of display data is determined by the content of the subaddress counter.
Storage is allowed only when the content of the subaddress counter match with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see Table 13). If the content of the subaddress counter
and the hardware subaddress do not match, then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF85133 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subaddress must not be changed whilst the device is being accessed on
the I2C-bus interface.
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7.10.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 7 (see Figure 12 as
well).
Table 7.
Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
outputs (BPn)
0
1
2
3
a7
a6
a5
-
a4
a3
a2
-
a1
a0
-
b7
b6
b5
-
b4
b3
b2
-
b1
b0
-
c7
c6
c5
-
c4
c3
c2
-
c1
c0
-
d7
d6
d5
-
:
:
:
:
-
-
-
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 8.
Table 8.
Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
outputs (BPn)
0
1
2
3
a7
a6
a5
-
a4
a3
a2
-
a1/b7 b4
a0/b6 b3
b1/c7 c4
b0/c6 c3
c1/d7 d4
c0/d6 d3
d1/e7 e4
d0/e6 e3
:
:
:
:
b5
-
b2
-
c5
-
c2
-
d5
-
d2
-
e5
-
e2
-
In the case described in Table 8 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written.
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
7.10.4 Writing over the RAM address boundary
In all multiplex drive modes, depending on the setting of the data pointer, it is possible to
fill the RAM over the RAM address boundary. If the PCF85133 is part of a cascade the
additional bits fall into the next device that also generates the acknowledge signal. If the
PCF85133 is a single device or the last device in a cascade the additional bits will be
discarded and no acknowledge signal will be generated.
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7.10.5 Output bank selector
The output bank selector (see Table 14) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
selected LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
The PCF85133 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. In the static drive mode, the bank-select command may request the contents of
row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode,
the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
7.10.6 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table 14). The input bank selector functions independently to the output bank selector.
7.11 Blinking
The display blink capabilities of the PCF85133 are very versatile. The whole display can
blink at frequencies selected by the blink-select command (see Table 15). The blink
frequencies are fractions of the clock frequency. The ratios between the clock and blink
frequencies depend on the blink mode selected (see Table 9).
Table 9.
Blink frequencies
Blink mode Operating mode ratio Blink frequency with respect to fclk (typical)
Unit
fclk = 1.970 kHz
blinking off
2.5
fclk = 2.640 kHz
blinking off
3.5
off
1
-
Hz
Hz
fclk
--------
768
2
3
1.3
0.6
1.7
0.9
Hz
Hz
fclk
-----------
1536
fclk
-----------
3072
An additional feature is for an arbitrary selection of LCD segments to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
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In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can blink by selectively changing the display RAM data at fixed time
intervals.
If the entire display can blink at a frequency other than the typical blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 11).
7.12 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The
commands available to the PCF85133 are defined in Table 10.
Table 10. Definition of commands
Command
Bit
Operation code
Reference
7
1
0
1
1
1
6
5
4
3
2
1
0
mode-set
1
0
0
E
B
M[1:0]
Table 11
Table 12
Table 13
Table 14
Table 15
load-data-pointer
device-select
bank-select
blink-select
P[6:0]
1
1
1
1
1
1
0
1
1
0
1
0
A[2:0]
0
I
O
AB
BF[1:0]
Table 11. Mode-set command bit description
Bit
7 to 4
3
Symbol Value
Description
-
1100
fixed value
E
display status[1]
disabled (blank)
enabled
0
1
2
B
LCD bias configuration[2]
0
1
1⁄3 bias
1⁄2 bias
1 to 0
M[1:0]
LCD drive mode selection
static; 1 backplane
01
10
11
00
1:2 multiplex; 2 backplanes
1:3 multiplex; 3 backplanes
1:4 multiplex; 4 backplanes
[1] The possibility to disable the display allows implementation of blinking under external control.
[2] Not applicable for static drive mode.
Table 12. Load-data-pointer command bit description
See Section 7.10.1.
Bit
7
Symbol Value
Description
-
0
fixed value
6 to 0
P[6:0]
0000000 to data pointer
1001111
7-bit binary value of 0 to 79, transferred to the data pointer to
define one of 80 display RAM addresses
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Table 13. Device-select command bit description
See Section 7.10.2.
Bit
Symbol Value
Description
fixed value
7 to 3
2 to 0
-
11100
A[2:0]
000 to 111
device selection
3-bit binary value of 0 to 7, transferred to the subaddress
counter to define one of 8 hardware subaddresses
Table 14. Bank-select command bit description[1]
See Section 7.10.5 and Section 7.10.6.
Bit
Symbol Value
Description
Static
1:2 multiplex
7 to 2
1
-
I
111110
fixed value
input bank selection: storage of arriving display data
0
1
RAM row 0
RAM row 2
RAM rows 0 and 1
RAM rows 2 and 3
0
O
output bank selection: retrieval of LCD display data
0
1
RAM row 0
RAM row 2
RAM rows 0 and 1
RAM rows 2 and 3
[1] The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes.
Table 15. Blink-select command bit description
See Section 7.11.
Bit
7 to 3
2
Symbol Value
Description
-
11110
fixed value
blink mode selection[1]
AB
0
1
normal blinking
blinking by alternating display RAM banks
1 to 0
BF[1:0]
blink frequency selection[2]
00
01
10
11
off
1
2
3
[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[2] For the blink frequencies see Table 9.
7.13 Display controller
The display controller executes the commands identified by the command decoder. It
contains the status registers and coordinates their effects. The display controller also
loads the display data into the display RAM as required by the storage order.
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8. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial Data line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
By connecting pin SDAACK to pin SDA on the PCF85133, the SDA line becomes fully
I2C-bus compatible. In COG applications where the track resistance from the SDAACK
pin to the system SDA line can be significant, possibly a voltage divider is generated by
the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a
consequence it may be possible that the acknowledge generated by the PCF85133 can’t
be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle
is required, it is therefore necessary to minimize the track resistance from the SDAACK
pin to the system SDA line to guarantee a valid LOW level.
By separating the acknowledge output from the serial data line (having the SDAACK open
circuit) design efforts to generate a valid acknowledge level can be avoided. However, in
that case the I2C-bus master has to be set up in such a way that it ignores the
acknowledge cycle.2
The following definition assumes SDA and SDAACK are connected and refers to the pair
as SDA.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 13).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 13. Bit transfer
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START
condition (S).
2. For further information, please consider the NXP application note: Ref. 1 “AN10170”.
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Universal LCD driver for low multiplex rates
A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P).
The START and STOP conditions are shown in Figure 14.
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 14. Definition of START and STOP conditions
8.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 15.
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
mga807
Fig 15. System configuration
8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 16.
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Universal LCD driver for low multiplex rates
data output
by transmitter
not acknowledge
acknowledge
data output
by receiver
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 16. Acknowledgement on the I2C-bus
8.5 I2C-bus controller
The PCF85133 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF85133 are
the acknowledge signals from the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data, and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that
no two devices with a common I2C-bus slave address have the same hardware
subaddress.
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCF85133. The entire I2C-bus slave address byte is shown in Table 16.
Table 16. I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
R/W
0
1
1
1
0
0
SA0
The PCF85133 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte that a PCF85133 will respond to,
is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
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Having two reserved slave addresses allows the following on the same I2C-bus:
• Up to 16 PCF85133s on the same I2C-bus for very large LCD applications
• The use of two types of LCD multiplex on the same I2C-bus
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the available PCF85133
slave addresses. All PCF85133 with the same SA0 level acknowledge in parallel to the
slave address. All PCF85133 with the alternative SA0 level ignore the whole I2C-bus
transfer.
R/W = 0
slave address
control byte
RAM/command byte
S
A
0
M
S
B
L
S
B
C
O
R
S
S
0
1
1
1
0
0
0
A
P
A
EXAMPLES
a) transmit two bytes of RAM data
S
S
0
1
1
1
0
0
A
0
0
A
0
1
1
0
RAM DATA
COMMAND
COMMAND
RAM DATA
A
A
A
A
A
A
P
A
A
A
b) transmit two command bytes
S
A
0
0
0
1
S
0
1
1
1
0
0
A
0
0
COMMAND
RAM DATA
A
A
P
c) transmit one command byte and two RAM date bytes
S
A
S
0
1
1
1
0
0
A
0
0
1
0
RAM DATA
A
P
mgl752
Fig 17. I2C-bus protocol
After acknowledgement, the control byte is sent, defining if the next byte is a RAM or
command information. The control byte also defines if the next byte is a control byte or
further RAM or command data (see Figure 18 and Figure 17). In this way it is possible to
configure the device and then fill the display RAM with little overhead.
MSB
LSB
7
6
5
4
3
2
1
0
CO RS
not relevant
mgl753
Fig 18. Control byte format
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Table 17. Control byte description
Bit
Symbol Value
Description
7
CO
continue bit
0
last control byte
control bytes continue
register selection
command register
data register
1
6
RS
0
1
5 to 0
-
not relevant
The command bytes and control bytes are also acknowledged by all addressed
PCF85133s connected to the bus.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter. Both data pointer and subaddress counter are
automatically updated.
The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed
PCF85133. After the last (display) byte, the I2C-bus master issues a STOP condition (P).
Alternatively a START may be asserted to RESTART an I2C-bus access.
9. Internal circuitry
V
V
V
V
DD
DD
SA0, CLK, SYNC, OSC,
FF, A0, A1, A2
SS
SS
SCL, SDA, SDAACK
V
V
SS
V
V
LCD
LCD
BP0, BP1, BP2,
BP3, S0 to S79
V
SS
SS
001aaj580
Fig 19. Device protection diagram
PCF85133
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10. Limiting values
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter
Conditions
Min
0.5
0.5
0.5
0.5
10
10
50
50
50
-
Max
+6.5
+9.0
+6.5
+9.0
+10
Unit
V
VDD
VLCD
Vi(n)
Vo(n)
II
supply voltage
LCD supply voltage
voltage on any input
voltage on any output
input current
V
VDD related inputs
V
VLCD related outputs
V
mA
mA
mA
mA
mA
mW
mW
V
IO
output current
+10
IDD
ISS
supply current
+50
ground supply current
+50
IDD(LCD) LCD supply current
+50
Ptot
total power dissipation
400
P/out
Vesd
power dissipation per output
electrostatic discharge voltage
-
100
[2]
[3]
[4]
[5]
Human Body Model
Machine Model
-
4500
250
200
-
V
Ilu
latch-up current
-
mA
C
C
Tstg
Tamb
storage temperature
ambient temperature
65
40
+150
+85
operating device
[1] Stresses above these values listed may cause permanent damage to the device.
[2] Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.
[3] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.
[4] Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).
[5] According to the NXP store and transport requirements (see Ref. 10 “SNW-SQ-623”) the devices have to
be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage
products deviant conditions are described in that document.
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
28 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
11. Static characteristics
Table 19. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
2.5
1.0
-
-
5.5
6.5
1.6
60
V
VLCD
LCD supply voltage
power-on reset voltage
-
V
VPOR
1.3
16
2
V
[1]
[1]
IDD(LCD) LCD supply current
fclk(ext) = 1536 Hz
fclk(ext) = 1536 Hz
A
A
IDD
supply current
-
20
Logic[2]
VI
input voltage
VSS 0.5 -
VDD + 0.5 V
VIH
VIL
HIGH-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, FF
0.7VDD
-
-
-
-
-
-
-
VDD
V
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
on pins CLK, SYNC, OSC, A0 to A2, SA0, FF
VSS
0.3VDD
V
VOH
VOL
IOH
IOL
0.8VDD
-
V
-
0.2VDD
V
HIGH-level output current at pin CLK; VOH = 4.6 V; VDD = 5 V
1
-
-
mA
mA
A
LOW-level output current at pins CLK, SYNC; VOL = 0.4 V; VDD = 5 V
1
+1
IL
leakage current
at pins OSC, CLK, SCL, SDA, A0 to A2, SA0,
FF; VI = VDD or VSS
1
[3]
CI
input capacitance
-
-
7
pF
I2C-bus
Input on pins SDA and SCL
VI
input voltage
VSS 0.5 -
5.5
V
VIH
VIL
CI
HIGH-level input voltage
LOW-level input voltage
input capacitance
0.7VDD
-
-
-
-
5.5
V
VSS
0.3VDD
V
[3]
-
7
-
pF
mA
IOL(SDA) LOW-level output current VOL = 0.4 V; VDD = 5 V
on pin SDA
3
LCD outputs
VO
output voltage variation
on pins BP0 to BP3; Cbpl = 35 nF
on pins S0 to S79; Csgm = 5 nF
VLCD = 5 V
100
100
-
-
+100
+100
mV
mV
RO
output resistance
[4]
[4]
on pins BP0 to BP3
-
-
1.5
6.0
10
k
k
on pins S0 to S79
13.5
[1] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[2] The I2C-bus interface of PCF85133 is 5 V tolerant.
[3] Not tested, design specification only.
[4] Outputs measured individually and sequentially.
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
29 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
Table 20. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Clock
Internal: output pin CLK
fclk clock frequency
Parameter
Conditions
Min
Typ
Max
Unit
[1][2]
[1][2]
FF = VDD
FF = VSS
FF = VDD
FF = VSS
1440
1920
60
1970
2640
82
2640
3600
110
Hz
Hz
Hz
Hz
ffr
frame frequency
80
110
150
External: input pin CLK
[2]
fclk(ext)
tclk(H)
tclk(L)
external clock frequency
800
130
130
-
-
-
3600
Hz
s
s
HIGH-level clock time
LOW-level clock time
-
-
Synchronization: input pin SYNC
tPD(SYNC_N) SYNC propagation delay
-
30
-
-
-
ns
tSYNC_NL
Outputs: pins BP0 to BP3 and S0 to S79
tPD(drv) driver propagation delay
SYNC LOW time
1
s
VLCD = 5 V
-
-
30
s
I2C-bus: timing[3]
Pin SCL
fSCL
SCL clock frequency
-
-
-
-
400
kHz
s
tHIGH
HIGH period of the SCL clock
LOW period of the SCL clock
0.6
1.3
-
-
tLOW
s
Pin SDA
tSU;DAT
tHD;DAT
data set-up time
data hold time
100
0
-
-
-
-
ns
ns
Pins SCL and SDA
tBUF
bus free time between a STOP and
1.3
-
-
s
START condition
tSU;STO
tHD;STA
tSU;STA
set-up time for STOP condition
hold time (repeated) START condition
0.6
0.6
0.6
-
-
-
-
-
-
s
s
s
set-up time for a repeated START
condition
tr
rise time of both SDA and SCL signals fSCL = 400 kHz
fSCL < 125 kHz
-
-
-
-
-
-
-
-
-
-
0.3
1.0
0.3
400
50
s
s
s
pF
ns
tf
fall time of both SDA and SCL signals
capacitive load for each bus line
Cb
tw(spike)
spike pulse width
on bus
[1] Typical output duty cycle of 50 %.
fclk
-------
24
[2] The corresponding frame frequency is ffr
=
.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD. For I2C-bus timings see Figure 21.
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
30 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
1 / f
CLK
t
t
clk(L)
clk(H)
0.7 V
0.3 V
DD
DD
CLK
0.7 V
0.3 V
DD
DD
SYNC
t
PD(SYNC_N)
t
SYNC_NL
0.5 V
BP0 to BP3,
and S0 to S79
(V
= 5 V)
DD
0.5 V
t
001aag591
PD(drv)
Fig 20. Driver timing waveforms
SDA
t
t
t
f
BUF
LOW
SCL
SDA
t
HD;STA
t
t
t
SU;DAT
r
HD;DAT
t
HIGH
t
SU;STA
t
SU;STO
mga728
Fig 21. I2C-bus timing waveforms
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
31 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
13. Application information
13.1 Cascaded operation
In large display configurations of up to 16 PCF85133s can be recognized on the same
I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable
I2C-bus slave address (SA0).
Table 21. Addressing cascaded PCF85133
Cluster
Bit SA0
Pin A2
Pin A1
Pin A0
Device
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2
1
8
9
10
11
12
13
14
15
When cascaded PCF85133 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCF85133 of the cascade contribute
additional segment outputs, but their backplane outputs are left open-circuit
(see Figure 22).
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
32 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
SDAACK
V
V
LCD
DD
SDA
SCL
SYNC
CLK
OSC
FF
80 segment drives
PCF85133
(2)
BP0 to BP3
(open-circuit)
LCD PANEL
A0 A1 A2 SA0 V
SS
(up to 5120
elements)
V
LCD
SDAACK
V
t
r
DD
≤
R
2C
V
V
LCD
b
DD
80 segment drives
SDA
SCL
SYNC
CLK
OSC
FF
HOST
MICRO-
PROCESSOR/
MICRO-
4 backplanes
BP0 to BP3
PCF85133
CONTROLLER
(1)
A0 A1 A2 SA0
V
SS
V
SS
001aaj581
(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 22. Cascaded PCF85133 configuration
For display sizes that are not multiple of 320 elements, a mixed cascaded system can be
considered containing only devices like PCF85133 and PCF8532. Depending on the
application, one must take care of the software command and pin connection
compatibility.
Only one master but multiple slaves are allowed in a cascade. No external clock should
be used; the slaves get the clock from the master.
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF85133s. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments, or by the definition of a multiplex mode when
PCF85133s with different SA0 levels are cascaded).
SYNC is organized as an input/output pin; The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCF85133 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF85133 to assert
SYNC. The timing relationships between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF85133 are shown in Figure 23.
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
33 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
1
T
=
fr
f
fr
BP0
SYNC
(a) static drive mode.
BP0
(1/2 bias)
BP0
(1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Fig 23. Synchronization of the cascade for the various PCF85133 drive modes
The contact resistance between the SYNC bumps of cascaded devices must be
controlled. If the resistance is too high then the device will not be able to synchronize
properly. This is particularly applicable to COG applications. Table 22 shows the limiting
values for contact resistance.
Table 22. SYNC contact resistance
Number of devices
Maximum contact resistance
2
6000
2200
1200
700
3 to 5
6 to 10
11 to 16
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
34 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
14. Bare die outline
Bare die; 110 bumps; 4.16 x 1.07 x 0.38 mm
PCF85133
D
X
96
41
+y
+x
E
0
0
PC85133-1
97
110 1
40
Y
b
A
e
e
1
A
1
L
detail Y
detail X
0
e
1
2 mm
scale
Dimensions
(1)
(1)
(1)
b
(1)
(1)
(1)
Unit
max
A
A
D
E
e
1
L
1
0.018
mm nom 0.380 0.015 0.0338 4.156 1.069 0.054 0.2026 0.090
min 0.012
Note
1. Dimension not drawn to scale.
pcf85133_do
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
09-02-03
09-08-18
PCF85133
Fig 24. Bare die outline of PCF85133
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
35 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 23. Bump locations
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 24.
Symbol
SDAACK
SDAACK
SDAACK
SDA
SDA
SDA
SCL
SCL
SCL
CLK
VDD
VDD
VDD
SYNC
OSC
FF
Bump X (m)
Y (m)
Description
I2C-bus acknowledge output
[1]
1
1022.67 436.5
2
968.67
914.67
712.17
658.17
604.17
433.17
379.17
325.17
173.52
61.47
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
3
[1]
4
I2C-bus serial data input
I2C-bus serial clock input
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
clock input/output
supply voltage
7.47
46.53
149.58
cascade synchronization input/output
oscillator select
262.08
345.78
frame frequency select
subaddress input
A0
429.48
A1
513.18
A2
596.88
SA0
VSS
680.58
I2C-bus slave address input; bit 0
ground supply voltage
765.63
VSS
819.63
VSS
873.63
VLCD
VLCD
VLCD
BP2
BP0
S0
979.83
LCD supply voltage
1033.83
1087.83
1176.03
1230.03
1284.03
1338.03
1392.03
1446.03
1500.03
1554.03
1608.03
1662.03
1716.03
1770.03
1824.03
LCD backplane output
LCD segment output
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
36 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 23. Bump locations
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 24.
Symbol
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
Bump X (m)
Y (m)
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
436.5
Description
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
1878.03
1423.53
1369.53
1315.53
1261.53
1207.53
1153.53
1099.53
1045.53
991.53
937.53
883.53
829.53
714.06
660.06
606.06
552.06
498.06
444.06
390.06
336.06
282.06
228.06
112.59
LCD segment output
58.59
4.59
49.41
103.41
157.41
211.41
265.41
319.41
373.41
427.41
481.41
596.88
650.88
704.88
758.88
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
37 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 23. Bump locations
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 24.
Symbol
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
BP3
BP1
D1
Bump X (m)
Y (m)
436.5
436.5
436.5
436.5
Description
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
-
812.88
866.88
920.88
974.88
LCD segment output
1028.88 436.5
1082.88 436.5
1136.88 436.5
1252.35 436.5
1306.35 436.5
1360.35 436.5
1414.35 436.5
1468.35 436.5
1522.35 436.5
1576.35 436.5
1630.35 436.5
1684.35 436.5
1738.35 436.5
1792.35 436.5
1876.05 436.5
1822.05 436.5
1768.05 436.5
1714.05 436.5
1660.05 436.5
1606.05 436.5
1552.05 436.5
1498.05 436.5
1444.05 436.5
1390.05 436.5
1336.05 436.5
1282.05 436.5
1228.05 436.5
1174.05 436.5
LCD backplane output
dummy pad
[2]
1932.03
1909.53
1801.53
1693.53
1585.53
1477.53
436.5
436.5
436.5
436.5
436.5
436.5
D2
-
D3
-
D4
-
D5
-
D6
-
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
38 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 23. Bump locations
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 24.
Symbol
D7
Bump X (m)
Y (m)
1846.35 436.5
1953 436.5
1930.05 436.5
Description
-
-
-
dummy pad
D8
D9
[1] For most applications SDA and SDAACK are shorted together; see Section 8.
[2] The dummy pads are connected to VSS but are not tested.
Table 24. Gold bump hardness
Type number
Min
Max
Unit[1]
PCF85133U/2DA/1
60
120
HV
[1] Pressure of diamond head: 10 g to 50 g.
REF
S1
REF
C1
001aah849
The approximate positions of the alignment marks are shown in Figure 24.
Fig 25. Alignment marks of PCF85133
Table 25. Alignment mark locations
Symbol
S1
Size (m)
81 81
X (m)
1916.1
1855.8
Y (m)
45
C1
81 81
45
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
39 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
16. Packing information
16.1 Tray information for PCF85133
A
C
1.1
1.2
1.3
2.1
2.2
3.1
x.1
D
F
1.y
B
y
E
x
001aai624
Fig 26. Tray details for PCF85133
Table 26. Tray dimensions of PCF85133 tray
See Figure 26.
Symbol
Description
Value
A
B
C
D
E
F
pocket pitch in x direction
pocket pitch in y direction
pocket width in x direction
pocket width in y direction
tray width in x direction
tray width in y direction
6.3 mm
3 mm
4.26 mm
1.17 mm
50.8 mm
50.8 mm
7
N
M
number of pockets, x direction
number of pockets, y direction
15
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
40 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
The orientation of the IC in a pocket is indicated by the position of the IC type name on the
die surface with respect to the chamfer on the upper left corner of the tray (see Figure 27).
Refer to the bump location diagram (Figure 24) for the orientation and position of the type
name on the die surface.
marking code
001aaj643
Fig 27. Tray alignment for PCF85133 tray
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
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PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
17. Abbreviations
Table 27. Abbreviations
Acronym
CMOS
COG
DC
Description
Complementary Metal-Oxide Semiconductor
Chip-On-Glass
Direct Current
HBM
I2C
Human Body Model
Inter-Integrated Circuit
Integrated Circuit
IC
ITO
Indium Tin Oxide
LCD
MM
Liquid Crystal Display
Machine Model
RAM
RC
Random Access Memory
Resistance-Capacitance
Root Mean Square
RMS
18. References
[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD
drivers
[2] AN10706 — Handling bare die
[3] AN10853 — ESD and EMC sensitivity of IC
[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[8] JESD78 — IC Latch-Up Test
[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[10] SNW-SQ-623 — NXP store and transport conditions
[11] UM10204 — I2C-bus specification and user manual
PCF85133
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Product data sheet
Rev. 2 — 4 July 2011
42 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
19. Revision history
Table 28. Revision history
Document ID
PCF85133 v.2
Modifications:
Release date
20110704
Data sheet status
Change notice
Supersedes
Product data sheet
-
PCF85133_1
• Added Section 7.10.3 and Section 7.10.4
• Changed Figure 24
• Added Section 18
• Changed Section 7.3 and Section 8
PCF85133_1
20090217
Product data sheet
-
-
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
43 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
20.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
20.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
44 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF85133
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 4 July 2011
45 of 46
PCF85133
NXP Semiconductors
Universal LCD driver for low multiplex rates
22. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
12
Dynamic characteristics. . . . . . . . . . . . . . . . . 30
Application information . . . . . . . . . . . . . . . . . 32
Cascaded operation. . . . . . . . . . . . . . . . . . . . 32
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 35
Handling information . . . . . . . . . . . . . . . . . . . 39
Packing information . . . . . . . . . . . . . . . . . . . . 40
Tray information for PCF85133 . . . . . . . . . . . 40
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 42
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision history . . . . . . . . . . . . . . . . . . . . . . . 43
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
13
13.1
14
15
16
16.1
17
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
7.3
7.3.1
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.5.1
7.5.2
7.6
Functional description . . . . . . . . . . . . . . . . . . . 4
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 5
LCD bias generator . . . . . . . . . . . . . . . . . . . . . 5
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 5
Electro-optical performance . . . . . . . . . . . . . . . 7
LCD drive mode waveforms . . . . . . . . . . . . . . . 9
Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 13
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timing and frame frequency. . . . . . . . . . . . . . 14
Display register. . . . . . . . . . . . . . . . . . . . . . . . 14
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 15
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 15
Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Subaddress counter . . . . . . . . . . . . . . . . . . . . 18
RAM writing in 1:3 multiplex drive mode. . . . . 19
Writing over the RAM address boundary . . . . 19
Output bank selector . . . . . . . . . . . . . . . . . . . 20
Input bank selector . . . . . . . . . . . . . . . . . . . . . 20
Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Command decoder. . . . . . . . . . . . . . . . . . . . . 21
Display controller . . . . . . . . . . . . . . . . . . . . . . 22
18
19
20
Legal information . . . . . . . . . . . . . . . . . . . . . . 44
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 44
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45
20.1
20.2
20.3
20.4
21
22
Contact information . . . . . . . . . . . . . . . . . . . . 45
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.7
7.8
7.9
7.10
7.10.1
7.10.2
7.10.3
7.10.4
7.10.5
7.10.6
7.11
7.12
7.13
8
Characteristics of the I2C-bus . . . . . . . . . . . . 23
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
START and STOP conditions . . . . . . . . . . . . . 23
System configuration . . . . . . . . . . . . . . . . . . . 24
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 25
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 25
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 27
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28
Static characteristics. . . . . . . . . . . . . . . . . . . . 29
10
11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 July 2011
Document identifier: PCF85133
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