PCF8563BS/4-T_技术文档

PCF8563

Real-time clock/calendar

Rev. 06 — 21 February 2008

Product data sheet

1. General description

The PCF8563 is a CMOS real-time clock/calendar optimized for low power consumption.

A programmable clock output, interrupt output and voltage-low detector are also provided.

All addresses and data are transferred serially via a two-line bidirectional I²C-bus.

Maximum bus speed is 400 kbit/s. The built-in word address register is incremented

automatically after each written or read data byte.

2. Features

I Provides year, month, day, weekday, hours, minutes and seconds based on

32.768 kHz quartz crystal

I Century ﬂag

I Clock operating voltage: 1.8 V to 5.5 V

I Low backup current; typical 0.25 µA at V_DD= 3.0 V and T_amb= 25 °C

I 400 kHz two-wire I²C-bus interface (at V_DD= 1.8 V to 5.5 V)

I Programmable clock output for peripheral devices (32.768 kHz, 1024 Hz, 32 Hz and

1 Hz)

I Alarm and timer functions

I Integrated oscillator capacitor

I Internal power-on reset

I I²C-bus slave address: read A3h and write A2h

I Open-drain interrupt pin

I ElectroStatic Discharge (ESD) protection exceeds 2000 V Human Body Model (HBM)

per JESD22-A114, 200 V Machine Model (MM) per JESD22-A115 and 2000 V

Charged Device Model (CDM) per JESD22-C101

I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA

3. Applications

I Mobile telephones

I Portable instruments

I Electronic metering

I Battery powered products

PCF8563

NXP Semiconductors

Real-time clock/calendar

4. Ordering information

Table 1.

Ordering information

Type number Topside

mark

Package

Name

DIP8

Description

Version

PCF8563P

PCF8563T

PCF8563TS

PCF8563P

8563T

plastic dual in-line package; 8 leads (300 mil)

SOT97-1

SO8

plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

8563

TSSOP8

plastic thin shrink small outline package; 8 leads; body width

3 mm

SOT505-1

PCF8563BS

8563S

HVSON10 plastic thermal enhanced very thin small outline package;

SOT650-1

no leads; 10 terminals; body 3 × 3 × 0.85 mm

5. Block diagram

OSCI

OSCILLATOR

32.768 kHz

DIVIDER

CLOCK OUT

CLKOUT

OSCO

CONTROL

MONITOR

00

01

0D

CONTROL_STATUS_1

CONTROL_STATUS_2

CLKOUT_CONTROL

POWER ON

RESET

TIME

VL_SECONDS

MINUTES

02

03

04

05

06

07

08

HOURS

V

DD

DAYS

V

SS

WEEKDAYS

CENTURY_MONTHS

YEARS

WATCH

DOG

ALARM FUNCTION

MINUTE_ALARM

HOUR_ALARM

09

0A

0B

0C

2

DAY_ALARM

SDA

SCL

I C-BUS

INTERFACE

WEEKDAY_ALARM

INT

INTERRUPT

TIMER FUNCTION

TIMER_CONTROL

TIMER

0E

0F

PCF8563

001aah658

Fig 1. Block diagram

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

2 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

6. Pinning information

6.1 Pinning

1

2

3

4

8

7

6

5

OSCI

OSCO

INT

V

DD

1

2

3

4

8

7

6

5

OSCI

OSCO

INT

V

DD

CLKOUT

SCL

CLKOUT

SCL

PCF8563T

PCF8563P

V

SS

SDA

V

SDA

SS

001aaf977

001aaf975

Fig 2. Pin conﬁguration DIP8

Fig 3. Pin conﬁguration SO8

terminal 1

index area

1

2

3

4

5

10

9

OSCI

OSCO

n.c.

V

DD

8

PCF8563BS

CLKOUT

SCL

1

2

3

4

8

7

6

5

OSCI

OSCO

INT

V

DD

7

INT

CLKOUT

SCL

PCF8563TS

6

V

SS

SDA

V

SS

SDA

001aaf981

001aaf976

Transparent top view

Fig 4. Pin conﬁguration TSSOP8

Fig 5. Pin conﬁguration HVSON10

8

1

V

DD

OSCI

7

2

CLKOUT

SCL

OSCO

6

5

3

INT

4

V

SS

SDA

PCF8563

mgr886

Fig 6. Device diode protection diagram

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

3 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

6.2 Pin description

Table 2.

Symbol

Pin description

Description

DIP8, SO8, TSSOP8 HVSON10

OSCI

OSCO

n.c.

1

2

-

1

2

oscillator input

oscillator output

3

not connected

INT

3

4

5

6

7

8

-

4

interrupt output (open-drain; active LOW)

ground

V_SS

5

SDA

SCL

6

serial data input and output

serial clock input

7

CLKOUT

V_DD

8

clock output, open-drain

positive supply voltage

not connected

9

n.c.

10

7. Functional description

The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address register,

an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which

provides the source clock for the Real-Time Clock/calender (RTC), a programmable clock

output, a timer, an alarm, a voltage-low detector and a 400 kHz I²C-bus interface.

All 16 registers are designed as addressable 8-bit parallel registers although not all bits

are implemented. The ﬁrst two registers (memory address 00h and 01h) are used as

control and/or status registers. The memory addresses 02h through 08h are used as

counters for the clock function (seconds up to years counters). Address locations 09h

through 0Ch contain alarm registers which deﬁne the conditions for an alarm.

Address 0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the timer control

and timer registers, respectively.

The seconds, minutes, hours, days, weekdays, months, years as well as the minute alarm,

hour alarm, day alarm and weekday alarm registers are all coded in Binary Coded

Decimal (BCD) format.

When one of the RTC registers is read the contents of all counters are frozen. Therefore,

faulty reading of the clock/calendar during a carry condition is prevented.

7.1 Alarm function modes

By clearing the MSB of one or more of the alarm registers (bit AE = Alarm Enable), the

corresponding alarm condition(s) will be active. In this way an alarm can be generated

from once per minute up to once per week. The alarm condition sets the Alarm Flag (AF).

The asserted AF can be used to generate an interrupt (on pin INT). The AF can only be

cleared by software.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

4 of 32

PCF8563

NXP Semiconductors

7.2 Timer

Real-time clock/calendar

The 8-bit countdown timer at address 0Fh is controlled by the timer control register at

address 0Eh. The timer control register determines one of 4 source clock frequencies for

the timer (4096 Hz, 64 Hz, 1 Hz, or ¹⁄₆₀Hz), and enables or disables the timer. The timer

counts down from a software-loaded 8-bit binary value. At the end of every countdown,

the timer sets the Timer Flag (TF). The TF may only be cleared by software. The

asserted TF can be used to generate an interrupt (on pin INT). The interrupt may be

generated as a pulsed signal every countdown period or as a permanently active signal

which follows the state of TF. Bit TI_TP is used to control this mode selection. When

reading the timer, the current countdown value is returned.

7.3 Clock output

A programmable square wave is available at pin CLKOUT. Operation is controlled by the

CLKOUT control register at address 0Dh. Frequencies of 32.768 kHz (default), 1024 Hz,

32 Hz and 1 Hz can be generated for use as a system clock, microcontroller clock, input to

a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and

enabled at power-on. If disabled it becomes high-impedance.

7.4 Reset

The PCF8563 includes an internal reset circuit which is active whenever the oscillator is

stopped. In the reset state the I²C-bus logic is initialized and all registers are reset

according to Table 25.

7.5 Voltage-low detector

The PCF8563 has an on-chip voltage-low detector (see Figure 7). When V_DDdrops below

V_low, bit VL in the seconds register is set to indicate that the integrity of the clock

information is no longer guaranteed. The VL ﬂag can only be cleared by software.

Bit VL is intended to detect the situation when V_DDis decreasing slowly, for example under

battery operation. Should V_DDreach V_lowbefore power is re-asserted then bit VL is set.

This will indicate that the time may be corrupted.

mgr887

V

DD

normal power

operation

period of battery

operation

V

low

t

VL set

Fig 7. Voltage-low detection

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

5 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

7.6 Register organization

Table 3.

Formatted registers overview

Bit positions labelled as x are not relevant. Bit positions labelled with 0 should always be written with logic 0; if read they could

be either logic 0 or logic 1.

Address Register name

Bit 7

Bit 6

Bit 5

STOP

0

Bit 4

0

Bit 3

TESTC

AF

Bit 2

0

Bit 1

0

Bit 0

0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

control_status_1

control_status_2

VL_seconds

minutes

TEST1

0

VL

x

TI_TP

TF

AIE

TIE

hours

x

days

x

weekdays

x

century_months

years

C

minute_alarm

hour_alarm

day_alarm

weekday_alarm

CLKOUT_control

timer_control

timer

AE

FE

TE

x

x

FD1

TD1

FD0

TD0

7.6.1 Control_status_1 register

Table 4.

Control_status_1 - Control and Status register 1 (address 00h) bit description

Symbol Value Description

Bit

7

TEST1

0

1

Normal mode

EXT_CLK test mode

default value is logic 0

RTC source clock runs

6

5

0

STOP

0

1

all RTC divider chain ﬂip-ﬂops are asynchronously set to logic 0; the

RTC clock is stopped (CLKOUT at 32.768 kHz is still available)

4

3

0

default value is logic 0

TESTC

0

1

Power-on reset override facility is disabled; set to logic 0 for normal

operation

Power-on reset override may be enabled

default value is logic 0

2 to 0

0

7.6.2 Control_status_2 register

Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a timer

countdown, TF is set to logic 1. These bits maintain their value until overwritten by

software. If both timer and alarm interrupts are required in the application, the source of

the interrupt can be determined by reading these bits. To prevent one ﬂag being

overwritten while clearing another a logic AND is performed during a write access.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

6 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when

TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions

when both AIE and TIE are set.

Table 5.

Bit

Control_status_2 - Control and Status register 2 (address 01h) bit description

Symbol Value

Description

7 to 5

4

0

default value is logic 0

TI_TP

0

1

INT is active when TF is active (subject to the status of TIE)

INT pulses active according to Table 6 (subject to the status of

TIE); note that if AF and AIE are active then INT will be

permanently active

3

2

AF

0 (read) alarm ﬂag inactive

1 (read) alarm ﬂag active

0 (write) alarm ﬂag is cleared

1 (write) alarm ﬂag remains unchanged

0 (read) timer ﬂag inactive

TF

1 (read) timer ﬂag active

0 (write) timer ﬂag is cleared

1 (write) timer ﬂag remains unchanged

1

0

AIE

TIE

0

1

0

1

alarm interrupt disabled

alarm interrupt enabled

timer interrupt disabled

timer interrupt enabled

Table 6.

INT operation (bit TI_TP = 1)

Source clock (Hz)

INT period (s)^[1]

n = 1^[2]

n > 1^[2]

1

4096

64

⁄

8192

128

64

4096

64

1

64

1

⁄

60

64

[1] TF and INT become active simultaneously.

[2] n = loaded countdown value. Timer stopped when n = 0.

7.6.3 Time and date registers

Table 7.

VL_seconds - Validity and Seconds register (address 02h) bit description

Bit

Symbol

Value

Description

7

VL

0

1

clock integrity is guaranteed

integrity of the clock information is no longer guaranteed

6 to 0

SECONDS[6:0] 00 to 59 the current seconds, coded in BCD format. Example:

seconds register contains x101 1001 = 59 seconds

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

7 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

Table 8.

Minutes - Minutes register (address 03h) bit description

Bit

7

Symbol

Value

Description

x

not relevant

6 to 0

MINUTES[6:0]

00 to 59 the current minutes, coded in BCD format

Table 9.

Bit

Hours - Hours register (address 04h) bit description

Symbol

x

Value

Description

7 to 6

5 to 0

not relevant

HOURS[5:0]

00 to 23 the current hours, coded in BCD format

Table 10. Days - Days register (address 05h) bit description

Bit

Symbol

x

Value

Description

7 to 6

5 to 0

not relevant

DAYS[5:0]

01 to 31 the current day, coded in BCD format^[1]

[1] The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a

value which is exactly divisible by 4, including the year 00.

Table 11. Weekdays - Weekdays register (address 06h) bit description

Bit

Symbol

Value

Description

7 to 3

2 to 0^[1]

x

not relevant

WEEKDAYS[2:0] 0 to 6

the current weekday, coded in BCD format,

see Table 12.

[1] These bits may be re-assigned by the user.

Table 12. Weekday assignments

Weekday

Sunday

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

x

0

1

0

1

0

1

0

1

0

1

0

1

0

Monday

Tuesday

Wednesday

Thursday

Friday

Saturday

Table 13. Century_months - Century and Months register (address 07h) bit description

Bit

Symbol

Value

Description

7

C^[1]

century; this bit is toggled when the years register

overﬂows from 99 to 00

0

1

indicates the century is 20xx

indicates the century is 19xx

not relevant

6 to 5

4 to 0

x

MONTHS[4:0]

01 to 12 the current month, coded in BCD format, see Table 14

[1] This bit may be re-assigned by the user.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

8 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

Table 14. Month assignments

Month

Bit 7

C

Bit 6

Bit 5

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

1

January

February

March

x

C

0

1

0

C

0

1

April

C

0

1

0

May

C

0

1

0

1

June

C

0

1

0

July

C

0

1

August

September

October

November

December

C

0

1

0

C

0

1

0

1

C

1

0

C

1

0

1

C

1

0

1

0

Table 15. Years - Years register (address 08h) bit description

Bit

Symbol

Value

Description

7 to 0

YEARS[7:0]

00 to 99 the current year, coded in BCD format

7.6.4 Alarm registers

When one or more of these registers are loaded with a valid minute, hour, day or weekday

and its corresponding bit Alarm Enable (AE) is logic 0, then that information will be

compared with the current minute, hour, day and weekday. When all enabled comparisons

ﬁrst match, the Alarm Flag (AF) is set. AF will remain set until cleared by software.

Once AF has been cleared it will only be set again when the time increments to match the

alarm condition once more. Alarm registers which have their bit AE at logic 1 will be

ignored.

Table 16. Minute_alarm - Minute alarm register (address 09h) bit description

Bit

Symbol

Value

Description

7

AE

0

1

minute alarm is enabled

minute alarm is disabled

6 to 0

ALARM _MINUTES[6:0] 00 to 59 the minute alarm information, coded in BCD

format

Table 17. Hour_alarm - Hour alarm register (address 0Ah) bit description

Bit

Symbol

Value

Description

7

AE

0

1

hour alarm is enabled

hour alarm is disabled

not relevant

6

x

5 to 0

ALARM_HOURS[5:0]

00 to 23 the hour alarm information, coded in BCD format

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

9 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

Table 18. Day_alarm - Day alarm register (address 0Bh) bit description

Bit

Symbol

Value

Description

7

AE

0

1

day alarm is enabled

day alarm is disabled

not relevant

6

x

5 to 0

ALARM_DAYS[5:0]

01 to 31 the day alarm information, coded in BCD format

Table 19. Weekday_alarm - Weekday alarm register (address 0Ch) bit description

Bit

Symbol

Value

Description

7

AE

0

1

weekday alarm is enabled

weekday alarm is disabled

not relevant

6 to 3

2 to 0

x

ALARM_

WEEKDAYS[2:0]

0 to 6

the weekday alarm information, coded in BCD

format

7.6.5 Clock output control register

Table 20. CLKOUT_control - CLKOUT control register (address 0Dh) bit description

Bit

Symbol

Value

Description

7

FE

0

the CLKOUT output is inhibited and set to

high-impedance

1

the CLKOUT output is activated

not relevant

6 to 2

1 to 0

x

FD[1:0]

see Table 21

these bits control the frequency output at

pin CLKOUT

Table 21. FD1 and FD0: CLKOUT frequency selection

FD1

0

FD0

0

CLKOUT frequency

32.768 kHz

1024 Hz

0

1

0

32 Hz

1

1 Hz

7.6.6 Countdown timer

The timer register is an 8-bit binary countdown timer. It is enabled and disabled via the

timer control register bit TE. The source clock for the timer is also selected by the timer

control register. Other timer properties such as interrupt generation are controlled via

control_status_2 register.

For accurate read back of the countdown value, the I²C-bus clock (SCL) must be

operating at a frequency of at least twice the selected timer clock.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

10 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

Table 22. Timer_control - Timer control register (address 0Eh) bit description

Bit

Symbol

Value

Description

7

TE

0

1

timer is disabled

timer is enabled

not relevant

6 to 2

1 to 0

x

TD[1:0]

see Table 23

timer source clock frequency select; these bits

determine the source clock for the countdown

timer; when not in use, TD[1:0] should be set

to 11 (¹⁄₆₀Hz) for power saving

Table 23. TD1 and TD0: Timer frequency selection

TD1

0

TD0

0

TIMER Source clock frequency

4096 Hz

64 Hz

0

1

0

1 Hz

1

⁄₆₀Hz

Table 24. Timer - Timer value register (address 0Fh) bit description

Bit

Symbol

Value

Description

7 to 0

TIMER

00h to FFh

countdown value = n;

n

CountdownPeriod =

--------------------------------------------------------------

SourceClockFrequency

7.7 EXT_CLK test mode

A Test mode is available which allows for on-board testing. In such a mode it is possible to

set up test conditions and control the operation of the RTC.

The Test mode is entered by setting bit TEST1 in control_status_1 register. Then

pin CLKOUT becomes an input. The Test mode replaces the internal 64 Hz signal with the

signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then

generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is

divided down to 1 Hz by a 2⁶divide chain called a pre-scaler. The pre-scaler can be set

into a known state by using bit STOP. When bit STOP is set, the pre-scaler is reset to 0

(STOP must be cleared before the pre-scaler can operate again).

From a STOP condition, the ﬁrst 1 second increment will take place after 32 positive

edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second

increment.

Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.

When entering the Test mode, no assumption as to the state of the pre-scaler can be

made.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

11 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

Operation example:

1. Set EXT_CLK test mode (control_status_1, bit TEST1 = 1)

2. Set STOP (control_status_1, bit STOP = 1)

3. Clear STOP (control_status_1, bit STOP = 0)

4. Set time registers to desired value

5. Apply 32 clock pulses to CLKOUT

6. Read time registers to see the ﬁrst change

7. Apply 64 clock pulses to CLKOUT

8. Read time registers to see the second change

Repeat steps 7 and 8 for additional increments.

7.8 Power-On Reset (POR) override

The POR duration is directly related to the crystal oscillator start-up time. Due to the long

start-up times experienced by these types of circuits, a mechanism has been built in to

disable the POR and hence speed up on-board test of the device. The setting of this mode

requires that the I²C-bus pins, SDA and SCL, be toggled in a speciﬁc order as shown in

Figure 8. All timings are required minimums.

Once the Override mode has been entered, the device immediately stops being reset and

normal operation may commence i.e. entry into the EXT_CLK test mode via I²C-bus

access. The Override mode may be cleared by writing a logic 0 to TESTC. TESTC must

be set to logic 1 before re-entry into the Override mode is possible. Setting TESTC to

logic 0 during normal operation has no effect except to prevent entry into the POR

override mode.

500 ns

2000 ns

SDA

SCL

8 ms

power up

mgm664

override active

Fig 8. POR override sequence

Table 25 shows the register reset values.

Table 25. Register reset value^[1]

Address Register name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00h

01h

02h

03h

04h

control_status_1

control_status_2

VL_seconds

minutes

0

x

1

x

0

x

0

x

0

x

1

0

x

0

x

0

x

0

x

hours

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

12 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

Table 25. Register reset value^[1]…continued

Address Register name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

days

x

1

0

x

0

1

x

0

1

x

weekdays

century_months

years

minute_alarm

hour_alarm

day_alarm

weekday_alarm

CLKOUT_control

timer_control

timer

[1] registers marked ‘x’ are undeﬁned at power-up and unchanged by subsequent resets.

8. Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 9).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mbc621

Fig 9. Bit transfer

8.2 Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P); see Figure 10.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

13 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Fig 10. Deﬁnition of start and stop conditions

8.3 System conﬁguration

A device generating a message is a transmitter, a device receiving a message is a

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves (see Figure 11).

SDA

SCL

MASTER

TRANSMITTER /

RECEIVER

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

mba605

Fig 11. System conﬁguration

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

bit. The acknowledge bit is a HIGH-level signal put on the bus by the transmitter during

which time the master generates an extra acknowledge-related clock pulse. A slave

receiver which is addressed must generate an acknowledge after the reception of each

byte. Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter (see Figure 12).

The device that acknowledges must pull down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge-related clock pulse (set-up and hold times must be taken into

consideration). A master receiver must signal an end of data to the transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

event the transmitter must leave the data line HIGH to enable the master to generate a

STOP condition.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

14 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

8

SCL from

master

1

2

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 12. Acknowledgement on the I²C-bus

8.5 I²C-bus protocol

8.5.1 Addressing

Before any data is transmitted on the I²C-bus, the device which should respond is

addressed ﬁrst. The addressing is always carried out with the ﬁrst byte transmitted after

the start procedure.

The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL

is only an input signal, but the data signal SDA is a bidirectional line.

The PCF8563 slave address is shown in Figure 13.

1

0

1

0

1

R/W

group 2

group 1

mce189

Fig 13. Slave address

8.5.2 Clock/calendar read/write cycles

The I²C-bus conﬁguration for the different PCF8563 read and write cycles is shown in

Figure 14, Figure 15 and Figure 16. The word address is a 4-bit value that deﬁnes which

register is to be accessed next. The upper four bits of the word address are not used.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

15 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

S

SLAVE ADDRESS

0

A

WORD ADDRESS

A

DATA

A

P

R/W

n bytes

auto increment

memory word address

mbd822

Fig 14. Master transmits to slave receiver (Write mode)

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from master

S

SLAVE ADDRESS

0

A

WORD ADDRESS

A

S

SLAVE ADDRESS

1

A

DATA

A

n bytes

R/W

at this moment master transmitter

becomes master receiver and

PCA8563 slave receiver

auto increment

memory word address

becomes slave transmitter

no acknowledgement

from master

DATA

1

P

last byte

auto increment

memory word address

001aag133

Fig 15. Master reads after setting word address (write word address; read data)

acknowledgement

from slave

acknowledgement

from master

no acknowledgement

from master

1

A

DATA

1

P

S

SLAVE ADDRESS

DATA

R/W

n bytes

last byte

auto increment

word address

auto increment

word address

mgl665

Fig 16. Master reads slave immediately after ﬁrst byte (Read mode)

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

16 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

9. Limiting values

Table 26. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

I_DD

Parameter

Conditions

Min

−0.5

−50

−0.5

−10

-

Max

+6.5

+50

Unit

V

supply voltage

supply current

input voltage

mA

V

V_I

on pins SCL and SDA

on pin OSCI

+6.5

V_DD+ 0.5

+6.5

+10

V

V_O

I_I

output voltage

on pins CLKOUT and INT

at any input

V

input current

mA

mW

°C

I_O

output current

at any output

+10

P_tot

T_amb

T_stg

total power dissipation

ambient temperature

storage temperature

300

−40

−65

+85

+150

10. Static characteristics

Table 27. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; f_osc= 32.768 kHz; quartz R_s= 40 kΩ; C_L= 8 pF; unless otherwise

speciﬁed.

Symbol

Supplies

V_DD

Parameter

Conditions

Min

Typ

Max

Unit

[1]

supply voltage

interface inactive; f_SCL= 0 Hz; T_amb= 25 °C;

see Figure 20

1.0

-

5.5

V

interface active; f_SCL= 400 kHz; see Figure 20

clock data integrity; T_amb= 25 °C

interface active; see Figure 19

f_SCL= 400 kHz

1.8

-

5.5

V

V_low

I_DD

supply current

-

800

200

µA

f_SCL= 100 kHz

[2]

interface inactive (f_SCL= 0 Hz); CLKOUT

disabled; T_amb= 25 °C; see Figure 17

V_DD= 5.0 V

V_DD= 3.0 V

V_DD= 2.0 V

-

275

250

225

550

500

450

nA

[2]

interface inactive (f_SCL= 0 Hz); CLKOUT

disabled; T_amb= −40 °C to +85 °C;

see Figure 17

V_DD= 5.0 V

V_DD= 3.0 V

V_DD= 2.0 V

-

500

400

750

650

600

nA

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

17 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

Table 27. Static characteristics …continued

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; f_osc= 32.768 kHz; quartz R_s= 40 kΩ; C_L= 8 pF; unless otherwise

speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[2]

I_DD

supply current

interface inactive (f_SCL= 0 Hz); CLKOUT

enabled at 32 kHz; T_amb= 25 °C; see Figure 18

V_DD= 5.0 V

V_DD= 3.0 V

V_DD= 2.0 V

-

825

550

425

1600

1000

800

nA

[2]

interface inactive (f_SCL= 0 Hz); CLKOUT

enabled at 32 kHz; T_amb= −40 °C to +85 °C;

see Figure 18

V_DD= 5.0 V

V_DD= 3.0 V

V_DD= 2.0 V

-

950

650

500

1700

1100

900

nA

Inputs

V_IL

LOW-level input

voltage

V_SS

-

0.3V_DD

V_DD

+1

V

V_IH

I_LI

HIGH-levelinput

voltage

0.7V_DD

-

V

input leakage

current

V_I= V_DDor V_SS

−1

0

-

µA

pF

[3]

C_i

input

-

7

capacitance

Outputs

I_OL

LOW-level

output current

V_OL= 0.4 V; V_DD= 5 V

on pin SDA

−3

−1

1

-

mA

on pin INT

on pin CLKOUT

I_OH

I_LO

HIGH-level

output current

on pin CLKOUT; V_OH= 4.6 V; V_DD= 5 V

output leakage V_O= V_DDor V_SS

current

−1

0

+1

µA

Voltage detector

V_lowlow voltage

T_amb= 25 °C; sets bit VL; see Figure 7

-

0.9

1.0

V

[1] For reliable oscillator start-up at power-up: V_{DD(min)power-up}= V_DD(min)+ 0.3 V.

[2] Timer source clock = ¹⁄₆₀Hz, level of pins SCL and SDA is V_DDor V_SS

.

[3] Tested on sample basis.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

18 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

mgr888

mgr889

1

I

DD

(µA)

0.8

0.6

0.4

0.2

0

0.6

0.4

0.2

0

2

4

6

0

2

4

6

V

DD

(V)

V

DD

(V)

T_amb= 25 °C; Timer = 1 minute.

Fig 17. Supply current I_DDas a function of supply

voltage V_DD; CLKOUT disabled

Fig 18. Supply current I_DDas a function of supply

voltage V_DD; CLKOUT = 32 kHz

mgr891

mgr890

1

I

DD

4

(µA)

frequency

deviation

0.8

(ppm)

2

0.6

0.4

0.2

0

−2

−4

0

2

4

6

−40

0

40

80

120

V

DD

(V)

T (°C)

V_DD= 3 V; Timer = 1 minute.

T_amb= 25 °C; normalized to V_DD= 3 V.

Fig 19. Supply current I_DDas a function of

temperature T; CLKOUT = 32 kHz

Fig 20. Frequency deviation as a function of supply

voltage V_DD

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

19 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

11. Dynamic characteristics

Table 28. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; f_osc= 32.768 kHz; quartz R_s= 40 kΩ; C_L= 8 pF; unless otherwise

speciﬁed.

Symbol

Oscillator

C_L(itg)

Parameter

Conditions

Min

Typ

Max

Unit

integrated load capacitance

15

-

25

2 × 10⁻⁷

35

-

pF

∆f_osc/f_osc

relative oscillator frequency variation

∆V_DD= 200 mV;

T

_amb= 25 °C

Quartz crystal parameters (f = 32.768 kHz)

R_s

series resistance

load capacitance

trimmer capacitance

-

40

-

kΩ

pF

C_L

parallel

-

10

-

C_trim

5

25

CLKOUT output

[1]

[2][3]

[4]

δ_CLKOUT

duty cycle on pin CLKOUT

-

50

-

%

I²C-bus timing characteristics (see Figure 21)

f_SCL

SCL clock frequency

-

400

-

kHz

µs

pF

ns

µs

ns

t_HD;STA

t_SU;STA

t_LOW

t_HIGH

t_r

hold time (repeated) START condition

set-up time for a repeated START condition

LOW period of the SCL clock

0.6

1.3

0.6

-

HIGH period of the SCL clock

-

rise time of both SDA and SCL signals

SDA

SCL

SDA

SCL

0.3

400

-

t_f

fall time of both SDA and SCL signals

-

C_b

capacitive load for each bus line

data set-up time

-

t_SU;DAT

t_HD;DAT

t_SU;STO

t_w(spike)

100

0

data hold time

-

set-up time for STOP condition

spike pulse width

0.6

-

on bus

50

[1] Unspeciﬁed for f_CLKOUT= 32.768 kHz.

[2] All timing values are valid within the operating supply voltage at ambient temperature and referenced to V_ILand V_IHwith an input voltage

swing of V_SSto V_DD

.

[3] A detailed description of the I²C-bus speciﬁcation, with applications, is given in brochure The I²C-bus speciﬁcation. This brochure may

be ordered using the code 9398 393 40011.

[4] I²C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

20 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

SDA

t

f

BUF

LOW

SCL

SDA

t

HD;STA

t

SU;DAT

r

HD;DAT

t

HIGH

t

SU;STA

t

SU;STO

mga728

Fig 21. I²C-bus timing waveforms

12. Application information

V

DD

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

1 F

V

DD

SCL

SDA

CLOCK CALENDAR

OSCI

PCF8563

V

R

DD

OSCO

V

SS

R

R: pull-up resistor

t

r

R =

C

b

SDA SCL

mgm665

2

(I C-bus)

Fig 22. Application diagram

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

21 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

12.1 Quartz frequency adjustment

12.1.1 Method 1: ﬁxed OSCI capacitor

By evaluating the average capacitance necessary for the application layout, a ﬁxed

capacitor can be used. The frequency is best measured via the 32.768 kHz signal

available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz

crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average

±5 × 10⁻⁶). Average deviations of ±5 minutes per year can be easily achieved.

12.1.2 Method 2: OSCI trimmer

Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a

trimmer is possible.

12.1.3 Method 3: OSCO output

Direct measurement of OSCO out (accounting for test probe capacitance).

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

22 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

13. Package outline

DIP8: plastic dual in-line package; 8 leads (300 mil)

SOT97-1

D

M

E

A

2

A

1

L

c

w M

Z

b

1

e

(e )

1

M

H

b

2

8

5

pin 1 index

E

1

4

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

Z

A

2

(1)

1

w

UNIT

mm

b

c

D

E

e

L

M

H

1

2

1

E

max.

min.

max.

1.73

1.14

0.53

0.38

1.07

0.89

0.36

0.23

9.8

9.2

6.48

6.20

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

1.15

0.068 0.021 0.042 0.014

0.045 0.015 0.035 0.009

0.39

0.36

0.26

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.045

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT97-1

050G01

MO-001

SC-504-8

Fig 23. Package outline SOT97-1 (DIP8)

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

23 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

4

e

w

M

detail X

b

p

0

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT96-1

076E03

MS-012

Fig 24. Package outline SOT96-1 (SO8)

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

24 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm

SOT505-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

A

(A )

2

A

3

A

1

pin 1 index

θ

L

p

L

1

4

detail X

e

w M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

E

L

p

UNIT

v

w

y

Z

θ

1

2

3

p

max.

0.15

0.05

0.95

0.80

0.45

0.25

0.28

0.15

3.1

2.9

3.1

2.9

5.1

4.7

0.7

0.4

0.70

0.35

6°

0°

mm

1.1

0.65

0.25

0.94

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-04-09

03-02-18

SOT505-1

Fig 25. Package outline SOT505-1 (TSSOP8)

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

25 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

HVSON10: plastic thermal enhanced very thin small outline package; no leads;

10 terminals; body 3 x 3 x 0.85 mm

SOT650-1

0

1

2 mm

scale

X

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

e

1

terminal 1

index area

y

v

M

e

C

A

B

b

C

1

5

w

M

L

E

h

6

10

D

h

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

(1)

UNIT

A

b

E

e

y

c

D

E

L

v

w

y

1

h

1

h

0.05 0.30

0.00 0.18

3.1

2.9

2.55

2.15

3.1

2.9

1.75

1.45

0.55

0.30

mm

0.05

0.1

1

0.2

0.5

2

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-01-22

02-02-08

SOT650-1

- - -

MO-229

- - -

Fig 26. Package outline SOT650-1 (HVSON10)

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

26 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

14. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

MOS devices; see JESD625-A and/or IEC61340-5.

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

15.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

27 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

15.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 27) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 29 and 30

Table 29. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 30. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 27.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

28 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 27. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

29 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

16. Revision history

Table 31. Revision history

Document ID

PCF8563_6

Release date

20080221

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCF8563_5

Modiﬁcations:

• Register names modiﬁed in Figure 1 and various tables.

• Figure 17, Figure 18 and Figure 19: corrected the unit on the vertical axis.

20070717 Product data sheet PCF8563-04

PCF8563_5

-

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Quick reference data table removed to comply with guidelines.

• Table 3: Table 3 and Table 4 combined in one table.

• Section 4: added topside mark.

• Section 4: added HVSON10 package.

PCF8563-04

(9397 750 12999)

20040312

20030414

19990416

19980325

Product data

-

PCF8563-03

PCF8563-02

PCF8563_N_1

-

PCF8563-03

(9397 750 11158)

Product data

PCF8563-02

(9397 750 04855)

Product data

PCF8563_N_1

Objective speciﬁcation

(9397 750 03282)

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

30 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

17.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

I²C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

31 of 32

PCF8563

NXP Semiconductors

Real-time clock/calendar

19. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

15.4

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 28

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

16

Revision history . . . . . . . . . . . . . . . . . . . . . . . 30

17

Legal information . . . . . . . . . . . . . . . . . . . . . . 31

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31

17.1

17.2

17.3

17.4

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

18

19

Contact information . . . . . . . . . . . . . . . . . . . . 31

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7

7.1

7.2

7.3

7.4

7.5

7.6

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.6

7.7

Functional description . . . . . . . . . . . . . . . . . . . 4

Alarm function modes. . . . . . . . . . . . . . . . . . . . 4

Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Voltage-low detector . . . . . . . . . . . . . . . . . . . . . 5

Register organization . . . . . . . . . . . . . . . . . . . . 6

Control_status_1 register . . . . . . . . . . . . . . . . . 6

Control_status_2 register . . . . . . . . . . . . . . . . . 6

Time and date registers . . . . . . . . . . . . . . . . . . 7

Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . . 9

Clock output control register. . . . . . . . . . . . . . 10

Countdown timer. . . . . . . . . . . . . . . . . . . . . . . 10

EXT_CLK test mode. . . . . . . . . . . . . . . . . . . . 11

Power-On Reset (POR) override . . . . . . . . . . 12

7.8

8

Characteristics of the I²C-bus. . . . . . . . . . . . . 13

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Start and stop conditions . . . . . . . . . . . . . . . . 13

System conﬁguration . . . . . . . . . . . . . . . . . . . 14

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 14

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 15

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Clock/calendar read/write cycles . . . . . . . . . . 15

8.1

8.2

8.3

8.4

8.5

8.5.1

8.5.2

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17

Static characteristics. . . . . . . . . . . . . . . . . . . . 17

Dynamic characteristics . . . . . . . . . . . . . . . . . 20

10

11

12

12.1

12.1.1

12.1.2

12.1.3

Application information. . . . . . . . . . . . . . . . . . 21

Quartz frequency adjustment . . . . . . . . . . . . . 22

Method 1: ﬁxed OSCI capacitor . . . . . . . . . . . 22

Method 2: OSCI trimmer. . . . . . . . . . . . . . . . . 22

Method 3: OSCO output . . . . . . . . . . . . . . . . . 22

13

14

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

Handling information. . . . . . . . . . . . . . . . . . . . 27

15

Soldering of SMD packages . . . . . . . . . . . . . . 27

Introduction to soldering . . . . . . . . . . . . . . . . . 27

Wave and reﬂow soldering . . . . . . . . . . . . . . . 27

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27

15.1

15.2

15.3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 February 2008

Document identifier: PCF8563_6


型号：	PCF8563BS/4-T
厂家：	NXP
描述：	IC,REAL-TIME CLOCK,CMOS,LLCC,10PIN,PLASTIC 光电二极管
文件：	总32页 (文件大小：167K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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