PCF8564AU/5BD/1 [NXP]
Real time clock and calendar; 实时时钟和日历
| 型号： | PCF8564AU/5BD/1 |
| 厂家： | 
NXP |
| 描述： | Real time clock and calendar |
| 文件： | 总44页 (文件大小：842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCF8564A
Real time clock and calendar
Rev. 1 — 8 October 2009
Product data sheet
1. General description
The PCF8564A is a CMOS1 real-time clock and calendar optimized for low power
consumption. A programmable clock output, interrupt output and voltage low detector are
also provided. All addresses and data are transferred serially via a two-line bidirectional
I2C-bus. Maximum bus speed is 400 kbit/s. The built-in word address register is
incremented automatically after each written or read data byte.
2. Features
I Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz quartz crystal
I Century flag
I Wide clock operating voltage: 1.0 V to 5.5 V
I Low back-up current typical 250 nA at 3.0 V and 25 °C
I 400 kHz two-wire I2C interface (1.8 V to 5.5 V)
I Low-voltage detector
I Alarm and timer functions
I Two integrated oscillator capacitors
I Programmable clock output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz and
1 Hz)
I Internal Power-On Reset (POR)
I I2C slave address: read A3h, write A2h
3. Applications
I Mobile telephones
I Portable instruments
I Electronic metering
I Battery powered products
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20.
PCF8564A
NXP Semiconductors
Real time clock and calendar
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Delivery form
Version
Die type 1[1]
PCF8564AU/5BD/1
PCF8564AU
PCF8564AU
PCF8564AU
wire bond die; 9 bonding pads
wire bond die; 9 bonding pads
wire bond die; 9 bonding pads
unsawn wafer;
thickness 280 µm
PCF8564AU
PCF8564AU
PCF8564AU
PCF8564AU/5GE/1
PCF8564AU/10AA/1
unsawn wafer;
thickness 687 µm
wafer sawn on FFC;
thickness 200 µm
Die type 2
PCF8564AU/5BB/1
PCF8564AU
PCF8564AU
PCF8564AU
wire bond die; 9 bonding pads
wire bond die; 9 bonding pads
wire bond die; 9 bonding pads
unsawn wafer;
thickness 280 µm
PCF8564AU
PCF8564AU
PCF8564AU
PCF8564AU/5GB/1
PCF8564AU/10AB/1
unsawn wafer;
thickness 687 µm
wafer sawn on FFC;
thickness 200 µm
Die type 3
PCF8564ACX9/1
PCF8564ACX9 wafer level chip-size package;
wafer sawn on FFC;
thickness 200 µm;
die with solder bumps
PCF8564ACX9
PCF8564ACX9
9 bumps; 1.27 × 1.9 × 0.29 mm
PCF8564ACX9/B/1
PCF8564ACX9 wafer level chip-size package;
tape and reel;
9 bumps; 1.27 × 1.9 × 0.29 mm
thickness 200 µm;
die with solder bumps
[1] Not to be used for new designs.
5. Marking
Table 2.
Marking codes
Type number
Marking code
Die type 1
PCF8564AU/5BD/1
PCF8564AU/5GE/1
PCF8564AU/10AA/1
Die type 2
PC8564A-1
PC8564A-1
PC8564A-1
PCF8564AU/5BB/1
PCF8564AU/5GB/1
PCF8564AU/10AB/1
Die type 3
PC8564A-1
PC8564A-1
PC8564A-1
PCF8564ACX9/1
PCF8564ACX9/B/1
PC8564A-1
PC8564A-1
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
2 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
6. Block diagram
CLKOE
OSCI
OSCILLATOR
32.768 kHz
DIVIDER
CLOCK OUT
CLKOUT
OSCO
CONTROL
Control_1
MONITOR
00h
01h
0Dh
Control_2
CLKOUT_ctrl
POWER ON
RESET
TIME
02h
03h
04h
05h
06h
07h
08h
Seconds
Minutes
Hours
VDD
VSS
Days
Weekdays
Months
Years
WATCH
DOG
ALARM FUNCTION
Minute_alarm
Hour_alarm
09h
0Ah
0Bh
0Ch
2
Day_alarm
SDA
SCL
I C
INTERFACE
Weekday_alarm
INT
INTERRUPT
TIMER FUNCTION
Timer_ctrl
0Eh
0Fh
PCF8564A
Timer
001aah660
Fig 1. Block diagram of PCF8564A
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
3 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
7. Pinning information
7.1 Pinning
CLKOE
9
8
CLKOE
9
7
OSCI
1
2
OSCI
OSCO
INT
1
2
V
8
y
DD
OSCO
V
DD
CLKOUT
y
CLKOUT
SCL
7
6
x
x
0,0
0,0
SCL
SDA
6
5
3
4
PCF8564AU
3
4
PCF8564ACX
INT
SDA
5
V
SS
V
SS
013aaa032
013aaa033
Viewed from pad side. For mechanical details, see
Figure 27.
Viewed from bump side. For mechanical details, see
Figure 28.
Fig 2. Pinning diagram of PCF8564AU
Fig 3. Pinning diagram of PCF8564ACX9
7.2 Pin description
Table 3.
Symbol
OSCI
OSCO
INT
Pin description
Pin
1
Description
oscillator input
2
oscillator output
3
interrupt output, open-drain, active LOW
ground[1]
VSS
4
SDA
5
serial data input and output
serial clock input
SCL
6
CLKOUT
VDD
7
clock output, push-pull
supply voltage
8
CLKOE
9
CLKOUT output enable
[1] The substrate (rear side of the die) is wired to VSS but should not be electrically contacted.
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
4 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
8. Functional description
The PCF8564A contains sixteen 8-bit registers with an auto-incrementing address
register, an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider
which provides the source clock for the RTC, a programmable clock output, a timer, a
voltage low detector, and a 400 kHz I2C-bus interface.
All sixteen registers (see Table 4) are designed as addressable 8-bit parallel registers
although not all bits are implemented. The first two registers (memory address 00h and
01h) are used as control and/or status registers. The addresses 02h through 08h are used
as counters for the clock function (seconds up to years counters). Address locations 09h
through 0Ch contain alarm registers which define the conditions for an alarm. Address
0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the timer control and timer
registers, respectively.
The seconds, minutes, hours, days, weekdays, months, years, as well as the minute
alarm, hour alarm, day alarm, and weekday alarm registers are all coded in BCD format.
8.1 CLKOUT output
A programmable square wave is available at the CLKOUT pin. Frequencies of 32.768 kHz,
1.024 kHz, 32 Hz and 1 Hz can be generated for use as a system clock, microcontroller
clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is a CMOS
push-pull output, and if disabled it becomes logic 0.
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
5 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
8.2 Register organization
Table 4.
Register overview
Bit positions labelled as - are not implemented. Bit positions labelled as N should always be written with logic 0. After reset, all
registers are set according to Table 27.
Address
Register name
Bit
7
6
5
4
3
2
1
0
Control registers
00h
01h
Control_1
Control_2
TEST1
N
N
N
STOP
N
N
TESTC
AF
N
N
N
TI_TP
TF
AIE
TIE
Time and date registers
02h
03h
04h
05h
06h
07h
08h
Seconds
Minutes
Hours
VL
-
SECONDS (0 to 59)
MINUTES (0 to 59)
-
-
-
-
-
HOURS (0 to 23)
DAYS (1 to 31)
Days
-
Weekdays
Months
Years
-
-
-
-
-
WEEKDAYS
C
MONTH (1 to 12)
YEARS (0 to 99)
Alarm registers
09h
0Ah
0Bh
0Ch
Minute_alarm
AE_M
AE_H
AE_D
AE_W
MINUTE_ALARM (0 to 59)
Hour_alarm
Day_alarm
-
-
-
HOUR_ALARM (0 to 23)
DAY_ALARM (1 to 31)
Weekday_alarm
-
-
-
-
-
-
-
-
-
WEEKDAY_ALARM
CLKOUT control register
0Dh CLKOUT_ctrl
Timer registers
FE
-
-
-
FD
TD
0Eh
0Fh
Timer_ctrl
Timer
TE
-
TIMER_VALUE
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
6 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
8.3 Control registers
8.3.1 Register Control_1
Table 5.
Control_1 - control and status register 1 (address 00h) bit description
Bit
Symbol
Value
Description
Reference
7
TEST1
0[1]
normal mode;
Section 8.9
• must be set to logic 0 during normal operations
EXT_CLK test mode (see Section 8.9)
default value
1
6
5
N
0[2]
0[1]
1
STOP
RTC source clock runs
Section 8.10
• RTC divider chain flip-flops are asynchronously set to logic 0
• the RTC clock is stopped (CLKOUT at 32.768 kHz is still available)
default value
4
3
N
0[2]
0
TESTC
Power-On Reset (POR) override facility is disabled;
• set to logic 0 for normal operation (see Section 8.11.1)
Power-On Reset (POR) override is enabled
default value
Section 8.11.1
1[1]
000[2]
2 to 0
N
[1] Default value.
[2] Bits labeled as N should always be written with logic 0.
8.3.2 Register Control_2
Table 6.
Bit
Control_2 - control and status register 2 (address 01h) bit description
Symbol
N
Value
000[1]
0[2]
Description
Reference
7 to 5
4
default value
TI_TP
INT is active when TF is active (subject to the status of TIE)
INT pulses active according to Table 7 (subject to the status of TIE);
1
Section 8.3.2.1
and
Section 8.8
• Remark: note that if AF and AIE are active then INT will be
permanently active
3
2
1
0
AF
0[2]
1
0[2]
alarm flag inactive
Section 8.3.2.1
Section 8.3.2.1
Section 8.3.2.1
Section 8.3.2.1
alarm flag active
TF
timer flag inactive
1
timer flag active
AIE
TIE
0[2]
1
0[2]
alarm interrupt disabled
alarm interrupt enabled
timer interrupt disabled
timer interrupt enabled
1
[1] Bits labeled as N should always be written with logic 0.
[2] Default value.
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
7 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
8.3.2.1 Interrupt output
Bits TF and AF: When an alarm occurs, AF is set to 1. Similarly, at the end of a timer
countdown, TF is set to 1. These bits maintain their value until overwritten using the
interface. If both timer and alarm interrupts are required in the application, the source of
the interrupt can be determined by reading these bits. To prevent one flag being
overwritten while clearing another, a logic AND is performed during a write access.
TI_TP
TE
E.G.AIE
to interface:
read TF
TF: TIMER
SET
TIE
0
1
COUNTDOWN COUNTER
0
1
PULSE
GENERATOR 2
CLEAR
TRIGGER
CLEAR
INT
from interface:
clear TF
AIE
to interface:
read AF
AF: ALARM
FLAG
set alarm
flag, AF
SET
CLEAR
from interface:
clear AF
013aaa087
When bits TIE and AIE are disabled, pin INT will remain high-impedance.
Fig 4. Interrupt scheme
Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when
TF or AF is asserted respectively. The interrupt is the logical OR of these two conditions
when both AIE and TIE are set.
Countdown timer interrupts: The pulse generator for the countdown timer interrupt
uses an internal clock and is dependent on the selected source clock for the countdown
timer and on the countdown value n. As a consequence, the width of the interrupt pulse
varies (see Table 7).
Table 7.
INT operation (bit TI_TP = 1)[1]
Source clock (Hz)
INT period (s)
n = 1[2]
n > 1
1
1
4096
64
⁄
⁄
8192
4096
1
1
⁄
⁄
128
64
1
1
1
⁄
⁄
64
64
1
1
1
⁄
⁄
⁄
64
60
64
[1] TF and INT become active simultaneously.
[2] n = loaded countdown value. Timer is stopped when n = 0.
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
8 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
8.4 Time and date registers
The majority of the registers are coded in the BCD format to simplify application use.
8.4.1 Register Seconds
Table 8.
Seconds - seconds and clock integrity status register (address 02h) bit
description
Bit
Symbol Value
Place value Description
7
VL
0
-
clock integrity is guaranteed
1[1]
-
integrity of the clock information is not guaranteed
actual seconds coded in BCD format, see Table 9
6 to 4 SECONDS 0 to 5
ten’s place
unit place
3 to 0
0 to 9
[1] Start-up value.
Table 9.
Seconds coded in BCD format
Seconds value in Upper-digit (ten’s place)
decimal
Digit (unit place)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
01
02
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
09
10
:
0
0
0
0
0
1
1
0
0
0
0
0
1
0
58
59
1
1
0
0
1
1
1
1
0
0
0
0
0
1
8.4.1.1 Voltage low detector and clock monitor
The PCF8564A has an on-chip voltage low detector. When VDD drops below Vlow the VL
(Voltage Low) flag is set to indicate that the integrity of the clock information is no longer
guaranteed. The VL flag can only be cleared by using the interface.
mgr887
V
DD
normal power
operation
period of battery
operation
V
low
t
VL set
Fig 5. Voltage low detection
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
9 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
The VL flag is intended to detect the situation when VDD is decreasing slowly, for example
under battery operation. Should the oscillator stop or VDD reach Vlow before power is
re-asserted, then the VL flag will be set. This indicates that the time is possibly corrupted.
8.4.2 Register Minutes
Table 10. Minutes - minutes register (address 03h) bit description
Bit
Symbol
Value
Place value Description
7
-
-
-
unused
6 to 4 MINUTES 0 to 5
ten’s place
unit place
actual minutes coded in BCD format
3 to 0
0 to 9
8.4.3 Register Hours
Table 11. Hours - hours register (address 04h) bit description
Bit
Symbol
Value
-
Place value Description
7 to 6 -
-
unused
5 to 4 HOURS
3 to 0
0 to 2
0 to 9
ten’s place
unit place
actual hours coded in BCD format
8.4.4 Register Days
Table 12. Days - days register (address 05h) bit description
Bit
Symbol
Value
-
Place value Description
7 to 6 -
-
unused
5 to 4 DAYS[1]
0 to 3
0 to 9
ten’s place
unit place
actual day coded in BCD format
3 to 0
[1] The PCF8564A compensates for leap years by adding a 29th day to February if the year counter contains a
value which is exactly divisible by 4, including the year 00.
8.4.5 Register Weekdays
Table 13. Weekdays - weekdays register (address 06h) bit description
Bit
Symbol
Value
-
Description
7 to 3 -
unused
2 to 0 WEEKDAYS
0 to 6
actual weekday values, see Table 14
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
10 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
Table 14. Weekday assignments
Day[1]
Bit
2
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
Sunday
0
Monday
Tuesday
Wednesday
Thursday
Friday
0
0
0
1
1
Saturday
1
[1] Definition may be re-assigned by the user.
8.4.6 Register Months
Table 15. Months - months and century flag register (address 07h) bit description
Bit
Symbol
Value
Place value Description
7
C[1]
0[2]
-
indicates the century is x
1
-
indicates the century is x + 1
unused
6 to 5 -
-
-
4
MONTHS 0 to 1
0 to 9
ten’s place
unit place
actual month coded in BCD format, see Table 16
3 to 0
[1] This bit may be re-assigned by the user.
[2] This bit is toggled when the register Years overflows from 99 to 00.
Table 16. Month assignments coded in BCD format
Month
Upper-digit
(ten’s place)
Digit (unit place)
Bit 4
0
Bit 3
0
Bit 2
Bit 1
0
Bit 0
1
January
February
March
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
April
0
0
0
0
May
0
0
0
1
June
0
0
1
0
July
0
0
1
1
August
September
October
November
December
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
11 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
8.4.7 Register Years
Table 17. Years - years register (08h) bit description
Bit
Symbol
Value
0 to 9
0 to 9
Place value Description
ten’s place actual year coded in BCD format[1]
7 to 4 YEARS
3 to 0
unit place
[1] When the register Years overflows from 99 to 00, the century bit C in the register Months is toggled.
The PCF8564A compensates for leap years by adding a 29th day to February if the year
counter contains a value which is divisible by 4, including the year 00.
8.5 Setting and reading the time
Figure 6 shows the data flow and data dependencies starting from the 1 Hz clock tick.
1 Hz tick
SECONDS
MINUTES
HOURS
LEAP YEAR
CALCULATION
DAYS
MONTHS
YEARS
C
WEEKDAY
013aaa092
Fig 6. Data flow for the time function
During read/write operations, the time counting circuits (memory locations 02h through
08h) are blocked.
This prevents
• Faulty reading of the clock and calendar during a carry condition
• Incrementing the time registers, during the read cycle
After this read/write access is completed, the time circuit is released again and any
pending request to increment the time counters, that occurred during the read access, is
serviced. A maximum of 1 request can be stored; therefore, all accesses must be
completed within 1 second (see Figure 7).
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
12 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
t < 1 s
START
slave address
data data data
STOP
013aaa215
Fig 7. Access time for read/write operations
As a consequence of this method, it is very important to make a read or write access in
one go, that is, setting or reading seconds through to years should be made in one single
access. Failing to comply with this method could result in the time becoming corrupted.
As an example, if the time (seconds through to hours) is set in one access and then in a
second access the date is set, it is possible that the time may increment between the two
accesses. A similar problem exists when reading. A roll over may occur between reads
thus giving the minutes from one moment and the hours from the next.
Recommended method for reading the time:
1. Send a START condition and the slave address for write (A2h).
2. Set the address pointer to 2 (seconds) by sending 02h.
3. Send a RE-START condition or STOP followed by START.
4. Send the slave address for read (A3h).
5. Read the seconds.
6. Read the minutes.
7. Read the hours.
8. Read the days.
9. Read the weekdays.
10. Read the century and month.
11. Read the years.
12. Send a STOP condition.
8.6 Alarm registers
8.6.1 Register Minute_alarm
Table 18. Minute_alarm - minute alarm register (address 09h) bit description
Bit
Symbol
Value
Place value Description
7
AE_M
0
1[1]
-
-
minute alarm is enabled
minute alarm is disabled
6 to 4 MINUTE_ALARM
3 to 0
0 to 5
0 to 9
ten’s place minute alarm information coded in BCD
format
unit place
[1] Default value.
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
13 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
8.6.2 Register Hour_alarm
Table 19. Hour_alarm - hour alarm register (address 0Ah) bit description
Bit
Symbol
Value
Place value Description
7
AE_H
0
1[1]
-
-
-
hour alarm is enabled
hour alarm is disabled
unused
6
-
-
5 to 4 HOUR_ALARM
3 to 0
0 to 2
0 to 9
ten’s place hour alarm information coded in BCD
format
unit place
[1] Default value.
8.6.3 Register Day_alarm
Table 20. Day_alarm - day alarm register (address 0Bh) bit description
Bit
Symbol
Value
Place value Description
7
AE_D
0
1[1]
-
-
-
day alarm is enabled
day alarm is disabled
unused
6
-
-
5 to 4 DAY_ALARM
3 to 0
0 to 3
0 to 9
ten’s place day alarm information coded in BCD
format
unit place
[1] Default value.
8.6.4 Register Weekday_alarm
Table 21. Weekday_alarm - weekday alarm register (address 0Ch) bit description
Bit
Symbol
Value
Description
7
AE_W
0
1[1]
weekday alarm is enabled
weekday alarm is disabled
unused
6 to 3 -
-
2 to 0 WEEKDAY_ALARM 0 to 6
[1] Default value.
weekday alarm information coded in BCD format
8.6.5 Alarm flag
By clearing the MSB of one or more of the alarm registers AE_x (Alarm Enable), the
corresponding alarm condition(s) are active. When an alarm occurs, AF is set to logic 1.
The asserted AF can be used to generate an interrupt (INT). The AF is cleared using the
interface.
The registers at addresses 09h through 0Ch contain alarm information. When one or
more of these registers is loaded with a valid minute, hour, day or weekday and its
corresponding Alarm Enable bit (AE_x) is logic 0, then that information is compared with
the current minute, hour, day and weekday. When all enabled comparisons first match, the
Alarm Flag (AF in register Control_2) is set to logic 1.
PCF8564A_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 8 October 2009
14 of 44
PCF8564A
NXP Semiconductors
Real time clock and calendar
The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is
enabled, the INT pin follows the condition of bit AF. AF will remain set until cleared by the
interface. Once AF has been cleared it will only be set again when the time increments to
match the alarm condition once more. Alarm registers which have their AE_x bit at logic 1
are ignored.
check now signal
example
AE_M
AE_M= 1
MINUTE ALARM
=
1
MINUTE TIME
0
AE_H
HOUR ALARM
=
HOUR TIME
(1)
set alarm flag, AF
AE_D
DAY ALARM
=
DAY TIME
AE_W
WEEKDAY ALARM
=
013aaa088
WEEKDAY TIME
(1) Only when all enabled alarm settings are matching.
It’s only on increment to a matched case that the alarm flag is set, see Section 8.6.5.
Fig 8. Alarm function block diagram
8.7 Register CLKOUT_ctrl and clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
FE bit in register CLKOUT_ctrl at address 0Dh and the CLKOUT output enable pin
(CLKOE). To enable pin CLKOUT pin CLKOE must be set HIGH.
Frequencies of 32.768 kHz (default), 1.024 kHz, 32 Hz and 1 Hz can be generated for use
as a system clock, microcontroller clock, input to a charge pump, or for calibration of the
oscillator.
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Real time clock and calendar
Table 22. CLKOUT_ctrl - CLKOUT control register (address 0Dh) bit description
Bit
Symbol
Value
Description
7
FE
0
the CLKOUT output is inhibited and CLKOUT output is
set to logic 0
1[1]
-
the CLKOUT output is activated
6 to 2 -
unused
1 to 0 FD[1:0]
frequency output at pin CLKOUT
00[1]
01
32.768 kHz
1.024 kHz
32 Hz
10
11
1 Hz
[1] Default value.
8.8 Timer function
The 8-bit countdown timer at address 0Fh is controlled by the timer control register at
address 0Eh. The timer control register determines one of 4 source clock frequencies for
the timer (4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz) and enables or disables the timer. The timer
counts down from a software-loaded 8-bit binary value. At the end of every countdown,
the timer sets the TF (Timer Flag) to logic 1. The TF may only be cleared using the
interface.
The generation of interrupts from the timer function is controlled via bit TIE. If bit TIE is
enabled the INT pin follows the condition of bit TF. The interrupt may be generated as a
pulsed signal every countdown period or as a permanently active signal which follows the
condition of the timer flag TF. TI_TP is used for this mode control. When reading the timer,
the current countdown value is returned.
8.8.1 Register Timer_ctrl
Table 23. Timer_ctrl - timer control register (address 0Eh) bit description
Bit
Symbol
Value
Description
7
TE
0[1]
timer is disabled
timer is enabled
unused
1
6 to 2 -
-
1 to 0 TD[1:0]
timer source clock frequency select[2]
00
4.096 kHz
01
64 Hz
10
1 Hz
1
11[2]
⁄60 Hz
[1] Default value.
[2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to
1
⁄
60 Hz for power saving.
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Real time clock and calendar
8.8.2 Register Timer
Table 24. Timer - timer register (address 0Fh) bit description
Bit Symbol Value Description
7 to 0 TIMER_VALUE[7:0] 00h to FFh countdown value = n;
n
CountdownPeriod =
--------------------------------------------------------------
SourceClockFrequency
Table 25. Timer register bits value range
Bit
7
6
5
4
3
2
1
0
128
64
32
16
8
4
2
1
The timer register is an 8-bit binary countdown timer. It is enabled or disabled via the timer
control register. The source clock for the timer is also selected by the timer control
register. Other timer properties such as single or periodic interrupt generation are
controlled via the register Control_2 (address 01h).
For accurate read back of the count down value, the I2C-bus clock (SDA) must be
operating at a frequency of at least twice the selected timer clock. Since it is not possible
to freeze the countdown timer counter during read back, it is recommended to read the
register twice and check for consistent results.
8.9 EXT_CLK test mode
The test mode is entered by setting the TEST1 bit of register Control_1 to logic 1. The
CLKOUT pin then becomes an input. The test mode replaces the internal 64 Hz signal
with that applied to the CLKOUT pin. Every 64 positive edges applied to CLKOUT then
generates an increment of one second.
The signal applied to the CLKOUT pin should have a minimum pulse width of 300 ns and
a maximum period of 1000 ns. The 64 Hz clock, now sourced from CLKOUT, is divided
down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set to a known
state by using the STOP bit. When the STOP bit is set, the prescaler is reset to logic 0.
(STOP must be cleared before the prescaler can operate.)
From a STOP condition, the first 1 second increment will take place after 32 positive
edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.
When entering the test mode, no assumption as to the state of the prescaler can be
made.
8.9.1 Operation example
1. Set EXT_CLK test mode (Bit 7 Control_1 = 1).
2. Set STOP (Bit 5 Control_1 = 1).
3. Clear STOP (Bit 5 Control_1 = 0).
4. Set time registers to desired value.
5. Apply 32 clock pulses to CLKOUT.
6. Read time registers to see the first change.
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Real time clock and calendar
7. Apply 64 clock pulses to CLKOUT.
8. Read time registers to see the second change.
Repeat 7 and 8 for additional increments.
8.10 STOP bit function
The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP
bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and
thus no 1 Hz ticks will be generated (see Figure 9). The time circuits can then be set and
will not increment until the STOP bit is released (see Figure 10 and Table 26).
OSC STOP
reset
DETECTOR
F
F
F
F
F
14
0
1
2
13
OSC
1 Hz tick
stop
RES
RES
RES
1 Hz
32 Hz
CLKOUT source
1024 Hz
32768 Hz
013aaa089
Fig 9. STOP bit functional diagram
The STOP bit function will not affect the output of 32.768 kHz on CLKOUT, but will stop
the generation of 1.024 kHz, 32 Hz and 1 Hz.
The lower two stages of the prescaler (F0 and F1) are not reset and because the I2C-bus
is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be
between zero and one 8.192 kHz cycle (see Figure 10).
8192 Hz
stop released
0 µs to 122 µs
001aaf912
Fig 10. STOP bit release timing
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PCF8564A
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Real time clock and calendar
Table 26. First increment of time circuits after STOP bit release
[1]
Bit
Prescaler bits
F0F1-F2 to F14
1 Hz tick
Time
Comment
STOP
hh:mm:ss
Clock is running normally
0
01-0 0001 1101 0100
12:45:12
prescaler counting normally
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally
1
XX-0 0000 0000 0000
12:45:12
prescaler is reset; time circuits are frozen
New time is set by user
1
XX-0 0000 0000 0000
08:00:00
prescaler is reset; time circuits are frozen
STOP bit is released by user
0
XX-0 0000 0000 0000
XX-1 0000 0000 0000
XX-0 1000 0000 0000
XX-1 1000 0000 0000
:
08:00:00
08:00:00
08:00:00
08:00:00
:
prescaler is now running
-
-
-
:
11-1 1111 1111 1110
00-0 0000 0000 0001
10-0 0000 0000 0001
:
08:00:00
08:00:01
08:00:01
:
-
0 to 1 transition of F14 increments the time circuits
-
:
11-1 1111 1111 1111
00-0 0000 0000 0000
10-0 0000 0000 0000
:
08:00:01
08:00:01
08:00:01
:
-
-
-
-
11-1 1111 1111 1110
00-0 0000 0000 0001
08:00:01
08:00:02
-
0 to 1 transition of F14 increments the time circuits
013aaa076
[1] F0 is clocked at 32.768 kHz.
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP
bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset
(see Table 26) and the unknown state of the 32 kHz clock.
8.11 Reset
The PCF8564A includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I2C-bus logic is initialized including the address pointer and
all registers are set according to Table 27. I2C-bus communication is not possible during
reset.
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Real time clock and calendar
Table 27. Register reset values[1]
Address Register name
Bit
7
0
0
1
x
6
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
0
x
x
x
x
x
x
x
x
x
x
x
0
1
x
0
0
0
x
x
x
x
x
x
x
x
x
x
x
0
1
x
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Control_1
Control_2
Seconds
Minutes
Hours
x
Days
x
Weekdays
Months
x
x
Years
x
Minute_alarm
Hour_alarm
Day_alarm
Weekday_alarm
CLKOUT_ctrl
Timer_ctrl
Timer
1
1
1
1
1
0
x
[1] Registers marked ‘x’ are undefined at power-on and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a circuit has been implemented to
disable the POR and speed up functional test of the module. The setting of this mode
requires that the I2C signals on the pins SDA and SCL are toggled as illustrated in
Figure 11. All timings shown are required minimums.
Once the override mode has been entered, the chip immediately stops, being reset, and
normal operation may begin, i.e., entry into the EXT_CLK test mode via I2C access. The
override mode may be cleared by writing logic 0 to TESTC. TESTC must be set to logic 1
before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal
operation has no effect, except to prevent entry into the POR override mode.
500 ns
2000 ns
SDA
SCL
8 ms
power up
mgm664
override active
Allow 500 ns between the edges of either signal.
Fig 11. POR override sequence
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PCF8564A
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Real time clock and calendar
9. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 12).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mbc621
Fig 12. Bit transfer
9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the STOP
condition (P), see Figure 13.
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 13. Definition of START and STOP conditions
9.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see Figure 14).
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PCF8564A
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Real time clock and calendar
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
mba605
Fig 14. System configuration
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 15.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 15. Acknowledgment on the I2C-bus
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Real time clock and calendar
10. I2C-bus protocol
10.1 Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the start procedure.
The PCF8564A acts as a slave receiver or slave transmitter. Therefore, the clock signal
SCL is only an input signal, but the data signal SDA is a bidirectional line.
Two slave addresses are reserved for the PCF8564A:
Read: A3h (10100011)
Write: A2h (10100010)
The PCF8564A slave address is shown in Figure 15.
1
0
1
0
0
0
1
R/W
group 2
group 1
mce189
Fig 16. Slave address
10.2 Clock and calendar READ or WRITE cycles
Figure 17, Figure 18, and Figure 19 show the I2C-bus configuration for the different
PCF8564A READ and WRITE cycles. The word address is a 4-bit value that defines
which register is to be accessed next. The upper four bits of the word address are not
used.
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
S
SLAVE ADDRESS
0
A
WORD ADDRESS
A
DATA
A
P
R/W
n bytes
auto increment
memory word address
mbd822
Fig 17. Master transmits to slave receiver (WRITE mode)
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PCF8564A
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Real time clock and calendar
acknowledgement
from master
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
DATA
S
SLAVE ADDRESS
0
A
WORD ADDRESS
A
S
SLAVE ADDRESS
1
A
A
n bytes
R/W
R/W
at this moment master transmitter
becomes master receiver and
PCF8564A slave receiver
auto increment
memory word address
becomes slave transmitter
no acknowledgement
from master
1
P
DATA
last byte
auto increment
memory word address
013aaa034
Fig 18. Master reads word after setting word address (write word address; READ data)
acknowledgement
from slave
acknowledgement
from master
no acknowledgement
from master
1
A
A
DATA
1
P
S
SLAVE ADDRESS
DATA
R/W
n bytes
last byte
auto increment
word address
auto increment
word address
mgl665
Fig 19. Master reads slave immediately after first byte (READ mode)
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Real time clock and calendar
11. Internal circuitry
CLKOE
OSCI
V
DD
OSCO
CLKOUT
SCL
INT
V
SS
SDA
PCF8564A
013aaa035
Fig 20. Device diode protection diagram
12. Limiting values
Table 28. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
+6.5
+6.5
+6.5
+50.0
+10.0
+10.0
+50.0
300
Unit
V
VDD
VI
supply voltage
−0.5
−0.5
−0.5
−50.0
−10.0
−10.0
−50.0
-
input voltage
V
VO
IDD
II
output voltage
V
supply current
mA
mA
mA
mA
mW
°C
input current
IO
output current
ISS
Ptot
Tamb
VESD
ground supply current
total power dissipation
ambient temperature
−40.0
+85
[1]
[2]
electrostatic discharge voltage HBM
die type 1 and 3
die type 2
MM
-
-
±2500
±3500
V
V
die type 1 and 3
die type 2
-
±200
±250
100
V
-
V
[3]
[4]
latch-up current
all pins but OSCI
-
mA
°C
Ilu
Tstg
storage temperature
−65.0
+150
[1] Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.
[2] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.
[3] Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature
(Tamb(max) = +85 °C).
[4] According to the NXP store and transport conditions (see Ref. 10 “SNW-SQ-623”) the devices have to be
stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.
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Real time clock and calendar
13. Static characteristics
Table 29. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 40 kΩ; CL = 8 pF; unless otherwise
specified.
Symbol
Supplies
VDD
Parameter
Conditions
Min
Typ
Max
Unit
[1]
[1]
supply voltage
interface inactive;
1.0
1.8
Vlow
-
-
-
5.5
5.5
5.5
V
V
V
T
amb = 25 °C
interface active;
SCL = 400 kHz
for clock data integrity;
amb = 25 °C
f
T
IDD
supply current
interface active
fSCL = 400 kHz
fSCL = 100 kHz
-
-
-
-
800
200
µA
µA
[2] [3]
[4]
interface inactive (fSCL = 0 Hz);
CLKOUT disabled;
T
amb = 25 °C
VDD = 5.0 V
VDD = 3.0 V
VDD = 2.0 V
-
-
-
275
250
225
550
500
450
nA
nA
nA
[2] [3]
[4]
interface inactive (fSCL = 0 Hz);
CLKOUT disabled;
T
amb = −40 °C to +85 °C
VDD = 5.0 V
-
-
-
500
400
400
750
650
600
nA
nA
nA
VDD = 3.0 V
VDD = 2.0 V
[4] [5]
[6]
interface inactive (fSCL = 0 Hz);
CLKOUT enabled at 32 kHz;
T
amb = 25 °C
VDD = 5.0 V
VDD = 3.0 V
VDD = 2.0 V
-
-
-
1500
1000
700
3000
2000
1400
nA
nA
nA
[4] [5]
[6]
interface inactive (fSCL = 0 Hz);
CLKOUT enabled at 32 kHz;
T
amb = −40 °C to +85 °C
VDD = 5.0 V
-
-
-
1700
1100
800
3400
2200
1600
nA
nA
nA
VDD = 3.0 V
VDD = 2.0 V
Inputs
VI
input voltage
on pins SDA and SCL
−0.5
−0.5
-
-
+5.5
V
on pins CLKOE and CLKOUT
(test mode)
VDD + 0.5 V
VIL
LOW-level input voltage
-
-
0.3VDD
V
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PCF8564A
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Real time clock and calendar
Table 29. Static characteristics …continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 40 kΩ; CL = 8 pF; unless otherwise
specified.
Symbol
VIH
Parameter
Conditions
Min
Typ
Max
-
Unit
V
HIGH-level input voltage
input leakage current
input capacitance
0.7VDD
-
ILI
VI = VDD or VSS
−1
0
-
+1
7
µA
pF
[7]
Ci
-
Outputs
VO
output voltage
on pin CLKOUT
on pin INT
−0.5
−0.5
3
-
-
-
VDD + 0.5 V
+5.5
-
V
IOL
LOW-level output current on pin SDA;
mA
VOL = 0.4 V; VDD = 5 V
on pin INT;
−1
−1
1
-
-
mA
mA
mA
µA
VOL = 0.4 V; VDD = 5 V
on pin CLKOUT:
VOL = 0.4 V; VDD = 5 V
-
-
IOH
HIGH-level output current on pin CLKOUT;
OH = 4.6 V; VDD = 5 V
-
-
V
ILO
Voltage detector
Vlow low voltage
output leakage current
VO = VDD or VSS
−1
0
+1
Tamb = 25 °C
-
0.9
1.0
V
[1] For reliable oscillator start-up at power-on: VDD(po)min = VDD(min) + 0.3 V.
[2] Timer source clock = 1⁄60 Hz.
[3] CLKOUT disabled (FE = 0 or CLKOE = 0).
[4] VIL and VIH with an input voltage swing of VSS to VDD
.
[5] CLKOUT is open circuit.
[6] Current consumption when the CLKOUT pin is enabled is a function of the load on the pin, the output frequency, and the supply voltage.
The additional current consumption for a given load is calculated from: IDD = C × V DD × FCLKOUT
.
[7] Tested on sample basis.
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PCF8564A
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Real time clock and calendar
mgr888
mgr889
1
1
I
I
DD
DD
(µA)
(µA)
0.8
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
0
2
4
6
0
2
4
6
V
DD
(V)
V
DD
(V)
Tamb = 25 °C; timer = 1 minute; CLKOUT disabled.
Tamb = 25 °C; timer = 1 minute; CLKOUT = 32 kHz.
Fig 21. IDD as a function of VDD
Fig 22. IDD as a function of VDD
mgr891
mgr890
1
I
DD
4
(µA)
frequency
deviation
0.8
(ppm)
2
0.6
0.4
0.2
0
0
−2
−4
−40
0
40
80
120
0
2
4
6
V
DD
(V)
T (°C)
VDD = 3 V; timer = 1 minute; CLKOUT = 32 kHz.
Tamb = 25 °C; normalized to VDD = 3 V.
Fig 23. IDD as a function of T
Fig 24. Frequency deviation as a function of VDD
PCF8564A_1
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PCF8564A
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Real time clock and calendar
14. Dynamic characteristics
Table 30. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 40 kΩ; CL = 8 pF; unless otherwise
specified.
Symbol
Oscillator
CL(itg)
Parameter
Conditions
Min
Typ
Max
Unit
[1]
integrated load capacitance
6
-
8
10
-
pF
∆fosc/fosc
relative oscillator frequency variation
∆VDD = 200 mV;
0.2
ppm
T
amb = 25 °C
Quartz crystal parameters
Rs
CL
series resistance
load capacitance
-
-
-
100
-
kΩ
8
pF
CLKOUT output
[2]
δCLKOUT
duty cycle on pin CLKOUT
-
50
-
%
I2C-bus timing characteristics (see Figure 25)[3][4]
fSCL
SCL clock frequency
-
-
-
-
400
kHz
µs
tHD;STA
tSU;STA
hold time (repeated) START condition
0.6
0.6
-
-
set-up time for a repeated START
condition
µs
tLOW
tHIGH
tr
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
data set-up time
1.3
0.6
-
-
-
-
-
-
-
-
-
-
-
µs
µs
µs
µs
pF
ns
ns
µs
ns
-
0.3
0.3
400
-
tf
-
Cb
-
tSU;DAT
tHD;DAT
tSU;STO
tw(spike)
100
0
data hold time
-
set-up time for STOP condition
spike pulse width
0.6
-
-
50
(COSCI COSCO
)
[1] Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: CL(itg)
=
.
--------------------------------------------
(COSCI + COSCO
)
[2] Unspecified for fCLKOUT = 32.768 kHz.
[3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage
swing of VSS to VDD
.
[4] A detailed description of the I2C-bus specification is given in Ref. 11 “UM10204”.
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PCF8564A
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Real time clock and calendar
SDA
t
t
t
f
BUF
LOW
SCL
SDA
t
HD;STA
t
t
t
SU;DAT
r
HD;DAT
t
HIGH
t
SU;STA
t
SU;STO
mga728
Fig 25. I2C-bus timing waveforms
15. Application information
V
DD
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
1 F
V
DD
SCL
SDA
CLOCK/CALENDAR
OSCI
PCF8564A
V
DD
OSCO
V
SS
R
R
SDA SCL
2
013aaa193
(I C-bus)
Fig 26. Application diagram
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PCF8564A
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Real time clock and calendar
16. Bare die outline
Wire bond die; 9 bonding pads
PCF8564AU
D
e
A
e
1
y
e
2
E
x
0,0
X
(2)
P
P
1
2
P
P
4
3
Dimensions Die type 1
(3)
(1)
(1)
Unit
max
A
D
E
e
e
1
e
2
P
P
P
P
4
1
2
3
detail X
mm nom 0.2 1.27 1.9 1.05 0.22 0.9 0.1 0.09 0.1 0.09
min
Dimensions Die type 2
(3)
(1)
(1)
Unit
max
A
D
E
e
e
1
e
2
P
P
P
P
4
1
2
3
0
0.5
1 mm
scale
mm nom 0.2 1.26 1.89 1.05 0.22 0.9 0.1 0.09 0.1 0.09
min
Note
1. Chip dimensions including sawline.
2. Marking code: PC8564A-1
3. Dimension depending on delivery form
pcf8564au_do
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
09-08-25
09-09-10
PCF8564AU
Fig 27. Bare die outline of PCF8564AU
PCF8564A_1
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Real time clock and calendar
Table 31. Bonding pad description for all PCF8564AU types
All x/y coordinates represent the position of the center of each pad with respect to the center
(x/y = 0) of the chip; see Figure 27.
Symbol
OSCI
OSCO
INT
Pad
1
X (µm)
−523.0
−523.0
−523.0
−523.0
524.9
Y (µm)
689.4
Description
oscillator input
2
469.4
oscillator output
3
−429.8
−684.4
−523.8
−138.6
162.5
open-drain interrupt output (active LOW)
ground (substrate)
serial data I/O
VSS
4
SDA
5
SCL
6
524.9
serial clock input
CLKOUT
VDD
7
524.9
CMOS push-pull clock output
supply
8
524.9
443.3
CLKOE
9
524.9
716.3
CLKOUT output enable
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PCF8564A
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Real time clock and calendar
WLCSP9: wafer level chip-size package; 9 bumps; 1.27 x 1.9 x 0.29 mm
PCF8564ACX9
D
e
b
e
2
y
X
A
2
E
A
e
1
x
0,0
A
1
detail X
(2)
Dimensions
(1)
(1)
Unit
max
A
A
A
b
D
E
e
e
1
e
2
1
2
mm nom 0.29 0.09 0.2 0.2 1.27 1.9 0.73 0.45 0.27
min
0
0.5
1 mm
scale
Note
1. Chip dimensions including sawline.
2. Marking code: PC8564A-1
pcf8564acx9_po
Issue date
References
Outline
European
projection
version
IEC
JEDEC
JEITA
09-08-25
09-09-09
PCF8564ACX9
Fig 28. Bare die outline of PCF8564ACX9
Table 32. Solder bump description for all PCF8564ACX types
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip; see Figure 28.
Symbol
OSCI
OSCO
INT
Bump
X (µm)
−368
−368
−368
−368
362
Y (µm)
738
Description
1
2
3
4
5
6
7
8
9
oscillator input
188
oscillator output
−262
−712
−712
−262
188
open-drain interrupt output (active LOW)
ground (substrate)
serial data I/O
VSS
SDA
SCL
362
serial clock input
CLKOUT
VDD
362
CMOS push-pull clock output
supply
0
456
CLKOE
362
738
CLKOUT output enable
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Product data sheet
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PCF8564A
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Real time clock and calendar
REF
REF
C2
C1
013aaa036
REF
F
Fig 29. Alignment marks of all PCF8564A types
Table 33. Alignment marks of all PCF8564A types
All x/y coordinates represent the position of the REF point (see Figure 29) with respect to the center
(x/y = 0) of the chip; see Figure 27 and Figure 28.
Alignment markers
Size (µm)
100 × 100
100 × 100
90 × 117
X (µm)
465.2
Y (µm)
−826.3
890.0
C1
C2
F
−523.0
−569.9
−885.5
17. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent
standards.
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Real time clock and calendar
18. Packing information
18.1 Wafer and FFC information
18 µm
18 µm
die type 1 = 84 µm
die type 2 = 74 µm
Saw lane
Seal ring plus gap to
active circuit ~18 µm
die type 1 = 84 µm
die type 2 = 74 µm
detail X
Marking code
Pin 1
Straight edge
of the wafer
X
013aaa037
Wafer thickness, see Table 1.
Fig 30. Wafer layout of PCF8564AU
PCF8564A_1
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Real time clock and calendar
18 µm
18 µm
84 µm
Saw lane
Seal ring plus gap to
active circuit ~18 µm
84 µm
detail X
Marking code
Pin 1
Straight edge
of the wafer
X
013aaa192
Wafer thickness, see Table 1.
Fig 31. Wafer layout of PCF8564ACX9
PCF8564A_1
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Real time clock and calendar
18.2 Tape and reel information
4 mm
A0
K0
W
B0
P1
direction of feed
013aaa202
Fig 32. Tape and reel details for PCF8564ACX9/B/1
Table 34. Tape and reel dimensions [1]
Dimension
Description
tape width
Value
W
8 mm
A0
B0
K0
P1
pocket length
pocket width
pocket depth
pocket pitch
1.5 mm
2.2 mm
0.25 mm
4 mm
[1] Die is placed in pocket bump side down.
013aaa191
pin 1
Transparent top view. The orientation of the IC in a pocket is indicated by the position of pin 1, with
respect to the sprocket holes.
Fig 33. Pin 1 indication for PCF8564ACX9/B/1
19. Soldering of WLCSP packages
19.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
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Real time clock and calendar
All NXP WLCSP packages are lead-free.
19.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
19.3 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 34) than a PbSn process, thus
reducing the process window
• Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 35.
Table 35. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
260
> 2000
260
< 1.6
1.6 to 2.5
> 2.5
260
250
245
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 34.
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PCF8564A
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Real time clock and calendar
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 34. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
19.3.1 Stand off
The stand off between the substrate and the chip is determined by:
• The amount of printed solder on the substrate
• The size of the solder land on the substrate
• The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
19.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
19.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
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PCF8564A
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Real time clock and calendar
Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on the solder lands. Apply flux on the bumps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
19.3.4 Cleaning
Cleaning can be done after reflow soldering.
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PCF8564A
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Real time clock and calendar
20. Abbreviations
Table 36. Abbreviations
Acronym
BCD
CMOS
FFC
Description
Binary Coded Decimal
Complementary Metal Oxide Semiconductor
Film Frame Carrier
HBM
I2C
Human Body Model
Inter-Integrated Circuit
Integrated Circuit
IC
LSB
Least Significant Bit
Machine Model
MM
MOS
MSB
MSL
PCB
POR
ROM
RTC
Metal Oxide Semiconductor
Most Significant Bit
Moisture Sensitivity Level
Printed-Circuit Board
Power-On Reset
Read Only Memory
Real Time Clock
SCL
Serial Clock Line
SDA
Serial Data Line
SRAM
WLCSP
Static Random Access Memory
Wafer Level Chip-Size Package
21. References
[1] AN10365 — Surface mount reflow soldering description
[2] AN10706 — Handling bare die
[3] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[5] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[8] JESD78 — IC Latch-Up Test
[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[10] SNW-SQ-623 — NXP store and transport conditions
[11] UM10204 — I2C-bus specification and user manual
PCF8564A_1
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PCF8564A
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Real time clock and calendar
22. Revision history
Table 37. Revision history
Document ID
Release date
20091008
Data sheet status
Change notice
Supersedes
PCF8564A_1
Product data sheet
-
-
PCF8564A_1
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PCF8564A
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Real time clock and calendar
23. Legal information
23.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Limiting values — Stress above one or more limiting values (as defined in
23.2 Definitions
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
23.3 Disclaimers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
23.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
I2C-bus — logo is a trademark of NXP B.V.
24. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF8564A_1
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Product data sheet
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PCF8564A
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Real time clock and calendar
25. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
10
10.1
10.2
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock and calendar READ or WRITE cycles . 23
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
11
12
13
14
15
16
17
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 25
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25
Static characteristics . . . . . . . . . . . . . . . . . . . 26
Dynamic characteristics. . . . . . . . . . . . . . . . . 29
Application information . . . . . . . . . . . . . . . . . 30
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 31
Handling information . . . . . . . . . . . . . . . . . . . 34
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
Functional description . . . . . . . . . . . . . . . . . . . 5
CLKOUT output . . . . . . . . . . . . . . . . . . . . . . . . 5
Register organization . . . . . . . . . . . . . . . . . . . . 6
Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7
Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 7
Register Control_2 . . . . . . . . . . . . . . . . . . . . . . 7
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8
Time and date registers . . . . . . . . . . . . . . . . . . 9
Register Seconds . . . . . . . . . . . . . . . . . . . . . . . 9
Voltage low detector and clock monitor . . . . . . 9
Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 10
Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 10
Register Days . . . . . . . . . . . . . . . . . . . . . . . . . 10
Register Weekdays. . . . . . . . . . . . . . . . . . . . . 10
Register Months . . . . . . . . . . . . . . . . . . . . . . . 11
Register Years . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting and reading the time. . . . . . . . . . . . . . 12
Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 13
Register Minute_alarm . . . . . . . . . . . . . . . . . . 13
Register Hour_alarm . . . . . . . . . . . . . . . . . . . 14
Register Day_alarm . . . . . . . . . . . . . . . . . . . . 14
Register Weekday_alarm . . . . . . . . . . . . . . . . 14
Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register CLKOUT_ctrl and clock output. . . . . 15
Timer function. . . . . . . . . . . . . . . . . . . . . . . . . 16
Register Timer_ctrl . . . . . . . . . . . . . . . . . . . . . 16
Register Timer . . . . . . . . . . . . . . . . . . . . . . . . 17
EXT_CLK test mode. . . . . . . . . . . . . . . . . . . . 17
Operation example . . . . . . . . . . . . . . . . . . . . . 17
STOP bit function . . . . . . . . . . . . . . . . . . . . . . 18
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power-On Reset (POR) override . . . . . . . . . . 20
8.1
8.2
8.3
18
18.1
18.2
Packing information . . . . . . . . . . . . . . . . . . . . 35
Wafer and FFC information . . . . . . . . . . . . . . 35
Tape and reel information. . . . . . . . . . . . . . . . 37
8.3.1
8.3.2
8.3.2.1
8.4
8.4.1
8.4.1.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.5
19
19.1
19.2
19.3
19.3.1
19.3.2
19.3.3
19.3.4
Soldering of WLCSP packages . . . . . . . . . . . 37
Introduction to soldering WLCSP packages. . 37
Board mounting . . . . . . . . . . . . . . . . . . . . . . . 38
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 38
Stand off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Quality of solder joint . . . . . . . . . . . . . . . . . . . 39
Rework. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Cleaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
20
21
22
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Revision history . . . . . . . . . . . . . . . . . . . . . . . 42
23
Legal information . . . . . . . . . . . . . . . . . . . . . . 43
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.6
23.1
23.2
23.3
23.4
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.7
24
25
Contact information . . . . . . . . . . . . . . . . . . . . 43
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.8
8.8.1
8.8.2
8.9
8.9.1
8.10
8.11
8.11.1
9
Characteristics of the I2C-bus. . . . . . . . . . . . . 21
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
START and STOP conditions . . . . . . . . . . . . . 21
System configuration . . . . . . . . . . . . . . . . . . . 21
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1
9.2
9.3
9.4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 October 2009
Document identifier: PCF8564A_1
相关型号：
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