PCF8570T [NXP]
256 x 8-bit static low-voltage RAM with I2C-bus interface; 256 ×8位的静态低电压内存与I 2 C总线接口
| 型号： | PCF8570T |
| 厂家： | 
NXP |
| 描述： | 256 x 8-bit static low-voltage RAM with I2C-bus interface |
| 文件： | 总20页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF8570
256 × 8-bit static low-voltage RAM
with I2C-bus interface
1999 Jan 06
Product specification
Supersedes data of 1997 Sep 02
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
CONTENTS
1
2
3
4
5
6
7
8
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
CHARACTERISTICS OF THE I2C-BUS
8.1
8.2
8.3
8.4
8.5
Bit transfer
Start and stop conditions
System configuration
Acknowledge
I2C-bus protocol
9
LIMITING VALUES
10
11
12
13
HANDLING
DC CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
13.1
13.2
13.3
Application example
Slave address
Power-saving mode
14
15
PACKAGE OUTLINES
SOLDERING
15.1
Introduction
15.2
Through-hole mount packages
Soldering by dipping or by solder wave
Manual soldering
Surface mount packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of IC packages for wave, reflow and
dipping soldering methods
15.2.1
15.2.2
15.3
15.3.1
15.3.2
15.3.3
15.4
16
17
18
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
1999 Jan 06
2
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
1
FEATURES
• Operating supply voltage 2.5 to 6.0 V
• Low data retention voltage; minimum 1.0 V
• Low standby current; maximum 15 µA
• Power-saving mode; typical 50 nA
• Serial input/output bus (I2C-bus)
3
GENERAL DESCRIPTION
• Address by 3 hardware address pins
• Automatic word address incrementing
• Available in DIP8 and SO8 packages.
The PCF8570 is a low power static CMOS RAM,
organized as 256 words by 8-bits.
Addresses and data are transferred serially via a two-line
bidirectional bus (I2C-bus). The built-in word address
register is incremented automatically after each written or
read data byte. Three address pins, A0, A1 and A2 are
used to define the hardware address, allowing the use of
up to 8 devices connected to the bus without additional
hardware.
2
APPLICATIONS
• Telephony:
– RAM expansion for stored numbers in repertory
dialling (e.g. PCD33xxA applications)
• General purpose RAM for applications requiring
extremely low current and low-voltage RAM retention,
such as battery or capacitor-backed.
• Radio, television and video cassette recorder:
– channel presets
• General purpose:
– RAM expansion for the microcontroller families
PCD33xxA, PCF84CxxxA, P80CLxxx and most other
microcontrollers.
4
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
VDD
IDD
supply voltage
2.5
−
6.0
15
supply current (standby)
fSCL = 0 Hz
Tamb = 25 °C
µA
nA
°C
IDDR
Tamb
Tstg
supply current (power-saving mode)
operating ambient temperature
storage temperature
−
400
+85
−40
−65
+150 °C
5
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
PCF8570P
PCF8570T
DIP8
SO8
plastic dual in-line package; 8 leads (300 mil)
SOT97-1
plastic small outline package; 8 leads; body width 7.5 mm
SOT176-1
1999 Jan 06
3
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
6
BLOCK DIAGRAM
WORD
ADDRESS
REGISTER
MEMORY
CELL
ARRAY
ROW
SELECT
PCF8570
7
1
2
3
A0
A1
A2
6
5
2
SCL
SDA
INPUT
FILTER
COLUMN
SELECT
I C BUS
MULTIPLEXER
CONTROL
8
SHIFT
REGISTER
R/W
CONTROL
POWER
ON
8
V
DD
RESET
4
7
V
SS
TEST
MLB928
Fig.1 Block diagram.
7
PINNING
SYMBOL
A0
PIN
DESCRIPTION
1
2
3
4
5
6
7
hardware address input 0
hardware address input 1
hardware address input 2
negative supply
A1
page
V
A2
A0
A1
A2
1
2
3
4
8
7
6
5
DD
VSS
SDA
SCL
TEST
TEST
PCF8570
serial data input/output
serial clock input
SCL
SDA
V
SS
Input for power-saving mode (see section
MLB929
“Power-saving mode”). Also used as a test output
during manufacture. TEST should be tied to VSS
during normal operation.
Fig.2 Pin configuration.
VDD
8
positive supply
1999 Jan 06
4
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
CHARACTERISTICS OF THE I2C-BUS
8.1
Bit transfer
8
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.3 Bit transfer.
8.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
SDA
SCL
SDA
SCL
S
P
STOP condition
START condition
MBA608
Fig.4 Definition of start and stop conditions.
1999 Jan 06
5
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
8.3
System configuration
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
MBA605
Fig.5 System configuration.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
8.4
Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
clock pulse for
acknowledgement
START
condition
SCL FROM
MASTER
2
9
1
8
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
BY RECEIVER
MBA606 - 1
Fig.6 Acknowledgement on the I2C-bus.
1999 Jan 06
6
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
8.5
I2C-bus protocol
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the start procedure. The I2C-bus configuration for the different
PCF8570 WRITE and READ cycles is shown in Figs 7, 8 and 9.
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
S
SLAVE ADDRESS
0
A
WORD ADDRESS
A
DATA
A
P
R/W
n bytes
auto increment
memory word address
MBD822
Fig.7 Master transmits to slave receiver (WRITE) mode.
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from master
S
SLAVE ADDRESS
0
A
WORD ADDRESS
A
S
SLAVE ADDRESS
1
A
DATA
A
n bytes
at this moment master -
transmitter becomes
master - receiver and
PCF8570 slave -
R/W
R/W
auto increment
memory word address
receiver becomes
slave - transmitter
no acknowledgement
from master
DATA
1
P
last byte
auto increment
memory word address
MLB930
Fig.8 Master reads after setting word address (WRITE word address; READ data).
1999 Jan 06
7
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
a
1
A
A
DATA
1
P
S
SLAVE ADDRESS
DATA
R/W
n bytes
last bytes
auto increment
word address
auto increment
word address
MBD824
Fig.9 Master reads slave immediately after first byte (READ mode).
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
−0.8
MAX.
UNIT
VDD
VI
supply voltage (pin 8)
input voltage (any input)
DC input current
+8.0
VDD + 0.8
±10
V
V
−0.8
−
II
mA
mA
mA
mA
mW
mW
°C
IO
DC output current
−
±10
IDD
ISS
Ptot
PO
Tamb
Tstg
positive supply current
negative supply current
−
±50
−
±50
total power dissipation per package
power dissipation per output
operating ambient temperature
storage temperature
−
300
−
50
−40
−65
+85
+150
°C
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under
“Handling MOS Devices”.
1999 Jan 06
8
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
11 DC CHARACTERISTICS
VDD = 2.5 to 6.0 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN.
TYP.
MAX.
UNIT
Supply
VDD
IDD
supply voltage
2.5
−
−
6.0
V
supply current
standby mode
VI = VDD or VSS
SCL = 0 Hz;
Tamb = −25 to +70 °C
;
−
5
µA
f
operating mode
VI = VDD or VSS
fSCL = 100 Hz
;
−
−
200
2.3
µA
VPOR
Power-on reset voltage
note 1
1.5
1.9
V
Inputs, input/output SDA
VIL
VIH
IOL
ILI
LOW level input voltage
note 2
−0.8
0.7VDD
3
−
−
−
−
0.3VDD
V
HIGH level input voltage
LOW level output current
input leakage current
note 2
VDD + 0.8 V
VOL = 0.4 V
VI = VDD or VSS
−
mA
−1
+1
µA
nA
pF
Inputs A0, A1, A2 and TEST
ILI input leakage current
Inputs SCL and SDA
VI = VDD or VSS
−250
−
−
+250
7
Ci
input capacitance
VI = VSS
−
Low VDD data retention
VDDR
IDDR
supply voltage for data retention
supply current
1
−
−
−
−
−
6
5
2
V
VDDR = 1 V
µA
µA
VDDR = 1 V;
Tamb = −25 to +70 °C
Power-saving mode (see Figs 13 and 14)
IDDR
tHD2
supply current
recovery time
TEST = VDD; Tamb = 25 °C
−
−
50
50
400
nA
−
µs
Notes
1. The Power-on reset circuit resets the I2C-bus logic when VDD < VPOR. The status of the device after a Power-on reset
condition can be tested by sending the slave address and testing the acknowledge bit.
2. If the input voltages are a diode voltage above or below the supply voltage VDD or VSS an input current will flow; this
current must not exceed ±0.5 mA.
1999 Jan 06
9
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
12 AC CHARACTERISTICS
All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL and
IH with an input voltage swing of VSS to VDD
V
.
SYMBOL PARAMETER
I2C-bus timing (see Fig.10; note 1)
MIN.
TYP.
MAX.
UNIT
fSCL
SCL clock frequency
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
kHz
tSP
tolerable spike width on bus
bus free time
100
−
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
tBUF
4.7
4.7
4.0
4.7
4.0
−
tSU;STA
tHD;STA
tLOW
tHIGH
tr
START condition set-up time
START condition hold time
SCL LOW time
−
−
−
SCL HIGH time
−
SCL and SDA rise time
SCL and SDA fall time
data set-up time
1.0
0.3
−
tf
−
tSU;DAT
tHD;DAT
tVD;DAT
tSU;STO
250
0
data hold time
−
SCL LOW-to-data out valid
STOP condition set-up time
−
3.4
−
4.0
Note
1. A detailed description of the I2C-bus specification, with applications, is given in brochure “The I2C-bus and how to
use it”. This brochure may be ordered using the code 9398 393 40011.
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
BIT 0
LSB
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
PROTOCOL
t
t
t
HIGH
SU;STA
LOW
1 / f
SCL
SCL
SDA
t
t
t
f
BUF
r
t
t
t
t
t
HD;STA
SU;DAT
VD;DAT
SU;STO
HD;DAT
MBD820
Fig.10 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
1999 Jan 06
10
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
13 APPLICATION INFORMATION
13.1 Application example
V
DD
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
V
DD
0
SCL
SDA
A0
A1
A2
0
0
PCF8570
'1010'
V
SS
TEST
V
DD
1
0
0
V
up to 8 PCF8570C
SCL
SDA
A0
A1
A2
DD
PCF8570
'1010'
V
SS
TEST
V
DD
1
1
1
V
V
V
SCL
SDA
A0
A1
A2
DD
DD
DD
PCF8570
V
'1010'
DD
V
SS
TEST
R
R
R: pull up resistor
t
r
R =
C
BUS
SDA SCL
MLB931
2
(I C bus)
It is recommended that a 4.7 µF/10 V solid aluminium capacitor (SAL) be connected between VDD and VSS
.
Fig.11 Application diagram.
1999 Jan 06
11
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
13.2 Slave address
The PCF8570 has a fixed combination 1 0 1 0 as group 1, while group 2 is fully programmable (see Fig.12).
handbook, halfpage
1
0
1
0
A2 A1 A0 R/W
group 2
group 1
MLB892
Fig.12 Slave address.
13.3 Power-saving mode
With the condition TEST = VDD or VDDR the PCF8570 goes into the power-saving mode and I2C-bus logic is reset.
power saving
mode (1)
power saving
mode (2)
operating mode
TEST = V
DDR
TEST = V
DD
V
V
DD
TEST
DDR
0 V
V
DD
SCL
SDA
V
DDR
0 V
(3)
(3)
(3)
(3)
t
t
t
t
HD2
SU
HD1
SU
V
DD
V
DDR
0 V
V
DD
V
DD
V
DDR
0 V
I
DD
I
DD
I
DDS
MLB932
(1) Power-saving mode without 5 V supply voltage.
(2) Power-saving mode with 5 V supply voltage.
(3) tSU and tHD1 ≥ 4 µs and tHD2 ≥ 50 µs.
Fig.13 Timing for power-saving mode.
12
1999 Jan 06
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
5 V
V
DD
8
SDA
SCL
A2
A1
5
6
3
2
V
DDR
1.2 V
PCF8570
(NiCd)
MICROCONTROLLER
(1)
TEST
A0
7
1
4
V
MLB933
SS
It is recommended that a 4.7 µF/10 V solid aluminium capacitor (SAL) be connected between VDD and VSS
.
(1) In the operating mode TEST = 0 V; in the power-saving mode TEST = VDDR
.
Fig.14 Application example for power-saving mode.
1999 Jan 06
13
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
14 PACKAGE OUTLINES
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
D
M
E
A
2
A
A
1
L
c
w M
Z
b
1
e
(e )
1
M
H
b
b
2
8
5
pin 1 index
E
1
4
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.14
0.53
0.38
1.07
0.89
0.36
0.23
9.8
9.2
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
1.15
0.068 0.021 0.042 0.014
0.045 0.015 0.035 0.009
0.39
0.36
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.045
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT97-1
050G01
MO-001AN
1999 Jan 06
14
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
SO8: plastic small outline package; 8 leads; body width 7.5 mm
SOT176-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
5
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
detail X
e
w
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
θ
1
2
3
p
E
Z
max.
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
7.65
7.45
7.6
7.4
10.65
10.00
1.1
0.45
1.1
1.0
2.0
1.8
mm
2.65
0.25
0.01
1.27
0.050
1.45
0.057
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.30
0.014 0.009 0.29
0.30
0.29
0.419
0.394
0.043 0.043
0.018 0.039
0.079
0.071
inches 0.10
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-25
97-05-22
SOT176-1
1999 Jan 06
15
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
Typical reflow peak temperatures range from
15 SOLDERING
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
15.1 Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
15.3.2 WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
15.2 Through-hole mount packages
15.2.1 SOLDERING BY DIPPING OR BY SOLDER WAVE
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
15.2.2 MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
300 and 400 °C, contact may be up to 5 seconds.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
15.3 Surface mount packages
15.3.1 REFLOW SOLDERING
15.3.3 MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Jan 06
16
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
15.4 Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
WAVE
REFLOW(1) DIPPING
suitable(2)
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(3)
MOUNTING
PACKAGE
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
−
suitable
Surface mount
BGA, SQFP
suitable
suitable
suitable
suitable
suitable
−
−
−
−
−
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(4)(5)
not recommended(6)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Jan 06
17
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
16 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Jan 06
18
Philips Semiconductors
Product specification
256 × 8-bit static low-voltage RAM with
I2C-bus interface
PCF8570
NOTES
1999 Jan 06
19
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© Philips Electronics N.V. 1999
SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Printed in The Netherlands
415106/00/04/pp20
Date of release: 1999 Jan 06
Document order number: 9397 750 04971
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