PCF8576CU/5 [NXP]
Universal LCD driver for low multiplex rates; 低复用率的通用LCD驱动器
| 型号： | PCF8576CU/5 |
| 厂家： | 
NXP |
| 描述： | Universal LCD driver for low multiplex rates |
| 文件： | 总44页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF8576C
Universal LCD driver for low
multiplex rates
1998 Jul 30
Product specification
Supersedes data of 1997 Nov 14
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
CONTENTS
8
LIMITING VALUES
HANDLING
9
1
2
3
4
5
6
FEATURES
10
11
DC CHARACTERISTICS
AC CHARACTERISTICS
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
11.1
11.2
Typical supply current characteristics
Typical characteristics of LC D outputs
PINNING
12
APPLICATION INFORMATION
Chip-on-glass cascadability in single plane
BONDING PAD LOCATIONS
PACKAGE OUTLINES
FUNCTIONAL DESCRIPTION
12.1
13
6.1
Power-on reset
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
LCD bias generator
LCD voltage selector
LCD drive mode waveforms
Static drive mode
1 : 2 multiplex drive mode
1 : 3 multiplex drive mode
1 : 4 multiplex drive mode
Oscillator
14
15
SOLDERING
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.4
Introduction
Reflow soldering
Wave soldering
LQFP
VSO
6.5.1
6.5.2
6.6
Internal clock
External clock
Timing
Method (LQFP and VSO)
Repairing soldered joints
16
17
18
DEFINITIONS
6.7
Display latch
6.8
Shift register
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
6.9
Segment outputs
Backplane outputs
Display RAM
6.10
6.11
6.12
6.13
6.14
6.15
6.16
Data pointer
Subaddress counter
Output bank selector
Input bank selector
Blinker
7
CHARACTERISTICS OF THE I2C-BUS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Bit transfer (see Fig.12)
Start and stop conditions (see Fig.13)
System configuration (see Fig.14)
Acknowledge (see Fig.15)
PCF8576C I2C-bus controller
Input filters
I2C-bus protocol
Command decoder
Display controller
Cascaded operation
1998 Jul 30
2
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
1
FEATURES
• Single-chip LCD controller/driver
• Selectable backplane drive configuration: static or 2/3/4
backplane multiplexing
• Selectable display bias configuration: static, 1/2 or 1/3
• Internal LCD bias generation with voltage-follower
• May be cascaded for large LCD applications (up to
buffers
2560 segments possible)
• 40 segment drives: up to twenty 8-segment numeric
characters; up to ten 15-segment alphanumeric
characters; or any graphics of up to 160 elements
• Cascadable with 24-segment LCD driver PCF8566
• Optimized pinning for plane wiring in both and multiple
PCF8576C applications
• 40 × 4-bit RAM for display data storage
• Space-saving 56-lead plastic very small outline package
(VSO56) or 64-lead low profile quad flat package
(LQFP64)
• Auto-incremented display data loading across device
subaddress boundaries
• Display memory bank switching in static and duplex
drive modes
• No external components
• Compatible with chip-on-glass technology
• Manufactured in silicon gate CMOS process.
• Versatile blinking modes
• LCD and logic supplies may be separated
• Wide power supply range: from 2 V for low-threshold
LCDs and up to 6 V for guest-host LCDs and
2
GENERAL DESCRIPTION
The PCF8576C is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments and can easily be cascaded for larger LCD
applications. The PCF8576C is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I2C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
high-threshold (automobile) twisted nematic LCDs.
A 9 V version is also available on request.
• Low power consumption
• Power-saving mode for extremely low power
consumption in battery-operated and telephone
applications
• I2C-bus interface
• TTL/CMOS compatible
• Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCF8576CT
VSO56
plastic very small outline package; 56 leads
chip in tray
SOT190-1
PCF8576CU
−
−
PCF8576CU/2
PCF8576CU/5
PCF8576CU/7
PCF8576CU/10
PCF8576CU/12
PCF8576CH
−
−
chip with bumps in tray
−
unsawn wafer
−
−
chip with bumps on tape
−
FFC
FFC
LQFP64
chip-on-film frame carrier
−
−
chip with bumps on film frame carrier
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
SOT314-2
1998 Jul 30
3
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
BP0 BP2 BP1 BP3
13 14 15 16
S0 to S39
40
17 to 56
5
V
BACKPLANE
OUTPUTS
DD
DISPLAY SEGMENT OUTPUTS
DISPLAY LATCH
LCD
VOLTAGE
SELECTOR
LCD BIAS
GENERATOR
SHIFT REGISTER
12
V
LCD
PCF8576C
4
3
CLK
INPUT
BANK
SELECTOR
DISPLAY
RAM
40 x 4 BITS
OUTPUT
BANK
SELECTOR
TIMING
BLINKER
SYNC
DISPLAY
CONTROLLER
6
OSC
OSCILLATOR
POWER-
ON
DATA
POINTER
RESET
COMMAND
DECODER
11
V
SS
2
1
SUB-
ADDRESS
COUNTER
SCL
SDA
2
INPUT
FILTERS
I C - BUS
CONTROLLER
10
7
8
9
SA0
A0 A1 A2
MLD332
Fig.1 Block diagram; VSO56.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
5
PINNING
SYMBOL
PIN
DESCRIPTION
SOT190
SOT314
SDA
1
10
11
I2C-bus serial data input/output
I2C-bus serial clock input
cascade synchronization input/output
external clock input
SCL
2
SYNC
3
12
CLK
4
13
VDD
5
6
14
supply voltage
OSC
15
oscillator input
A0 to A2
7 to 9
10
16 to 18
19
I2C-bus subaddress inputs
I2C-bus slave address input; bit 0
logic ground
SA0
VSS
11
20
VLCD
12
21
LCD supply voltage
BP0, BP2, BP1, BP3
S0 to S39
13 to 16
17 to 56
−
25 to 28
LCD backplane outputs
29 to 32, 34 to 47, 49 to 64, 2 to 7 LCD segment outputs
1, 8, 9, 22 to 24, 33 and 48 not connected
n.c.
1998 Jul 30
5
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
handbook, halfpage
SDA
SCL
1
2
3
4
5
6
7
8
9
56 S39
55 S38
54 S37
53 S36
52 S35
51 S34
50 S33
49 S32
48 S31
47 S30
46 S29
45 S28
44 S27
43 S26
42 S25
41 S24
40 S23
39 S22
38 S21
37 S20
36 S19
35 S18
34 S17
33 S16
32 S15
31 S14
30 S13
29 S12
SYNC
CLK
V
DD
OSC
A0
A1
A2
SA0 10
V
11
12
SS
V
LCD
BP0 13
BP2 14
BP1 15
BP3 16
S0 17
S1 18
S2 19
S3 20
S4 21
S5 22
S6 23
S7 24
S8 25
S9 26
S10 27
S11 28
PCF8576CT
MLD334
Fig.2 Pin configuration; VSO56.
6
1998 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
n.c.
S34
S35
S36
S37
S38
S39
n.c.
n.c.
1
2
3
4
5
6
7
8
9
48 n.c.
47 S17
46 S16
45 S15
44 S14
43 S13
42 S12
41 S11
40 S10
39 S9
38 S8
37 S7
36 S6
35 S5
34 S4
33 n.c.
PCF8576CH
SDA 10
SCL 11
12
SYNC
CLK 13
V
14
DD
OSC 15
A0 16
MLD333
Fig.3 Pin configuration; LQFP64.
1998 Jul 30
7
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
The host microprocessor/microcontroller maintains the
2-line I2C-bus communication channel with the
PCF8576C. The internal oscillator is selected by tying
OSC (pin 6) to VSS (pin 11). The appropriate biasing
voltages for the multiplexed LCD waveforms are
generated internally. The only other connections required
to complete the system are to the power supplies (VDD
VSS and VLCD) and the LCD panel chosen for the
application.
6
FUNCTIONAL DESCRIPTION
The PCF8576C is a versatile peripheral device designed
to interface to any microprocessor/microcontroller to a
wide variety of LCDs. It can directly drive any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments. The display configurations possible with
the PCF8576C depend on the number of active backplane
outputs required; a selection of display configurations is
given in Table 1.
,
All of the display configurations given in Table 1 can be
implemented in the typical system shown in Fig.4.
Table 1 Selection of display configurations
14-SEGMENTS
ALPHANUMERIC
NUMBER OF
7-SEGMENTS NUMERIC
DOT MATRIX
INDICATOR
DIGITS
INDICATOR
SYMBOLS
BACKPLANES SEGMENTS
CHARACTERS
SYMBOLS
4
3
2
1
160
120
80
20
15
10
5
20
15
10
5
10
8
20
8
160 dots (4 × 40)
120 dots (3 × 40)
80 dots (2 × 40)
40 dots (1 × 40)
5
10
12
40
2
V
DD
t
r
R
2C
B
V
V
DD
LCD
5
12
SDA
SCL
HOST
MICRO-
1
2
6
17 to 56 40 segment drives
LCD PANEL
PCF8576CT
PROCESSOR/
MICRO-
CONTROLLER
(up to 160
elements)
OSC
4 backplanes
13 to 16
10 11
A0 A1 A2 SA0 V
7
8
9
MBE524
SS
V
SS
Fig.4 Typical system configuration.
8
1998 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
6.1
Power-on reset
6.3
LCD voltage selector
At power-on the PCF8576C resets to a starting condition
as follows:
The LCD voltage selector co-ordinates the multiplexing of
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of Vop = VDD − VLCD and the
resulting discrimination ratios (D), are given in Table 2.
1. All backplane outputs are set to VDD
2. All segment outputs are set to VDD
.
.
3. The drive mode ‘1 : 4 multiplex with 1⁄3bias’ is selected.
4. Blinking is switched off.
5. Input and output bank selectors are reset (as defined
in Table 5).
6. The I2C-bus interface is initialized.
A practical value for Vop is determined by equating Voff(rms)
with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is Vop > 3Vth approximately.
7. The data pointer and the subaddress counter are
cleared.
Multiplex drive ratios of 1 : 3 and 1 : 4 with 1⁄2bias are
possible but the discrimination and hence the contrast
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on to allow completion of the reset action.
ratios are smaller ( 3 = 1.732 for 1 : 3 multiplex or
21
6.2
The full-scale LCD voltage (Vop) is obtained from
DD − VLCD. The LCD voltage may be temperature
compensated externally through the VLCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an
internal voltage divider of the three series resistors
connected between VDD and VLCD. The centre resistor can
be switched out of the circuit to provide a 1⁄2bias voltage
level for the 1 : 2 multiplex configuration.
LCD bias generator
= 1.528 for 1 : 4 multiplex).
----------
3
V
The advantage of these modes is a reduction of the LCD
full-scale voltage Vop as follows:
• 1 : 3 multiplex (1⁄2bias):
Vop
=
6 × Voff
= 2.449 Voff(rms)
rms
• 1 : 4 multiplex (1⁄2bias):
(4 × 3)
-----------------------
3
Vop
=
= 2.309 Voff(rms)
These compare with Vop = 3 Voff(rms) when 1⁄3bias is used.
Table 2 Preferred LCD drive modes: summary of characteristics
NUMBER OF
V on(rms)
Voff(rms)
V on(rms)
LCD BIAS
CONFIGURATION
D =
--------------------
Voff(rms)
--------------------
Vop
--------------------
Vop
LCD DRIVE MODE
BACKPLANES LEVELS
static
1 : 2
1 : 2
1 : 3
1 : 4
1
2
2
3
4
2
3
4
4
4
static
0
1
∞
1
⁄
0.354
0.333
0.333
0.333
0.791
0.745
0.638
0.577
2.236
2.236
1.915
1.732
2
1
⁄
3
1
⁄
3
1
⁄
3
1998 Jul 30
9
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
6.4
LCD drive mode waveforms
6.4.1
STATIC DRIVE MODE
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive
waveforms for this mode are shown in Fig.5.
T
frame
LCD segments
V
DD
BP0
V
V
LCD
state 1
(on)
state 2
(off)
V
DD
S
n
LCD
V
DD
S
n
1
V
LCD
(a) waveforms at driver
V
op
0
state 1
V
op
V
op
state 2
0
V
op
(b) resultant waveforms
at LCD segment
MBE539
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = Vop
V
state2(t) = VS (t) – VBP0(t)
n + 1
Voff(rms) = 0 V
Fig.5 Static drive mode waveforms (Vop = VDD − VLCD).
1998 Jul 30
10
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
6.4.2
1 : 2 MULTIPLEX DRIVE MODE
When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The PCF8576C allows use of 1⁄2bias or
1⁄3bias in this mode as shown in Figs 6 and 7.
T
frame
V
DD
LCD segments
(V
V
V
)/2
)/2
BP0
DD
LCD
LCD
V
V
LCD
state 1
DD
state 2
BP1 (V
V
DD
LCD
DD
V
S
n
V
V
LCD
DD
S
n
1
V
V
LCD
(a) waveforms at driver
op
V
/2
/2
op
0
state 1
V
V
op
op
V
op
V
/2
/2
op
0
state 2
V
V
op
op
(b) resultant waveforms
at LCD segment
MBE540
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = 0.791Vop
Vstate2(t) = VS (t) – VBP1(t)
n
Voff(rms) = 0.354Vop
Fig.6 Waveforms for the 1 : 2 multiplex drive mode with 1⁄2bias (Vop = VDD − VLCD).
1998 Jul 30
11
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
T
frame
V
DD
LCD segments
V
V
/3
op
2V /3
DD
BP0
BP1
V
V
op
DD
LCD
state 1
V
V
DD
state 2
V
/3
op
2V /3
DD
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
1
V
V
op
DD
LCD
(a) waveforms at driver
V
op
2V /3
op
V
/3
0
op
state 1
V
/3
op
2V /3
op
V
op
V
op
2V /3
op
V
V
/3
0
/3
op
state 2
op
2V /3
op
V
op
(b) resultant waveforms
at LCD segment
MBE541
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = 0.745Vop
Vstate2(t) = VS (t) – VBP1(t)
n
Voff(rms) = 0.333Vop
Fig.7 Waveforms for the 1 : 2 multiplex drive mode with 1⁄3bias (Vop = VDD − VLCD).
1998 Jul 30
12
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
6.4.3
1 : 3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies, as shown in Fig.8.
T
frame
V
DD
LCD segments
V
V
/3
op
2V /3
DD
BP0
BP1
V
V
op
DD
LCD
state 1
state 2
V
V
DD
V
/3
op
2V /3
DD
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
BP2/S23
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
n
1
2
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
V
V
op
DD
LCD
(a) waveforms at driver
V
op
2V /3
op
V
/3
0
op
state 1
V
/3
op
2V /3
op
V
op
V
op
2V /3
op
V
V
/3
0
/3
op
state 2
op
2V /3
op
V
op
(b) resultant waveforms
at LCD segment
MBE542
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = 0.638Vop
Vstate2(t) = VS (t) – VBP1(t)
n
Voff(rms) = 0.333Vop
Fig.8 Waveforms for the 1 : 3 multiplex drive mode (Vop = VDD − VLCD).
1998 Jul 30
13
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
6.4.4
1 : 4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies, as shown in Fig.9.
T
frame
V
V
LCD segments
DD
V
/3
op
2V /3
DD
BP0
BP1
BP2
BP3
V
V
op
DD
LCD
state 1
state 2
V
V
DD
V
/3
op
2V /3
DD
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
n
n
1
2
3
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
S
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
V
V
op
DD
LCD
(a) waveforms at driver
V
op
2V /3
op
V
/3
0
op
state 1
V
/3
op
2V /3
op
Vstate1(t) = VS (t) – VBP0(t)
V
op
n
V
op
Von(rms) = 0.577Vop
2V /3
op
V
state2(t) = VS (t) – VBP1(t)
n
V
V
/3
0
/3
op
op
state 2
Voff(rms) = 0.333Vop
2V /3
op
V
op
(b) resultant waveforms
at LCD segment
MBE543
Fig.9 Waveforms for the 1 : 4 multiplex drive mode (Vop = VDD − VLCD).
1998 Jul 30
14
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
When a device is unable to digest a display data byte
before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the
transmission rate of the I2C-bus but no data loss occurs.
6.5
Oscillator
6.5.1
INTERNAL CLOCK
The internal logic and the LCD drive signals of the
PCF8576C are timed either by the built-in oscillator or from
an external clock. When the internal oscillator is used,
OSC (pin 6) should be connected to VSS (pin 11). In this
event, the output from CLK (pin 4) provides the clock
signal for cascaded PCF8566s or PCF8576Cs in the
system.
6.7
Display latch
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
Note that the PCF8576C is backwards compatible with the
PCF8576. Where resistor Rosc to VSS is present, the
internal oscillator is selected.
6.8
Shift register
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data is displayed.
6.5.2
EXTERNAL CLOCK
The condition for external clock is made by tying OSC
(pin 6) to VDD; CLK (pin 4) then becomes the external
clock input.
6.9
Segment outputs
The clock frequency (fclk) determines the LCD frame
frequency and the maximum rate for data reception from
the I2C-bus. To allow I2C-bus transmissions at their
maximum data rate of 100 kHz, fclk should be chosen to be
above 125 kHz.
The LCD drive section includes 40 segment outputs
S0 to S39 (pins 17 to 56) which should be connected
directly to the LCD. The segment output signals are
generated in accordance with the multiplexed backplane
signals and with data resident in the display latch. When
less than 40 segment outputs are required the unused
segment outputs should be left open-circuit.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.10 Backplane outputs
6.6
Timing
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open-circuit. In the 1 : 3 multiplex drive mode
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode BP0
and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
The timing of the PCF8576C organizes the internal data
flow of the device. This includes the transfer of display data
from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal SYNC
maintains the correct timing relationship between the
PCF8576Cs in the system. The timing also generates the
LCD frame frequency which it derives as an integer
multiple of the clock frequency (see Table 3). The frame
frequency is set by the MODE SET commands when
internal clock is used, or by the frequency applied to pin 4
when external clock is used.
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power-saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.
The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I2C-bus.
1998 Jul 30
15
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
In the 1 : 2 multiplex drive mode the eight transmitted data
bits are placed in bits 0 and 1 of four successive display
RAM addresses. In the 1 : 3 multiplex drive mode these
bits are placed in bits 0, 1 and 2 of three successive
addresses, with bit 2 of the third address left unchanged.
This last bit may, if necessary, be controlled by an
additional transfer to this address but care should be taken
to avoid overriding adjacent data because full bytes are
always transmitted. In the 1 : 4 multiplex drive mode the
eight transmitted data bits are placed in bits 0, 1, 2 and 3
of two successive display RAM addresses.
6.11 Display RAM
The display RAM is a static 40 × 4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the on
state of the corresponding LCD segment; similarly, a
logic 0 indicates the off state. There is a one-to-one
correspondence between the RAM addresses and the
segment outputs, and between the individual bits of a RAM
word and the backplane outputs. The first RAM column
corresponds to the 40 segments operated with respect to
backplane BP0 (see Fig.10). In multiplexed LCD
applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed
with BP1, BP2 and BP3 respectively.
Table 3 LCD frame frequencies
NOMINAL
When display data is transmitted to the PCF8576C the
display bytes received are stored in the display RAM in
accordance with the selected LCD drive mode.
To illustrate the filling order, an example of a 7-segment
numeric display showing all drive modes is given in Fig.11;
the RAM filling organization depicted applies equally to
other LCD types.
FRAME
FREQUENCY
FRAME
FREQUENCY
(Hz)
PCF8576C MODE
fclk
Normal mode
64
64
------------
2880
f clk
Power-saving mode
With reference to Fig.11, in the static drive mode the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses.
---------
480
display RAM addresses (rows) / segment outputs (S)
0
1
2
3
4
35 36 37 38 39
0
1
2
3
display RAM bits
(columns) /
backplane outputs
(BP)
MBE525
Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses
and segment outputs, and between bits in a RAM word and backplane outputs.
1998 Jul 30
16
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
6.12 Data pointer
6.14 Output bank selector
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM. The sequence
commences with the initialization of the data pointer by the
LOAD DATA POINTER command. Following this, an
arriving data byte is stored starting at the display RAM
address indicated by the data pointer thereby observing
the filling order shown in Fig.11. The data pointer is
automatically incremented in accordance with the chosen
LCD configuration. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1 : 2 multiplex drive mode) or
by two (1 : 4 multiplex drive mode).
This selects one of the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence.
In 1 : 4 multiplex, all RAM addresses of bit 0 are the first to
be selected, these are followed by the contents of
bit 1, bit 2 and then bit 3. Similarly in 1 : 3 multiplex,
bits 0, 1 and 2 are selected sequentially. In 1 : 2 multiplex,
bits 0 and 1 are selected and, in the static mode, bit 0 is
selected.
The PCF8576C includes a RAM bank switching feature in
the static and 1 : 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
the contents of bit 2 to be selected for display instead of
bit 0 contents. In the 1 : 2 drive mode, the contents of
bits 2 and 3 may be selected instead of bits 0 and 1. This
gives the provision for preparing display information in an
alternative bank and to be able to switch to it once it is
assembled.
6.13 Subaddress counter
The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to
A0, A1 and A2. The subaddress counter value is defined
by the DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddress do not
agree then data storage is inhibited but the data pointer is
incremented as if data storage had taken place.
The subaddress counter is also incremented when the
data pointer overflows.
6.15 Input bank selector
The input bank selector loads display data into the display
RAM in accordance with the selected LCD drive
configuration. Display data can be loaded in bit 2 in static
drive mode or in bits 2 and 3 in 1 : 2 drive mode by using
the BANK SELECT command. The input bank selector
functions independent of the output bank selector.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8576C occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character (such as during the 14th display data byte
transmitted in 1 : 3 multiplex mode).
1998 Jul 30
17
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the
blinking frequency. This mode can also be specified by the
BLINK command.
6.16 Blinker
The display blinking capabilities of the PCF8576C are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, as shown in
Table 4.
In the 1 : 3 and 1 : 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.
If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bit E
at the required rate using the MODE SET command.
An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and
1 : 2 LCD drive modes and can be implemented without
any communication overheads.
Table 4 Blinking frequencies
NORMAL OPERATING
BLINKING MODE
POWER-SAVING MODE
RATIO
NOMINAL BLINKING
FREQUENCY
MODE RATIO
Off
−
−
blinking off
fclk
f clk
2 Hz
2 Hz
----------------
92160
----------------
15360
f clk
f clk
1 Hz
1 Hz
-------------------
184320
----------------
30720
f clk
f clk
0.5 Hz
0.5 Hz
-------------------
368640
----------------
61440
1998 Jul 30
18
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
a
S
2
n
n
1
n
2
n
3
n
4
n
5
n
6
n 7
n
n
b
BP0
f
S
1
7
S
3
MSB
LSB
DP
n
n
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP
bit/
BP
g
4
S
S
S
n
n
x
x
x
x
x
x
c
b
a
f
g e d
static
e
S
5
6
c
n
d
DP
S
n
BP0
S
n
a
n
n
n
n
1
1
1
n
2
n 3
b
b
b
1 : 2
f
S
1
n
MSB
LSB
DP
0
1
2
3
a
b
x
x
f
e
c
x
x
d
bit/
BP
g
g
x
x
DP
x
x
a
b
f
g
e c d
BP1
S
S
e
2
3
multiplex
n
n
c
c
c
d
d
d
DP
BP0
BP1
S
1
a
n
n
n 2
S
S
2
f
1 : 3
n
n
MSB
LSB
e
0
1
2
3
b
DP
c
a
d
g
x
f
bit/
BP
g
e
x
x
BP2
b DP
c
a
d
g
f
e
multiplex
x
DP
S
n
a
n
BP2
BP3
BP0
BP1
f
1 : 4
0
1
2
3
a
c
f
bit/
BP
MSB
LSB
d
g
e
g
d
b
DP
e
multiplex
a
c
b
DP
f
e
g
S
1
DP
n
MBE534
x = data bit unchanged.
2
ahdnbok,uflapegwidt
Fig.11 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I C-bus.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
7
CHARACTERISTICS OF THE I2C-BUS
7.5
PCF8576C I2C-bus controller
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
The PCF8576C acts as an I2C-bus slave receiver. It does
not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8576C
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.
In single device application, the hardware subaddress
inputs A0, A1 and A2 are normally tied to VSS which
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are tied to VSS or VDD in
accordance with a binary coding scheme such that no two
devices with a common I2C-bus slave address have the
same hardware subaddress.
7.1
Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
7.2
Start and stop conditions (see Fig.13)
In the power-saving mode it is possible that the PCF8576C
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8576C forces the SCL line LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I2C-bus and
serves to slow down fast transmitters. Data loss does not
occur.
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
7.3
System configuration (see Fig.14)
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
7.6
Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.4
Acknowledge (see Fig.15)
7.7
I2C-bus protocol
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
Two I2C-bus slave addresses (0111000 and 0111001) are
reserved for the PCF8576C. The least significant bit of the
slave address that a PCF8576C will respond to is defined
by the level tied at its input SA0 (pin 10). Therefore, two
types of PCF8576C can be distinguished on the same
I2C-bus which allows:
1. Up to 16 PCF8576Cs on the same I2C-bus for very
large LCD applications.
2. The use of two types of LCD multiplex on the same
I2C-bus.
The I2C-bus protocol is shown in Fig.16. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of the two PCF8675C
slave addresses available. All PCF8576Cs with the
corresponding SA0 level acknowledge in parallel with the
slave address but all PCF8576Cs with the alternative SA0
level ignore the whole I2C-bus transfer.
1998 Jul 30
20
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
After acknowledgement, one or more command bytes (m)
follow which define the status of the addressed
PCF8576Cs.
7.8
Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. All available commands carry a
continuation bit C in their most significant bit position
(Fig.17). When this bit is set, it indicates that the next byte
of the transfer to arrive will also represent a command.
If this bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.
The last command byte is tagged with a cleared most
significant bit, the continuation bit C. The command bytes
are also acknowledged by all addressed PCF8576Cs on
the bus.
After the last command byte, a series of display data bytes
(n) may follow. These display bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data is directed to the intended PCF8576C device.
The acknowledgement after each byte is made only by the
(A0, A1 and A2) addressed PCF8576C. After the last
display byte, the I2C-bus master issues a STOP
condition (P).
The five commands available to the PCF8576C are
defined in Table 5.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.12 Bit transfer.
SDA
SCL
SDA
SCL
S
P
STOP condition
START condition
MBC622
Fig.13 Definition of START and STOP conditions.
1998 Jul 30
21
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.14 System configuration.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
MASTER
1
2
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.15 Acknowledgement on the I2C-bus.
22
1998 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
acknowledge
by A0, A1 and A2
selected
acknowledge by
all addressed
PCF8576Cs
R / W
PCF8576C only
slave address
S
A
0
0
1
1
1
0
0
0
A C
A
DISPLAY DATA
A
P
COMMAND
S
1 byte
n
1 byte(s)
n
0 byte(s)
update data pointers
and if necessary,
subaddress counter
MBE538
Fig.16 I2C-bus protocol.
MSB
LSB
C
REST OF OPCODE
MSA833
C = 0; last command.
C = 1; commands continue.
Fig.17 General format of command byte.
1998 Jul 30
23
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
Table 5 Definition of PCF8576C commands
COMMAND
OPCODE
LP
OPTIONS
DESCRIPTION
MODE SET
C
1
0
E
B
M1 M0
Table 6
Table 7
Table 8
Defines LCD drive mode.
Defines LCD bias configuration.
Defines display status. The possibility to
disable the display allows implementation
of blinking under external control.
Table 9
Defines power dissipation mode.
LOADDATA
POINTER
C
C
C
0
1
1
P5 P4 P3 P2 P1 P0
Table 10 Six bits of immediate data, bits P5 to P0,
are transferred to the data pointer to
define one of forty display RAM
addresses.
DEVICE
SELECT
1
1
0
1
0
1
A2 A1 A0
Table 11
Three bits of immediate data, bits A0 to
A3, are transferred to the subaddress
counter to define one of eight hardware
subaddresses.
BANK
SELECT
0
I
O
Table 12 Defines input bank selection (storage of
arriving display data).
Table 13 Defines output bank selection (retrieval of
LCD display data).
The BANK SELECT command has no
effect in 1 : 3 and 1 : 4 multiplex drive
modes.
BLINK
C
1
1
1
0
A
BF1 BF0 Table 14 Defines the blinking frequency.
Table 15 Selects the blinking mode; normal
operation with frequency set by BF1, BF0
or blinking by alternation of display RAM
banks. Alternation blinking does not apply
in 1 : 3 and 1 : 4 multiplex drive modes.
Table 6 Mode set option 1
Table 8 Mode set option 3
LCD DRIVE MODE
BITS
DISPLAY STATUS
Disabled (blank)
BIT E
0
1
DRIVE
BACKPLANE
MODE
M1
M0
Enabled
Static
1 : 2
1 : 3
1 : 4
1 BP
0
1
1
0
1
0
1
0
Table 9 Mode set option 4
MUX (2 BP)
MUX (3 BP)
MUX (4 BP)
MODE
Normal mode
BIT LP
0
1
Power-saving mode
Table 7 Mode set option 2
LCD BIAS
BIT B
1⁄3bias
1⁄2bias
0
1
1998 Jul 30
24
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
Table 10 Load data pointer option 1
Table 14 Blink option 1
DESCRIPTION
BITS
BITS
BLINK FREQUENCY
6 bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0
BF1
BF0
Off
0
0
1
1
0
1
0
1
Table 11 Device select option 1
2 Hz
1 Hz
0.5 Hz
DESCRIPTION
BITS
3 bit binary value of 0 to 7
A0
A1
A2
Table 12 Bank select option 1
Table 15 Blink option 2
STATIC
RAM bit 0
RAM bit 2
1 : 2 MUX
BIT I
BLINK MODE
BIT A
RAM bits 0 and 1
RAM bits 2 and 3
0
1
Normal blinking
0
1
Alternation blinking
Table 13 Bank select option 2
STATIC 1 : 2 MUX
RAM bit 0
RAM bit 2
BIT O
RAM bits 0 and 1
RAM bits 2 and 3
0
1
The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8576Cs. This
synchronization is guaranteed after the power-on reset.
The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when PCF8576Cs with differing SA0
levels are cascaded). SYNC is organized as an
input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor.
A PCF8576C asserts the SYNC line at the onset of its last
active backplane signal and monitors the SYNC line at all
other times. Should synchronization in the cascade be
lost, it will be restored by the first PCF8675C to assert
SYNC. The timing relationship between the backplane
waveforms and the SYNC signal for the various drive
modes of the PCF8576C are shown in Fig.19.
7.9
Display controller
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8576C and co-ordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
7.10 Cascaded operation
In large display configurations, up to 16 PCF8576Cs can
be distinguished on the same I2C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0). When
cascaded PCF8576Cs are synchronized so that they can
share the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other PCF8576Cs of the
cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (Fig.18).
For single plane wiring of packaged PCF8576Cs and
chip-on-glass cascading, see Chapter “Application
information”.
1998 Jul 30
25
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
V
V
LCD
DD
SDA
1
5
12
40 segment drives
SCL
17 to 56
2
LCD PANEL
SYNC
3
PCF8576CT
CLK
(up to 2560
elements)
13,15,
14,16
4
OSC
6
BP0 to BP3
(open-circuit)
A0 A1 A2 SAO V
SS
V
V
LCD
t
DD
r
R
V
V
2C
DD
LCD
B
5
12
SDA
SCL
HOST
MICRO-
1
2
3
4
6
40 segment drives
17 to 56
PROCESSOR/
MICRO-
PCF8576CT
SYNC
CLK
13,15,
14,16
CONTROLLER
4 backplanes
BP0 to BP3
OSC
MBE533
7
8
9
10 11
A0 A1 A2 SA0 V
SS
V
SS
Fig.18 Cascaded PCF8576C configuration.
1998 Jul 30
26
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
1
T
= f
frame
frame
BP0
SYNC
(a) static drive mode.
BP1
(1/2 bias)
BP1
(1/3 bias)
SYNC
(b) 1 : 2 multiplex drive mode.
BP2
SYNC
(c) 1 : 3 multiplex drive mode.
BP3
SYNC
MBE535
(d) 1 : 4 multiplex drive mode.
Excessive capacitive coupling between SCL or CLK and SYNC may cause erroneous synchronization. If this proves to be a problem, the capacitance of
the SYNC line should be increased (e.g. by an external capacitor between SYNC and VDD). Degradation of the positive edge of the SYNC pulse may be
countered by an external pull-up resistor.
(a) static drive mode.
(b) 1 : 2 multiplex drive mode.
(c) 1 : 3 multiplex drive mode.
(d) 1 : 4 multiplex drive mode.
Fig.19 Synchronization of the cascade for the various PCF8576C drive modes.
1998 Jul 30
27
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
8
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
VDD
MIN.
−0.5
MAX.
+8.0
UNIT
supply voltage
V
V
V
V
V
VLCD
VI1
VI2
VO
II
LCD supply voltage
VDD − 8.0
VSS − 0.5
VSS − 0.5
VLCD − 0.5
VDD
input voltage CLK, SYNC, SA0, OSC, A0 to A2
input voltage SDA, SCL
VDD + 0.5
+8.0
output voltage S0 to S39, BP0 to BP3
DC input current
VDD + 0.5
+20
−20
−25
−50
−
mA
mA
mA
mW
mW
°C
IO
DC output current
+25
IDD, ISS, ILCD VDD, VSS or VLCD current
+50
Ptot
PO
Tstg
total power dissipation
power dissipation per output
storage temperature
400
−
100
−65
+150
9
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
1998 Jul 30
28
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
10 DC CHARACTERISTICS
VDD = 2 to 6 V; VSS = 0 V; VLCD = VDD − 2 V to VDD − 6 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
VLCD
IDD
supply voltage
2
−
6
V
LCD supply voltage
supply current
note 1
V
DD − 6
−
V
DD − 2
V
note 2
normal mode
fclk = 200 kHz
−
−
−
−
120
60
µA
µA
power-saving mode
f
clk = 35 kHz;
DD = 3.5 V; VLCD = 0 V;
V
A0, A1 and A2 tied to VSS
Logic
VIL
LOW-level input voltage SDA, SCL,
CLK, SYNC, SA0, OSC, A0 to A2
VSS
−
−
0.3VDD
VDD
V
V
VIH1
HIGH-level input voltage CLK, SYNC,
SA0, OSC, A0 to A2
0.7VDD
VIH2
VOL
VOH
IOL1
IOH1
IOL2
IL1
HIGH-level input voltage SDA, SCL
LOW-level output voltage
0.7VDD
−
−
6.0
0.05
−
V
IOL = 0 mA
IOH = 0 mA
−
V
HIGH-level output voltage
VDD − 0.05 −
V
LOW-level output current CLK, SYNC VOL = 1 V; VDD = 5 V
HIGH-level output current CLK VOH = 4 V; VDD = 5 V
1
−
−
mA
mA
mA
µA
−1
3
−
−
−
−
LOW-level output current SDA, SCL VOL = 0.4 V; VDD = 5 V
−
leakage current SA0, A0 to A2, CLK, VI = VDD or VSS
SDA and SCL
−1
+1
IL2
Ipd
leakage current OSC
VI = VDD
−1
−
+1
µA
µA
A0, A1, A2 and OSC pull-down
current
VI = 1 V; VDD = 5 V
15
50
150
RSYNC
VPOR
tSW
pull-up resistor (SYNC)
power-on reset voltage level
tolerable spike width on bus
input capacitance
20
−
50
1.0
−
150
1.6
100
7
kΩ
V
note 3
note 4
−
ns
pF
CI
−
−
LCD outputs
VBP
VS
DC voltage component BP0 to BP3
CBP = 35 nF
−20
−20
−
−
−
−
−
+20
+20
5
mV
mV
kΩ
kΩ
DC voltage component S0 to S39
output resistance BP0 to BP3
output resistance S0 to S39
CS = 5 nF
RBP
RS
note 5; VLCD = VDD − 5 V
note 5; VLCD = VDD − 5 V
−
7.5
Notes
1. VLCD ≤ VDD − 3 V for 1⁄3bias.
2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.
3. Resets all logic when VDD < VPOR
.
4. Periodically sampled, not 100% tested.
5. Outputs measured one at a time.
1998 Jul 30
29
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
11 AC CHARACTERISTICS
VDD = 2 to 6 V; VSS = 0 V; VLCD = VDD − 2 V to VDD − 6 V; Tamb = −40 to + 85 °C; unless otherwise specified.
SYMBOL
PARAMETER
oscillator frequency
CONDITIONS
MIN.
TYP. MAX. UNIT
fclk
normal mode
V
DD = 5 V; note 1
DD = 3.5 V
125
200
31
−
315
48
−
kHz
kHz
µs
power-saving mode
CLK HIGH time
V
21
1
tclkH
tclkL
CLK LOW time
1
−
−
µs
tPSYNC
tSYNCL
tPLCD
SYNC propagation delay time
SYNC LOW time
−
−
400
−
ns
1
−
µs
driver delays with test loads
VLCD = VDD − 5 V
−
−
30
µs
Timing characteristics: I2C-bus; note 2
tBUF
bus free time
4.7
4.0
4.7
4.7
4.0
−
−
−
−
−
−
−
−
−
−
−
−
−
µs
µs
µs
µs
µs
µs
µs
pF
ns
ns
µs
tHD;STA
tSU;STA
tLOW
tHIGH
tr
START condition hold time
set-up time for a repeated START condition
SCL LOW time
−
−
−
SCL HIGH time
−
SCL and SDA rise time
SCL and SDA fall time
capacitive bus line load
data set-up time
1
tf
−
0.3
400
−
CB
−
tSU;DAT
tHD;DAT
tSU;STO
250
0
data hold time
−
set-up time for STOP condition
4.0
−
Notes
1. At fclk < 125 kHz, I2C-bus maximum transmission speed is derated.
2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD
.
6.8 Ω
SYNC
CLK
V
DD
(2%)
3.3 kΩ
1.5 kΩ
SDA,
SCL
V
0.5V
DD
DD
(2%)
(2%)
1 nF
BP0 to BP3, and
S0 to S39
V
DD
MBE544
Fig.20 Test loads.
30
1998 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
1/ f
clk
t
t
clkL
clkH
0.7V
0.3V
DD
CLK
DD
0.7V
0.3V
DD
SYNC
DD
t
t
PSYNC
PSYNC
SYNCL
t
0.5 V
BP0 to BP3,
and S0 to S39
(V
= 5 V)
DD
0.5 V
t
PLCD
MBE545
Fig.21 Driver timing waveforms.
SDA
SCL
SDA
t
t
t
f
BUF
LOW
t
t
t
SU;DAT
t
HD;STA
r
t
HIGH
HD;DAT
t
SU;STA
MGA728
t
SU;STO
Fig.22 I2C-bus timing waveforms.
31
1998 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
11.1 Typical supply current characteristics
MBE530
MBE529
50
50
40
I
I
SS
LCD
(µA)
(µA)
normal
mode
40
30
20
30
20
power-saving
mode
10
0
10
0
0
100
200
f
(Hz)
0
100
200
f
(Hz)
frame
frame
VDD = 5 V; VLCD = 0 V; Tamb = 25 °C.
VDD = 5 V; VLCD = 0 V; Tamb = 25 °C.
Fig.24 −ILCD as a function of fframe
.
Fig.23 −ISS as a function of fframe
.
MBE528 - 1
MBE527 - 1
50
50
handbook, halfpage
handbook, halfpage
I
I
LCD
(µA)
SS
(µA)
normal mode
= 200 kHz
40
40
85oC
f
clk
30
20
30
20
25oC
40oC
power-saving mode
10
f
= 35 kHz
10
clk
0
0
0
0
5
10
5
10
V
(V)
V
(V)
DD
DD
VLCD = 0 V; external clock; Tamb = 25 °C.
VLCD = 0 V; external clock; fclk = nominal frequency.
Fig.25 ISS as a function of VDD
.
Fig.26 ILCD as a function of VDD.
1998 Jul 30
32
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
11.2 Typical characteristics of LC D outputs
MBE532 - 1
MBE526
2.5
O(max)
(kΩ)
10
handbook, halfpage
R
S
R
R
O(max)
(kΩ)
2.0
R
S
1.5
1.0
1
R
R
BP
BP
0.5
0
-1
10
40
0
40
80
120
( C)
amb
0
3
6
o
V
(V)
DD
T
VLCD = 0 V; Tamb = 25 °C.
VDD = 5 V; VLCD = 0 V.
Fig.27 RO(max) as a function of VDD
.
Fig.28 RO(max) as a function of Tamb.
1998 Jul 30
33
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
a
SDA
SCL
SYNC
CLK
V
DD
V
SS
V
LCD
SDA
SCL
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
SYNC
CLK
3
3
4
4
V
5
5
DD
OSC
A0
6
6
7
7
A1
8
8
A2
9
9
SA0
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
V
SS
V
LCD
BP0
BP2
BP1
BP3
S0
BP0
BP2
BP1
BP3
S40
S41
S42
S43
open
PCF
8576CT
PCF
8576CT
S1
S2
S3
34
33
32
31
30
29
S17
S16
S15
34
33
32
31
30
29
S57
S56
S55
S7
S8
24
25
26
27
28
S47
S48
S49
S50
S51
24
25
26
27
28
S9
S14
S13
S12
S54
S53
S52
S10
S11
S0
S10
S11
S12
S13
S39
S40
S50
S51
S52
S53
S79
backplanes
segments
MBE537
Fig.29 Single plane wiring of packaged PCF8576CTs.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
The only bus line that does not require a second opening
to lead through to the next PCF8576C is VLCD, being the
cascade centre. The placing of VLCD adjacent to VSS
allows the two supplies to be tied together.
12.1 Chip-on-glass cascadability in single plane
In chip-on-glass technology, where driver devices are
bonded directly onto glass of the LCD, it is important that
the devices may be cascaded without the crossing of
conductors, but the paths of conductors can be continued
on the glass under the chip. All of this is facilitated by the
PCF8576C bonding pad layout (Fig.30). Pads needing bus
interconnection between all PCF8576Cs of the cascade
are VDD, VSS, VLCD, CLK, SCL, SDA and SYNC. These
lines may be led to the corresponding pads of the next
PCF8576C through the wide opening between VLCD pad
and the backplane output pads.
When an external clocking source is to be used, OSC of all
devices should be tied to VDD. The pads OSC, A0, A1, A2
and SA0 have been placed between VSS and VDD to
facilitate wiring of oscillator, hardware subaddress and
slave address.
13 BONDING PAD LOCATIONS
34 33 32 31 30 29 28 27 26 25 24 23 22 21
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
20
19
18
17
16
15
14
13
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S3
S2
S1
S0
BP3
BP1
BP2
BP0
x
3.20
mm
0
0
y
V
12
LCD
PCF8576C
V
11
10
9
SS
SA0
A2
8
A1
51 52 53 54 55 56
1
2
3
4
5
6
7
MBE536
2.92 mm
Chip dimensions: approximately 2.92 × 3.20 mm.
Pad area: 0.0121 mm2.
Bonding pad dimensions: 110 × 110 µm.
Fig.30 Bonding pad locations.
35
1998 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
Table 16 Bonding pad locations (dimensions in µm)
All x/y coordinates are referenced to the centre of the chip
(see Fig.30).
SYMBOL
S15
PAD
x
y
SYMBOL
SDA
PAD
x
y
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
−751
1380
1380
1380
1243
1083
910
1
−74
−1380
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
−924
−1084
−1290
−1290
−1290
−1290
−1290
−1290
−1290
−1290
−1290
−1290
−1290
−1290
−1290
−1290
−1290
−1290
−1083
−923
SCL
SYNC
CLK
VDD
OSC
A0
2
148
355
−1380
−1380
−1380
−1380
−1380
−1380
−1284
−1116
−945
−751
−485
125
3
4
534
5
742
6
913
750
7
1087
1290
1290
1290
1290
1290
1290
1290
1290
1290
1290
1290
1290
1290
1074
914
577
A1
8
417
A2
9
244
SA0
VSS
VLCD
BP0
BP2
BP1
BP3
S0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
84
−89
−249
−422
−582
−755
−915
−1088
−1248
−1380
−1380
−1380
−1380
−1380
−1380
285
458
618
791
S1
951
S2
1124
1284
1380
1380
1380
1380
1380
1380
1380
1380
1380
1380
1380
S3
S4
−750
S5
−590
S6
741
−417
S7
581
−257
S8
408
S9
248
Alignment marks
S10
S11
S12
S13
S14
75
C1
C2
F
−
−
−
−1290
−1295
1305
1385
−1385
−1405
−85
−258
−418
−591
1998 Jul 30
36
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
14 PACKAGE OUTLINES
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
H
v
M
A
E
Z
56
29
Q
p
A
2
A
(A )
3
A
1
pin 1 index
θ
L
L
detail X
1
28
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(2)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
0.3
0.1
3.0
2.8
0.42
0.30
0.22 21.65 11.1
0.14 21.35 11.0
15.8
15.2
1.6
1.4
1.45
1.30
0.90
0.55
3.3
0.25
0.01
0.75
2.25
0.2
0.1
0.1
7o
0o
0.012 0.12
0.004 0.11
0.017 0.0087 0.85
0.012 0.0055 0.84
0.44
0.43
0.62
0.60
0.063 0.057
0.055 0.051
0.035
0.022
inches
0.008 0.004 0.004
0.0295
0.089
0.13
Note
1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
96-04-02
97-08-11
SOT190-1
1998 Jul 30
37
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
y
X
A
48
33
Z
49
32
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-01
SOT314-2
1998 Jul 30
38
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
If wave soldering cannot be avoided, for LQFP
15 SOLDERING
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
15.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
15.3.2 VSO
Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
15.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP and
VSO packages.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• The package footprint must incorporate solder thieves at
the downstream end.
15.3.3 METHOD (LQFP AND VSO)
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
15.3 Wave soldering
15.3.1 LQFP
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
15.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
CAUTION
Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Jul 30
39
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
16 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Jul 30
40
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
NOTES
1998 Jul 30
41
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
NOTES
1998 Jul 30
42
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576C
NOTES
1998 Jul 30
43
Philips Semiconductors – a worldwide company
Argentina: see South America
Middle East: see Italy
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Fax. +43 160 101 1210
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
Norway: Box 1, Manglerud 0612, OSLO,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belgium: see The Netherlands
Brazil: see South America
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Portugal: see Spain
Romania: see Italy
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Colombia: see South America
Czech Republic: see Austria
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Slovakia: see Austria
Slovenia: see Italy
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Spain: Balmes 22, 08007 BARCELONA,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/06/pp44
Date of release: 1998 Jul 30
Document order number: 9397 750 04196
相关型号：
PCF8576DH/2,518
IC LIQUID CRYSTAL DISPLAY DRIVER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT-357-1, TQFP-64, Display Driver
NXP
©2020 ICPDF网 联系我们和版权申明