PCF8576U/7 [NXP]
Universal LCD driver for low multiplex rates; 低复用率的通用LCD驱动器
| 型号： | PCF8576U/7 |
| 厂家： | 
NXP |
| 描述： | Universal LCD driver for low multiplex rates |
| 文件： | 总40页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF8576
Universal LCD driver for low
multiplex rates
1998 Feb 06
Product specification
Supersedes data of 1997 Nov 18
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
CONTENTS
7
CHARACTERISTICS OF THE I2C-BUS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Bit transfer
1
2
3
4
5
6
FEATURES
START and STOP conditions
System configuration
Acknowledge
PCF8576 I2C-bus controller
Input filters
I2C-bus protocol
Command decoder
Display controller
Cascaded operation
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.5.1
6.5.2
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
Power-on reset
LCD bias generator
LCD voltage selector
LCD drive mode waveforms
Static drive mode
1 : 2 multiplex drive mode
1 : 3 multiplex drive mode
1 : 4 multiplex drive mode
Oscillator
Internal clock
External clock
Timing
Display latch
8
LIMITING VALUES
HANDLING
9
10
11
DC CHARACTERISTICS
AC CHARACTERISTICS
11.1
11.2
Typical supply current characteristics
Typical characteristics of LCD outputs
12
APPLICATION INFORMATION
Chip-on-glass cascadability in single plane
BONDING PAD LOCATIONS
PACKAGE OUTLINES
12.1
13
Shift register
14
Segment outputs
Backplane outputs
Display RAM
15
SOLDERING
15.1
15.2
15.3
15.4
Introduction
Reflow soldering
Wave soldering
Data pointer
Subaddress counter
Output bank selector
Input bank selector
Blinker
Repairing soldered joints
16
17
18
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
1998 Feb 06
2
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
• Compatible with any 4-bit, 8-bit or 16-bit
1
FEATURES
microprocessors/microcontrollers
• Single-chip LCD controller/driver
• May be cascaded for large LCD applications (up to
2560 segments possible)
• Selectable backplane drive configuration: static or 2/3/4
backplane multiplexing
• Selectable display bias configuration: static, 1⁄2 or 1⁄3
• Cascadable with 24-segment LCD driver PCF8566
• Optimized pinning for plane wiring in both single and
multiple PCF8576 applications
• Internal LCD bias generation with voltage-follower
buffers
• Space-saving 56-lead plastic very small outline package
(VSO56)
• 40 segment drives: up to twenty 8-segment numeric
characters; up to ten 15-segment alphanumeric
characters; or any graphics of up to 160 elements
• Very low external component count (at most one
resistor, even in multiple device applications)
• 40 × 4-bit RAM for display data storage
• Compatible with chip-on-glass technology
• Manufactured in silicon gate CMOS process.
• Auto-incremented display data loading across device
subaddress boundaries
• Display memory bank switching in static and duplex
drive modes
2
GENERAL DESCRIPTION
• Versatile blinking modes
The PCF8576 is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments and can easily be cascaded for larger LCD
applications. The PCF8576 is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I2C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
• LCD and logic supplies may be separated
• Wide power supply range: from 2 V for low-threshold
LCDs and up to 9 V for guest-host LCDs and
high-threshold (automobile) twisted nematic LCDs
• Low power consumption
• Power-saving mode for extremely low power
consumption in battery-operated and telephone
applications
• I2C-bus interface
• TTL/CMOS compatible
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCF8576T
VSO56
plastic very small outline package; 56 leads
chip in tray
SOT190-1
PCF8576U
−
−
−
−
−
−
−
−
PCF8576U/2
PCF8576U/5
PCF8576U/7
PCF8576U/10
PCF8576U/12
chip with bumps in tray
−
unsawn wafer
−
chip with bumps on tape
FFC
FFC
chip on film frame carrier (FFC)
chip with bumps on film frame carrier (FFC)
1998 Feb 06
3
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BP0 BP2 BP1 BP3
13 14 15 16
S0 to S39
40
17 to 56
5
V
BACKPLANE
OUTPUTS
DD
DISPLAY SEGMENT OUTPUTS
DISPLAY LATCH
R
R
R
LCD
VOLTAGE
SELECTOR
LCD BIAS
GENERATOR
SHIFT REGISTER
12
V
LCD
PCF8576
4
3
CLK
INPUT
BANK
SELECTOR
DISPLAY
RAM
40 x 4 BITS
OUTPUT
BANK
SELECTOR
TIMING
BLINKER
SYNC
DISPLAY
CONTROLLER
6
OSC
OSCILLATOR
POWER-
ON
DATA
POINTER
RESET
COMMAND
DECODER
11
V
SS
2
1
SUB-
ADDRESS
COUNTER
SCL
SDA
2
INPUT
FILTERS
I C - BUS
CONTROLLER
10
7
8
9
SA0
A0 A1 A2
MBK276
Fig.1 Block diagram (for VSO56 package; SOT190-1).
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
5
PINNING
SYMBOL
PIN
DESCRIPTION
I2C-bus serial data input/output
SDA
1
SCL
SYNC
CLK
VDD
2
I2C-bus serial clock input
cascade synchronization input/output
external clock input/output
supply voltage
3
4
5
OSC
6
oscillator input
A0 to A2
7 to 9
10
I2C-bus subaddress inputs
I2C-bus slave address input; bit 0
logic ground
SA0
VSS
11
VLCD
12
LCD supply voltage
BP0, BP2, BP1 and BP3
S0 to S39
13 to 16
17 to 56
LCD backplane outputs
LCD segment outputs
1998 Feb 06
5
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
handbook, halfpage
SDA
SCL
1
2
3
4
5
6
7
8
9
56 S39
55 S38
54 S37
53 S36
52 S35
51 S34
50 S33
49 S32
48 S31
47 S30
46 S29
45 S28
44 S27
43 S26
42 S25
41 S24
40 S23
39 S22
38 S21
37 S20
36 S19
35 S18
34 S17
33 S16
32 S15
31 S14
30 S13
29 S12
SYNC
CLK
V
DD
OSC
A0
A1
A2
SA0 10
V
11
12
SS
V
LCD
BP0 13
BP2 14
BP1 15
BP3 16
S0 17
S1 18
S2 19
S3 20
S4 21
S5 22
S6 23
S7 24
S8 25
S9 26
S10 27
S11 28
PCF8576T
MBK278
Fig.2 Pin configuration; SOT190-1.
6
1998 Feb 06
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
The host microprocessor/microcontroller maintains the
2-line I2C-bus communication channel with the PCF8576.
The internal oscillator is selected by connecting pin OSC
to pin VSS. The appropriate biasing voltages for the
multiplexed LCD waveforms are generated internally.
The only other connections required to complete the
system are to the power supplies (VDD, VSS and VLCD) and
the LCD panel chosen for the application.
6
FUNCTIONAL DESCRIPTION
The PCF8576 is a versatile peripheral device designed to
interface to any microprocessor/microcontroller to a wide
variety of LCDs. It can directly drive any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments. The display configurations possible with
the PCF8576 depend on the number of active backplane
outputs required; a selection of display configurations is
given in Table 1.
All of the display configurations given in Table 1 can be
implemented in the typical system shown in Fig.3.
Table 1 Selection of display configurations
14-SEGMENTS
ALPHANUMERIC
NUMBER OF
7-SEGMENTS NUMERIC
DOT MATRIX
INDICATOR
SYMBOLS
INDICATOR
SYMBOLS
BACKPLANES SEGMENTS
DIGITS
CHARACTERS
4
3
2
1
160
120
80
20
15
10
5
20
15
10
5
10
8
20
8
160 dots (4 × 40)
120 dots (3 × 40)
80 dots (2 × 40)
40 dots (1 × 40)
5
10
12
40
2
V
DD
t
r
R
2C
B
V
V
DD
LCD
5
12
SDA
SCL
OSC
HOST
MICRO-
1
2
6
17 to 56 40 segment drives
LCD PANEL
PROCESSOR/
MICRO-
CONTROLLER
PCF8576
(up to 160
elements)
4 backplanes
13 to 16
10 11
A0 A1 A2 SA0 V
7
8
9
R
MBK277
OSC
SS
V
SS
Fig.3 Typical system configuration.
7
1998 Feb 06
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
6.3
LCD voltage selector
6.1
Power-on reset
The LCD voltage selector co-ordinates the multiplexing of
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of Vop = VDD − VLCD and the
resulting discrimination ratios (D), are given in Table 2.
At power-on the PCF8576 resets to a starting condition as
follows:
1. All backplane outputs are set to VDD
2. All segment outputs are set to VDD
.
.
3. The drive mode ‘1 : 4 multiplex with 1⁄3bias’ is selected.
4. Blinking is switched off.
5. Input and output bank selectors are reset (as defined
in Table 5).
6. The I2C-bus interface is initialized.
A practical value for Vop is determined by equating Voff(rms)
with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is Vop > 3Vth approximately.
7. The data pointer and the subaddress counter are
cleared.
Multiplex drive ratios of 1 : 3 and 1 : 4 with 1⁄2bias are
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on to allow completion of the reset action.
possible but the discrimination and hence the contrast
ratios are smaller ( 3 = 1.732 for 1 : 3 multiplex or
21
6.2
The full-scale LCD voltage (Vop) is obtained from
DD − VLCD. The LCD voltage may be temperature
LCD bias generator
= 1.528 for 1 : 4 multiplex).
----------
3
The advantage of these modes is a reduction of the LCD
full-scale voltage Vop as follows:
V
compensated externally through the VLCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an
internal voltage divider of the three series resistors
connected between VDD and VLCD. The centre resistor can
be switched out of the circuit to provide a 1⁄2bias voltage
level for the 1 : 2 multiplex configuration.
• 1 : 3 multiplex (1⁄2bias):
Vop
=
6 × Voff rms = 2.449 Voff(rms)
• 1 : 4 multiplex (1⁄2bias):
(4 × 3)
-----------------------
3
Vop
=
= 2.309 Voff(rms)
These compare with Vop = 3 Voff(rms) when 1⁄3bias is used.
Table 2 Preferred LCD drive modes: summary of characteristics
NUMBER OF
V on(rms)
Voff(rms) V on(rms)
-------------------- --------------------
LCD BIAS
CONFIGURATION
D =
--------------------
Voff(rms)
LCD DRIVE MODE
Vop
Vop
BACKPLANES
LEVELS
static
1 : 2
1 : 2
1 : 3
1 : 4
1
2
2
3
4
2
3
4
4
4
static
0
1
∞
1
⁄
2
0.354
0.333
0.333
0.333
0.791
0.745
0.638
0.577
2.236
2.236
1.915
1.732
1
⁄
3
1
⁄
3
1
⁄
3
1998 Feb 06
8
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
6.4
LCD drive mode waveforms
6.4.3
1 : 3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3
multiplex drive mode applies, as shown in Fig.7.
6.4.1
STATIC DRIVE MODE
The static LCD drive mode is used when a single
backplane is provided in the LCD. Backplane and
segment drive waveforms for this mode are shown in
Fig.4.
6.4.4
1 : 4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1 : 4
multiplex drive mode applies, as shown in Fig.8.
6.4.2
1 : 2 MULTIPLEX DRIVE MODE
When two backplanes are provided in the LCD, the 1 : 2
multiplex mode applies. The PCF8576 allows use of
1⁄2bias or 1⁄3bias in this mode as shown in Figs 5 and 6.
T
frame
LCD segments
V
DD
BP0
V
LCD
state 1
(on)
state 2
(off)
V
DD
S
n
V
LCD
V
DD
S
n
1
V
LCD
(a) waveforms at driver
V
op
0
state 1
V
op
V
op
state 2
0
V
op
(b) resultant waveforms
at LCD segment
MBE539
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = Vop
Vstate2(t) = VS (t) – VBP0(t)
n + 1
Voff(rms) = 0 V
Fig.4 Static drive mode waveforms (Vop = VDD − VLCD).
1998 Feb 06
9
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
T
frame
V
DD
LCD segments
(V
DD
V
V
)/2
)/2
BP0
LCD
LCD
V
LCD
DD
state 1
V
state 2
BP1 (V
V
DD
LCD
DD
V
S
n
V
V
LCD
DD
S
n
1
V
V
LCD
(a) waveforms at driver
op
V
/2
/2
op
0
state 1
V
V
op
op
V
op
V
/2
/2
op
0
state 2
V
V
op
op
(b) resultant waveforms
at LCD segment
MBE540
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = 0.791Vop
Vstate2(t) = VS (t) – VBP1(t)
n
Voff(rms) = 0.354Vop
Fig.5 Waveforms for the 1 : 2 multiplex drive mode with 1⁄2bias (Vop = VDD − VLCD).
1998 Feb 06
10
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
T
frame
V
DD
LCD segments
V
V
/3
op
2V /3
DD
BP0
BP1
V
V
op
DD
LCD
state 1
V
V
DD
state 2
V
/3
op
2V /3
DD
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
1
V
V
op
DD
LCD
(a) waveforms at driver
V
op
2V /3
op
V
/3
0
op
state 1
V
/3
op
2V /3
op
V
op
V
op
2V /3
op
V
V
/3
0
/3
op
state 2
op
2V /3
op
V
op
(b) resultant waveforms
at LCD segment
MBE541
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = 0.745Vop
Vstate2(t) = VS (t) – VBP1(t)
n
Voff(rms) = 0.333Vop
Fig.6 Waveforms for the 1 : 2 multiplex drive mode with 1⁄3bias (Vop = VDD − VLCD).
1998 Feb 06
11
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
T
frame
V
V
DD
LCD segments
V
/3
op
2V /3
DD
BP0
BP1
V
V
op
DD
LCD
state 1
state 2
V
V
DD
V
/3
op
2V /3
DD
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
BP2/S23
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
n
1
2
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
V
V
op
DD
LCD
(a) waveforms at driver
V
op
2V /3
op
V
/3
0
op
state 1
V
/3
op
2V /3
op
V
op
V
op
2V /3
op
V
V
/3
0
/3
op
state 2
op
2V /3
op
V
op
(b) resultant waveforms
at LCD segment
MBE542
Vstate1(t) = VS (t) – VBP0(t)
n
Von(rms) = 0.638Vop
Vstate2(t) = VS (t) – VBP1(t)
n
Voff(rms) = 0.333Vop
Fig.7 Waveforms for the 1 : 3 multiplex drive mode (Vop = VDD − VLCD).
1998 Feb 06
12
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
T
frame
V
LCD segments
DD
V
V
/3
op
2V /3
DD
BP0
BP1
BP2
BP3
V
V
op
DD
LCD
state 1
state 2
V
V
DD
V
/3
op
2V /3
DD
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
n
n
n
1
2
3
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
S
S
V
V
op
DD
LCD
V
V
DD
V
/3
op
2V /3
DD
V
V
op
DD
LCD
(a) waveforms at driver
V
op
2V /3
op
V
/3
0
op
state 1
V
/3
op
2V /3
op
V
op
V
op
2V /3
op
V
V
/3
0
/3
op
op
state 2
Vstate1(t) = VS (t) – VBP0(t)
n
2V /3
Von(rms) = 0.577Vop
op
V
op
(b) resultant waveforms
at LCD segment
Vstate2(t) = VS (t) – VBP1(t)
n
MBE543
Voff(rms) = 0.333Vop
Fig.8 Waveforms for the 1 : 4 multiplex drive mode (Vop = VDD − VLCD).
1998 Feb 06
13
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
6.5
Oscillator
6.6
Timing
The timing of the PCF8576 organizes the internal data flow
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal
SYNC maintains the correct timing relationship between
the PCF8576s in the system. The timing also generates
the LCD frame frequency which it derives as an integer
multiple of the clock frequency (see Table 3). The frame
frequency is set by the MODE SET commands when
internal clock is used, or by the frequency applied to
pin CLK when external clock is used.
6.5.1
INTERNAL CLOCK
The internal logic and the LCD drive signals of the
PCF8576 are timed either by the internal oscillator or from
an external clock. When the internal oscillator is used,
pin OSC should be connected to pin VSS. In this event, the
output from pin CLK provides the clock signal for
cascaded PCF8566s in the system.
Where resistor Rosc to VSS is present, the internal oscillator
is selected. The relationship between the oscillator
frequency on pin CLK (fclk) and Rosc is shown in Fig.9.
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power-saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.
The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I2C-bus.
MBE531
3
10
f
clk
(kHz)
When a device is unable to digest a display data byte
before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the
transmission rate of the I2C-bus but no data loss occurs.
max
2
10
min
Table 3 LCD frame frequencies
NOMINAL
10
10
FRAME
FREQUENCY
FRAME
FREQUENCY
(Hz)
2
3
4
10
R
(kΩ)
10
PCF8576 MODE
osc
3.4 × 107
fclk
fclk
≈
----------------------- (kHz)
Rosc
Normal mode
64
64
------------
2880
f clk
Fig.9 Oscillator frequency as a function of Rosc
.
Power-saving mode
---------
480
6.5.2
EXTERNAL CLOCK
6.7
Display latch
The condition for external clock is made by connecting
pin OSC to pin VDD; pin CLK then becomes the external
clock input.
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
The clock frequency (fclk) determines the LCD frame
frequency and the maximum rate for data reception from
the I2C-bus. To allow I2C-bus transmissions at their
maximum data rate of 100 kHz, fclk should be chosen to be
above 125 kHz.
6.8
Shift register
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data is displayed.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
1998 Feb 06
14
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
correspondence between the RAM addresses and the
segment outputs, and between the individual bits of a RAM
word and the backplane outputs. The first RAM column
corresponds to the 40 segments operated with respect to
backplane BP0 (see Fig.10). In multiplexed LCD
applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed
with BP1, BP2 and BP3 respectively.
6.9
Segment outputs
The LCD drive section includes 40 segment outputs
pins S0 to S39 which should be connected directly to the
LCD. The segment output signals are generated in
accordance with the multiplexed backplane signals and
with data resident in the display latch. When less than
40 segment outputs are required the unused segment
outputs should be left open-circuit.
When display data is transmitted to the PCF8576 the
display bytes received are stored in the display RAM in
accordance with the selected LCD drive mode.
To illustrate the filling order, an example of a 7-segment
numeric display showing all drive modes is given in Fig.11;
the RAM filling organization depicted applies equally to
other LCD types.
6.10 Backplane outputs
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open-circuit. In the 1 : 3 multiplex drive mode
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be connected together to give
enhanced drive capabilities. In the 1 : 2 multiplex drive
mode BP0 and BP2, BP1 and BP3 respectively carry the
same signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
With reference to Fig.11, in the static drive mode the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses. In the 1 : 2 multiplex drive mode
the eight transmitted data bits are placed in bits 0 and 1 of
four successive display RAM addresses. In the 1 : 3
multiplex drive mode these bits are placed in
bits 0, 1 and 2 of three successive addresses, with bit 2 of
the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding
adjacent data because full bytes are always transmitted.
In the 1 : 4 multiplex drive mode the eight transmitted data
bits are placed in bits 0, 1, 2 and 3 of two successive
display RAM addresses.
6.11 Display RAM
The display RAM is a static 40 × 4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the on
state of the corresponding LCD segment; similarly, a
logic 0 indicates the off state. There is a one-to-one
display RAM addresses (rows) / segment outputs (S)
0
1
2
3
4
35 36 37 38 39
0
1
2
3
display RAM bits
(columns) /
backplane outputs
(BP)
MBE525
Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,
and between bits in a RAM word and backplane outputs.
1998 Feb 06
15
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
The PCF8576 includes a RAM bank switching feature in
the static and 1 : 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
the contents of bit 2 to be selected for display instead of
bit 0 contents. In the 1 : 2 drive mode, the contents of
bits 2 and 3 may be selected instead of bits 0 and 1.
This gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it
is assembled.
6.12 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM. The sequence
commences with the initialization of the data pointer by the
LOAD DATA POINTER command. Following this, an
arriving data byte is stored starting at the display RAM
address indicated by the data pointer thereby observing
the filling order shown in Fig.11. The data pointer is
automatically incremented in accordance with the chosen
LCD configuration. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1 : 2 multiplex drive mode) or
by two (1 : 4 multiplex drive mode).
6.15 Input bank selector
The input bank selector loads display data into the display
RAM in accordance with the selected LCD drive
configuration. Display data can be loaded in bit 2 in static
drive mode or in bits 2 and 3 in 1 : 2 drive mode by using
the BANK SELECT command. The input bank selector
functions independent of the output bank selector.
6.13 Subaddress counter
The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to A0, A1
and A2. The subaddress counter value is defined by the
DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddress do not
agree then data storage is inhibited but the data pointer is
incremented as if data storage had taken place.
The subaddress counter is also incremented when the
data pointer overflows.
6.16 Blinker
The display blinking capabilities of the PCF8576 are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, as shown in
Table 4.
An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and
1 : 2 LCD drive modes and can be implemented without
any communication overheads. By means of the output
bank selector, the displayed RAM banks are exchanged
with alternate RAM banks at the blinking frequency.
This mode can also be specified by the BLINK command.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8576 occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character (such as during the 14th display data byte
transmitted in 1 : 3 multiplex mode).
In the 1 : 3 and 1 : 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.
If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bit E
at the required rate using the MODE SET command.
6.14 Output bank selector
This selects one of the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence. In 1 : 4
multiplex, all RAM addresses of bit 0 are the first to be
selected, these are followed by the contents of bit 1, bit 2
and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2
are selected sequentially. In 1 : 2 multiplex, bits 0 and 1
are selected and, in the static mode, bit 0 is selected.
1998 Feb 06
16
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
Table 4 Blinking frequencies
NORMAL OPERATING
BLINKING MODE
POWER-SAVING MODE
RATIO
NOMINAL BLINKING
FREQUENCY
MODE RATIO
Off
−
−
blinking off
fclk
f clk
2 Hz
2 Hz
----------------
92160
----------------
15360
f clk
f clk
1 Hz
1 Hz
-------------------
184320
----------------
30720
f clk
f clk
0.5 Hz
0.5 Hz
-------------------
368640
----------------
61440
1998 Feb 06
17
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drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
a
S
2
n
n
1
n
2
n
3
n
4
n
5
n
6
n 7
n
n
b
BP0
f
S
1
7
S
3
MSB
LSB
DP
n
n
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP
bit/
BP
g
4
S
S
S
n
n
x
x
x
x
x
x
c
b
a
f
g e d
static
e
S
5
6
c
n
d
DP
S
n
BP0
S
n
a
n
n
n
n
1
1
1
n
2
n 3
b
b
b
1 : 2
f
S
1
n
MSB
LSB
DP
0
1
2
3
a
b
x
x
f
e
c
x
x
d
bit/
BP
g
g
x
x
DP
x
x
a
b
f
g
e c d
BP1
S
S
e
2
3
multiplex
n
n
c
c
c
d
d
d
DP
BP0
BP1
S
1
a
n
n
n 2
S
S
2
f
1 : 3
n
n
MSB
LSB
e
0
1
2
3
b
DP
c
a
d
g
x
f
bit/
BP
g
e
x
x
BP2
b DP
c
a
d
g
f
e
multiplex
x
DP
S
n
a
n
BP2
BP3
BP0
BP1
f
1 : 4
0
1
2
3
a
c
f
bit/
BP
MSB
LSB
d
g
e
g
d
b
DP
e
multiplex
a
c
b
DP
f
e
g
S
1
DP
n
MBK389
x = data bit unchanged.
Fig.11 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
7
CHARACTERISTICS OF THE I2C-BUS
7.5
PCF8576 I2C-bus controller
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
The PCF8576 acts as an I2C-bus slave receiver. It does
not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8576
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.
In single device application, the hardware subaddress
inputs A0, A1 and A2 are normally connected to VSS which
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are connected to VSS or VDD in
accordance with a binary coding scheme such that no two
devices with a common I2C-bus slave address have the
same hardware subaddress.
7.1
Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
7.2
START and STOP conditions (see Fig.13)
In the power-saving mode it is possible that the PCF8576
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8576 forces the SCL line to LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I2C-bus and
serves to slow down fast transmitters. Data loss does not
occur.
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
7.3
System configuration (see Fig.14)
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
7.6
Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.4
Acknowledge (see Fig.15)
7.7
I2C-bus protocol
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
Two I2C-bus slave addresses (0111000 and 0111001) are
reserved for the PCF8576. The least significant bit of the
slave address that a PCF8576 will respond to is defined by
the level connected at its input pin SA0. Therefore, two
types of PCF8576 can be distinguished on the same
I2C-bus which allows:
• Up to 16 PCF8576s on the same I2C-bus for very large
LCD applications
• The use of two types of LCD multiplex on the same
I2C-bus.
The I2C-bus protocol is shown in Fig.16. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of the two PCF8576 slave
addresses available. All PCF8576s with the corresponding
SA0 level acknowledge in parallel with the slave address
but all PCF8576s with the alternative SA0 level ignore the
whole I2C-bus transfer.
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
After acknowledgement, one or more command bytes (m)
follow which define the status of the addressed PCF8576s.
7.8
Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. All available commands carry a
continuation bit C in their most significant bit position
(Fig.17). When this bit is set, it indicates that the next byte
of the transfer to arrive will also represent a command.
If this bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.
The last command byte is tagged with a cleared most
significant bit, the continuation bit C. The command bytes
are also acknowledged by all addressed PCF8576s on the
bus.
After the last command byte, a series of display data bytes
(n) may follow. These display bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data is directed to the intended PCF8576 device.
The five commands available to the PCF8576 are defined
in Table 5.
The acknowledgement after each byte is made only by the
(A0, A1 and A2) addressed PCF8576. After the last display
byte, the I2C-bus master issues a STOP condition (P).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.12 Bit transfer.
SDA
SCL
SDA
SCL
S
P
STOP condition
START condition
MBC622
Fig.13 Definition of START and STOP conditions.
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.14 System configuration.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
MASTER
1
2
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.15 Acknowledgement on the I2C-bus.
21
1998 Feb 06
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
acknowledge
by A0, A1 and A2
selected
acknowledge by
all addressed
PCF8576s
R / W
PCF8576 only
slave address
S
A
0
0
1
1
1
0
0
0
A C
A
DISPLAY DATA
A
P
COMMAND
S
1 byte
n
1 byte(s)
n
0 byte(s)
update data pointers
and if necessary,
subaddress counter
MBK279
Fig.16 I2C-bus protocol.
MSB
LSB
C
REST OF OPCODE
MSA833
C = 0; last command.
C = 1; commands continue.
Fig.17 General format of command byte.
22
1998 Feb 06
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
Table 5 Definition of PCF8576 commands
COMMAND
OPCODE
LP
OPTIONS
DESCRIPTION
MODE SET C 1
0
E
B
M1 M0
Table 6 Defines LCD drive mode.
Table 7 Defines LCD bias configuration.
Table 8 Defines display status. The possibility to disable the
display allows implementation of blinking under
external control.
Table 9 Defines power dissipation mode.
LOADDATA C 0 P5 P4 P3 P2 P1 P0 Table 10 Six bits of immediate data, bits P5 to P0, are
POINTER
transferred to the data pointer to define one of forty
display RAM addresses.
DEVICE
SELECT
C 1
C 1
1
1
0
1
0
1
A2 A1 A0
Table 11 Three bits of immediate data, bits A2 to A0, are
transferred to the subaddress counter to define one of
eight hardware subaddresses.
BANK
SELECT
0
I
O
Table 12 Defines input bank selection (storage of arriving
display data).
Table 13 Defines output bank selection (retrieval of LCD display
data). The BANK SELECT command has no effect in
1 : 3 and 1 : 4 multiplex drive modes.
BLINK
C 1
1
1
0
A
BF1 BF0 Table 14 Defines the blinking frequency.
Table 15 Selects the blinking mode; normal operation with
frequency set by BF1, BF0 or blinking by alternation of
display RAM banks. Alternation blinking does not
apply in 1 : 3 and 1 : 4 multiplex drive modes.
Table 6 MODE SET option 1
Table 9 MODE SET option 4
LCD DRIVE MODE
BITS
MODE
Normal mode
Power-saving mode
BIT LP
0
1
DRIVE MODE
Static
BACKPLANE
1 BP
M1
0
M0
1
1 : 2
MUX (2 BP)
MUX (3 BP)
MUX (4 BP)
1
0
Table 10 LOAD DATA POINTER option 1
1 : 3
1
1
DESCRIPTION
BITS
1 : 4
0
0
6-bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0
Table 7 MODE SET option 2
Table 11 DEVICE SELECT option 1
LCD BIAS
1⁄3bias
1⁄2bias
BIT B
DESCRIPTION
BITS
0
1
3-bit binary value of 0 to 7
A2
A1
A0
Table 12 BANK SELECT option 1
Table 8 MODE SET option 3
STATIC
RAM bit 0
RAM bit 2
1 : 2 MUX
BIT I
DISPLAY STATUS
BIT E
RAM bits 0 and 1
RAM bits 2 and 3
0
1
Disabled (blank)
Enabled
0
1
1998 Feb 06
23
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
Table 13 BANK SELECT option 2
7.10 Cascaded operation
In large display configurations, up to 16 PCF8576s can be
distinguished on the same I2C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
STATIC
RAM bit 0
RAM bit 2
1 : 2 MUX
BIT O
RAM bits 0 and 1
RAM bits 2 and 3
0
1
programmable I2C-bus slave address (SA0). When
cascaded PCF8576s are synchronized so that they can
share the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other PCF8576s of the
cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (see Fig.18).
Table 14 BLINK option 1
BITS
BLINK FREQUENCY
BF1
BF0
Off
0
0
1
1
0
1
0
1
2 Hz
1 Hz
0.5 Hz
The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8576s.
This synchronization is guaranteed after the Power-on
reset. The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when PCF8576s with differing SA0 levels
are cascaded). SYNC is organized as an input/output pin;
the output selection being realized as an open-drain driver
with an internal pull-up resistor. A PCF8576 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times. Should
synchronization in the cascade be lost, it will be restored
by the first PCF8576 to assert SYNC. The timing
relationship between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8576
are shown in Fig.19.
Table 15 BLINK option 2
BLINK MODE
BIT A
Normal blinking
0
1
Alternation blinking
7.9
Display controller
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8576 and co-ordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
For single plane wiring of packaged PCF8576s and
chip-on-glass cascading, see Chapter 12.
1998 Feb 06
24
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
V
V
LCD
DD
SDA
1
5
12
40 segment drives
SCL
17 to 56
2
LCD PANEL
SYNC
3
PCF8576
CLK
(up to 2560
elements)
4
13, 15
14, 16
OSC
6
BP0 to BP3
(open-circuit)
7
8
9
10 11
A0 A1 A2 SA0 V
SS
V
V
LCD
t
DD
r
R
V
V
2C
DD
LCD
B
5
12
SDA
SCL
HOST
MICRO-
1
2
3
4
6
40 segment drives
17 to 56
PROCESSOR/
MICRO-
PCF8576
SYNC
CLK
13, 15
14, 16
4 backplanes
BP0 to BP3
CONTROLLER
OSC
MBK280
7
8
9
10 11
A0 A1 A2 SA0 V
V
SS
SS
Fig.18 Cascaded PCF8576 configuration.
25
1998 Feb 06
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
1
T
= f
frame
frame
BP0
SYNC
(a) static drive mode.
BP1
(1/2 bias)
BP1
(1/3 bias)
SYNC
(b) 1 : 2 multiplex drive mode.
BP2
SYNC
(c) 1 : 3 multiplex drive mode.
BP3
SYNC
MBE535
(d) 1 : 4 multiplex drive mode.
Excessive capacitive coupling between SCL or CLK and SYNC may cause erroneous synchronization. If this proves to be a problem, the capacitance
of the SYNC line should be increased (e.g. by an external capacitor between SYNC and VDD). Degradation of the positive edge of the SYNC pulse may
be countered by an external pull-up resistor.
Fig.19 Synchronization of the cascade for the various PCF8576 drive modes.
1998 Feb 06
26
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
8
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
VDD
MIN.
MAX.
+11.0
DD − 11.0 VDD
UNIT
supply voltage
−0.5
V
V
V
V
VLCD
VI
LCD supply voltage
V
V
V
−
−
−
−
−
input voltage SDA, SCL, CLK, SYNC, SA0, OSC, A0 to A2
output voltage S0 to S39, BP0 to BP3
DC input current
SS − 0.5
VDD + 0.5
VO
II
LCD − 0.5 VDD + 0.5
20
mA
mA
mA
mW
mW
°C
IO
DC output current
25
IDD, ISS, ILCD VDD, VSS or VLCD current
50
Ptot
PO
Tstg
total power dissipation
power dissipation per output
storage temperature
400
100
−65
+150
9
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
1998 Feb 06
27
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
10 DC CHARACTERISTICS
VDD = 2 to 9 V; VSS = 0 V; VLCD = VDD − 2 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
VLCD
IDD
supply voltage
2
−
9
V
LCD supply voltage
supply current
note 1
note 2
V
DD − 9
−
V
DD − 2
V
normal mode
fclk = 200 kHz
clk = 35 kHz; VDD = 3.5 V;
LCD = 0 V; A0, A1 and A2
−
−
−
−
180
60
µA
µA
power-saving mode
f
V
connected to VSS
Logic
VIL
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
HIGH-level output voltage
VSS
0.7VDD
−
−
−
−
0.3VDD
VDD
0.05
−
V
VIH
V
VOL
VOH
IOL1
IOL = 0 mA
V
IOH = 0 mA
VDD − 0.05 −
V
LOW-level output current
CLK, SYNC
VOL = 1 V; VDD = 5 V
1
−
−
mA
IOH1
IOL2
HIGH-level output current CLK
VOH = 4 V; VDD = 5 V
VOL = 0.4 V; VDD = 5 V
1
3
−
−
−
−
mA
mA
LOW-level output current
SDA and SCL
IL1
leakage current SA0, A0 to A2,
CLK, SDA and SCL
VI = VDD or VSS
−
−
1
µA
IL2
Ipd
leakage current OSC
VI = VDD
−
−
1
µA
µA
A0, A1, A2 and OSC pull-down
current
VI = 1 V; VDD = 5 V
20
50
150
RSYNC
VPOR
CI
pull-up resistor (SYNC)
Power-on reset voltage level
input capacitance
20
−
50
1.0
−
150
1.6
7
kΩ
V
note 3
note 4
−
pF
LCD outputs
VBP
VS
DC voltage component BP0 to BP3 CBP = 35 nF
−
−
−
−
20
20
−
−
mV
mV
kΩ
kΩ
DC voltage component S0 to S39
output resistance BP0 to BP3
output resistance S0 to S39
CS = 5 nF
−
RBP
RS
note 5; VLCD = VDD − 5 V
note 5; VLCD = VDD − 5 V
5
−
7.5
Notes
1. VLCD ≤ VDD − 3 V for 1⁄3bias.
2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.
3. Resets all logic when VDD < VPOR
.
4. Periodically sampled, not 100% tested.
5. Outputs measured one at a time.
1998 Feb 06
28
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
11 AC CHARACTERISTICS
VDD = 2 to 9 V; VSS = 0 V; VLCD = VDD − 2 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
fclk
oscillator frequency on pin CLK
normal mode
V
DD = 5 V; note 1
DD = 3.5 V
125
21
1
200
31
−
288
48
−
kHz
kHz
µs
power-saving mode
CLK HIGH time
V
tclkH
see Fig.21
tclkL
CLK LOW time
1
−
−
µs
tPSYNC
tSYNCL
tPLCD
SYNC propagation delay time
SYNC LOW time
−
−
400
−
ns
1
−
µs
driver delays with test loads
VLCD = VDD − 5 V; see Fig.20
−
−
30
µs
Timing characteristics: I2C-bus; note 2; see Fig.22
tSW
tolerable spike width on bus
bus free time
−
−
−
−
−
−
−
−
−
−
−
−
−
100
−
ns
µs
µs
µs
µs
µs
µs
µs
pF
ns
ns
µs
tBUF
4.7
4.0
4.7
4.7
4.0
−
tHD;STA
tSU;STA
tLOW
tHIGH
tr
START condition hold time
set-up time for a repeated START condition
SCL LOW time
−
−
−
SCL HIGH time
−
SCL and SDA rise time
SCL and SDA fall time
capacitive bus line load
data set-up time
1
tf
−
0.3
400
−
CB
−
tSU;DAT
tHD;DAT
tSU;STO
250
0
data hold time
−
set-up time for STOP condition
4.0
−
Notes
1. At fclk < 125 kHz, I2C-bus maximum transmission speed is derated.
2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD
.
6.8 Ω
SYNC
CLK
V
DD
(2%)
3.3 kΩ
1.5 kΩ
SDA,
SCL
V
0.5V
DD
DD
(2%)
(2%)
1 nF
BP0 to BP3, and
S0 to S39
V
DD
MBE544
Fig.20 Test loads.
29
1998 Feb 06
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
1/ f
clk
t
t
clkL
clkH
0.7V
0.3V
DD
CLK
DD
0.7V
0.3V
DD
SYNC
DD
t
t
PSYNC
PSYNC
SYNCL
t
0.5 V
BP0 to BP3,
and S0 to S39
(V
= 5 V)
DD
0.5 V
t
PLCD
MBE545
Fig.21 Driver timing waveforms.
n
SDA
SCL
t
t
t
f
BUF
LOW
t
t
t
t
HD;STA
r
t
HIGH
HD;DAT
SU;DAT
SDA
t
SU;STA
MGA728
t
SU;STO
Fig.22 I2C-bus timing waveforms.
30
1998 Feb 06
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
11.1 Typical supply current characteristics
MBE529
MBE530
50
50
40
I
I
SS
LCD
(µA)
(µA)
normal
mode
40
30
20
30
20
power-saving
mode
10
0
10
0
0
100
200
f
(Hz)
0
100
200
f
(Hz)
frame
frame
VDD = 5 V; VLCD = 0 V; Tamb = 25 °C.
VDD = 5 V; VLCD = 0 V; Tamb = 25 °C.
Fig.23 −ISS as a function of fframe
.
Fig.24 −ILCD as a function of fframe.
MBE528 - 1
MBE527 - 1
50
50
handbook, halfpage
handbook, halfpage
I
I
LCD
(µA)
SS
(µA)
normal mode
= 200 kHz
40
40
85oC
f
clk
30
20
30
20
25oC
40oC
power-saving mode
10
f
= 35 kHz
10
clk
0
0
0
0
5
10
5
10
V
(V)
V
(V)
DD
DD
VLCD = 0 V; external clock; Tamb = 25 °C.
VLCD = 0 V; external clock; fclk = nominal frequency.
Fig.25 ISS as a function of VDD
.
Fig.26 ILCD as a function of VDD.
1998 Feb 06
31
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
11.2 Typical characteristics of LCD outputs
MBE532 - 1
MBE526
2.5
O(max)
(kΩ)
10
handbook, halfpage
R
S
R
R
O(max)
(kΩ)
2.0
R
S
1.5
1.0
1
R
R
BP
BP
0.5
0
-1
10
40
0
40
80
120
( C)
amb
0
3
6
o
V
(V)
T
DD
VDD = 5 V; VLCD = 0 V.
VLCD = 0 V; Tamb = 25 °C.
Fig.27 RO(max) as a function of VDD
.
Fig.28 RO(max) as a function of Tamb.
1998 Feb 06
32
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g
SDA
SCL
SYNC
CLK
V
DD
V
SS
V
LCD
SDA
SCL
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
SYNC
CLK
3
3
4
4
V
5
5
DD
OSC
A0
6
6
7
7
A1
8
8
A2
9
9
SA0
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
V
SS
V
LCD
BP0
BP2
BP1
BP3
S0
BP0
BP2
BP1
BP3
S40
S41
S42
S43
open
PCF8576T
PCF8576T
S1
S2
S3
34
33
32
31
30
29
S17
S16
S15
34
33
32
31
30
29
S57
S56
S55
S7
S8
24
25
26
27
28
S47
S48
S49
S50
S51
24
25
26
27
28
S9
S14
S13
S12
S54
S53
S52
S10
S11
S0
S10
S11
S12
S13
S39
S40
S50
S51
S52
S53
S79
MBK281
backplanes
segments
Fig.29 Single plane wiring of packaged PCF8576Ts.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
and the backplane output pads. The only bus line that does
not require a second opening to lead through to the next
PCF8576 is VLCD, being the cascade centre. The placing
of VLCD adjacent to VSS allows the two supplies to be
connected together.
12.1 Chip-on-glass cascadability in single plane
In chip-on-glass technology, where driver devices are
bonded directly onto glass of the LCD, it is important that
the devices may be cascaded without the crossing of
conductors, but the paths of conductors can be continued
on the glass under the chip. All of this is facilitated by the
PCF8576 bonding pad layout (see Fig.30). Pads needing
bus interconnection between all PCF8576s of the cascade
are VDD, VSS, VLCD, CLK, SCL, SDA and SYNC. These
lines may be led to the corresponding pads of the next
PCF8576 through the wide opening between VLCD pad
When an external clocking source is to be used, OSC of all
devices should be connected to VDD
.
The pads OSC, A0, A1, A2 and SA0 have been placed
between VSS and VDD to facilitate wiring of oscillator,
hardware subaddress and slave address.
13 BONDING PAD LOCATIONS
34
35
36
33 32 31 30 29 28 27 26 25 24
23
22
21
20
19
18
17
16
15
14
13
S3
S18
S19
S2
S1
37
38
39
40
41
42
S20
S21
S22
S23
S24
S25
S0
BP3
BP1
BP2
BP0
x
4.12
mm
0
0
y
43
44
45
46
47
48
S26
S27
S28
S29
S30
S31
PCF8576
cascade
centre
V
12
11
10
9
LCD
V
SS
49
50
51
S32
S33
SA0
A2
52 53 54 55 56
1
2
3
4
5
6
7
8
3.07 mm
MBK282
Bonding pad dimensions: 120 × 120 µm.
Fig.30 Bonding pad locations.
34
1998 Feb 06
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
Table 16 Bonding pad locations (dimensions in µm)
All x/y coordinates are referenced to centre of chip
(see Fig.30).
SYMBOL
SDA
PAD
x
y
SYMBOL
S12
PAD
x
y
1
−155
45
−1900
−1900
−1900
−1900
−1900
−1900
−1900
−1900
−1700
−1500
−1300
−1100
300
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
−355
−555
−755
−955
1900
1900
1900
1900
SCL
SYNC
CLK
VDD
OSC
A0
2
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
3
245
4
445
5
645
−1155
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1375
−1155
−955
1900
1900
1660
1420
1200
1000
800
6
865
7
1105
1375
1375
1375
1375
1375
1375
1375
1375
1375
1375
1375
1375
1375
1375
1105
865
A1
8
A2
9
SA0
VSS
VLCD
BP0
BP2
BP1
BP3
S0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
600
400
500
200
700
−200
−400
−600
−800
−1000
−1200
−1420
−1660
−1900
−1900
−1900
−1900
−1900
−900
900
1100
1300
1500
1700
1900
1900
1900
1900
1900
1900
1900
1900
S1
S2
S3
S4
S5
S6
S7
645
S8
445
S9
245
−755
S10
S11
45
−555
−155
−355
1998 Feb 06
35
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
14 PACKAGE OUTLINE
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
H
v
M
A
E
Z
56
29
Q
p
A
2
A
(A )
3
A
1
pin 1 index
θ
L
L
detail X
1
28
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(2)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
0.3
0.1
3.0
2.8
0.42
0.30
0.22 21.65 11.1
0.14 21.35 11.0
15.8
15.2
1.6
1.4
1.45
1.30
0.90
0.55
3.3
0.25
0.01
0.75
2.25
0.2
0.1
0.1
7o
0o
0.012 0.12
0.004 0.11
0.017 0.0087 0.85
0.012 0.0055 0.84
0.44
0.43
0.62
0.60
0.063 0.057
0.055 0.051
0.035
0.022
inches
0.008 0.004 0.004
0.0295
0.089
0.13
Note
1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
96-04-02
97-08-11
SOT190-1
1998 Feb 06
36
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
15 SOLDERING
15.3 Wave soldering
Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:
15.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
15.2 Reflow soldering
Reflow soldering techniques are suitable for all VSO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
15.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1998 Feb 06
37
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
16 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Feb 06
38
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8576
NOTES
1998 Feb 06
39
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Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Uruguay: see South America
Vietnam: see Singapore
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/03/pp40
Date of release: 1998 Feb 06
Document order number: 9397 750 03252
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