PCF8578H/1,118 [NXP]
IC LIQUID CRYSTAL DISPLAY DRIVER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64, Display Driver;
| 型号： | PCF8578H/1,118 |
| 厂家： | 
NXP |
| 描述： | IC LIQUID CRYSTAL DISPLAY DRIVER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64, Display Driver 驱动 接口集成电路 |
| 文件： | 总46页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCF8578
LCD row/column driver for dot matrix graphic displays
Rev. 06 — 5 May 2009
Product data sheet
1. General description
The PCF8578 is a low power CMOS1 LCD row and column driver, designed to drive dot
matrix graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has
40 outputs, of which 24 are programmable and configurable for the following ratios of
rows/columns: 32⁄8, 24⁄16, 16 24 or 8⁄32. The PCF8578 can function as a stand-alone LCD
⁄
controller and driver for use in small systems. For larger systems it can be used in
conjunction with up to 32 PCF8579s for which it has been optimized. Together these two
devices form a general purpose LCD dot matrix driver chip set, capable of driving displays
of up to 40960 dots. The PCF8578 is compatible with most microcontrollers and
communicates via a two-line bidirectional bus (I2C-bus). Communication overhead is
minimized by a display RAM with auto-incremented addressing and display bank
switching.
2. Features
I Single chip LCD controller and driver
I Stand-alone or may be used with up to 32 PCF8579s (40960 dots possible)
I 40 driver outputs, configurable for several ratios of rows/columns: 32⁄8, 24⁄16, 16
I Selectable multiplex rates: 1:8, 1:16, 1:24 or 1:32
I Externally selectable bias configuration, 5 or 6 levels
I 1280-bit RAM for display data storage and scratch pad
I Display memory bank switching
⁄
24 or 8⁄32
I Auto-incremented data loading across hardware subaddress boundaries (with
PCF8579)
I Provides display synchronization for PCF8579
I On-chip oscillator, requires only 1 external resistor
I Power-On Reset (POR) blanks display
I Logic voltage supply range 2.5 V to 6 V
I Maximum LCD supply voltage 9 V
I Low power consumption
I I2C-bus interface
I Compatible with most microcontrollers
I Optimized pinning for single plane wiring in multiple device applications (with
PCF8579)
I Space saving 56-lead small outline package and 64 pin quad flat pack
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 15.
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
3. Applications
I Automotive information systems
I Telecommunication systems
I Point-of-sale terminals
I Industrial computer terminals
I Instrumentation
4. Ordering information
Table 1.
Ordering information
Type number Package
Name
Description
Version
PCF8578T/1
PCF8578H/1
VSO56
plastic very small outline package; 56 leads
SOT190-1
SOT314-2
LQFP64 plastic low profile quad flat package; 64 leads; body
10 × 10 × 1.4 mm[1]
PCF8578HT/1 TQFP64 plastic thin quad flat package; 64 leads;
SOT357-1
body 10 × 10 × 1.0 mm
[1] Should not be used for new designs.
5. Marking
Table 2.
Marking codes
Type number
PCF8578T/1
PCF8578H/1
PCF8578HT/1
Marking code
PCF8578T
PCF8578H
PCF8578HT
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
2 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
6. Block diagram
C39 - C32
R31/C31 - R8/C8
R7 - R0
V
DD
V
V
V
V
2
3
4
5
(1)
ROW/COLUMN
PCF8578
DRIVERS
V
LCD
TEST
DISPLAY
MODE
OUTPUT
CONTROLLER
CONTROLLER
Y DECODER
AND SENSING
AMPLIFIERS
32 × 40-BIT
DISPLAY RAM
DISPLAY
DECODER
X DECODER
SYNC
CLK
SUBADDRESS
COUNTER
TIMING
GENERATOR
POWER-ON
RESET
RAM DATA POINTER
Y
X
OSC
SCL
SDA
2
INPUT
FILTERS
I C-BUS
CONTROLLER
COMMAND
DECODER
OSCILLATOR
R
ext(OSC)
V
SS
msa842
n.c.
n.c.
SA0
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
Fig 1. Block diagram
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
3 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
7. Pinning information
7.1 Pinning
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SDA
SCL
R0
2
R1
3
SYNC
CLK
R2
4
R3
5
V
SS
R4
6
TEST
SA0
R5
7
R6
8
OSC
R7
9
V
DD
R8/C8
R9/C9
R10/C10
R11/C11
R12/C12
R13/C13
R14/C14
R15/C15
R16/C16
R17/C17
R18/C18
R19/C19
R20/C20
R21/C21
R22/C22
R23/C23
R24/C24
R25/C25
R26/C26
R27/C27
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
2
V
3
V
4
V
5
V
LCD
PCF8578T
n.c.
n.c.
C39
C38
C37
C36
C35
C34
C33
C32
R31/C31
R30/C30
R29/C29
R28/C28
001aaj842
Top view. For mechanical details, see Figure 29.
Fig 2. Pinning diagram of PCF8578T/1 (VSO56)
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
4 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R5
R4
R22/C22
n.c.
3
R3
R23/C23
R24/C24
R25/C25
R26/C26
R27/C27
R28/C28
R29/C29
R30/C30
R31/C31
C32
4
R2
5
R1
6
R0
7
SDA
SCL
SYNC
CLK
8
PCF8578H
9
10
11
12
13
14
15
16
V
SS
TEST
SA0
n.c.
n.c.
C33
n.c.
C34
OSC
C35
001aaj840
Top view. For mechanical details, see Figure 30.
Fig 3. Pinning diagram of PCF8578H/1 (LQFP64)
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
5 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R5
R4
R22/C22
n.c.
3
R3
R23/C23
R24/C24
R25/C25
R26/C26
R27/C27
R28/C28
R29/C29
R30/C30
R31/C31
C32
4
R2
5
R1
6
R0
7
SDA
SCL
SYNC
CLK
8
PCF8576HT
9
10
11
12
13
14
15
16
V
SS
TEST
SA0
n.c.
n.c.
C33
n.c.
C34
OSC
C35
001aaj911
Top view. For mechanical details, see Figure 31.
Fig 4. Pinning diagram of PCF8578HT/1 (TQFP64)
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
6 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
VSO56
LQFP64,
TQFP64
SDA
1
7
I2C-bus serial data input/output
I2C-bus serial clock input
cascade synchronization output
external clock input/output
ground
SCL
2
8
SYNC
CLK
3
9
4
10
VSS
5
11
TEST[1]
6
12
test pin
SA0
7
13
I2C-bus slave address input (bit 0)
OSC
VDD
8
16
oscillator input
9
20
supply voltage
V2 to V5
VLCD
n.c.
10 to 13
14
21 to 24
25
LCD bias voltage inputs
LCD supply voltage
not connected
15, 16
14, 15,
17 to 19,
26 to 28, 36,
47
C39 to C32
17 to 24
25 to 48
29 to 35, 37
LCD column driver outputs
R31/C31 to R8/C8
38 to 46,
48 to 62
LCD row and column driver outputs
R7 to R0
49 to 56
63, 64, 1 to 6 LCD row driver outputs
.
[1] The TEST pin must be connected to VSS
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
7 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
8. Functional description
8.1 Display configurations
The PCF8578 row and column driver is designed for use in one of three ways:
• Stand-alone row and column driver for small displays (mixed mode)
• Row and column driver with cascaded PCF8579s (mixed mode)
• Row driver with cascaded PCF8579s (mixed mode and row mode)
Table 4.
Possible display configurations
Applicatio Multiplex rate Mixed mode
Row mode
Columns Rows Columns
Typical applications
n
Rows
8
stand alone 1:8
1:16
32
-
-
-
-
-
small digital or
alphanumeric displays
16
24
-
-
-
1:24
1:32
1:8
24
16
32
8[1]
16[1]
24[1]
32[1]
8
with
PCF8579
632[1]
624[1]
616[1]
608[1]
8 × 4[2] 640[2]
16 × 2[2] 640[2]
alphanumeric displays
and dot matrix graphic
displays
1:16
1:24
1:32
24[2]
32[2]
640[2]
640[2]
[1] Using 15 PCF8579s.
[2] Using 16 PCF8579s.
In mixed mode, the device functions as both a row and column driver. It can be used in
small stand-alone applications, or for larger displays with up to 15 PCF8579s
(31 PCF8579s when two slave addresses are used). See Table 4 for common display
configurations.
In row mode, the device functions as a row driver with up to 32 row outputs and provides
the clock and synchronization signals for the PCF8579. Up to 16 PCF8579s can normally
be cascaded (32 when two slave addresses are used).
Timing signals are derived from the on-chip oscillator, whose frequency is determined by
the value of the resistor connected between pin OSC and pin VSS
.
Five commands are available to configure and control the operation of the device.
Communication is made via a two-line bidirectional I2C-bus. The device may have one of
two slave addresses. The only difference between these slave addresses is the least
significant bit, which is set by the logic level applied to SA0. The PCF8578 and PCF8579
have different subaddresses. The subaddress of the PCF8578 is only defined in mixed
mode and is fixed at 0111 100 (see Section 8.8.7 on page 19). The RAM may only be
accessed in mixed mode and data is loaded as described for the PCF8579.
Bias levels may be generated by an external potential divider with appropriate decoupling
capacitors. For large displays, bias sources with high drive capability should be used. A
typical mixed mode system operating with up to 15 PCF8579s is shown in Figure 5 (a
stand-alone system would be identical but without the PCF8579).
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
8 of 46
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LCD DISPLAY
n
rows
40
columns
n
V
V
V
V
V
V
DD
DD
2
40
columns
R1
R2
R3
R2
R1
C
C
C
C
C
3
4
5
V
V
V
V
A0
A1
DD
DD
LCD
SS
HOST
MICROCONTROLLER
V
LCD
subaddress 1
/V
PCF8578
PCF8579
V
SS DD
V
A2
A3
SS
SCL
SDA
V
/V
SS DD
SA0
V
V
3
CLK SYNC
4
SDA SCL
V
V
LCD
SA0
V
/V
SS DD
SS
OSC
V
V
LCD
R
ext(OSC)
SS
CLK SYNC
SDA SCL
msa843
Fig 5. Typical mixed mode configuration
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
Table 5 shows the relative values of the resistors required in the configuration of Figure 5
to produce the standard multiplex rates.
Table 5.
Multiplex rates and resistor values for Figure 5
Resistors
Multiplex rate (1:n)
n = 8
n = 16, 24, 32
R1
R2
R3
R
R
( n – 2)R
(3 – n)R
R
( n – 3)R
8.2 Power-on reset
At power-on the PCF8578 resets to a defined starting condition as follows:
1. Display blank
2. 1:32 multiplex rate, row mode
3. Start bank 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I2C-bus interface is initialized
Remark: Do not transfer data on the I2C-bus for at least 1 ms after power-on to allow the
reset action to complete.
8.3 Multiplexed LCD bias generation
The bias levels required to produce maximum contrast depend on the multiplex rate and
the LCD threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the
LCD exhibits 10 % contrast. Table 6 shows the optimum voltage bias levels and Table 7
the discrimination ratios (D) for the different multiplex rates as functions of Voper
.
Voper = VDD – VLCD
(1)
(2)
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
1
n
n – 1
V
Von(RMS)
=
+
-- ------------------------
oper
n( n + 1)
and the RMS off-state voltage (Voff(RMS)) with the equation
2( n – 1)
n( n + 1)2
V
Voff (RMS)
=
------------------------------
(3)
oper
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
10 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
where the values for n are determined by the multiplex rate (1:n). Valid values for n are:
n = 8 for 1:8 multiplex
n = 16 for 1:16 multiplex
n = 24 for 1:24 multiplex
n = 32 for 1:32 multiplex
Table 6.
Optimum LCD voltages
Bias ratios
Multiplex rate
1:8
1:16
1:24
1:32
0.739
0.800
0.830
0.850
V
2
-------------
V
oper
0.522
0.478
0.261
0.600
0.400
0.200
0.661
0.339
0.170
0.700
0.300
0.150
V
3
-------------
V
oper
V
4
-------------
V
oper
V
5
-------------
V
oper
Table 7.
Discrimination ratios
Discrimination
ratios
Multiplex rate
1:8
1:16
1:24
1:32
0.297
0.245
0.214
0.193
V
off (RMS)
------------------------
V
oper
0.430
1.447
3.370
0.316
1.291
4.080
0.263
1.230
4.680
0.230
1.196
5.190
V
on(RMS)
-----------------------
V
oper
V
on(RMS)
D =
------------------------
V
off (RMS)
V
oper
-------------
V
th
Figure 6 shows the values of Table 6 as graphs.
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
11 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
msa838
1.0
0.8
0.6
0.4
0.2
0
V
bias
V
oper
V /V
2
oper
oper
V /V
3
V /V
4
oper
oper
V /V
5
1:8
1:16
1:24
1:32
multiplex rate
Vbias = V2, V3, V4, V5; see Table 6.
Fig 6. Vbias/Voper as a function of the multiplex rate
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
12 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
8.4 LCD drive mode waveforms
T
fr
ON
OFF
0
1
2
3
4
5
6
7
V
V
V
V
V
V
DD
2
3
4
ROW 0
5
LCD
1:8
V
V
V
V
V
V
DD
2
3
4
COLUMN
5
LCD
SYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
V
DD
V
V
V
V
V
2
3
ROW 0
4
5
LCD
1:16
V
V
V
V
V
V
DD
2
3
COLUMN
4
5
LCD
SYNC
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
V
DD
V
2
V
V
V
V
3
ROW 0
4
5
LCD
1:24
V
V
DD
2
V
V
V
V
3
COLUMN
4
5
LCD
SYNC
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
V
DD
V
2
V
V
V
V
3
ROW 0
4
5
LCD
1:32
V
V
DD
2
V
V
V
V
3
COLUMN
4
5
LCD
SYNC
column
display
msa841
Fig 7. LCD row and column waveforms
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
13 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
T
state 1 (OFF)
state 2 (ON)
fr
V
V
V
V
V
V
DD
2
3
ROW 1
R1 (t)
4
5
LCD
V
V
V
V
V
V
DD
2
3
ROW 2
R2 (t)
dot matrix
1:8 multiplex rate
4
5
LCD
V
V
V
V
V
V
DD
2
3
COL 1
C1 (t)
4
5
LCD
V
V
V
V
V
V
DD
2
3
COL 2
C2 (t)
4
5
LCD
V
oper
0.261 V
oper
oper
(t)
V
state 1
0 V
0.261 V
V
V
oper
oper
0.478 V
0.261 V
oper
oper
(t)
V
0 V
state 2
0.261 V
oper
oper
0.478 V
V
oper
msa840
Vstate1(t) = C1(t) − R1(t).
Von(RMS)
1
8
8 – 1
=
+ = 0.430
-- ------------------------
----------------------
Voper
8( 8 + 1)
Vstate2(t) = C2(t) − R2(t).
Voff (RMS)
2( 8 – 1)
8( 8 + 1)2
=
------------------------------- = 0.297
------------------------
Voper
Fig 8. LCD drive mode waveforms for 1:8 multiplex rate
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
14 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
state 1 (OFF)
state 2 (ON)
T
fr
V
DD
V2
V3
V4
V5
ROW 1
R1 (t)
V
LCD
V
DD
V2
V3
V4
V5
ROW 2
R2 (t)
V
LCD
V
DD
V2
V3
V4
V5
COL 1
C1 (t)
dot matrix
1:16 multiplex rate
V
LCD
V
DD
V2
V3
V4
V5
COL 2
C2 (t)
V
LCD
V
oper
0.2 V
oper
oper
(t)
V
0 V
0.2 V
state 1
V
V
oper
oper
0.6 V
0.2 V
0 V
oper
oper
(t)
V
state 2
0.2 V
oper
oper
0.6 V
V
oper
msa836
Vstate1(t) = C1(t) − R1(t).
Von(RMS)
1
16 – 1
----- ------------------------------
16
=
+
= 0.316
----------------------
Voper
16( 16 + 1)
Vstate2(t) = C2(t) − R2(t).
Voff (RMS)
2( 16 – 1)
------------------------------------- = 0.254
=
------------------------
16( 16 + 1)2
Voper
Fig 9. LCD drive mode waveform for 1:16 multiplex rate
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
15 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
8.5 Oscillator
8.5.1 Internal clock
The clock signal for the system may be generated by the internal oscillator and prescaler.
The frequency is determined by the value of the resistor Rext(OSC), see Figure 10. For
normal use a value of 330 kΩ is recommended. The clock signal, for cascaded
PCF8579s, is output at CLK and has a frequency of 1⁄6 (multiplex rate 1:8, 1:16 and 1:32)
or 1⁄8 (multiplex rate 1:24) of the oscillator frequency.
msa837
3
10
f
osc
(kHz)
2
10
10
1
10
2
3
4
10
10
10
(kΩ)
R
ext(OSC)
To avoid capacitive coupling, which could adversely affect oscillator stability, Rext(OSC) should be
placed as closely as possible to the OSC pin. If this proves to be a problem, a filtering capacitor
may be connected in parallel to Rext(OSC)
.
Fig 10. Oscillator frequency as a function of external oscillator resistor, Rext(OSC)
8.5.2 External clock
If an external clock is used, OSC must be connected to VDD and the external clock signal
to CLK. Table 8 summarizes the nominal CLK and SYNC frequencies.
Table 8.
Signal frequencies required for nominal 64 Hz frame frequency[1]
Oscillator frequency, Frame frequency, Multiplex rate, Division ratio Clock frequency,
f
osc (Hz)[2]
ffr (Hz)
64
(1:n)
fclk (Hz)
12288
12288
1:8, 1:16, 1:32
1:24
6
8
2048
1536
64
[1] A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
[2] Rext(OSC) = 330 kΩ.
8.6 Timing generator
The timing generator of the PCF8578 organizes the internal data flow of the device and
generates the LCD frame synchronization pulse SYNC, whose period is an integer
multiple of the clock period. In cascaded applications, this signal maintains the correct
timing relationship between the PCF8578 and PCF8579s in the system.
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PCF8578
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LCD row/column driver for dot matrix graphic displays
8.7 Row and column drivers
Outputs R0 to R7 and C32 to C39 are fixed as row and column drivers respectively. The
remaining 24 outputs R8/C8 to R31/C31 are programmable and may be configured (in
blocks of 8) to be either row or column drivers. The row select signal is produced
sequentially at each output from R0 up to the number defined by the multiplex rate (see
Table 4). In mixed mode the remaining outputs are configured as columns. In row mode all
programmable outputs (R8/C8 to R31/C31) are defined as row drivers and the outputs
C32 to C39 should be left open-circuit.
Using a 1:16 multiplex rate, two sets of row outputs are driven, thus facilitating split-screen
configurations, i.e. a row select pulse appears simultaneously at R0 and R16/C16, R1 and
R17/C17 etc. Similarly, using a multiplex rate of 1:8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly to the LCD. Unused outputs
should be left open circuit.
Depending on the multiplex rate the following outputs are rows:
• In MUX 1:8 R0 to R7
• In MUX 1:16 R0 to R15/C15
• In MUX 1:24 R0 to R23/C23
• In MUX 1:32 R0 to R31/C31
The configuration of the outputs (row or column) and the selection of the appropriate
driver waveforms are controlled by the display mode controller.
8.8 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL) which must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
8.8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this
moment will be interpreted as control signals.
8.8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH, is defined as the STOP
condition (P).
8.8.3 System configuration
A device transmitting a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message flow is the master and the devices which
are controlled by the master are the slaves.
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LCD row/column driver for dot matrix graphic displays
8.8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after the reception of each byte. Also
a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges must pull down the
SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be
taken into consideration). A master receiver must signal the end of a data transmission to
the transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this event the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 11. Bit transfer
SDA
SCL
S
P
STOP condition
START condition
mba608
Fig 12. Definition of START and STOP condition
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
mba605
Fig 13. System configuration
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Product data sheet
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PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
clock pulse for
START
acknowledgement
condition
SCL FROM
MASTER
2
9
1
8
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
BY RECEIVER
mba606
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig 14. Acknowledgement on the I2C-bus
8.8.5 I2C-bus controller
The I2C-bus controller detects the I2C-bus protocol, slave address, commands and display
data bytes. It performs the conversion of the data input (serial-to-parallel) and the data
output (parallel-to-serial). The PCF8578 acts as an I2C-bus slave transmitter/receiver in
mixed mode, and as a slave receiver in row mode. A slave device cannot control bus
communication.
8.8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.8.7 I2C-bus protocol
Two 7-bit slave addresses (0111 100 and 0111 101) are reserved for both the PCF8578
and PCF8579. The least significant bit of the slave address is set by connecting input SA0
to either logic 0 (VSS) or logic 1 (VDD). Therefore, two types of PCF8578 or PCF8579 can
be distinguished on the same I2C-bus which allows:
1. One PCF8578 to operate with up to 32 PCF8579s on the same I2C-bus for very large
applications.
2. The use of two types of LCD multiplex schemes on the same I2C-bus.
In most applications the PCF8578 will have the same slave address as the PCF8579.
The I2C-bus protocol is shown in Figure 15. All communications are initiated with a START
condition (S) from the I2C-bus master, which is followed by the desired slave address and
read/write bit. All devices with this slave address acknowledge in parallel. All other devices
ignore the bus transfer.
In WRITE mode (indicated by setting the read/write bit LOW) one or more commands
follow the slave address acknowledgement. The commands are also acknowledged by all
addressed devices on the bus. The last command must clear the continuation bit C.
After the last command a series of data bytes may follow. The acknowledgement after
each byte is made only by the (A0, A1, A2 and A3) addressed PCF8579 or PCF8578 with
its implicit subaddress 0. After the last data byte has been acknowledged, the I2C-bus
master issues a STOP condition (P).
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PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
acknowledge
acknowledge by
all addressed
PCF8578s / PCF8579s
by A0, A1, A2 and A3
selected PCF8578s /
PCF8579s only
R/ W
slave address
S
A
0
0
1
1
1
1
0
0
A C
A
DISPLAY DATA
A
COMMAND
S
P
1 byte
n ≥ 0 byte(s)
n ≥ 0 byte(s)
update data pointers
and if necessary,
subaddress counter
(a)
msa830
a. Master transmits to slave receiver (WRITE mode)
acknowledge by
all addressed
PCF8578s / PCF8579s
acknowledge
from master
no acknowledge
from master
slave address
slave address
S
A
0
S
A
0
0
1
1
1
1
0
0
A C
A
0
1
1
1
1
0
1
A
DATA
A
DATA
1
COMMAND
P
S
S
n ≥ 1 byte
n bytes
last byte
R/W
R /W
at this moment master
transmitter becomes a
master receiver and
update data pointers
and if necessary
PCF8578/PCF8579 slave
receiver becomes a
slave transmitter
subaddress counter
msa832
(b)
b. Master reads after sending command string (write commands; read data)
acknowledge by
acknowledge
from master
no acknowledge
from master
all addressed
PCF8578s / PCF8579s
slave address
S
A
0
0
1
1
1
1
0
1
A
A
DATA
1
S
DATA
P
n bytes
last byte
R/ W
update data pointers
and if necessary,
subaddress counter
(c)
msa831
c. Master reads slave immediately after sending slave address (READ mode)
Fig 15. I2C-bus protocol
In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read from
the RAM following the slave address acknowledgement. After this acknowledgement the
master transmitter becomes a master receiver and the PCF8578 becomes a slave
transmitter. The master receiver must acknowledge the reception of each byte in turn. The
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LCD row/column driver for dot matrix graphic displays
master receiver must signal an end of data to the slave transmitter, by not generating an
acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves
the data line HIGH, enabling the master to generate a STOP condition (P).
Display bytes are written into, or read from the RAM at the address specified by the data
pointer and subaddress counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be transferred either to, or from
the intended devices.
In multiple device applications, the hardware subaddress pins of the PCF8579s (A0 to A3)
are connected to VSS or VDD to represent the desired hardware subaddress code. If two or
more devices share the same slave address, then each device must be allocated to a
unique hardware subaddress.
8.9 Display RAM
The PCF8578 contains a 32 × 40-bit static RAM which stores the display data. The RAM
is divided into 4 banks of 40 bytes (4 × 8 × 40 bits). During RAM access, data is
transferred to and from the RAM via the I2C-bus. The first eight columns of data (0 to 7)
cannot be displayed but are available for general data storage and provide compatibility
with the PCF8579. There is a direct correspondence between X-address and column
output number.
8.9.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows an individual data byte or a series of data bytes to be written into, or read from, the
display RAM, controlled by commands sent on the I2C-bus.
8.9.2 Subaddress counter
The storage and retrieval of display data is dependent on the content of the subaddress
counter. Storage takes place only when the contents of the subaddress counter match
with the hardware subaddress. The hardware subaddress of the PCF8578, valid in mixed
mode only, is fixed at 0000.
8.10 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus.
The five commands available to the PCF8578 are defined in Table 9.
Table 9.
Definition of PCF8578 commands
Operation code
Command
Bit
Reference
7
6
1
1
1
1
0
5
4
T
1
0
1
3
2
1
0
set-mode
C
C
C
C
C
0
E[1:0]
1
M[1:0]
B[1:0]
Table 11
Table 12
Table 13
Table 14
Table 15
set-start-bank
device-select
RAM-access
load-X-address
1
1
1
A[3:0]
G[1:0]
1
Y[1:0]
X[5:0]
The most-significant bit of a command is the continuation bit C (see Table 10 and
Figure 16). Commands are transferred in WRITE mode only.
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LCD row/column driver for dot matrix graphic displays
Table 10. C bit description
Bit
Symbol Value
Description
7
C
continue bit
0
last control byte in the transfer; next byte will be regarded
as display data
1
control bytes continue; next byte will be a command too
MSB
LSB
C
REST OF OPCODE
msa833
C = 0; last command.
C = 1; commands continue.
Fig 16. General information of command byte
Table 11. Set-mode - command bit description
Bit
7
Symbol
Value
0, 1
10
Description
see Table 10
fixed value
display mode
row mode
mixed mode
display status
blank
C
-
6, 5
4
T
0
1
3, 2
E[1:0]
M[1:0]
00
01
10
11
normal
all segments on
inverse video
1, 0
LCD drive mode
01
10
11
00
1:8 MUX (8 rows)
1:16 MUX (16 rows)
1:24 MUX (24 rows)
1:32 MUX (32 rows)
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LCD row/column driver for dot matrix graphic displays
Table 12. Set-start-bank - command bit description
Bit
Symbol
Value
0, 1
Description
7
C
see Table 10
6 to 2
1, 0
-
11111
fixed value
start bank pointer (see Figure 20)[1]
B[1:0]
00
01
10
11
bank 0
bank 1
bank 2
bank 3
[1] Useful for scrolling, pseudo-motion and background preparation of new display content.
Table 13. Device-select - command bit description
Bit
Symbol
Value
0, 1
Description
7
C
see Table 10
6 to 4
3 to 0
-
110
0 to 15[1]
fixed value
A[3:0]
hardware subaddress;
4 bit binary value; transferred to the subaddress
counter to define one of sixteen hardware
subaddresses
[1] Values shown in decimal.
Table 14. RAM-access - command bit description
Bit
Symbol
Value
0, 1
Description
7
C
see Table 10
fixed value
6 to 4
3, 2
-
111
G[1:0]
RAM access mode;
defines the auto-increment behavior of the
address for RAM access (see Figure 18)
00
character
01
half-graphic
10
full-graphic
11
0 to 3[2]
not allowed[1]
RAM row address;
1, 0
Y[1:0]
two bits of immediate data, transferred to the
Y-address pointer to define one of four display
RAM rows (see Figure 17)
[1] See operation code for set-start-bank in Table 12.
[2] Values shown in decimal.
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LCD row/column driver for dot matrix graphic displays
Table 15. Load-X-address - command bit description
Bit
7
Symbol
Value
0, 1
Description
C
see Table 10
6
-
0
fixed value
5 to 0
X[5:0]
0 to 39[1]
RAM column address;
six bits of immediate data, transferred to the
X-address pointer to define one of forty display
RAM columns (see Figure 17)
[1] Values shown in decimal.
8.11 RAM access
1 byte
0
LSB
Y address
Y max
MSB
0
X address
X max
001aaj920
Fig 17. RAM addressing scheme
RAM operations are only possible when the PCF8578 is in mixed mode. In this event its
hardware subaddress is internally fixed at 0000 and the hardware subaddresses of any
PCF8579 used in conjunction with the PCF8578 must start at 0001.
There are three RAM-access modes:
• Character
• Half-graphic
• Full-graphic
These modes are specified by the bits G[1:0] of the RAM-access command. The
RAM-access command controls the order in which data is written to or read from the RAM
(see Figure 18).
To store RAM data, the user specifies the location into which the first byte will be loaded
(see Figure 19):
• Device subaddress (specified by the device-select command)
• RAM X-address (specified by the bits X[5:0] of the load-X-address command)
• RAM bank (specified by the bits Y[1:0] of the RAM-access command)
Subsequent data bytes will be written or read according to the chosen RAM-access mode.
Device subaddresses are automatically incremented between devices until the last device
is reached. If the last device has subaddress 15, further display data transfers will lead to
a wrap-around of the subaddress to 0.
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Product data sheet
Rev. 06 — 5 May 2009
24 of 46
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PCF8578/PCF8579
PCF8579
driver 1
driver 2
driver k
bank 0
bank 1
bank 2
bank 3
RAM
4 bytes
PCF8578/PCF8579 system RAM
1 ≤ k ≤ 16
LSB
40-bits
1 byte
0
1
2
3
4
5
6
7
8
9 10 11
character mode
MSB
0
1
2
3
4
5
6
7
8
9
10 12 14 16 18 20 22
11 13 15 17 19 21 23
2 bytes
half-graphic mode
0
1
2
3
4
5
6
7
8
9
12 16 20 24 28 32 36 40 44
13 17 21 25 29 33 37 41 45
4 bytes
10 14 18 22 26 30 34 38 42 46
11 15 19 23 27 31 35 39 43 47
msa849
full-graphic mode
RAM data bytes are
written or read as
indicated above
Fig 18. RAM access mode
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
DEVICE SELECT:
subaddress 12
bank 0
bank 1
bank 2
bank 3
RAM ACCESS:
character mode
bank 1
RAM
LOAD X-ADDRESS: X-address = 8
R/W
slave address
0 1 1 1 1 0
S
A
0
READ
DATA
1 A
A
S
R/W
slave address
DEVICE SELECT
LOAD X-ADDRESS
RAM ACCESS
S
0 1 1 1 1 0 A 0 A 1 1 1 0 1 1 0
0
A 1 0 0 0 1 0 0
A 0 1 1 1 0 0 0
A
1
0
0
S
last command
DATA
A
DATA
A
WRITE
msa835
Fig 19. Example of commands specifying initial data byte RAM locations
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
8.12 Display control
The display is generated by continuously shifting rows of RAM data to the dot matrix LCD
via the column outputs. The number of rows scanned depends on the multiplex rate set by
bits M[1:0] of the set-mode command.
RAM
bank 0
top of LCD
bank 1
LCD
bank 2
bank 3
msa851
1:32 multiplex rate and start bank = 2.
Fig 20. Relationship between display and set-start-bank
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Product data sheet
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PCF8578
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LCD row/column driver for dot matrix graphic displays
The display status (all dots on or off and normal or inverse video) is set by the bits E[1:0]
of the set-mode command. For bank switching, the RAM bank corresponding to the top of
the display is set by the bits B[1:0] of the set-start-bank command. This is shown in
Figure 20. This feature is useful when scrolling in alphanumeric applications.
9. Limiting values
Table 16. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
Parameter
Conditions
Min
Max
Unit
V
supply voltage
LCD supply voltage
input voltage
−0.5
+8.0
VLCD
VI
V
DD − 11 +8.0
V
VDD related;
−0.5 +8.0
V
on pins SDA, SCL,
CLK, TEST, SA0
and OSC
V
LCD related;
V
DD − 11 +8.0
V
V
V
V2 to V5
VO
output voltage
VDD related;
−0.5
+8.0
SYNC and CLK
VLCD related;
VDD − 11 +8.0
R0 to R7, R8/C8 to
R31/C31 and C32
to C39
II
input current
−10
−10
−50
−50
−50
-
+10
+10
+50
+50
+50
400
100
+150
mA
mA
mA
mA
mA
mW
mW
°C
IO
output current
IDD
IDD(LCD)
ISS
supply current
LCD supply current
ground supply current
total power dissipation
output power
Ptot
Po
per package
-
[1]
Tstg
storage temperature
−65
[1] According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be
stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.
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PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
10. Static characteristics
Table 17. Static characteristics
VDD = 2.5 V to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Supplies
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
2.5
-
6.0
V
VLCD
LCD supply voltage
supply current
V
-
DD − 9
-
V
DD − 3.5
V
[1]
[2]
IDD
external clock;
fclk = 2 kHz
6
15
µA
internal clock;
-
20
50
µA
R
ext(OSC) = 330 kΩ
VPOR
Logic
VIL
power-on reset voltage
0.8
1.3
1.8
V
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
VSS
0.7VDD
1
-
-
-
0.3VDD
V
VIH
VDD
-
V
IOL
at pins SYNC and CLK;
mA
VOL = 1 V; VDD = 5 V
at pin SDA;
3
-
-
mA
VOL = 0.4 V; VDD = 5 V
IOH
IL
HIGH-level output current
leakage current
at pins SYNC and CLK;
-
-
-
−1
mA
mA
VOH = 4 V; VDD = 5 V;
at pins SDA, SCL, SYNC,
CLK, TEST and SA0;
Vi = VDD or VSS
−1
+1
at pin OSC;
Vi = VDD
−1
-
-
+1
5
µA
[3]
Ci
capacitance for each I/O pin
-
pF
LCD outputs
IL
leakage current
at pins V2 to V5;
Vi = VDD or VLCD
−2
-
-
+2
-
µA
mV
kΩ
kΩ
Voffset(DC) DC offset voltage
on pins R0 to R7, R8/C8 to
R31/C31 and C32 to C39
±20
1.5
3
[4]
[4]
RO
output resistance
on row output pins: R0 to
R7 and R8/C8 to R31/C31
-
3
on column output pins:
R8/C8 to R31/C31 and C32
to C39
-
6
[1] Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50 % duty factor.
[2] Resets all logic when VDD < VPOR
[3] Periodically sampled; not 100 % tested.
.
[4] Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input (V2 to V5, VDD and VLCD
)
when the specified current flows through one output under the following conditions (see Table 6 on page 11):
a) Voper = VDD − VLCD = 9 V.
b) Row mode, R0 to R7 and R8/C8 to R31/C31: V2 − VLCD ≥ 6.65 V; V5 − VLCD ≤ 2.35 V; Iload = 150 µA.
c) Column mode, R8/C8 to R31/C31 and C32 to C39: V3 − VLCD ≥ 4.70 V; V4 − VLCD ≤ 4.30 V; Iload = 100 µA.
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Product data sheet
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LCD row/column driver for dot matrix graphic displays
11. Dynamic characteristics
Table 18. Dynamic characteristics
All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 V to 6 V; VSS = 0 V;
LCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
V
Symbol
fclk
Parameter
Conditions
Min
Typ
Max
Unit
clock frequency
at multiplex rate 1:8, 1:16
and 1:32;
1.2
2.1
3.3
kHz
R
ext(OSC) = 330 kΩ;
VDD = 6 V
at multiplex rate 1:24;
ext(OSC) = 330 kΩ;
0.9
1.6
2.5
kHz
R
VDD = 6 V
tPD(SYNC_N) SYNC propagation delay
-
-
-
-
500
100
ns
tPD(drv)
driver propagation delay
VDD − VLCD = 9 V;
µs
with test load of 45 pF
I2C-bus
fSCL
SCL clock frequency
spike pulse width
-
-
-
-
100
100
-
kHz
ns
tw(spike)
tBUF
-
bus free time between a STOP
and START condition
4.7
µs
tSU;STA
tHD;STA
set-up time for a repeated START
condition
4.7
4.0
-
-
-
µs
µs
hold time (repeated) START
condition
4.0
tLOW
tHIGH
tr
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
-
-
-
-
-
µs
µs
µs
-
rise time of both SDA and SCL
signals
1
tf
fall time of both SDA and SCL
signals
-
-
0.3
µs
tSU;DAT
tHD;DAT
tSU;STO
data set-up time
250
0
-
-
-
-
-
-
ns
ns
µs
data hold time
set-up time for STOP condition
4.0
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
30 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
1/f
clk
0.7 V
0.3 V
DD
CLK
DD
0.7 V
DD
SYNC
0.3 V
DD
t
t
PD(SYNC_N)
PD(SYNC_N)
0.5 V
C39 to C32,
R31/C31 to R8/C8
and R7 to R0
(V − V
DD
= 9 V)
LCD
0.5 V
t
PD(drv)
msa834
Fig 21. Driver timing waveforms
SDA
t
t
t
f
BUF
LOW
SCL
SDA
t
HD;STA
t
t
t
SU;DAT
r
HD;DAT
t
HIGH
t
SU;STA
t
SU;STO
mga728
Fig 22. I2C-bus timing waveforms
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
31 of 46
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
LCD DISPLAY
R0 R1 R2 R3 R4 R5 R6 R7
R8/ R9/ R10/ R11/ R12/ R13/ R14/ R15/ R16/ R17/ R18/ R19/ R20/ R21/ R22/ R23/ R24/ R25/ R26/ R27/
C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27
PCF8578
V
CLK
R31/ R30/ R29/ R28/
C31 C30 C29 C28
SS
SA0
V
DD
V
2
V
3
V
4
V
V
OSC
C39 C38 C37 C36 C35 C34 C33
C32
SDA SCL SYNC
5 LCD n.c. n.c.
TEST
R
ext(OSC)
msa844
Fig 23. Stand alone application using 8 rows and 32 columns
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
PCF8578: Segment Driver
Application
a
R0
f
b
g
one line of 24 digits 7 segment
one line of 12 digits star-burst
e
c
R7
R8
d
dp
(mux 1:16)
Total: 384 segments
LCD
R15
12
1
(Using 1:16 mux, the first
character data must be
loaded in bank 0 and 1
starting at byte number 16)
C16
C17
C39
LSB
a
b
f
g
c
16 17
39
0
Bank
0
e
d
dp
1
2
MSB
DISPLAY
RAM
PCF8578
(1)
ALTERNATE DISPLAY BANK
ALTERNATE DISPLAY BANK
3
mlb423
1-byte
Fig 24. Segment driver application for up to 384 segments
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
33 of 46
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
V
DD
V
DD
1:32 multiplex rate
32 × 40 × k dots (k ≤ 16)
(20480 dots max.)
32
R
C
C
C
C
C
LCD DISPLAY
subaddress 0
V
V
2
rows
R
(4
R
R
3
8
2
3)R
40
columns
40
columns
40
columns
V
4
V
5
PCF8578
unused columns
subaddress 1
subaddress k−1
(ROW MODE)
V
DD
V
V
V
V
DD
V
V
V
V
DD
V
V
DD
A0
DD
A0
A1
A2
A3
DD
A0
A1
A2
A3
SA0
V
SS
V
LCD
SS
A1
LCD
LCD
LCD
#2
PCF8579
#k
PCF8579
#1
PCF8579
A2
A3
V
V
3
4
3
4
3
V
LCD
V
OSC
R
ext(OSC)
V
V
V
4
V
SS
V
SS
SYNC CLK
SCL SDA SA0
SS SYNC CLK
SYNC CLK
SDA SCL CLK SYNC
SCL SDA SA0
SCL SDA SA0
V
SS
V
SS
V
SS
V
V
V
SS
V
SS
V
SS
SS
SS
V
DD
SCL
SDA
msa845
Fig 25. Typical LCD driver system with 1:32 multiplex rate
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
V
DD
V
SS
V
SS
V
DD
V
V
SS
DD
V
V
V
SYNC
CLK
SS
SS
SS
SA0 SDA SCL
A3
SYNC
SA0 SDA SCL
A3
SYNC
SA0 SDA SCL
A3
CLK
#k
CLK
#2
V
3
V
3
V
3
V
4
V
4
V
4
A2
A2
A2
#1
PCF8579
PCF8579
PCF8579
V
V
V
LCD
LCD
LCD
A1
A0
A1
A0
A1
A0
V
V
DD
V
DD
V
V
V
DD
DD
DD
DD
40
columns
40
columns
40
columns
subaddress k
1
subaddress 1
subaddress 0
V
DD
16
1:16 multiplex rate
16 × 40 × k dots (k ≤ 16)
(10240 dots max.)
V
DD
LCD DISPLAY
rows
R
C
C
C
C
C
V
2
3
16
1:16 multiplex rate
16 × 40 × k dots (k ≤ 16)
(10240 dots max.)
R
R
R
R
rows
V
8
40
columns
40
columns
40
columns
V
V
PCF8578
(ROW MODE)
4
subaddress 0
subaddress 1
subaddress k 1
unused columns
5
V
V
V
DD
V
V
DD
V
DD
DD
DD
DD
A0
A1
A2
A0
A1
A2
A3
A0
SA0
V
/V
SS DD
V
LCD
V
V
V
LCD
LCD
LCD
A1
A2
A3
#2
#k
#1
PCF8579
PCF8579
PCF8579
V
V
V
3
3
3
V
LCD
V
SS
OSC
V
V
V
V
V
4
4
4
A3
V
R
SS
SS
SS
ext(OSC)
SCL CLK SYNC
SYNC CLK SCL
SYNC CLK SCL
SYNC CLK SCL
V
SDA
SDA SA0
SDA SA0
SDA SA0
SS
V
SS
V
V
SS
V
SS
V
SS
V
SS
V
SS
SS
V
DD
SCL
SDA
msa847
Fig 26. Split screen application with 1:16 multiplex rate for improved contrast
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
V
DD
V
SS
V
DD
V
SS
V
V
SS
DD
V
V
SS
V
SA0 SDA SCL CLK SYNC SS
SS
SA0 SDA SCL CLK SYNC
A3
SA0 SDA SCL CLK SYNC
A3
V
3
V
3
A3
V
3
4
V
4
V
4
A2
#k
A2
#2
A2
V
#1
PCF8579
PCF8579
PCF8579
V
V
LCD
V
LCD
A1
A1
A1
A0
LCD
V
V
DD
V
V
DD
V
V
DD
DD
DD
A0
A0
DD
40
columns
40
columns
40
columns
subaddress k
1
subaddress 1
subaddress 0
V
DD
1:32 multiplex rate
32 × 40 × k dots (k ≤ 16)
(20480 dots max.)
V
DD
LCD DISPLAY
R
R
C
C
C
C
C
32
V
V
2
3
32
1:32 multiplex rate
32 × 40 × k dots (k ≤ 16)
(20480 dots max.)
(4
2 3)R
rows
8
40
columns
40
columns
40
columns
PCF8578
V
V
4
subaddress 0
V
subaddress 1
V
subaddress k 1
(ROW MODE)
unused columns
R
R
5
V
DD
V
V
V
A0
A1
A2
A0
A1
A2
A3
A0
DD
DD
DD
DD
DD
SA0
V
/V
SS DD
V
V
V
V
LCD
LCD
LCD
LCD
A1
A2
A3
#2
#k
#1
PCF8579
PCF8579
PCF8579
V
V
V
V
V
V
3
3
3
V
LCD
V
SS
OSC
A3
4
4
4
R
V
V
SS
V
SS
ext(OSC)
SS
SYNC CLK SCL
SYNC CLK SCL
SYNC CLK SCL
SDA SCL CLK SYNC
SDA SA0
SDA SA0
SDA SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
SCL
SDA
msa846
Fig 27. Split screen application with 1:32 multiplex rate
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
V
SS
V
SCL DD
V
SDA
LCD
R0
R
ext(OSC)
2 3)R
(4
R
R
R
R
n.c.
n.c.
LCD DISPLAY
PCF8578
R31/C31
C0
C27
C28
C39
C0
C27
C28
C39
PCF8579
PCF8579
to other
PCF8579s
msa852
Fig 28. Example of wiring, single screen with 1:32 multiplex rate (PCF8578 in row driver mode)
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
13. Package outline
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
H
v M
A
E
Z
56
29
Q
p
A
2
A
(A )
3
A
1
pin 1 index
θ
L
L
detail X
1
28
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(2)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
0.3
0.1
3.0
2.8
0.42
0.30
0.22 21.65 11.1
0.14 21.35 11.0
15.8
15.2
1.6
1.4
1.45
1.30
0.90
0.55
3.3
0.25
0.01
0.75
2.25
0.2
0.1
0.1
7o
0o
0.012 0.12
0.004 0.11
0.017 0.0087 0.85
0.012 0.0055 0.84
0.44
0.43
0.62
0.60
0.063 0.057
0.055 0.051
0.035
0.022
inches
0.0295
0.089
0.008 0.004 0.004
0.13
Notes
1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
97-08-11
03-02-19
SOT190-1
Fig 29. Package outline SOT190-1 (VSO56) of PCF8578T/1
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
38 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
y
X
A
48
33
Z
49
32
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
D
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT314-2
136E10
MS-026
Fig 30. Package outline SOT314-2 (LQFP64) of PCF8578H/1
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
39 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm
SOT357-1
y
X
A
48
33
Z
49
32
E
e
H
E
E
(A )
3
A
2
A
A
1
w M
p
θ
pin 1 index
b
L
p
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.05
0.05 0.95
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.2
mm
0.25
0.5
1
0.2 0.08 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
02-03-14
SOT357-1
137E10
MS-026
Fig 31. Package outline SOT357-1 (TQFP64) of PCF8578HT/1
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
40 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
41 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 32) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 19 and 20
Table 19. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 20. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 32.
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
42 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 21. Abbreviations
Acronym
CMOS
DC
Description
Complementary Metal Oxide Semiconductor
Direct Current
I2C
Inter-Integrated Circuit
Integrated Circuit
IC
LCD
LSB
Liquid Crystal Display
Least Significant Bit
Most Significant Bit
MSB
MSL
PCB
POR
RC
Moisture Sensitivity Level
Printed-Circuit Board
Power-On Reset
Resistance-Capacitance
Random Access Memory
Root Mean Square
RAM
RMS
SCL
SDA
SMD
Serial Clock Line
Serial Data Line
Surface Mount Device
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
43 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
16. Revision history
Table 22. Revision history
Document ID
PCF8578_6
Release date
20090505
Data sheet status
Change notice
Supersedes
Product data sheet
-
PCF8578_5
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added package type TQFP64 (PCF8578HT/1)
• Removed bare die types
• Rearranged information in data sheet
• Corrected values for 1:32 multiplex mode in Table 4
• Changed letter symbols to NXP approved symbols
• Added RAM addressing scheme (Figure 17)
PCF8578_5
PCF8578_4
PCF8578_3
PCF8578_2
PCF8578_1
20030414
19980908
19970328
19961028
19940125
Product specification
Product specification
Product specification
Product specification
Product specification
-
-
-
-
-
PCF8578_4
PCF8578_3
PCF8578_2
PCF8578_1
-
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
44 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF8578_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
45 of 46
PCF8578
NXP Semiconductors
LCD row/column driver for dot matrix graphic displays
19. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
17
Legal information . . . . . . . . . . . . . . . . . . . . . . 45
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 45
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45
17.1
17.2
17.3
17.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 45
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
8
8.1
8.2
8.3
8.4
8.5
8.5.1
8.5.2
8.6
Functional description . . . . . . . . . . . . . . . . . . . 8
Display configurations. . . . . . . . . . . . . . . . . . . . 8
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10
Multiplexed LCD bias generation . . . . . . . . . . 10
LCD drive mode waveforms . . . . . . . . . . . . . . 13
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 16
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing generator. . . . . . . . . . . . . . . . . . . . . . . 16
Row and column drivers . . . . . . . . . . . . . . . . . 17
Characteristics of the I2C-bus. . . . . . . . . . . . . 17
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
START and STOP conditions . . . . . . . . . . . . . 17
System configuration . . . . . . . . . . . . . . . . . . . 17
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 18
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 19
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 19
Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Subaddress counter . . . . . . . . . . . . . . . . . . . . 21
Command decoder . . . . . . . . . . . . . . . . . . . . . 21
RAM access . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Display control . . . . . . . . . . . . . . . . . . . . . . . . 27
8.7
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.8.7
8.9
8.9.1
8.9.2
8.10
8.11
8.12
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28
Static characteristics. . . . . . . . . . . . . . . . . . . . 29
Dynamic characteristics . . . . . . . . . . . . . . . . . 30
Application information. . . . . . . . . . . . . . . . . . 32
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 38
10
11
12
13
14
Soldering of SMD packages . . . . . . . . . . . . . . 41
Introduction to soldering . . . . . . . . . . . . . . . . . 41
Wave and reflow soldering . . . . . . . . . . . . . . . 41
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 41
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 42
14.1
14.2
14.3
14.4
15
16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 44
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 May 2009
Document identifier: PCF8578_6
相关型号：
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