PCF8583T/5,118_技术文档

PCF8583

Clock and calendar with 240 x 8-bit RAM

Rev. 06 — 6 October 2010

Product data sheet

1. General description

The PCF8583 is a clock and calendar chip, based on a 2048 bit static CMOS¹RAM

organized as 256 words by 8 bits. Addresses and data are transferred serially via the

two-line bidirectional I²C-bus. The built-in word address register is incremented

automatically after each written or read data byte. Address pin A0 is used for

programming the hardware address, allowing the connection of two devices to the bus

without additional hardware.

The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM are used for the

clock, calendar, and counter functions. The next 8 bytes can be programmed as alarm

registers or used as free RAM space. The remaining 240 bytes are free RAM locations.

2. Features and benefits

I²C-bus interface operating supply voltage: 2.5 V to 6 V

Clock operating supply voltage 1.0 V to 6.0 V at 0 °C to +70 °C

240 × 8-bit low-voltage RAM

Data retention voltage: 1.0 V to 6.0 V

Operating current (at f_SCL= 0 Hz): max 50 μA

Clock function with four year calendar

Universal timer with alarm and overflow indication

24 hour or 12 hour format

32.768 kHz or 50 Hz time base

Serial input and output bus (I²C-bus)

Automatic word address incrementing

Programmable alarm, timer, and interrupt function

Slave addresses: A1h or A3h for reading, A0h or A2h for writing

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 14.

PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

DIP8

Description

Version

PCF8583P

PCF8583T

plastic dual in-line package; 8 leads (300 mil)

SOT97-1

SO8

plastic small outline package; 8 leads;

body width 7.5 mm

SOT176-1

PCF8583BS

HVQFN20 plastic thermal enhanced very thin quad flat package; SOT662-1

no leads; 20 terminals; body 5 × 5 × 0.85 mm

4. Marking

Table 2.

Marking codes

Type number

PCF8583P

PCF8583T

PCF8583BS

Marking code

PCF8583P

8583T

8583S

5. Block diagram

00h

control/status

OSCI

DIVIDER

01h hundredth second

OSCILLATOR

OSCO

INT

02h

03h

04h

seconds

minutes

hours

year/date

05h

06h

07h

08h

V

DD

CONTROL

LOGIC

POWER-ON

RESET

weekdays/months

timer

SS

alarm control

PCF8583

to

alarm or RAM

0Fh

A0

2

I C-BUS

ADDRESS

REGISTER

SCL

SDA

RAM

(240 x 8 bit)

INTERFACE

FFh

013aaa365

Fig 1. Block diagram of PCF8583

PCF8583

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

6. Pinning information

6.1 Pinning

1

2

3

4

8

7

6

5

OSCI

OSCO

A0

V

DD

INT

PCF8583P

SCL

SDA

V

SS

013aaa366

Top view. For mechanical details, see Figure 24.

Fig 2. Pin configuration for DIP8 (PCF8583P)

1

2

3

4

8

OSCI

OSCO

A0

V

DD

7

6

5

INT

PCF8583T

SCL

SDA

V

SS

013aaa367

Top view. For mechanical details, see Figure 25.

Fig 3. Pin configuration for SO8 (PCF8583T)

terminal 1

index area

1

2

3

4

5

15

V

n.c.

OSCI

OSCO

A0

DD

14

13

12

11

INT

PCF8583BS

SCL

SDA

n.c.

V

SS

013aaa368

Transparent top view

For mechanical details, see Figure 26.

Fig 4. Pin configuration for HVQFN20 (PCF8583BS)

PCF8583

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

6.2 Pin description

Table 3.

Symbol

Pin description

Type

Description

DIP8

SO8

HVQFN20

(PCF8583P)

(PCF8583T)

(PCF8583BS)

OSCI

1

2

input

oscillator input, 50 Hz or event-pulse

input

OSCO

A0

2

3

4

5

6

7

8

-

2

3

4

5

6

7

8

-

3

output

input

oscillator output

address input

4

V_SS

5^[1]

12

13

14

15

supply

ground supply voltage

SDA

SCL

INT

input/output

input

serial data line

serial clock line

output

supply

-

open-drain interrupt output (active LOW)

supply voltage

V_DD

n.c.

1, 6 to 11, 16 to

20

not connected; do not connect and do not

use as feed through

[1] The die paddle (exposed pad) is connected to V_SSand should be electrically isolated.

PCF8583

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

7. Functional description

The PCF8583 contains a 256 by 8 bit RAM with an 8 bit auto-increment address register,

an on-chip 32.768 kHz oscillator circuit, a frequency divider, a serial two-line bidirectional

I²C-bus interface, and a Power-On Reset (POR) circuit.

The first 16 bytes of the RAM (memory addresses 00h to 0Fh) are designed as

addressable 8 bit parallel special function registers. The first register (memory

address 00h) is used as a control and status register. The memory addresses 01h to 07h

are used as counters for the clock function. The memory addresses 08h to 0Fh may be

programmed as alarm registers or used as free RAM locations, when the alarm is

disabled.

7.1 Counter function modes

When the control and status register is programmed, a 32.768 kHz clock mode, a 50 Hz

clock mode or an event-counter mode can be selected.

In the clock modes the hundredths of a second, seconds, minutes, hours, date, month

(four year calendar) and weekday are stored in a Binary Coded Decimal (BCD) format.

The timer register stores up to 99 days. The event counter mode is used to count pulses

applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6

digits of data.

When one of the counters is read (memory locations 01h to 07h), the contents of all

counters are strobed into capture latches at the beginning of a read cycle. Therefore,

faulty reading of the counter during a carry condition is prevented.

When a counter is written, other counters are not affected.

7.2 Alarm function modes

By setting the alarm enable bit of the control and status register the alarm control register

(address 08h) is activated.

By setting the alarm control register, a dated alarm, a daily alarm, a weekday alarm, or a

timer alarm may be programmed. In the clock modes, the timer register (address 07h)

may be programmed to count hundredths of a second, seconds, minutes, hours, or days.

Days are counted when an alarm is not programmed.

Whenever an alarm event occurs the alarm flag of the control and status register is set. A

timer alarm event will set the alarm flag and an overflow condition of the timer will set the

timer flag. The open-drain interrupt output is switched on (active LOW) when the alarm or

timer flag is set (enabled). The flags remain set until directly reset by a write operation.

When the alarm is disabled (bit 2 of control and status register set logic 0) the alarm

registers at addresses 08h to 0Fh may be used as free RAM.

PCF8583

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Product data sheet

Rev. 06 — 6 October 2010

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

7.3 Control and status register

The control and status register is defined as the memory location 00h with free access for

reading and writing via the I²C-bus. All functions and options are controlled by the

contents of the control and status register (see Figure 5).

MSB

7

LSB

0

memory location 00h

reset state: 0000 0000

6

5

4

3

2

1

timer flag:

50 % duty factor

seconds flag if alarm enable bit

is logic 0

alarm flag: 50 % duty factor

minutes flag if alarm enable bit

is logic 0

alarm enable bit:

logic 0:

alarm disabled: flags toggle

alarm control register to disabled

(memory locations 08h to 0Fh

are free RAM space)

logic 1:

enable alarm control register

(memory location 08h is the

alarm control register)

mask flag:

logic 0:

read locations 05h to 06h

unmasked

logic 1:

read date and month count

directly

function mode:

clock mode 32.768 kHz

clock mode 50 Hz

event-counter mode

test modes

00

01

10

11

hold last count flag:

count

logic 0:

logic 1:

store and hold last count in

capture latches

stop counting flag:

013aaa370

count pulses

stop counting, reset divider

logic 0:

logic 1:

Fig 5. Control and status register

PCF8583

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

7.4 Counter registers

The format for 24 hour or 12 hour clock modes can be selected by setting the most

significant bit of the hours counter register. The format of the hours counter is shown in

Figure 6.

MSB

7

LSB

0

memory location 04h (hours counter)

reset state: 0000 0000

6

5

4

3

2

1

hours in BCD format:

unit place

ten's place (0 to 2 binary)

AM/PM flag:

logic 0: AM

logic 1: PM

format:

logic 0: 24 hour format, AM/PM flag remains unchanged

logic 1: 12 h format, AM/PM flag will be updated

013aaa371

Fig 6. Format of the hours counter

The year and date are stored in memory location 05h (see Figure 7). The weekdays and

months are in memory location 06h (see Figure 8).

MSB

7

LSB

0

memory location 05h (year/date)

reset state: 0000 0001

6

5

4

3

2

1

days in BCD format:

unit place

ten's place (0 to 3 binary)

year (0 to 3 binary, read as logic 0

if the mask flag is set)

013aaa372

Fig 7. Format of the year and date counter

MSB

7

LSB

memory location 06h (weekdays/months)

reset state: 0000 0001

6

5

4

3

2

1

0

months in BCD format:

unit place

ten's place

weekdays (0 to 6 binary, read as logic 0

if the mask flag is set)

013aaa373

Fig 8. Format of the weekdays and month counter

When reading these memory locations the year and weekdays are masked out when the

mask flag of the control and status register is set. This allows the user to read the date

and month count directly. In the event-counter mode, events are stored in BCD format. D5

is the most significant and D0 the least significant digit. The divider is by-passed.

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

In the different modes the counter registers are programmed and arranged as shown in

Figure 9. Counter cycles are listed in Table 4.

00h

01h

02h

control/status

hundredth of a second

D1

D3

D5

D0

D2

D4

1/10 s

1/100 s

seconds

minutes

hours

10 s

1 s

03h

04h

05h

06h

10 min

1 min

free

10 h

1 h

year/date

10 day

1 day

weekdays/months

free

10 month

1 month

timer

07h

08h

09h

0Ah

T1

T0

10 day

1 day

alarm control

hundredth of a second alarm

1/100 s

alarm

D1

alarm

D0

1/10 s

alarm seconds

D3

D5

D2

D4

alarm minutes

0Bh

0Ch

alarm hours

alarm date

free

0Dh

0Eh

0Fh

alarm month

alarm timer

free

alarm timer

free RAM

CLOCK MODES

EVENT COUNTER

013aaa369

Fig 9. Register arrangement

PCF8583

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

Table 4.

Cycle length of the time counters, clock modes

Counting cycle Carry to next unit

Unit

Contents of month

calendar

hundredths of a second

seconds

00 to 99

00 to 59

00 to 23

12 am

99 to 00

-

59 to 00

-

minutes

59 to 00

-

hours (24)

23 to 00

-

hours (12)

-

01 am to 11 am

12 pm

-

01 pm to 11 pm 11 pm to 12 am

-

date

01 to 31

01 to 30

01 to 29

01 to 28

01 to 12

0 to 3

31 to 01

30 to 01

29 to 01

28 to 01

12 to 01

-

1, 3, 5, 7, 8, 10, and 12

4, 6, 9, and 11

2, year = 0

2, year = 1, 2, and 3

months

year

-

weekdays

timer

0 to 6

6 to 0

00 to 99

no carry

7.5 Alarm control register

When the alarm enable bit of the control and status register is set (address 00h, bit 2) the

alarm control register (address 08h) is activated. All alarm, timer, and interrupt output

functions are controlled by the contents of the alarm control register (see Figure 10).

PCF8583

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

MSB

7

LSB

memory location 08h

reset state: 0000 0000

6

5

4

3

2

1

0

timer function:

no timer

000

hundredths of a second

seconds

minutes

hours

days

not used

test mode, all counters

in parallel (factory use only)

001

010

011

100

101

110

111

timer interrupt enable:

timer flag, no interrupt

timer flag, interrupt

0

1

clock alarm function:

no clock alarm

daily alarm

weekday alarm

dated alarm

00

01

10

11

timer alarm enable:

no timer alarm

timer alarm

0

1

alarm interrupt enable:

013aaa374

(only valid when alarm enable in

the control and status register is set)

alarm flag, no interrupt

alarm flag, interrupt

0

1

Fig 10. Alarm control registers, clock mode

7.6 Alarm registers

All alarm registers are allocated with a constant address offset of 08h to the

corresponding counter registers (see Figure 9).

An alarm signal is generated when the contents of the alarm registers match bit-by-bit the

contents of the involved counter registers. The year and weekday bits are ignored in a

dated alarm. A daily alarm ignores the month and date bits. When a weekday alarm is

selected, the contents of the alarm weekday and month register selects the weekdays on

which an alarm is activated (see Figure 11).

Remark: In the 12 hour mode, bits 6 and 7 of the alarm hours register must be the same

as the hours counter.

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

MSB

7

LSB

0

memory location 0Eh (alarm_weekday/month)

6

5

4

3

2

1

weekday 0 enabled when set

weekday 1 enabled when set

weekday 2 enabled when set

weekday 3 enabled when set

weekday 4 enabled when set

weekday 5 enabled when set

weekday 6 enabled when set

not used

013aaa375

Fig 11. Selection of alarm weekdays

7.7 Timer

The timer (location 07h) is enabled by setting the control and status register to

XX0X X1XX. The timer counts up from 0 (or a programmed value) to 99. On overflow, the

timer resets to 0. The timer flag (LSB of control and status register) is set on overflow of

the timer. This flag must be reset by software. The inverted value of this flag can be

transferred to the external interrupt by setting bit 3 of the alarm control register.

Additionally, a timer alarm can be programmed by setting the timer alarm enable (bit 6 of

the alarm control register). When the value of the timer equals a pre-programmed value in

the alarm timer register (location 0Fh), the alarm flag is set (bit 1 of the control and status

register). The inverted value of the alarm flag can be transferred to the external interrupt

by enabling the alarm interrupt (bit 6 of the alarm control register).

Resolution of the timer is programmed via the 3 LSBs of the alarm control register (see

Figure 12).

PCF8583

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

MUX

mode

oscillator

select

CLOCK/CALENDAR

counter

control

ALARM

TIMER

clock

alarm

control alarm

timer

control

overflow

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

ALARM CONTROL

REGISTER

CONTROL/STATUS

REGISTER (1)

timer overflow

interrupt

alarm

interrupt

INT

013aaa377

(1) If the alarm enable bit of the control and status register is reset (logic 0), a 1 Hz signal is observed on the interrupt pin INT.

Fig 12. Alarm and timer interrupt logic diagram

7.8 Event counter mode

Event counter mode is selected by bits 4 and 5 which are logic 10 in the control and status

register. The event counter mode is used to count pulses externally applied to the

oscillator input (OSCO left open-circuit).

The event counter stores up to 6 digits of data, which are stored as 6 hexadecimal values

located in the registers 1h, 2h, and 3h. Therefore, up to 1 million events may be recorded.

An event counter alarm occurs when the event counter registers match the value

programmed in the registers 9h, Ah, and Bh, and the event alarm is enabled (bits 4 and 5

which are logic 01 in the alarm control register). In this event, the alarm flag (bit 1 of the

control and status register) is set. The inverted value of this flag can be transferred to the

interrupt pin (pin 7) by setting the alarm interrupt enable in the alarm control register. In

PCF8583

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

this mode, the timer (location 07h) increments once for every one, one hundred, ten

thousand, or 1 million events, depending on the value programmed in bits 0, 1 and 2 of

the alarm control register. In all other events, the timer functions are as in the clock mode.

MSB

7

LSB

0

memory location 08h

reset state: 0000 0000

6

5

4

3

2

1

timer function:

no timer

units

100

10 000

1 000 000

not allowed

test mode, all counters

in parallel

000

001

010

011

100

101

110

111

timer interrupt enable:

0

1

timer flag, no interrupt

timer flag, interrupt

clock alarm function:

no event alarm

event alarm

not allowed

00

01

10

11

timer alarm enable:

no timer alarm

timer alarm

0

1

alarm interrupt enable:

013aaa376

alarm flag, no interrupt

alarm flag, interrupt

0

1

Fig 13. Alarm control register, event counter mode

7.9 Interrupt output

The conditions for activating the output INT (active LOW) are determined by appropriate

programming of the alarm control register. These conditions are clock alarm, timer alarm,

timer overflow, and event counter alarm. An interrupt occurs when the alarm flag or the

timer flag is set, and the corresponding interrupt is enabled. In all events, the interrupt is

cleared only by software resetting of the flag which initiated the interrupt.

In the clock mode, if the alarm enable is not activated (alarm enable bit of the control and

status register is logic 0), the interrupt output toggles at 1 Hz with a 50 % duty cycle (may

be used for calibration). This is the default power-on state of the device. The OFF voltage

of the interrupt output may exceed the supply voltage, up to a maximum of 6.0 V. A logic

diagram of the interrupt output is shown in Figure 12.

7.10 Oscillator and divider

A 32.768 kHz quartz crystal has to be connected to OSCI and OSCO. A trimmer capacitor

between OSCI and V_DDis used for tuning the oscillator (see Section 11.1). A 100 Hz clock

signal is derived from the quartz oscillator for the clock counters.

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Product data sheet

Rev. 06 — 6 October 2010

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

In the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator

input is switched to a high-impedance state. This allows the user to feed the 50 Hz

reference frequency or an external high speed event signal into the input OSCI.

7.11 Initialization

When power-on occurs the I²C-bus interface, the control and status register and all clock

counters are reset. The device starts time-keeping in the 32.768 kHz clock mode with the

24 hour format on the first of January at 0.00.00:00. A 1 Hz square wave with 50 % duty

cycle appears at the interrupt output pin (starts HIGH).

The stop counting flag of the control and status register must be set before loading the

actual time into the counters. Loading of illegal states leads to a temporary clock

malfunction.

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

8. Characteristics of the I²C-bus

8.1 Characteristics

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when

the bus is not busy.

8.1.1 Bit transfer

One data bit is transferred during each clock pulse (see Figure 14). The data on the SDA

line must remain stable during the HIGH period of the clock pulse as changes in the data

line at this time are interpreted as a control signal.

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mbc621

Fig 14. Bit transfer

8.1.2 Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 15).

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Fig 15. Definition of start and stop conditions

8.1.3 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver (see Figure 16). The device that controls the message is the master; and the

devices which are controlled by the master are the slaves.

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

SDA

SCL

MASTER

TRANSMITTER

RECEIVER

SLAVE

TRANSMITTER

RECEIVER

MASTER

SLAVE

RECEIVER

TRANSMITTER

RECEIVER

mba605

Fig 16. System configuration

8.1.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is illustrated in Figure 17.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from

master

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 17. Acknowledgement on the I²C-bus

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

8.2 I²C-bus protocol

8.2.1 Addressing

Before any data is transmitted on the I²C-bus, the device which must respond is

addressed first. The addressing is always carried out with the first byte transmitted after

the start procedure.

The clock and calendar acts as a slave receiver or slave transmitter. The clock signal SCL

is only an input signal but the data signal SDA is a bidirectional line.

The clock and calendar slave address is shown in Table 5. Bit A0 corresponds to

hardware address pin A0. Connecting this pin to V_DDor V_SSallows the device to have one

of two different addresses.

Table 5.

I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

1

0

1

0

A0

8.2.2 Clock and calendar READ or WRITE cycles

The I²C-bus configuration for the different PCF8583 READ and WRITE cycles is shown in

Figure 18, Figure 19 and Figure 20.

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

S

SLAVE ADDRESS

0

A

REGISTER ADDRESS

A

DATA

A

P

R/W

n bytes

auto increment

memory register address

013aaa346

Fig 18. Master transmits to slave receiver (WRITE mode)

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

SLAVE ADDRESS

DATA

S

0

A

REGISTER ADDRESS

A

S

1

A

SLAVE ADDRESS

n bytes

R/W

auto increment

memory register address

(1)

no acknowledgement

from master

1

P

DATA

last byte

auto increment

memory register address

013aaa041

(1) At this moment master transmitter becomes master receiver and PCF8583 slave receiver becomes slave transmitter.

Fig 19. Master reads after setting word address (write word address; READ data)

acknowledgement

from slave

acknowledgement

from master

no acknowledgement

from master

1

A

DATA

1

P

S

SLAVE ADDRESS

DATA

R/W

n bytes

last byte

auto increment

register address

auto increment

register address

013aaa347

Fig 20. Master reads slave immediately after first byte (READ mode)

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

9. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

+7.0

50

Unit

V

V_DD

I_DD

I_SS

V_I

supply voltage

supply current

−0.8

-

mA

V

ground supply current

input voltage

-

50

−0.8

V_DD+ 0.8

10

I_I

input current

-

mA

mW

V

I_O

output current

-

10

P_tot

P_o

total power dissipation

output power

-

300

-

50

[1]

[2]

[3]

[4]

V_ESD

electrostatic discharge

voltage

HBM

MM

-

±3000

±200

100

-

V

I_lu

latch-up current

-

mA

°C

T_stg

T_amb

storage temperature

ambient temperature

−65

−40

+150

+85

operating device

°C

[1] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”.

[2] Pass level; Machine Model (MM), according to Ref. 6 “JESD22-A115”.

[3] Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature (T_amb(max)).

[4] According to the NXP store and transport requirements (see Ref. 9 “NX3-00092”) the devices have to be

stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products

deviant conditions are described in that document.

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

10. Characteristics

10.1 Static characteristics

Table 7.

Static characteristics

V_DD= 2.5 V to 6.0 V; V_SS= 0 V; T_amb= −40 °C to +85 °C unless otherwise specified.

Symbol

V_DD

Parameter

Conditions

Min

Typ^[1]

Max

Unit

supply voltage

operating mode

I²C-bus active

2.5

1.0

-

6.0

V

I²C-bus inactive

quartz oscillator

T_amb= 0 °C to +70 °C

operating mode

f_SCL= 100 kHz clock mode

clock mode; f_SCL= 0 Hz

V_DD= 5.0 V

[2]

[3]

1.0

-

6.0

V

I_DD

supply current

200

μA

[4]

-

10

2

50

10

μA

V_DD= 1.0 V

data retention;

f_OSCI= 0 Hz; V_DD= 1.0 V

T_amb= −40 °C to +85 °C

T_amb= −25 °C to +70 °C

I²C-bus enable level

-

5

μA

V

-

2

[5]

V_en

Pin SDA

V_IL

enable voltage

1.5

1.9

2.3

[6]

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

input leakage current

input capacitance

−0.8

0.7V_DD

3.0

-

0.3V_DD

V

V_IH

V_DD+ 0.8

V

I_OL

-

mA

μA

pF

I_LI

−1

+1

7

[7]

C_I

-

Pins A0 and OSCI

I_LI

input leakage current

V_I= V_DDor V_SS

−250

-

+250

nA

Pin INT

I_OL

LOW-level output current V_OL= 0.4 V

3

-

mA

I_LI

input leakage current

V_I= V_DDor V_SS

−1

+1

μA

Pin SCL

I_LI

C_I

input leakage current

input capacitance

V_I= V_DDor V_SS

−1

-

+1

7

μA

[7]

-

pF

[1] Typical values measured at T_amb= 25 °C.

[2] When the device is powered on, V_DDmust exceed 1.5 V until the stable operation of the oscillator is established.

[3] Event counter mode: supply current dependant upon input frequency.

[4] See Figure 21.

[5] The I²C-bus logic is disabled if V_DD< V_en

.

[6] When the voltages are above or below the supply voltages V_DDor V_SS, an input current will flow; this current must not exceed ±0.5 mA.

[7] Tested on a sample basis.

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

001aam492

12

I

DD

(μA)

8

4

0

2

4

6

V

DD

(V)

f_SCL= 32 kHz; T_amb= 25 °C

Fig 21. Typical supply current in clock mode as a function of supply voltage

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PCF8583

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Clock and calendar with 240 x 8-bit RAM

10.2 Dynamic characteristics

Table 8.

Dynamic characteristics

V_DD= 2.5 V to 6.0 V; V_SS= 0 V; T_amb= −40 °C to +85 °C unless otherwise specified.

Symbol

Oscillator

C_OSCO

Parameter

Conditions

Min

Typ

Max

Unit

capacitance on pin OSCO

-

40

-

pF

Δf_osc/f_osc

relative oscillator frequency

variation

for ΔV_DD= 100 mV; T_amb= 25 °C;

0.2

ppm

V_DD= 1.5 V

[1]

f_clk(ext)

external clock frequency

on pin OSCI

-

1

MHz

Quartz crystal parameters (f = 32.768 kHz)

R_S

series resistance

-

40

-

kΩ

pF

C_L

parallel load capacitance

-

10

-

C_trim

trimmer capacitance

5

25

I²C-bus timing (see Figure 21)^[2]

f_SCL

t_SP

SCL clock frequency

-

100

kHz

ns

pulse width of spikes that

must be suppressed by the

input filter

t_BUF

bus free time between a

STOP and START condition

4.7

4.0

-

μs

t_SU;STA

t_HD;STA

set-up time for a repeated

START condition

hold time (repeated) START

condition

t_LOW

t_HIGH

t_r

LOW period of the SCL clock

HIGH period of the SCL clock

4.7

4.0

-

μs

-

rise time of both SDA and

SCL signals

1.0

t_f

fall time of both SDA and SCL

signals

-

0.3

μs

t_SU;DAT

t_HD;DAT

t_VD;DAT

t_SU;STO

data set-up time

data hold time

data valid time

250

0

-

ns

μs

-

3.4

-

set-up time for STOP

condition

4.0

[1] Event counter mode only.

[2] All timing values are valid within the operating supply voltage, ambient temperature range, reference to V_ILand V_IHand with an input

voltage swing of V_SSto V_DD

.

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6)

BIT 0

LSB

(R/W)

ACKNOWLEDGE

(A)

STOP

CONDITION

(P)

PROTOCOL

t

SU;STA

LOW

HIGH

1 / f

SCL

SDA

t

BUF

r

f

t

HD;STA

SU;DAT

HD;DAT

VD;DAT

SU;STO

mbd820

Fig 22. I²C-bus timing diagram; rise and fall times refer to V_ILand V_IH

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

11. Application information

11.1 Quartz frequency adjustment

11.1.1 Method 1: Fixed OSCI capacitor

By evaluating the average capacitance necessary for the application layout, a fixed

capacitor can be used. The frequency is measured using the 1 Hz signal available after

power-on at the interrupt output (pin 7). The frequency tolerance depends on the quartz

crystal tolerance, the capacitor tolerance and the device-to-device tolerance. Average

deviations of ±5 minutes per year are possible.

11.1.2 Method 2: OSCI trimmer

Using the alarm function (via the I²C-bus) a signal faster than the 1 Hz is generated at the

interrupt output for fast setting of a trimmer.

Procedure:

• Power the device on

• Initialize the device (alarm functions).

Routine:

• Set clock to time t and set alarm to time t + Δt

• at time t + Δt (interrupt) repeat routine.

11.1.3 Method 3: Direct measurement

Direct measurement of oscillator output (allowing for test probe capacitance).

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

V

DD

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

V

DD

V

SS

A0

SCL

SDA

CLOCK/CALENDAR

OSCI

PCF8583

OSCO

V

SS

V

DD

V

DD

A0

SCL

SDA

EVENT COUNTER

OSCI

PCF8583

OSCO

V

SS

V

DD

R: pull-up resistor

R

t

r

R =

C

b

SDA SCL

(I C-bus)

2

013aaa378

Fig 23. Application example

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

12. Package outline

DIP8: plastic dual in-line package; 8 leads (300 mil)

SOT97-1

D

M

E

A

2

A

1

L

c

w M

Z

b

1

e

(e )

1

M

H

b

2

8

5

pin 1 index

E

1

4

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

2

(1)

Z

1

w

UNIT

mm

b

c

D

E

e

L

M

H

1

2

1

E

max.

min.

max.

1.73

1.14

0.53

0.38

1.07

0.89

0.36

0.23

9.8

9.2

6.48

6.20

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

1.15

0.068 0.021 0.042 0.014

0.045 0.015 0.035 0.009

0.39

0.36

0.26

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.045

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT97-1

050G01

MO-001

SC-504-8

Fig 24. Package outline SOT97-1 (DIP8) of PCF8583P

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Product data sheet

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

SO8: plastic small outline package; 8 leads; body width 7.5 mm

SOT176-1

D

E

A

X

c

y

H

v

M

A

E

Z

8

5

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

4

detail X

e

w

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

θ

1

2

3

p

E

Z

max.

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

7.65

7.45

7.6

7.4

10.65

10.00

1.1

0.45

1.1

1.0

2.0

1.8

mm

2.65

0.25

0.01

1.27

0.05

1.45

0.057

0.25

0.01

0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.30

0.014 0.009 0.29

0.30

0.29

0.419

0.394

0.043 0.043

0.018 0.039

0.079

0.071

inches

0.1

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

97-05-22

03-02-19

SOT176-1

Fig 25. Package outline SOT176-1 (SO8) of PCF8583T

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

HVQFN20: plastic thermal enhanced very thin quad flat package; no leads;

20 terminals; body 5 x 5 x 0.85 mm

SOT662-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

b

v

M

C

A B

C

1

w

6

10

L

11

5

e

E

h

2

1

15

terminal 1

index area

20

16

X

D

h

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

0.05 0.38

0.00 0.23

5.1

4.9

3.25 5.1

2.95 4.9

3.25

2.95

0.75

0.50

mm

0.05

0.1

1

0.2

0.65

2.6

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-22

SOT662-1

- - -

MO-220

- - -

Fig 26. Package outline SOT662-1 (HVQFN20) of PCF8583BS

PCF8583

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

13.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 27) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 9 and 10

Table 9.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

≥ 350

220

< 2.5

235

220

≥ 2.5

220

Table 10. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 27.

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 27. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

14. Abbreviations

Table 11. Abbreviations

Acronym

AM

Description

Ante Meridiem

BCD

CDM

CMOS

ESD

HBM

I²C

Binary Coded Decimal

Charged-Device Model

Complementary Metal-Oxide Semiconductor

ElectroStatic Discharge

Human Body Model

Inter-Integrated Circuit bus

Integrated Circuit

IC

LSB

MM

Least Significant Bit

Machine Model

MSB

MSL

MUX

PCB

PM

Most Significant Bit

Moisture Sensitivity Level

Multiplexer

Printed-Circuit Board

Post Meridiem

POR

PPM

RF

Power-On Reset

Parts Per Million

Radio Frequency

RAM

SCL

SDA

SMD

Random Access Memory

Serial Clock Line

Serial DAta line

Surface-Mount Device

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

15. References

[1] AN10365 — Surface mount reflow soldering description

[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[4] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[7] JESD78 — IC Latch-Up Test

[8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[9] NX3-00092 — NXP store and transport requirements

[10] SNV-FA-01-02 — Marking Formats Integrated Circuits

[11] UM10204 — I²C-bus specification and user manual

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

16. Revision history

Table 12. Revision history

Document ID

PCF8583 v.6

Modifications:

Release date

20101006

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCF8583_5

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Add HVQFN20 package

PCF8583_5

19970715

19970328

19961003

Product Specification

-

PCF8583_4

PCF8583_CNV_3

PCF8583_2

PCF8583_CNV_3

PCF8583

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PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

17.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

17.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

PCF8583

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 06 — 6 October 2010

35 of 37

PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCF8583

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 06 — 6 October 2010

36 of 37

PCF8583

NXP Semiconductors

Clock and calendar with 240 x 8-bit RAM

19. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

15

16

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Revision history . . . . . . . . . . . . . . . . . . . . . . . 34

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

17

Legal information . . . . . . . . . . . . . . . . . . . . . . 35

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 35

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36

17.1

17.2

17.3

17.4

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

18

19

Contact information . . . . . . . . . . . . . . . . . . . . 36

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7

Functional description . . . . . . . . . . . . . . . . . . . 5

Counter function modes . . . . . . . . . . . . . . . . . . 5

Alarm function modes. . . . . . . . . . . . . . . . . . . . 5

Control and status register . . . . . . . . . . . . . . . . 6

Counter registers . . . . . . . . . . . . . . . . . . . . . . . 7

Alarm control register . . . . . . . . . . . . . . . . . . . . 9

Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 10

Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Event counter mode . . . . . . . . . . . . . . . . . . . . 12

Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 13

Oscillator and divider . . . . . . . . . . . . . . . . . . . 13

Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

8

8.1

8.1.1

8.1.2

8.1.3

8.1.4

8.2

Characteristics of the I²C-bus . . . . . . . . . . . . 15

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Start and stop conditions . . . . . . . . . . . . . . . . 15

System configuration . . . . . . . . . . . . . . . . . . . 15

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 16

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 17

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clock and calendar READ or WRITE cycles . 17

8.2.1

8.2.2

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19

10

10.1

10.2

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 20

Static characteristics. . . . . . . . . . . . . . . . . . . . 20

Dynamic characteristics . . . . . . . . . . . . . . . . . 22

11

11.1

11.1.1

11.1.2

11.1.3

Application information. . . . . . . . . . . . . . . . . . 24

Quartz frequency adjustment . . . . . . . . . . . . . 24

Method 1: Fixed OSCI capacitor. . . . . . . . . . . 24

Method 2: OSCI trimmer. . . . . . . . . . . . . . . . . 24

Method 3: Direct measurement . . . . . . . . . . . 24

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26

13

Soldering of SMD packages . . . . . . . . . . . . . . 29

Introduction to soldering . . . . . . . . . . . . . . . . . 29

Wave and reflow soldering . . . . . . . . . . . . . . . 29

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 29

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 30

13.1

13.2

13.3

13.4

14

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 32

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 6 October 2010

Document identifier: PCF8583


型号：	PCF8583T/5,118
厂家：	NXP
描述：	PCF8583 - Clock and calendar with 240 x 8-bit RAM SOIC 8-Pin PC
文件：	总37页 (文件大小：229K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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