PCK2021 [NXP]
CK00 100/133 MHz spread spectrum differential system clock generator; CK00 100/133兆赫扩频差分系统时钟发生器
| 型号： | PCK2021 |
| 厂家： | 
NXP |
| 描述： | CK00 100/133 MHz spread spectrum differential system clock generator |
| 文件： | 总15页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCK2021
CK00 (100/133 MHz) spread spectrum
differential system clock generator
Product data
2001 Oct 11
File under Integrated Circuits, ICL03
Philips
Semiconductors
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum
differential system clock generator
PCK2021
FEATURES
PIN CONFIGURATION
• 3.3 V operation
V
1
2
3
4
5
6
7
8
9
48 PCI0
47 PCI1
• Six differential CPU clock pairs
DDPCI
V
DD48
• Two PCI clocks at 33 MHz and one 3V66 clock
• Two 48 MHz clocks at 3.3 V
48M_0/SELA
48M_1/SELB
46
V
SSPCI
45 SEL133/100
44 NC
• One 14.318 MHz reference clock
V
SS48
• Power management control pins
3V66
43
42
41
40
V
V
DDA
SSA
V
SS3V66
DD3V66
• Host clock jitter less than 200 ps cycle-to-cycle
• Host clock skew less than 150 ps pin-to-pin
• Spread Spectrum capability
PWRDWN
V
V
V
DDCPU
DDCPU
HCLK0 10
39 HCLK3
• Optimized frequency and spread spectrum performance
HCLKB0 11
38 HCLKB3
V
12
37 V
DDCPU
DDCPU
HCLK1 13
36 HCLK4
DESCRIPTION
The PCK2021 is a clock synthesizer/driver for a Pentium III and
other similar processors.
HCLKB1 14
35 HCLKB4
V
15
34 V
SSCPU
SSCPU
HCLK2 16
33 HCLK5
The PCK2021 has six differential pair CPU current source outputs,
two 33 MHz outputs, one 3V66 output, and two 48 MHz clocks
which can be disabled on power-up, and one 3.3 V reference clock
at 14.318 MHz which can also be disabled on power-up.
HCLKB2 17
32 HCLKB5
V
18
31 V
DD
DDCPU
REF 19
SPREAD 20
21
30 MULTSEL0
29 MULTSEL1
The part possesses a dedicated power-down input pin for power
management control. This input is synchronized on chip, and
ensures glitch-free output transitions. In addition, the part can be
configured to disable the 48 MHz outputs for lower power operation
and an increase in the performance of the functioning outputs. The
REF and PCI outputs can also be disabled for the highest
performance of the Host outputs.
V
28
27
26
25
V
SS
SSREF
XIN 22
V
SSIREF
I
REF
XOUT 23
V
24
V
DDIREF
DDREF
SW00960
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
0 to +70 °C
ORDER CODE
PCK2021DGG
PCK2021DL
DRAWING NUMBER
SOT362-1
48-Pin Plastic TSSOP
48-Pin Plastic SSOP
0 to +70 °C
SOT370-1
Intel and Pentium III are trademarks of Intel Corporation.
2
2001 Oct 11
853-2301 27233
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
PIN DESCRIPTION
PIN(S)
SYMBOL
FUNCTION
1, 2, 8, 9,
12, 18, 24,
25, 31, 37,
40
V
DD
3.3 V power supply
Pins 9, 12, and 18 supply host output pairs 0, 1, and 2.
Pins 37 and 40 supply host output pairs 3, 4, and 5.
3, 4
48M_0/SELA
48M_1/SELB
3.3 V fixed 48 MHz clock outputs. During power-up pins function as latched inputs that enable SELA and
SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in.
6
3V66
66 MHz clock: 66 MHZ reference clock
Host output pair 0
10, 11
HCLK0
HCLKB0
13, 14
16, 17
47, 48
39, 38
36, 35
33, 32
HCLK1
HCLKB1
Host output pair 1
HCLK2
HCLKB2
Host output pair 2
PCI0
PCI1
33 MHz clocks: 33 MHz reference clocks
Host output pair 3
HCLK3
HCLKB3
HCLK4
HCLKB4
Host output pair 4
HCLK5
HCLKB5
Host output pair 5
19
20
REF
3.3 V fixed 14.318 MHz output
SPREAD
Enables spread spectrum mode when held LOW on differential host outputs, 3V66 and PCI clocks.
Asserts LOW.
22
23
26
XIN
Crystal input
XOUT
Crystal output
I
This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the correct current.
REF
29, 30
MULTSEL0
MULTSEL1
Select input pin used to control the scaling of the HCLK and HCLKB output current.
41
45
PWRDWN
Device enters power-down mode when held LOW. Asserts LOW.
Select input pin for enabling 133 MHz or 100 MHz CPU outputs
Ground
SEL133/100
5, 7, 15,
21, 27, 28,
34, 46
V
SS
43
42
V
V
3.3 V power supply for analog circuits
Ground for analog circuits
DDA
SSA
3
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
BLOCK DIAGRAM
REF[0] (14.318 MHz)
48MHz[0..1] (3 V)
PWRDWN
XIN
SELC
14.318 MHz
USB PLL
OSC
XOUT
PWRDWN
SELA/B
HOST[0..5] (100/133 MHz)
PWRDWN
I
IBIAS
REF
HOST_BAR[0..5] (100/133 MHz)
PCI[0..1] (33 MHz)
PWRDWN
PWRDWN
PWRDWN
SYS PLL
PWRDWN
SEL133/100
SPREAD
3V66[0] (66 MHz)
LOGIC
MULTSEL0
MULTSEL1
SW00961
FUNCTION TABLE
SEL100/133
SELA
SELB
HOST
100 MHz
100 MHz
100 MHz
Hi-Z
48MHz
PCI33MHz
66MHz
66.7 MHz
66.7 MHz
REFCLK
14.3 MHz
14.3 MHz
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
48 MHz
Disable/Low
Disable/Low
Hi-Z
33.3 MHz
33.3 MHz
Disable/Low
Hi-Z
66.7 MHz
Hi-Z
Disable/Low
Hi-Z
133 MHz
133 MHz
200 MHz
48 MHz
33.3 MHz
33.3 MHz
33.3 MHz
66.7 MHz
66.7 MHz
66.7 MHz
14.3 MHz
14.3 MHz
14.3 MHz
Disable/Low
48 MHz
4
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
Table 1. Host swing select functions
BOARD
IMPEDANCE
MULTSEL0
MULTSEL1
I
I
V
OH
@ IREF = 2.32 mA
0.71 V
REF
OH
R
= 475 1%
= 2.32 mA
REF
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
60 Ω
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= 5*I
= 5*I
= 6*I
= 6*I
= 4*I
= 4*I
= 7*I
= 7*I
= 5*I
= 5*I
= 6*I
= 6*I
= 4*I
= 4*I
= 7*I
= 7*I
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
I
REF
= 475 1%
= 2.32 mA
REF
50 Ω
60 Ω
50 Ω
60 Ω
50 Ω
60 Ω
50 Ω
30 Ω
25 Ω
30 Ω
25 Ω
30 Ω
25 Ω
30 Ω
25 Ω
0.59 V
= 475 1%
= 2.32 mA
REF
0.85 V
= 475 1%
= 2.32 mA
REF
0.71 V
= 475 1%
= 2.32 mA
REF
0.56 V
= 475 1%
= 2.32 mA
REF
0.47 V
= 475 1%
= 2.32 mA
REF
0.99 V
= 475 1%
= 2.32 mA
REF
0.82 V
= 221 1%
= 5 mA
REF
I
0.75 V
REF
= 221 1%
= 5 mA
REF
I
0.62 V
REF
= 221 1%
= 5 mA
REF
I
0.90 V
REF
= 221 1%
= 5 mA
REF
I
0.75 V
REF
= 221 1%
= 5 mA
REF
I
0.60 V
REF
= 221 1%
= 5 mA
REF
I
0.50 V
REF
= 221 1%
= 5 mA
REF
I
1.05 V
REF
= 221 1%
= 5 mA
REF
I
0.84 V
REF
NOTE:
The outputs are optimized for the configurations shown shaded.
CONDITIONS
CONFIGURATION
LOAD
MIN.
MAX.
All combinations;
see Table 1 above
Nominal test load for
given configuration
–7% of I
see Table 1 above
+7% of I
OH
see Table 1 above
OH
I
I
V
V
= 3.3 V
OUT
DD
All combinations;
see Table 1 above
Nominal test load for
given configuration
–12% of I
see Table 1 above
+12% of I
OH
OH
= 3.3 V ±5%
OUT
DD
see Table 1 above
POWER-DOWN MODE
PWRDWN
HCLK/HCLKB
3V66
PCI
48MHz
REFCLK
Asserts LOW
0 = Active
Host = 2*I
REF
Host_bar = undriven
LOW
LOW
LOW
LOW
NOTE:
The differential outputs should have a voltage forced across them when power-down is asserted.
SPREAD SPECTRUM FUNCTION
48 MHz PLL
REFCLK
SPREAD #
FUNCTION
Host, PCI, and 3V66
No Spread
1
0
No Spread
Host, PCI, and 3V66
spread t0.5%
No Spread
5
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
ABSOLUTE MAXIMUM RATINGS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MAX
MIN
–0.5
—
V
DD3
DC 3.3 V supply
4.6
V
mA
V
I
IK
DC input diode current
DC input voltage
V < 0
I
–50
V
I
Note 2
–0.5
—
V
DD
I
DC output diode current
DC output voltage
V
> V or V < 0
±50
+0.5
DD
mA
V
OK
O
DD
O
V
O
Note 2
–0.5
—
V
I
O
DC output source or sink current
Storage temperature range
V
O
= 0 to V
±50
+150
850
mA
°C
DD
T
stg
–65
—
P
tot
Power dissipation per package
plastic medium-shrink (TSSOP)
For temperature range 0 °C to +70 °C;
above +55 °C derate linearly with 11.3 mW/K
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other condition beyond those indicated under “recommended operating condition” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage rating may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
MAX
3.465
3.465
V
DD3
DC 3.3 V supply voltage
3.135
3.135
V
V
AV
DC 3.3 V analog supply voltage
DD
Capacitive load on:
3V666
PCI
1 device load, possible 2
10
10
30
30
pF
pF
Must meet JEDEC
PCI 2.1 Spec. Requirements
C
L
48 MHz clock
1 device load
1 device load
10
20
20
pF
pF
REF
10
14.31818
0
f
ref
Reference frequency, oscillator normal value
Operating ambient temperature range in free air
14.31818
+70
MHz
°C
T
amb
POWER MANAGEMENT
MAXIMUM 3.3 V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAPACITANCE LOADS
= 3.465 V
CONDITION
V
DDL
ALL STATIC INPUTS = V
OR V
SS
DD3
Power-down mode (PWRDWN = 0)
Full active 100/133 MHz
60 mA
250 mA
6
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0 to +70 °C
CONDITIONS
OTHER
LIMITS
TYP
—
SYMBOL
PARAMETER
UNIT
MAX
V
(V)
MIN
DD
V
IH
HIGH level input voltage
LOW level input voltage
3.135 to 3.465
3.135 to 3.465
2.0
V
+0.3
V
V
DD
V
IL
V
–0.3
—
0.8
SS
3.3 V output HIGH voltage
REF, 48M
V
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
I
= –1 mA
OH
2.0
—
—
—
—
—
0.4
—
V
V
V
V
OH3
3.3 V output LOW voltage
REF, 48M
V
I
= 1 mA
= –1 mA
= 1 mA
—
2.4
—
OL3
OH
3.3 V output HIGH voltage
3V66/PCI
V
OHP
I
OH
3.3 V output LOW voltage
3V66/PCI
V
I
0.55
OLP
OH
OH
3.135
3.465
3.135
3.465
V
= 1.0 V
–33
—
—
—
—
—
—
—
—
—
—
—
—
–33
—
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
OUT
Output HIGH current
3V66/PCI
Type 5
12 – 55 Ω
I
V
= 3.135 V
OUT
V
= 1.0 V
–29
—
OUT
Output HIGH current
48 MHz, REF
Type 3
20 – 60 Ω
I
I
OH
OH
V
= 3.135 V
–23
—
OUT
0.66 V
0.76 V
11
Output HIGH current
HOST/HOST_BAR
3.135 to 3.465
Type X1
—
12.7
—
3.135
3.465
3.135
3.465
V
V
= 1.95 V
30
—
OUT
Output LOW current
3V66/PCI
Type 5
12 – 55 Ω
I
OL
OL
V
= 0.4 V
= 1.95 V
= 0.4 V
38
OUT
29
—
—
OUT
Output LOW current
48 MHz, REF
Type 3
20 – 60 Ω
I
V
27
OUT
R
R
= 33.2 Ω
= 49.9 Ω
S
P
V
HOST/HOST_BAR
V
SS
= 0 V
Type X1
—
–50
—
—
—
—
0.05
50
V
OL
±I
Input leakage current
3.465
3.465
0 < V < V
DD3
µA
µA
I
IN
3-State output
OFF-State current
V
=
OUT
1
±I
I
O
= 0
10
OZ
V
DD
or GND
C
Input pin capacitance
Output pin capacitance
Crystal input capacitance
—
—
—
—
—
5
6
pF
pF
pF
in
C
out
C
13.5
22.5
xtal
NOTE:
1. REF output limit is 100 mA.
7
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
AC ELECTRICAL CHARACTERISTICS
V
DD3
= 3.3 V ±5%; f
= 14.31818 MHz
crystal
Host clock outputs
T
amb
= 0 to +70 °C; see Figure 1 for waveforms and Figure 6 for test setup.
LIMITS
133 MHz MODE
100 MHz MODE
SYMBOL
PARAMETER
UNITS
NOTES
MIN
7.5
7.35
175
175
—
MAX
7.65
N/A
700
700
150
55
MIN
10.0
9.85
175
175
—
MAX
10.2
N/A
700
700
150
55
t
HOST CLK average period
Absolute minimum host clock period
HOST CLK rise time
ns
ns
ns
ps
ps
%
11, 14, 19
11, 14, 19
11, 15, 19
11, 15, 19
11, 12, 14, 19
11, 14, 19
11, 14, 19
11, 14, 19
PERIOD
Abs Min Period
t
RISE
FALL
t
HOST CLK fall time
t
HOST_CLK cycle-to-cycle jitter
Output duty cycle
JITTER
DUTY CYCLE
45
45
t
HOST CLK pin-to-pin skew
—
150
—
110
ps
V
SKEW
V
45% V
55% V
45% V
55% V
OH
crossover
OH
OH
OH
REFER TO NOTES ON PAGE 10.
USB clock output, 48MHz
T
amb
= 0 to +70 °C; lump capacitance test load = 20 pF
LIMITS
48 MHz MODE
MIN MAX
SYMBOL
PARAMETER
UNITS
NOTES
f
Frequency, actual
48.000
MHz
ppm
ns
4
f
Deviation from 48 MHz
3V48MHZCLK rise time
3V48MHZCLK fall time
Cycle-to-cycle jitter
–0
1.0
1.0
—
+167
4
D
t
t
4.0
4.0
450
55
8, 19
8, 19
17, 19
17, 19
RISE
FALL
ns
t
ps
JITTER
DUTY CYCLE Output duty cycle
45
%
REFER TO NOTES ON PAGE 10.
PCI Outputs
T
amb
= 0 to +70 °C
LIMITS
SYMBOL
PARAMETER
UNITS
NOTES
MIN
30.0
12.0
12.0
0.5
0.5
45
MAX
N/A
N/A
N/A
2.0
t
Period
ns
ns
ns
ns
ns
%
2, 3, 9, 19
5, 10, 19
6, 10, 19
8, 19
PERIOD
t
High time
Low time
Rise time
Fall time
HIGH
t
LOW
RISE
FALL
t
t
2.0
17, 19
17, 19
17, 19
2
DUTY CYCLE Duty cycle
55
t
Cycle-to-cycle jitter
Pin-to-pin skew
—
200
150
ps
ps
JITTER
t
—
SKEW
REFER TO NOTES ON PAGE 10.
8
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
3V66 Outputs
T
amb
= 0 to +70 °C
LIMITS
SYMBOL
PARAMETER
UNITS
NOTES
MIN
15.0
5.25
5.05
0.5
MAX
16.0
N/A
N/A
2.0
t
Period
ns
ns
ns
ns
ns
%
2, 3, 9, 19
5, 10, 19
6, 10, 19
8, 19
PERIOD
t
High time
Low time
Rise time
Fall time
HIGH
t
LOW
RISE
FALL
t
t
0.5
2.0
17, 19
DUTY CYCLE Duty cycle
Cycle-to-cycle jitter
45
55
17, 19
t
—
400
ps
17, 19
JITTER
REFER TO NOTES ON PAGE 10.
REF clock output
T
amb
= 0 to +70 °C; lump capacitance test load = 20 pF
LIMITS
48 MHz MODE
MIN MAX
SYMBOL
PARAMETER
UNITS
NOTES
f
Frequency, actual
Cycle-to-cycle jitter
14.318
MHz
ps
16, 19
17, 19
17, 19
t
—
300
55
JITTER
DUTY CYCLE Output duty cycle
45
%
REFER TO NOTES ON PAGE 10.
All outputs
T
amb
= 0 to +70 °C
LIMITS
133 MHz MODE
100 MHz MODE
SYMBOL
PARAMETER
UNITS
NOTES
MIN
1.0
1.0
—
MAX
10.0
10.0
3
MIN
1.0
1.0
—
MAX
10.0
10.0
3
t
t
, t
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock stabilization from power-up
ns
ns
19
19
PZL PZH
, t
PZL PZH
t
ms
7, 19
STABLE
REFER TO NOTES ON PAGE 10.
9
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
Group offset limits
MEASUREMENT LOADS
GROUP
OFFSET
MEASUREMENT POINTS
NOTES
(LUMPED)
3V66 to PCI
0–500 ps, 3V66 leads
30 pF
1.5 V
18, 19
NOTES TO THE AC TABLES:
1. Output drivers must have monotonic rise/fall times through the specified V /V levels.
OL OH
2. Period, jitter, offset, and skew measured on rising edge at 1.5 V for 3.3 V clocks.
3. PCI is a fixed 33 MHz and 3V66 is a fixed 66 MHz.
4. Frequency accuracy of 48 MHz must be +167 ppm to match USB default.
5. t
6. t
is measured at 2.4 V for 3.3 V outputs, as shown in Figure 7.
is measured at 0.4 V for all outputs as shown in Figure 7.
HIGH
LOW
7. the time is specified from when V
achieves its normal operating level (typical condition V
= 3.3 V) until the frequency output is stable
DDQ
DDQ
and operating within specification.
8. t and t are measured as a transition through the threshold region V = 0.4 V and V = 2.4 V (1 mA) JEDEC specification.
RISE
FALL
OL
OH
9. The average period over any 1 µs period of time must be greater than the minimum specified period.
10.Calculated at minimum edge rate (1 V/ns) to guarantee 45–55% duty cycle. Pulse width is required to be wider at faster edge rate to ensure
duty specification is met.
11. Test load is R = 33.2 Ω, R = 49.9 Ω.
S
P
12.Must be guaranteed in a realistic system environment.
13.Configured for V = 0.71 V in a 50 Ω environment.
OH
14.Measured at crossing points.
15.Measured at 20% to 80%.
16.Frequency generated by crystal oscillator
17.Voltage measure point (V = 1.5 V).
M
18.All offsets are to be measured at rising edges.
19.Parameters are guaranteed by design.
10
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
AC WAVEFORMS
V
V
V
V
= 1.25 V @ V
and 1.5 V @ V
M
DDL DD3
= V + 0.3 V
X
OL
= V – 0.3 V
Y
OH
and V are the typical output voltage drop that occur with the output load.
OL
OH
V
V
OH
I
HOST CLK
50%
50%
SEL1,
SEL0
V
M
V
SS
GND
t
PERIOD
SW00962
t
t
PZL
PLZ
Figure 1. HOST CLOCK
V
DD
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
M
V
X
COMPONENT
MEASUREMENT
POINTS
V
OL
V
DDL
V
= 2.4 V
OH
t
t
PZH
PHZ
V
= 2.0 V
IH
1.5 V
= 0.7 V
V
OH
V
IL
V
= 0.4 V
OL
V
Y
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
SYSTEM
MEASUREMENT
POINTS
V
V
M
SS
V
SS
outputs
enabled
outputs
enabled
outputs
disabled
SW00668
Figure 2. 3.3 V clock waveforms
SW00662
Figure 3. State enable and disable times
V
S
2 V
DD
1
DD
Open
V
SS
500 Ω
500 Ω
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
TEST
/t
S
1
t
Open
2 V
PLH PHL
t
/t
PLZ PZL
DD
t
/t
V
SS
PHZ PZH
V
DD
= V
DD3
SW00963
Figure 4. Load circuitry for switching times
11
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
PWRDWN
HOST CLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
HOST CLK
(EXTERNAL)
PCICLK
(EXTERNAL)
OSC & VCO
USB (48 MHz)
SW00669
Figure 5. Power management
V
DD
C
L
R
= 50 Ω
P
R
S
HOST
CRYSTAL
14.318 MHz
DUT
R
= 33.2 Ω
S
HOST_BAR
R
S
C
R
= 50 Ω
L
P
SW00671
Figure 6. HOST CLOCK measurements
t
PERIOD
DUTY CYCLE
t
HIGH
2.4 V
1.5 V
0.4 V
3.3V CLOCKING
INTERFACE
t
LOW
t
t
FALL
RISE
SW00943
Figure 7. 3.3 V clock waveforms
12
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
13
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
14
2001 Oct 11
Philips Semiconductors
Product data
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PCK2021
Data sheet status
Product
status
Definitions
[1]
Data sheet status
[2]
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Koninklijke Philips Electronics N.V. 2001
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 10-01
9397 750 08953
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
相关型号：
PCK2021DL,112
PCK2021 - CK00 (100/133 MHz) spread spectrum differential system clock generator SSOP 48-Pin
NXP
PCK2021DL,118
PCK2021 - CK00 (100/133 MHz) spread spectrum differential system clock generator SSOP 48-Pin
NXP
PCK2021DL-T
IC 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48, 7.50 MM, PLASTIC, SOT-370-1, SSOP-48, Clock Generator
NXP
PCK2022RADGG-T
IC 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48, Clock Generator
NXP
©2020 ICPDF网 联系我们和版权申明