PCU9956ATWY_技术文档

PCU9956A

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current

LED driver

Rev. 2 — 29 June 2015

Product data sheet

1. General description

The PCU9956A is an Ultra Fast-mode (UFm) I²C-bus controlled 24-channel constant

current LED driver optimized for dimming and blinking 57 mA Red/Green/Blue/Amber

(RGBA) LEDs in amusement products. Each LED output has its own 8-bit resolution

(256 steps) fixed frequency individual PWM controller that operates at 31.25 kHz with a

duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific

brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both

a fixed frequency of 122 Hz and an adjustable frequency between 15 Hz to once every

16.8 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either

dim or blink all LEDs with the same value.

Each LED output can be off, on (no PWM control), set at its individual PWM controller

value or at both individual and group PWM controller values. The PCU9956A operates

with a supply voltage range of 3 V to 5.5 V and the constant current sink LED outputs

allow up to 20 V for the LED supply. The output peak current is adjustable with an 8-bit

linear DAC from 225 A to 57 mA.

A thermal shutdown feature protects the device when internal junction temperature

exceeds the limit allowed for the process.

The PCU9956A device is the first LED controller device in a new Ultra Fast-mode (UFm)

I²C-bus family. UFm I²C-bus devices offer higher frequency (up to 5 MHz). the UFm

I²C-bus slave devices operate in receive-only mode. That is, only I²C writes to PCU9956A

are supported. As such, there are no status registers in PCU9956A. The PCU9956A

allows significantly higher data transfer rate compared to the Fast-mode Plus version

(PCA9956A).

The active LOW output enable input pin (OE) blinks all the LED outputs and can be used

to externally PWM the outputs, which is useful when multiple devices need to be dimmed

or blinked together without using software control.

Software programmable LED Group and three Sub Call I²C-bus addresses allow all or

defined groups of PCU9956A devices to respond to a common I²C-bus address, allowing

for example, all red LEDs to be turned on or off at the same time or marquee chasing

effect, thus minimizing I²C-bus commands. On power-up, PCU9956A will have a unique

Sub Call address to identify it as a 24-channel LED driver. This allows mixing of devices

with different channel widths. Three hardware address pins on PCU9956A allow up to

125 devices on the same bus.

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

The Software Reset (SWRST) function allows the master to perform a reset of the

PCU9956A through the I²C-bus, identical to the Power-On Reset (POR) that initializes the

registers to their default state causing the output current switches to be OFF (LED off).

This allows an easy and quick way to reconfigure all device registers to the same

condition.

2. Features and benefits

 24 LED drivers. Each output programmable at:

 Off

 On

 Programmable LED brightness

 Programmable group dimming/blinking mixed with individual LED brightness

 Programmable LED output delay to reduce EMI and surge currents

 24 constant current output channels can sink up to 57 mA, tolerate up to 20 V when

OFF

 Output current adjusted through an external resistor (REXT input)

 Output current accuracy

 4 % between output channels

 6 % between PCU9956A devices

 Thermal shut-down for overtemperature

 5 MHz Ultra Fast-mode I²C-bus interface

 256-step (8-bit) linear programmable brightness per LED output varying from fully off

(default) to maximum brightness using a 31.25 kHz PWM signal

 256-step group brightness control allows general dimming (using a 122 Hz PWM

signal) from fully off to maximum brightness (default)

 256-step group blinking with frequency programmable from 15 Hz to 16.8 s and duty

cycle from 0 % to 99.6 %

 Output state change programmable on the Acknowledge (bit 9, this bit is always set

to 1 by I²C-bus master) or the STOP Command to update outputs byte-by-byte or all at

the same time (default to ‘Change on STOP’).

 Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of

the LEDs

 Three quinary hardware address pins allow 125 PCU9956A devices to be connected

to the same I²C-bus and to be individually programmed

 4 software programmable I²C-bus addresses (one LED Group Call address and three

LED Sub Call addresses) allow groups of devices to be addressed at the same time in

any combination (for example, one register used for ‘All Call’ so that all the

PCU9956As on the I²C-bus can be addressed at the same time and the second

register used for three different addresses so that ¹⁄₃of all devices on the bus can be

addressed at the same time in a group). Software enable and disable for each

programmable I²C-bus address.

 Unique power-up default Sub Call address allows mixing of devices with different

channel widths

 Software Reset feature (SWRST Call) allows the device to be reset through the

I²C-bus

 8 MHz internal oscillator requires no external components

PCU9956A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 June 2015

2 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

 Internal power-on reset

 Noise filter on USDA/USCL inputs

 No glitch on LED outputs on power-up

 Low standby current

 Operating power supply voltage (V_DD) range of 3 V to 5.5 V

 5.5 V tolerant inputs on non-LED pins

 40 C to +85 C operation

 ESD protection exceeds 3000 V HBM per JESD22-A114

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

 Packages offered: HTSSOP38

3. Applications

 Amusement products

 RGB or RGBA LED drivers

 LED status information

 LED displays

 LCD backlights

 Keypad backlights for cellular phones or handheld devices

4. Ordering information

Table 1.

Ordering information

Topside mark Package

Name

Type number

Description

Version

PCU9956ATW PCU9956ATW HTSSOP38 plastic thermal enhanced thin shrink small outline package; SOT1331-1

38 leads; body width 4.4 mm; lead pitch 0.5 mm;

exposed die pad

4.1 Ordering options

Table 2.

Ordering options

Type number

Orderable

part number

Package

Packing method

Minimum

order

Temperature

quantity

PCU9956ATW PCU9956ATWY HTSSOP38 Reel 13” Q1/T1

*standard mark SMD dry pack

2500

T_amb= 40 C to +85 C

PCU9956A

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Product data sheet

Rev. 2 — 29 June 2015

3 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

5. Block diagram

AD0

AD2

REXT

LED0

LED1

LED22

LED23

AD1

I/O

REGULATOR

PCU9956A

DAC0

USCL

INPUT FILTER

DAC1

USDA

individual LED

current setting

8-bit DACs

2

I C-BUS

DAC

22

CONTROL

DAC

23

POWER-ON

RESET

V

DD

OUTPUT DRIVER, DELAY CONTROL

AND THERMAL SHUTDOWN

200 kΩ

V

SS

INPUT

FILTER

LED STATE

RESET

SELECT

REGISTER

PWM

REGISTER X

BRIGHTNESS

CONTROL

MUX/

CONTROL

÷ 256

31.25 kHz

GRPFREQ

REGISTER

GRPPWM

8 MHz

OSCILLATOR

REGISTER

DIM CLOCK

'0' – permanently OFF

'1' – permanently ON

OE

002aag458

Dim repetition rate = 122 Hz.

Blink repetition rate = 15 Hz to every 16.8 seconds.

Fig 1. Block diagram of PCU9956A

PCU9956A

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Product data sheet

Rev. 2 — 29 June 2015

4 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

6. Pinning information

6.1 Pinning

REXT

AD0

1

2

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

V

DD

USDA

USCL

RESET

AD1

3

AD2

4

OE

5

V

SS

LED0

LED1

LED2

LED3

LED4

LED5

LED6

LED7

6

LED23

LED22

LED21

LED20

LED19

LED18

LED17

LED16

7

8

9

PCU9956ATW

10

11

12

13

14

15

16

17

18

19

V

SS

V

SS

(1)

LED8

LED9

LED15

LED14

LED13

LED10

V

SS

V

SS

LED11

LED12

Transparant top view

002aag459

(1) Thermal pad; connected to V_SS

.

Fig 2. Pin configuration for HTSSOP38

PCU9956A

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Product data sheet

Rev. 2 — 29 June 2015

5 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

6.2 Pin description

Table 3.

Pin description

Symbol

REXT

AD0

1

Type

I

Description

current set resistor input; resistor to ground

address input 0

address input 1

address input 2

active LOW output enable for LEDs

LED driver 0

2

I

AD1

3

I

AD2

4

I

OE

5

I

LED0

LED1

LED2

LED3

LED4

LED5

LED6

LED7

LED8

LED9

LED10

LED11

LED12

LED13

LED14

LED15

LED16

LED17

LED18

LED19

LED20

LED21

LED22

LED23

RESET

USCL

USDA

V_SS

6

O

I

7

LED driver 1

8

LED driver 2

9

LED driver 3

10

11

12

13

15

16

17

19

20

22

23

24

26

27

28

29

30

31

32

33

35

36

37

LED driver 4

LED driver 5

LED driver 6

LED driver 7

LED driver 8

LED driver 9

LED driver 10

LED driver 11

LED driver 12

LED driver 13

LED driver 14

LED driver 15

LED driver 16

LED driver 17

LED driver 18

LED driver 19

LED driver 20

LED driver 21

LED driver 22

LED driver 23

active LOW reset input

UFm serial clock line

UFm serial data line

supply ground

I

14, 18, 21, 25, 34^[1]ground

V_DD

38 power supply

supply voltage

[1] HTSSOP38 package supply ground is connected to both V_SSpins and exposed center pad. V_SSpins must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

printed-circuit board in the thermal pad region.

PCU9956A

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Product data sheet

Rev. 2 — 29 June 2015

6 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

7. Functional description

Refer to Figure 1 “Block diagram of PCU9956A”.

7.1 Device addresses

Following a START condition, the bus master must output the address of the slave it is

accessing.

For PCU9956A there are a maximum of 125 possible programmable addresses using the

three quinary hardware address pins.

7.1.1 Regular I²C-bus slave address

The I²C-bus slave address of the PCU9956A is shown in Figure 3. The 7-bit slave

address is determined by the quinary input pads AD0, AD1 and AD2. Each pad can have

one of five states (GND, pull-up, floating, pull-down, and V_DD) based on how the input pad

is connected on the board. At power-up or hardware/software reset, the quinary input

pads are sampled and set the slave address of the device internally. To conserve power,

once the slave address is determined, the quinary input pads are turned off and will not be

sampled until the next time the device is power cycled. Table 4 lists the five possible

connections for the quinary input pads along with the external resistor values that must be

used.

Table 4.

Quinary input pad connection

Pad connection

Mnemonic

External resistor (k)

(pins AD2, AD1, AD0)^[1]

Min.

0

Max.

17.9

270



tie to ground

GND

PD

resistor pull-down to ground

open (floating)

34.8

503

31.7

0

FLT

PU

resistor pull-up to V_DD

tie to V_DD

340

22.1

V_DD

[1] These AD[2:0] inputs must be stable before the supply V_DDto chip.

Table 5 lists all 125 possible slave addresses of the device based on all combinations of

the five states connected to three address input pins AD0, AD1 and AD2.

Table 5.

Hardware selectable input pins

I²C-bus slave address

I²C-bus slave address for PCU9956A

Decimal Hex Binary (A[6:0]) Address (R/W = 0)

AD2

AD1

GND

PD

AD0

GND

PD

GND

1

2

3

4

5

6

7

8

9

01

02

03

04

05

06

07

08

09

0000001^[1]

0000010^[1]

0000011^[1]

0000100^[1]

0000101^[1]

0000110^[1]

0000111^[1]

0001000

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

FLT

PU

V_DD

GND

PD

FLT

PU

PD

0001001

PCU9956A

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Product data sheet

Rev. 2 — 29 June 2015

7 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

Table 5.

I²C-bus slave address …continued

Hardware selectable input pins

I²C-bus slave address for PCU9956A

AD2

GND

PD

AD1

PD

AD0

V_DD

GND

PD

Decimal Hex Binary (A[6:0]) Address (R/W = 0)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

0A

0B

0C

0D

0E

0F

10

11

0001010

0001011

0001100

0001101

0001110

0001111

0010000

0010001

0010010

0010011

0010100

0010101

0010110

0010111

0011000

0011001

0011010

0011011

0011100

0011101

0011110

0011111

0100000

0100001

0100010

0100011

0100100

0100101

0100110

0100111

0101000

0101001

0101010

0101011

0101100

0101101

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

36h

38h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

4Eh

50h

52h

54h

56h

58h

5Ah

FLT

PU

FLT

PU

V_DD

GND

PD

PU

FLT

PU

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

PU

V_DD

GND

PD

V_DD

GND

PD

FLT

PU

V_DD

GND

PD

FLT

PU

PD

V_DD

GND

PD

FLT

PU

PD

V_DD

GND

PD

FLT

PU

PD

FLT

PU

PD

V_DD

GND

PD

PU

PD

PU

FLT

PU

PD

PU

PD

PU

V_DD

PCU9956A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 June 2015

8 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

Table 5.

I²C-bus slave address …continued

Hardware selectable input pins

I²C-bus slave address for PCU9956A

AD2

PD

AD1

V_DD

GND

PD

AD0

GND

PD

Decimal Hex Binary (A[6:0]) Address (R/W = 0)

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

0101110

0101111

0110000

0110001

0110010

0110011

0110100

0110101

0110110

0110111

0111000

0111001

0111010

0111011

0111100

0111101

0111110

0111111

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1001001

1001010

1001011

1001100

1001101

1001110

1001111

1010000

5Ch

5Eh

60h

62h

64h

66h

68h

6Ah

6Ch

6Eh

70h

72h

74h

76h

78h

7Ah

7Ch

7Eh

80h

82h

84h

86h

88h

8Ah

8Ch

8Eh

90h

92h

94h

96h

98h

9Ah

9Ch

9Eh

A0h

PD

FLT

PU

PD

V_DD

GND

PD

FLT

PU

FLT

PU

V_DD

GND

PD

FLT

PU

PD

V_DD

GND

PD

FLT

PU

FLT

PU

V_DD

GND

PD

PU

FLT

PU

V_DD

GND

PD

V_DD

GND

FLT

PU

V_DD

GND

PD

PU

FLT

PU

V_DD

PCU9956A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 June 2015

9 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

Table 5.

I²C-bus slave address …continued

Hardware selectable input pins

I²C-bus slave address for PCU9956A

AD2

PU

AD1

PD

AD0

GND

PD

Decimal Hex Binary (A[6:0]) Address (R/W = 0)

81

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

1010001

1010010

1010011

1010100

1010101

1010110

1010111

1011000

1011001

1011010

1011011

1011100

1011101

1011110

1011111

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000^[1]

A2h

A4h

A6h

A8h

AAh

ACh

AEh

B0h

B2h

B4h

B6h

B8h

BAh

BCh

BEh

C0h

C2h

C4h

C6h

C8h

CAh

CCh

CEh

D0h

D2h

D4h

D6h

D8h

DAh

DCh

DEh

E0h

E2h

E4h

E6h

E8h

EAh

ECh

EEh

F0h

PU

PD

82

PU

PD

FLT

PU

83

PU

PD

84

PU

PD

V_DD

GND

PD

85

PU

FLT

PU

86

PU

87

PU

FLT

PU

88

PU

89

PU

V_DD

GND

PD

90

PU

91

PU

92

PU

FLT

PU

93

PU

94

PU

V_DD

GND

PD

95

PU

V_DD

GND

PD

96

PU

97

PU

FLT

PU

98

PU

99

PU

V_DD

GND

PD

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

V_DD

FLT

PU

V_DD

GND

PD

FLT

PU

PD

V_DD

GND

PD

FLT

PU

FLT

PU

V_DD

GND

PD

PU

FLT

PU

V_DD

PCU9956A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 June 2015

10 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

Table 5.

I²C-bus slave address …continued

Hardware selectable input pins

I²C-bus slave address for PCU9956A

AD2

V_DD

AD1

V_DD

AD0

GND

PD

Decimal Hex Binary (A[6:0]) Address (R/W = 0)

121

122

123

124

125

79

7A

7B

7C

7D

1111001^[1]

1111010^[1]

1111011^[1]

1111100^[1]

1111101^[1]

F2h

F4h

F6h

F8h

FAh

FLT

PU

V_DD

[1] See ‘Remark’ below.

Remark: Reserved I²C-bus addresses must be used with caution since they can interfere

with:

• ‘reserved for future use’ I²C-bus addresses (0000 011, 1111 1XX)

• slave devices that use the 10-bit addressing scheme (1111 0XX)

• slave devices that are designed to respond to the General Call address (0000 000)

• High-speed mode (Hs-mode) master code (0000 1XX)

(1)

write only

0

slave address

A6 A5 A4 A3 A2 A1 A0

002aag460

(1) This slave address must match one of the 125 internal addresses as shown in Table 5.

Fig 3. PCU9956A slave address

The last bit of the address byte defines the operation to be performed. Only writes to

PCU9956A are supported, therefore the last bit is set to 0. No Read available with UFm

I²C-bus.

7.1.2 LED All Call I²C-bus address

• Default power-up value (ALLCALLADR register): E0h or 1110 000X

• Programmable through I²C-bus (volatile programming)

• At power-up, LED All Call I²C-bus address is enabled.

See Section 7.3.10 “ALLCALLADR, LED All Call I²C-bus address” for more detail.

Remark: The default LED All Call I²C-bus address (E0h or 1110 000X) must not be used

as a regular I²C-bus slave address since this address is enabled at power-up. All of the

PCU9956As on the I²C-bus will recognize the address if sent by the I²C-bus master.

PCU9956A

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Product data sheet

Rev. 2 — 29 June 2015

11 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

7.1.3 LED Sub Call I²C-bus addresses

• 3 different I²C-bus addresses can be used

• Default power-up values:

– SUBADR1 register: EEh or 1110 111X

– SUBADR2 register: EEh or 1110 111X

– SUBADR3 register: EEh or 1110 111X

• Programmable through I²C-bus (volatile programming)

• At power-up, SUBADR1 is enabled while SUBADR2 and SUBADR3 I²C-bus

addresses are disabled.

Remark: At power-up SUBADR1 identifies this device as a 24-channel driver.

See Section 7.3.9 “LED Sub Call I²C-bus addresses for PCU9956A” for more detail.

Remark: The default LED Sub Call I²C-bus addresses may be used as regular I²C-bus

slave addresses as long as they are disabled.

7.2 Control register

Following the slave address, LED All Call address or LED Sub Call address, the bus

master will send a byte to the PCU9956A, which will be stored in the Control register.

The lowest 7 bits are used as a pointer to determine which register will be accessed

(D[6:0]). The highest bit is used as Auto-Increment Flag (AIF).

This bit along with the MODE1 register bit 5 and bit 6 provide the Auto-Increment feature.

register address

AIF D6 D5 D4 D3 D2 D1 D0

Auto-Increment Flag

002aad850

reset state = 80h

Remark: The Control register does not apply to the Software Reset I²C-bus address.

Fig 4. Control register

When the Auto-Increment Flag is set (AIF = logic 1), the seven low order bits of the

Control register are automatically incremented after a write. This allows the user to

program the registers sequentially. Four different types of Auto-Increment are possible,

depending on AI1 and AI0 values of MODE1 register.

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PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

Table 6.

Auto-Increment options

AI1^[1]AI0^[1]Function

AIF

0

no Auto-Increment

1

Auto-Increment for registers (00h to 3Eh). D[6:0] roll over to 00h after the

last register 3Eh is accessed.

1

0

1

0

1

Auto-Increment for individual brightness registers only (0Ah to 21h).

D[6:0] roll over to 0Ah after the last register (21h) is accessed.

Auto-Increment for MODE1 to IREF23 control registers (00h to 39h).

D[6:0] roll over to 00h after the last register (39h) is accessed.

Auto-Increment for global control registers and individual brightness

registers (08h to 21h). D[6:0] roll over to 08h after the last register (21h) is

accessed.

[1] AI1 and AI0 come from MODE1 register.

Remark: Other combinations not shown in Table 6 (AIF + AI[1:0] = 001b, 010b and 011b)

are reserved and must not be used for proper device operation.

AIF + AI[1:0] = 000b is used when the same register must be accessed several times

during a single I²C-bus communication, for example, changes the brightness of a single

LED. Data is overwritten each time the register is accessed during a write operation.

AIF + AI[1:0] = 100b is used when all the registers must be sequentially accessed, for

example, power-up programming.

AIF + AI[1:0] = 101b is used when the 24 LED drivers must be individually programmed

with different values during the same I²C-bus communication, for example, changing color

setting to another color setting.

AIF + AI[1:0] = 110b is used when MODE1 to IREF23 registers must be programmed with

different settings during the same I²C-bus communication.

AIF + AI[1:0] = 111b is used when the 24 LED drivers must be individually programmed

with different values in addition to global programming.

Only the 7 least significant bits D[6:0] are affected by the AIF, AI1 and AI0 bits.

When the Control register is written, the register entry point determined by D[6:0] is the

first register that will be addressed (write operation), and can be anywhere between 00h

and 3Eh (as defined in Table 7). When AIF = 1, the Auto-Increment Flag is set and the

rollover value at which the register increment stops and goes to the next one is

determined by AIF, AI1 and AI0. See Table 6 for rollover values. For example, if MODE1

register bit AI1 = 0 and AI0 = 1 and if the Control register = 1001 0000, then the register

addressing sequence will be (in hex):

10  11  …  21  0A  0B  …  21  0A  0B  … as long as the master

keeps sending data.

If MODE1 register bit AI1 = 0 and AI0 = 0 and if the Control register = 1010 0010, then the

register addressing sequence will be (in hex):

22  23  …  3E  00  01  …  21  0A  0B  … as long as the master

keeps sending data.

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PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

If MODE1 register bit AI1 = 0 and AI0 = 1 and if the Control register = 1000 0101, then the

register addressing sequence will be (in hex):

05  06  …  21  0A  0B  …  21  0A  0B  … as long as the master

keeps sending data.

Remark: Writing to registers marked ‘not used’ will be ignored.

7.3 Register definitions

Table 7.

Register

Register summary

D6 D5 D4 D3 D2 D1 D0 Name

Type

Function

number (hex)

00h

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MODE1

MODE2

LEDOUT0

LEDOUT1

LEDOUT2

LEDOUT3

LEDOUT4

LEDOUT5

GRPPWM

GRPFREQ

PWM0

write only

Mode register 1

01h

Mode register 2

02h

LED output state 0

03h

LED output state 1

04h

LED output state 2

05h

LED output state 3

06h

LED output state 4

07h

LED output state 5

08h

group duty cycle control

group frequency

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

brightness control LED0

brightness control LED1

brightness control LED2

brightness control LED3

brightness control LED4

brightness control LED5

brightness control LED6

brightness control LED7

brightness control LED8

brightness control LED9

brightness control LED10

brightness control LED11

brightness control LED12

brightness control LED13

brightness control LED14

brightness control LED15

brightness control LED16

brightness control LED17

brightness control LED18

brightness control LED19

brightness control LED20

brightness control LED21

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

11h

PWM7

12h

PWM8

13h

PWM9

14h

PWM10

PWM11

PWM12

PWM13

PWM14

PWM15

PWM16

PWM17

PWM18

PWM19

PWM20

PWM21

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

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24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

Table 7.

Register summary …continued

D6 D5 D4 D3 D2 D1 D0 Name

Register

Type

Function

number (hex)

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

PWM22

PWM23

IREF0

write only

brightness control LED22

brightness control LED23

output gain control register 0

output gain control register 1

output gain control register 2

output gain control register 3

output gain control register 4

output gain control register 5

output gain control register 6

output gain control register 7

output gain control register 8

output gain control register 9

output gain control register 10

output gain control register 11

output gain control register 12

output gain control register 13

output gain control register 14

output gain control register 15

output gain control register 16

output gain control register 17

output gain control register 18

output gain control register 19

output gain control register 20

output gain control register 21

output gain control register 22

output gain control register 23

Offset/delay on LEDn outputs

I²C-bus subaddress 1

IREF1

IREF2

IREF3

IREF4

IREF5

IREF6

IREF7

IREF8

IREF9

IREF10

IREF11

IREF12

IREF13

IREF14

IREF15

IREF16

IREF17

IREF18

IREF19

IREF20

IREF21

IREF22

IREF23

OFFSET

SUBADR1

SUBADR2

SUBADR3

ALLCALLADR

PWMALL

IREFALL

I²C-bus subaddress 2

I²C-bus subaddress 3

All Call I²C-bus address

brightness control for all LEDn

output gain control for all

registers IREF0 to IREF23

41h to 7Fh

-

reserved

write only

not used^[1]

[1] Writing to registers marked ‘not used’ will be ignored.

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7.3.1 MODE1 — Mode register 1

Table 8.

MODE1 - Mode register 1 (address 00h) bit description

Legend: * default value.

Bit

Symbol

Access

Value

0

Description

7

AIF

write only

Register Auto-Increment disabled.

1*

0*

1

Register Auto-Increment enabled (write default logic 1).

Auto-Increment bit 1 = 0. Auto-increment range as defined in Table 6.

Auto-Increment bit 1 = 1. Auto-increment range as defined in Table 6.

Auto-Increment bit 0 = 0. Auto-increment range as defined in Table 6.

Auto-Increment bit 0 = 1. Auto-increment range as defined in Table 6.

Normal mode^[1].

6

5

4

3

2

1

0

AI1

write only

AI0

0*

1

SLEEP

SUB1

SUB2

SUB3

ALLCALL

0*

1

Low power mode. Oscillator off^[2][3]

.

0

PCU9956A does not respond to I²C-bus subaddress 1.

PCU9956A responds to I²C-bus subaddress 1.

PCU9956A does not respond to I²C-bus subaddress 2.

PCU9956A responds to I²C-bus subaddress 2.

PCU9956A does not respond to I²C-bus subaddress 3.

PCU9956A responds to I²C-bus subaddress 3.

PCU9956A does not respond to LED All Call I²C-bus address.

PCU9956A responds to LED All Call I²C-bus address.

1*

0*

1

0*

1

0

1*

[1] It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not

guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window.

[2] No blinking or dimming is possible when the oscillator is off.

[3] The device must be reset if the LED driver output state is set to LDRx=11 after the device is set back to Normal mode.

7.3.2 MODE2 — Mode register 2

Table 9.

MODE2 - Mode register 2 (address 01h) bit description

Legend: * default value.

Bit

7

Symbol

Access

Value Description

-

0*

not used (must write a logic 0)

6

-

not used (must write a logic 0)

group control = dimming.

5

DMBLNK

write only 0*

1

group control = blinking.

4

3

-

0*

reserved (must write a logic 0)

outputs change on STOP command

OCH

write only 0*

1

outputs change on ACK; this ninth bit is always set

to 1 by UFm I²C-bus master

2

1

0

-

1*

0*

1*

reserved (must write a logic 1)

reserved (must write a logic 0)

reserved (must write a logic 1)

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24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

7.3.3 LEDOUT0 to LEDOUT5, LED driver output state

Table 10. LEDOUT0 to LEDOUT5 - LED driver output state registers (address 02h to 07h)

bit description

Legend: * default value.

Address Register

Bit

Symbol

Access

Value

10*

Description

02h

03h

04h

05h

06h

07h

LEDOUT0

LEDOUT1

LEDOUT2

LEDOUT3

LEDOUT4

LEDOUT5

7:6 LDR3

5:4 LDR2

3:2 LDR1

1:0 LDR0

7:6 LDR7

5:4 LDR6

3:2 LDR5

1:0 LDR4

7:6 LDR11

5:4 LDR10

3:2 LDR9

1:0 LDR8

7:6 LDR15

5:4 LDR14

3:2 LDR13

1:0 LDR12

7:6 LDR19

5:4 LDR18

3:2 LDR17

1:0 LDR16

7:6 LDR23

5:4 LDR22

3:2 LDR21

1:0 LDR20

write only

LED3 output state control

LED2 output state control

LED1 output state control

LED0 output state control

LED7 output state control

LED6 output state control

LED5 output state control

LED4 output state control

LED11 output state control

LED10 output state control

LED9 output state control

LED8 output state control

LED15 output state control

LED14 output state control

LED13 output state control

LED12 output state control

LED19 output state control

LED18 output state control

LED17 output state control

LED16 output state control

LED23 output state control

LED22 output state control

LED21 output state control

LED20 output state control

LDRx = 00 — LED driver x is off (x = 0 to 23).

LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking

not controlled). The OE pin can be used as external dimming/blinking control in this state.

LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx

register (default power-up state).

LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be

controlled through its PWMx register and the GRPPWM registers.

Remark: Setting the device in low power mode while being on group dimming/blinking

mode may cause the LED output state to be in an unknown state after the device is set

back to normal mode. The device must be reset and all register values reprogrammed.

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24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

7.3.4 GRPPWM, group duty cycle control

Table 11. GRPPWM - Group brightness control register (address 08h) bit description

Legend: * default value

Address Register

08h GRPPWM

Bit

Symbol

Access

Value

Description

7:0 GDC[7:0]

write only

1111 1111*

GRPPWM register

When DMBLNK bit (MODE2 register) is programmed with logic 0, a 122 Hz fixed

frequency signal is superimposed with the 31.25 kHz individual brightness control signal.

GRPPWM is then used as a global brightness control allowing the LED outputs to be

dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.

General brightness for the 24 outputs is controlled through 256 linear steps from 00h

(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5

registers).

When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers

define a global blinking pattern, where GRPFREQ contains the blinking period (from

67 ms to 16.8 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

GDC7:0

--------------------------

duty cycle =

(1)

256

7.3.5 GRPFREQ, group frequency

Table 12. GRPFREQ - Group frequency register (address 09h) bit description

Legend: * default value.

Address Register

Bit

Symbol

Access

Value

Description

09h GRPFREQ 7:0 GFRQ[7:0] write only

0000 0000* GRPFREQ register

GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2

register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5

registers).

Blinking period is controlled through 256 linear steps from 00h (67 ms, frequency 15 Hz)

to FFh (16.8 s).

GFRQ7:0 + 1

---------------------------------------

global blinking period =

s

(2)

15.26

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24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

7.3.6 PWM0 to PWM23, individual brightness control

Table 13. PWM0 to PWM23 - PWM registers 0 to 23 (address 0Ah to 21h) bit description

Legend: * default value.

Address Register Bit Symbol

Access Value

Description

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

PWM8

PWM9

7:0 IDC0[7:0] write only 0000 0000* PWM0 Individual Duty Cycle

7:0 IDC1[7:0] write only 0000 0000* PWM1 Individual Duty Cycle

7:0 IDC2[7:0] write only 0000 0000* PWM2 Individual Duty Cycle

7:0 IDC3[7:0] write only 0000 0000* PWM3 Individual Duty Cycle

7:0 IDC4[7:0] write only 0000 0000* PWM4 Individual Duty Cycle

7:0 IDC5[7:0] write only 0000 0000* PWM5 Individual Duty Cycle

7:0 IDC6[7:0] write only 0000 0000* PWM6 Individual Duty Cycle

7:0 IDC7[7:0] write only 0000 0000* PWM7 Individual Duty Cycle

7:0 IDC8[7:0] write only 0000 0000* PWM8 Individual Duty Cycle

7:0 IDC9[7:0] write only 0000 0000* PWM9 Individual Duty Cycle

PWM10 7:0 IDC10[7:0] write only 0000 0000* PWM10 Individual Duty Cycle

PWM11 7:0 IDC11[7:0] write only 0000 0000* PWM11 Individual Duty Cycle

PWM12 7:0 IDC12[7:0] write only 0000 0000* PWM12 Individual Duty Cycle

PWM13 7:0 IDC13[7:0] write only 0000 0000* PWM13 Individual Duty Cycle

PWM14 7:0 IDC14[7:0] write only 0000 0000* PWM14 Individual Duty Cycle

PWM15 7:0 IDC15[7:0] write only 0000 0000* PWM15 Individual Duty Cycle

PWM16 7:0 IDC16[7:0] write only 0000 0000* PWM16 Individual Duty Cycle

PWM17 7:0 IDC17[7:0] write only 0000 0000* PWM17 Individual Duty Cycle

PWM18 7:0 IDC18[7:0] write only 0000 0000* PWM18 Individual Duty Cycle

PWM19 7:0 IDC19[7:0] write only 0000 0000* PWM19 Individual Duty Cycle

PWM20 7:0 IDC20[7:0] write only 0000 0000* PWM20 Individual Duty Cycle

PWM21 7:0 IDC21[7:0] write only 0000 0000* PWM21 Individual Duty Cycle

PWM22 7:0 IDC22[7:0] write only 0000 0000* PWM22 Individual Duty Cycle

PWM23 7:0 IDC23[7:0] write only 0000 0000* PWM23 Individual Duty Cycle

A 31.25 kHz fixed frequency signal is used for each output. Duty cycle is controlled

through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh

(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs

programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT5 registers).

IDCx7:0

---------------------------

duty cycle =

(3)

256

Remark: The first lower end 8 steps of PWM and the last (higher end) steps of PWM will

not have effective brightness control of LEDs due to edge rate control of LED output pins.

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PCU9956A

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24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

7.3.7 IREF0 to IREF23, LED output current value registers

These registers reflect the gain settings for output current for LED0 to LED23.

Table 14. IREF0 to IREF23 - LED output gain control registers (address 22h to 39h)

bit description

Legend: * default value.

Address Register Bit

Access

Value

Description

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

IREF0

7:0

write only 00h*

LED0 output current setting

LED1 output current setting

LED2 output current setting

LED3 output current setting

LED4 output current setting

LED5 output current setting

LED6 output current setting

LED7 output current setting

LED8 output current setting

LED9 output current setting

LED10 output current setting

LED11 output current setting

LED12 output current setting

LED13 output current setting

LED14 output current setting

LED15 output current setting

LED16 output current setting

LED17 output current setting

LED18 output current setting

LED19 output current setting

LED20 output current setting

LED21 output current setting

LED22 output current setting

LED23 output current setting

IREF1

IREF2

IREF3

IREF4

IREF5

IREF6

IREF7

IREF8

IREF9

IREF10

IREF11

IREF12

IREF13

IREF14

IREF15

IREF16

IREF17

IREF18

IREF19

IREF20

IREF21

IREF22

IREF23

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24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

7.3.8 OFFSET — LEDn output delay offset register

Table 15. OFFSET - LEDn output delay offset register (address 3Ah) bit description

Legend: * default value.

Address Register Bit

Access

Value

Description

3Ah

OFFSET 7:4

3:0

-

0000*

not used (must write a logic 0)

LEDn output delay offset factor

write only 1000*

The PCU9956A can be programmed to have turn-on delay between LED outputs. This

helps to reduce peak current for the V_DDsupply and reduces EMI.

The order in which the LED outputs are enabled will always be the same (channel 0 will

enable first and channel 23 will enable last).

OFFSET control register bits [3:0] determine the delay used between the turn-on times as

follows:

0000 = no delay between outputs (all on, all off at the same time)

0001 = delay of 1 clock cycle (125 ns) between successive outputs

0010 = delay of 2 clock cycles (250 ns) between successive outputs

0011 = delay of 3 clock cycles (375 ns) between successive outputs

:

0111 = delay of 7 clock cycles (875 ns) between successive outputs

1000 = delay of 8 clock cycles (1 s) between successive outputs

1001 = delay of 9 clock cycles (1.125 s) between successive outputs

1010 = delay of 10 clock cycles (1.25 s) between successive outputs

1011 = delay of 11 clock cycles (1.375 s) between successive outputs

1100 to 1111 = reserved and do not use

Example: If the value in the OFFSET register is 1000 the corresponding delay =

8  125 ns = 1 s delay between successive outputs.

channel 0 turns on at time 0 s

channel 1 turns on at time 1 s

channel 2 turns on at time 2 s

channel 3 turns on at time 3 s

channel 4 turns on at time 4 s

channel 5 turns on at time 5 s

channel 6 turns on at time 6 s

channel 7 turns on at time 7 s

channel 8 turns on at time 8 s

channel 9 turns on at time 9 s

channel 10 turns on at time 10 s

channel 11 turns on at time 11 s

channel 12 turns on at time 12 s

channel 13 turns on at time 13 s

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PCU9956A

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24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

channel 14 turns on at time 14 s

channel 15 turns on at time 15 s

channel 16 turns on at time 16 s

channel 17 turns on at time 17 s

channel 18 turns on at time 18 s

channel 19 turns on at time 19 s

channel 20 turns on at time 20 s

channel 21 turns on at time 21 s

channel 22 turns on at time 22 s

channel 23 turns on at time 23 s

7.3.9 LED Sub Call I²C-bus addresses for PCU9956A

Table 16. SUBADR1 to SUBADR3 - I²C-bus subaddress registers 1 to 3 (address 3Bh to

3Dh) bit description

Legend: * default value.

Address Register

Bit

7:1

0

Symbol

A1[7:1]

A1[0]

Access

Value

Description

I²C-bus subaddress 1

3Bh

3Ch

3Dh

SUBADR1

SUBADR2

SUBADR3

write only 1110 111*

write only 0*

reserved

7:1

0

A2[7:1]

A2[0]

write only 1110 111*

write only 0*

I²C-bus subaddress 2

reserved

7:1

0

A3[7:1]

A3[0]

write only 1110 111*

write only 0*

I²C-bus subaddress 3

reserved

Default power-up values are EEh, EEh, EEh. At power-up, SUBADR1 is enabled while

SUBADR2 and SUBADR3 are disabled. The power-up default bit subaddress of EEh

indicates that this device is a 24-channel LED driver.

All three subaddresses are programmable. Once subaddresses have been programmed

to their right values, SUBx bits need to be set to logic 1 in order to have the device

respond to these addresses (MODE1 register) (0). When SUBx is set to logic 1, the

corresponding I²C-bus subaddress can be used during a UFm I²C-bus write sequence.

7.3.10 ALLCALLADR, LED All Call I²C-bus address

Table 17. ALLCALLADR - LED All Call I²C-bus address register (address 3Eh) bit

description

Legend: * default value.

Address Register

Bit

Symbol Access

Value

Description

3Eh

ALLCALLADR 7:1

AC[7:1]

write only 1110 000*

ALLCALL I²C-bus

address register

0

AC[0]

write only 0*

reserved

The LED All Call I²C-bus address allows all the PCU9956As on the bus to be

programmed at the same time (ALLCALL bit in register MODE1 must be equal to logic 1

[power-up default state]). This address is programmable through the I²C-bus and can be

used during an I²C-bus write sequence. The register address can also be programmed as

a Sub Call.

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Only the 7 MSBs representing the All Call I²C-bus address are valid. The LSB in

ALLCALLADR register must write a logic 0.

If ALLCALL bit = 0 in MODE1 register, the device does not recognize the address

programmed in register ALLCALLADR.

7.3.11 PWMALL — brightness control for all LEDn outputs

When programmed, the value in this register will be used for PWM duty cycle for all the

LEDn outputs and will be reflected in PWM 0 through PWM23 registers.

Table 18. PWMALL - brightness control for all LEDn outputs register (address 3Fh)

bit description

Legend: * default value.

Address Register Bit

3Fh PWMALL 7:0

Access

Value

Description

write only

0000 0000*

duty cycle for all LEDn outputs

Remark: Write to any of the PWM0 to PWM23 registers will overwrite the value in

corresponding PWMn register programmed by PWMALL.

7.3.12 IREFALL register: output current value for all LED outputs

The output current setting for all outputs is held in this register. When this register is

written to or updated, all LED outputs will be set to a current corresponding to this register

value.

Writes to IREF0 to IREF23 will overwrite the output current settings.

Table 19. IREFALL - Output gain control for all LED outputs (address 40h) bit description

Legend: * default value.

Address Register Bit

40h IREFALL 7:0

Access

Value

Description

write only

00h*

current gain setting for all LED outputs

7.3.13 LED driver constant current outputs

In LED display applications, PCU9956A provides nearly no current variations from

channel to channel and from device to device. The maximum current skew between

channels is less than 4 % and less than 6 % between devices.

7.3.13.1 Adjusting output current

The PCU9956A scales up the reference current (I_ref) set by the external resistor (R_ext) to

sink the output current (I_O) at each output port. The maximum output current for the

outputs can be set using R_ext. In addition, the constant value for current drive at each of

the outputs is independently programmable using command registers IREF0 to IREF23.

Alternatively, programming the IREFALL register allows all outputs to be set at one current

value determined by the value in IREFALL register.

Equation 4 and Equation 5 can be used to calculate the minimum and maximum constant

current values that can be programmed for the outputs for a chosen R_ext

.

900 mV

R_ext

1

4

------------------ --

I_O_LED_MIN =



minimum constant current

(4)

(5)

900 mV 255









------------------ --------

I_O_LED_MAX = 255  I_O_LED_MIN =



R_ext

4

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900 mV

------------------ --

.

1

4

For a given IREFx setting, I_O_LED = IREFx 



R_ext

002aag288

80

IREFx = 255

I

O(LEDn)

(mA)

60

40

20

0

1

2

3

4

5

6

7

8

9

10

(kΩ)

R

ext

I_O(LEDn)(mA) = IREFx  (0.9 / 4) / R_ext(k)

maximum I_O(LEDn)(mA) = 255  (0.9 / 4) / R_ext(k)

Remark: Default IREFx at power-up = 0.

Fig 5. Maximum I_LEDversus R_ext

Example 1: If R_ext= 1 k, I_O_LED_MIN = 225 A, I_O_LED_MAX = 57.375 mA (as shown

in Figure 6).

So each channel can be programmed with its individual IREFx in 256 steps and in 225 A

increments to a maximum output current of 57.375 mA independently.

002aah691

60

57.375

I

O(target)

(mA)

50

40

30

20

10

0

32

64

96

128

160

192

224

255

IREFx[7:0] value

Fig 6. I_O(target)versus IREFx value with R_ext= 1 k

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Example 2: If R_ext= 2 k, I_O_LED_MIN = 112.5 A, I_O_LED_MAX = 28.687 mA

(as shown in Figure 7).

So each channel can be programmed with its individual IREFx in 256 steps and in

112.5 A increments to a maximum output channel of 28.687 mA independently.

002aah667

30

I

O(target)

(mA)

20

10

0

32

64

96

128

160

192

224

255

IREFx[7:0] value

Fig 7. I_O(target)versus IREFx value with R_ext= 2 k

7.3.14 Overtemperature protection

If the PCU9956A chip temperature exceeds its limit (T_max, see Table 22), all output

channels will be disabled until the temperature drops below its limit minus a small

hysteresis (T_hys, see Table 22). Once the die temperature reduces below the T_max T_hys

the chip will return to the same condition it was prior to the overtemperature event.

,

7.4 Active LOW output enable input

The active LOW output enable (OE) pin on PCU9956A allows to enable or disable all the

LED outputs at the same time.

• When a LOW level is applied to OE pin, all the LED outputs are enabled.

• When a HIGH level is applied to OE pin, all the LED outputs are high-impedance.

The OE pin can be used as a synchronization signal to switch on/off several PCU9956A

devices at the same time when LED drive output state is set fully ON (LDRx = 01 in

LEDOUTx register) in these devices. This requires an external clock reference that

provides blinking period and the duty cycle.

The OE pin can also be used as an external dimming control signal. The frequency of the

external clock must be high enough not to be seen by the human eye, and the duty cycle

value determines the brightness of the LEDs.

Remark: Do not use OE as an external blinking control signal when internal global

blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined

blinking pattern. Do not use OE as an external dimming control signal when internal global

dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined

dimming pattern.

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7.5 Power-on reset

When power is applied to V_DD, an internal power-on reset holds the PCU9956A in a reset

condition until V_DDhas reached V_POR. At this point, the reset condition is released and the

PCU9956A registers and I²C-bus state machine are initialized to their default states (all

zeroes) causing all the channels to be deselected. Thereafter, V_DDmust be pulled lower

than 1 V and stay LOW for longer than 20 s. The device will reset itself, and allow 2 ms

for the device to fully wake up.

Remark: In order to guarantee a proper Power-On Reset operation for device, the rising

rate of V_DDmust be less than 3 ms per 1 V or less than 10 ms from 0 V to 3.3 V. Also,

V

_DDmust return to 0 V for a minimum of 10 ms before rising again while V_DDpower is

re-cycling.

7.6 Hardware reset recovery

When a reset of PCU9956A is activated using an active LOW input on the RESET pin, a

reset pulse width of 2.5 s minimum is required. The maximum wait time after RESET pin

is released is 1.5 ms.

7.7 Software reset

The Software Reset Call (SWRST Call) allows all the devices in the I²C-bus to be reset to

the power-up state value through a specific formatted I²C-bus command. To be performed

correctly, it implies that the I²C-bus is functional and that there is no device hanging the

bus.

The maximum wait time after software reset is 1 ms.

The SWRST Call function is defined as the following:

1. A START command is sent by the I²C-bus master.

2. The reserved General Call address ‘0000 000’ with the R/W bit set to ‘0’ (write) is sent

by the I²C-bus master.

3. Since PCU9956A is a UFm I²C-bus device, no acknowledge is returned to the I²C-bus

master.

4. Once the General Call address has been sent, the master sends 1 byte with 1 specific

value (SWRST data byte 1): Byte 1 = 06h.

If more than 1 byte of data is sent, they will be ignored by the PCU9956A.

5. Once the correct byte (SWRST data byte 1) has been sent, the master sends a STOP

command to end the SWRST function: the PCU9956A then resets to the default value

(power-up value) and is ready to be addressed again within the specified bus free

time (t_BUF).

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General Call address

SWRST data byte 1

S

0

1

0

1

0

1

P

START condition

this bit is

always = 1

STOP

condition

002aaf099

Fig 8. SWRST Call

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7.8 Individual brightness control with group dimming/blinking

A 31.25 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is

used to control individually the brightness for each LED.

On top of this signal, one of the following signals can be superimposed (this signal can be

applied to the 24 LED outputs LED0 to LED23).

• A lower 122 Hz fixed frequency signal with programmable duty cycle (8 bits,

256 steps) is used to provide a global brightness control.

• A programmable frequency signal from 15 Hz to every 16.8 seconds (8 bits,

256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a

global blinking control.

252

254

256

1

2

3

4

5

6

7

8

9

10 11 12

251

253

255

1

2

3

4

5

6

7

8

9

10 11

Brightness Control signal (LEDn)

N × 125 ns

with N = (0 to 255)

(PWMx Register)

M × 256 × 125 ns

with M = (0 to 255)

(GRPPWM Register)

256 × 125 ns = 32 μs

(31.25 kHz)

Group Dimming signal

256 × 256 × 125 ns = 8.19 ms (122 Hz)

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

002aaf935

resulting Brightness + Group Dimming signal

Minimum pulse width for LEDn Brightness Control is 125 ns.

Minimum pulse width for Group Dimming is 32 s.

When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 1 pulse of the

LED Brightness Control signal (pulse width = N  125 ns, with ‘N’ defined in PWMx register).

This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 8.

Fig 9. Brightness + Group Dimming signals

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8. Characteristics of the PCU9956A Ultra Fast-mode I²C-bus

The PCU9956A LED controller uses the new Ultra Fast-mode (UFm) I²C-bus to

communicate with the UFm I²C-bus capable host controller. Like the Standard mode and

Fast-mode Plus (Fm+) I²C-bus, it uses two lines for communication. They are a serial data

line (USDA) and a serial clock line (USCL). The UFm is a unidirectional bus that is

capable of higher frequency (up to 5 MHz). The UFm I²C-bus slave devices operate in

receive-only mode. That is, only I²C writes to PCU9956A are supported.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the USDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at this

time will be interpreted as control signals (see Figure 10).

USDA

USCL

data line

stable;

data valid

change

of data

allowed

002aaf113

Fig 10. Bit transfer

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 11).

USDA

USCL

S

P

STOP condition

START condition

002aaf114

Fig 11. Definition of START and STOP conditions

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8.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 12).

USDA

MASTER UFm

TRANSMITTER

USCL

SLAVE UFm

RECEIVER

SLAVE UFm

RECEIVER

SLAVE UFm

RECEIVER

002aaf100

Fig 12. System configuration

8.3 Data transfer

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one bit that is

always set to 1. The master generates an extra related clock pulse.

USDA data output by

master UFm transmitter

USCL clock from master

1

2

8

9

S

START

condition

002aaf101

Fig 13. Data transfer

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9. Bus transactions

(1)

slave address

control register

data for register D[7:0]

S

A6 A5 A4 A3 A2 A1 A0

0

1

X

D6 D5 D4 D3 D2 D1 D0

1

P

(2)

register address

START condition

write

only

this bit

always = 1

Auto-Increment flag

(don’t care)

STOP

this bit

condition

always = 1

002aag461

(1) See Table 5 for I²C-bus slave address.

(2) See Table 7 for register definition.

Fig 14. Write to a specific register

(1)

slave address

control register

MODE1 register data

MODE2 register data

(cont.)

S

A6 A5 A4 A3 A2 A1 A0

0

1

0

1

MODE1

register selection

Auto-Increment on

START condition

write

only

this bit

always = 1

this bit

always = 1

ALLCALLADR register data

(cont.)

1

P

this bit

always = 1

STOP

condition

002aag462

(1) AI1, AI0 = 00. See Table 6 for Auto-Increment options.

Remark: Care should be taken to load the appropriate value here in the AI1 and AI0 bits of the MODE1 register for

programming the part with the required Auto-Increment options.

Fig 15. Write to all registers using the Auto-Increment feature

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(1)

2

(2)

X

slave address

control register

new LED All Call I C address

sequence (A)

S

A6 A5 A4 A3 A2 A1 A0

0

1

0

1

0

1

0

1

0

1

0

1

P

ALLCALLADR

register selection

START condition

write

only

this bit

always = 1

this bit

always = 1

this bit Auto-Increment on

always = 1

STOP condition

(3)

multiple LEDs are on at the 9th bit

LEDOUT0 register (LED fully ON)

2

LED All Call I C address

control register

(cont.)

1

sequence (B)

S

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LEDOUT0

register selection

START condition

write

only

this bit

always = 1

this bit

always = 1

this bit Auto-Increment on

always = 1

multiple LEDs are on

(3)

at the 9th bit

LEDOUT3 register (LED fully ON) LEDOUT4 register (LED fully ON) LEDOUT5 register (LED fully ON)

(cont.)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P

this bit

always = 1

this bit

always = 1

this bit

always = 1

STOP condition

002aah722

(1) In this example, several PCU9956As are used and the same sequence (A) (above) is sent to each of them.

(2) ALLCALL bit in MODE1 register is previously set to 1 for this example.

(3) OCH bit in MODE2 register is previously set to 1 for this example.

Fig 17. LED All Call I²C-bus address programming and LED All Call sequence example

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10. Application design-in information

V

= 3.3 V or 5.0 V

DD

1.1 kΩ

(optional)

(1)

10 kΩ

up to 20 V

2

UFm I C-BUS/

SMBus

V

DD

LED0

LED1

LED2

LED3

LED4

MASTER

USDA

USCL

OE

USCL

OE

RESET

PCU9956A

LED5

LED6

LED7

REXT

LED8

ISET

LED9

LED10

LED11

LED12

LED13

LED14

LED15

LED16

LED17

LED18

LED19

LED20

LED21

LED22

LED23

(2)

AD0

AD1

AD2

V

SS

V

C

10 μF

SS

002aag465

(1) OE requires pull-up resistor if control signal from the master is open-drain.

(2) I²C-bus address = 1101001 when AD0, AD2 tied to V_DDand AD1 tied to V_SS(see Table 5).

Fig 18. Typical application

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10.1 Thermal considerations

Since the PCU9956A device integrates 24 linear current sources, thermal considerations

should be taken into account to prevent overheating, which can cause the device to go

into thermal shutdown.

Perhaps the major contributor for device’s overheating is the LED forward voltage

mismatch. This is because it can cause significant voltage differences between the LED

strings of the same type (e.g., 2 V to 3 V), which ultimately translates into higher power

dissipation in the device. The voltage drop across the LED channels of the device is given

by the difference between the supply voltage and the LED forward voltage of each LED

string. Reducing this to a minimum (e.g., 0.8 V) helps to keep the power dissipation down.

Therefore LEDs binning is recommended to minimize LED voltage forward variation and

reduce power dissipation in the device.

In order to ensure that the device will not go into thermal shutdown when operating under

certain application conditions, its junction temperature (T_j) should be calculated to ensure

that is below the overtemperature threshold limit (130 C). The T_jof the device depends

on the ambient temperature (T_amb), device’s total power dissipation (P_tot), and thermal

resistance.

The device junction temperature can be calculated by using the following equation:

T_j= T_amb+ R_thj-a P_tot

(6)

where:

T_j= junction temperature

T_amb= ambient temperature

R_th(j-a)= junction to ambient thermal resistance

P_tot= (device) total power dissipation

An example of this calculation is show below:

Conditions:

T_amb= 50 C

R_th(j-a)= 33.9 C/W (per JEDEC 51 standard for multilayer PCB)

I_LED= 30 mA / channel

I_DD(max)= 20 mA

V_DD= 5 V

LEDs per channel = 5 LEDs / channel

LED V_F(typ)= 3 V per LED (15 V total for 5 LEDs in series)

LED V_Fmismatch = 0.2 V per LED (1 V total for 5 LEDs in series)

V_reg(drv)= 0.8 V (This will be present only in the LED string with the highest LED forward

voltage.)

V_sup= LED V_F(typ)+ LED V_Fmismatch + V_reg(drv)= 15 V + 1 V + 0.8 V = 16.8 V

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P_totcalculation:

P_tot= IC_power + LED drivers_power;

IC_power = (I_DD V_DD

)

IC_power = (0.02 A  5 V) = 0.1 W

LED drivers_power = [(24  1)  (I_LED)  (LED V_Fmismatch + V_reg(drv))] +

(I_LED V_reg(drv)

)

LED drivers_power = [23  0.03 A  (1 V + 0.8 V)] + (0.03 A  0.8 V)] = 1.266 W

P_tot= 0.1 W + 1.266 W = 1.366 W

T_jcalculation:

T_j= T_amb+ R_th(j-a) P_tot

T_j= 50 C + (33.9 C/W  1.366 W) = 96.31 C

This confirms that the junction temperature is below the minimum overtemperature

threshold of 130 C, which ensures the device will not go into thermal shutdown under

these conditions.

It is important to mention that the value of the thermal resistance junction-to-ambient

(R_th(j-a)) strongly depends in the PCB design. Therefore, the thermal pad of the device

should be attached to a big enough PCB copper area to ensure proper thermal dissipation

(similar to JEDEC 51 standard). Several thermal vias in the PCB thermal pad should be

used as well to increase the effectiveness of the heat dissipation (for example, 15 thermal

vias). The thermal vias should be distributed evenly in the PCB thermal pad.

Finally, it is important to point out that this calculation should be taken as a reference only

and therefore evaluations should still be performed under the application environment and

conditions to confirm proper system operation.

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11. Limiting values

Table 20. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

Max

+6.0

5.5

Unit

V

supply voltage

0.5

V_I/O

voltage on an input/output pin

LED driver voltage

V_SS 0.5

V

V_drv(LED)

I_O(LEDn)

I_SS

V_SS 0.5

20

V

output current on pin LEDn

ground supply current

total power dissipation

-

65

mA

A

-

2.5

P_tot

T_amb= 25 C

T_amb= 85 C

-

2.95

1.18

+150

+85

+125

W

C

-

T_stg

T_amb

T_j

storage temperature

ambient temperature

junction temperature

65

40

operating

12. Thermal characteristics

Table 21. Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

C/W

[1]

R_th(j-a)

thermal resistance from junction to ambient HTSSOP38

33.9

[1] Per JEDEC 51 standard for multilayer PCB and wind speed (nm/s) = 0.

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13. Static characteristics

Table 22. Static characteristics

V_DD= 3 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Supply

Conditions

Min

Typ^[1]Max

Unit

V_DD

I_DD

supply voltage

supply current

3

-

5.5

V

on pin V_DD; operating mode;

f_SCL= 1 MHz

R_ext= 2 k; LED[23:0] = off;

IREFx = 00h

-

11

13

15

17

12

14

19

21

mA

R_ext= 1 k; LED[23:0] = off;

IREFx = 00h

R_ext= 2 k; LED[23:0] = on;

IREFx = FFh

R

_ext= 1 k; LED[23:0] = on;

IREFx = FFh

I_stb

standby current

on pin V_DD; no load; f_SCL= 0 Hz;

MODE1[4] = 1; V_I= V_DD

V_DD= 3.3 V

-

100

2

600

A

V

V_DD= 5.5 V

700

V_POR

V_PDR

power-on reset voltage

no load; V_I= V_DDor V_SS

-

[2]

power-down reset voltage

1

V

Inputs USCL, USDA

V_IL

V_IH

I_L

LOW-level input voltage

0.5

0.7V_DD

1

-

+0.3V_DD

5.5

V

HIGH-level input voltage

leakage current

-

V

V_I= V_DDor V_SS

V_I= V_SS

-

+1

A

pF

C_i

input capacitance

-

6

10

Current controlled outputs (LED[23:0])

I_O(LEDn)

output current on pin LEDn

V_O= 0.8 V; IREFx = 80h; R_ext= 1 k

V_O= 0.8 V; IREFx = FFh; R_ext= 1 k

25

50

-

30

60

mA

I_O

output current variation

V_DD= 3.0 V; T_amb= 25 C; V_O= 0.8 V;

IREFx = 80h; R_ext= 1 k;

guaranteed by design

[3]

[4]

between bits (different ICs, same

channel)

-

6

%

between bits (2 channels, same IC)

-

4

%

V

V_reg(drv)

I_L(off)

driver regulation voltage

off-state leakage current

minimum regulation voltage;

0.8

1

20

IREFx = FFh; R_ext= 1 k

V_O= 20 V

-

1

A

OE input, RESET input

V_IL

V_IH

I_LI

LOW-level input voltage

0.5

0.7V_DD

1

-

+0.3V_DD

V

HIGH-level input voltage

input leakage current

input capacitance

-

5.5

+1

5

V

-

A

pF

C_i

-

3.7

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Table 22. Static characteristics …continued

V_DD= 3 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ^[1]Max

Unit

Address inputs AD2, AD1, AD0

V_I

I_LI

C_i

input voltage

voltage on an input pin

0.5

1

-

+5.5

+1

5

V

input leakage current

input capacitance

-

A

pF

3.7

Overtemperature protection

T_th(otp)overtemperature protection

threshold temperature

rising

130

15

-

150

30

C

hysteresis

[1] Typical limits at V_DD= 3.3 V, T_amb= 25 C.

[2] V_DDmust be lowered to 0.8 V in order to reset part.

[3] Part-to-part mismatch is calculated:

I

_OLED0+ I_OLED1+  + I_OLED22+ I_OLED23



















---------------------------------------------------------------------------------------------------------------------------

– ideal output current



24

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

% =

 100

ideal output current

where ‘ideal output current’ = 28.68 mA (R_ext= 1 k, IREFx = 80h).

[4] Channel-to-channel mismatch is calculated:







I_OLEDnwhere n = 0 to 23

---------------------------------------------------------------------------------------------------------------------------------





% =

– 1  100



I

_OLED0+ I_OLED1+  + I_OLED22+ I







^OLED23

---------------------------------------------------------------------------------------------------------------------------





24

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14. Dynamic characteristics

Table 23. Dynamic characteristics

All the timing limits are valid within the operating supply voltage and ambient temperature range; V_DD= 3 V  0.2 V and

5.5 V  0.3 V; T_amb= 40 C to +85 C; and refer to V_ILand V_IHwith an input voltage of V_SSto V_DD

.

Symbol Parameter

f_USCLUSCL clock frequency

t_BUF

Conditions

Min

0

Typ

Max

5000

Unit

kHz

s

[1]

-

bus free time between a STOP and START

condition

0.08

-

t_HD;STA

t_SU;STA

t_SU;STO

t_HD;DAT

t_VD;DAT

t_SU;DAT

t_LOW

hold time (repeated) START condition

set-up time for a repeated START condition

set-up time for STOP condition

data hold time

0.05

10

-

s

ns

-

[2]

data valid time

-

data set-up time

30

50

-

LOW period of the USCL clock

HIGH period of the USCL clock

fall time of both USDA and USCL signals

rise time of both USDA and USCL signals

-

t_HIGH

t_f

-

50

10

t_r

-

t_SP

pulse width of spikes that must be suppressed

by the input filter

-

[1] Minimum USCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either USDA or USCL is

held LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[2] t_VD;DATis not applicable to the UFm I²C-bus slave device.

0.7 × V

0.3 × V

DD

USDA

USCL

DD

t

r

t

f

t

SP

t

HD;STA

BUF

t

LOW

0.7 × V

0.3 × V

DD

t

SU;STO

HD;STA

SU;STA

t

SU;DAT

HD;DAT

HIGH

P

S

Sr

P

002aag331

Fig 19. Definition of timing

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START

condition

(S)

STOP

condition

(P)

(always set

to 1

by master)

bit 7

MSB

bit 1

(D1)

bit 0

(D0)

protocol

bit 6

t

HIGH

SU;STA

LOW

9th

clock

1 / f

USCL

0.7 × V

0.3 × V

DD

USCL

USDA

t

f

BUF

t

r

0.7 × V

0.3 × V

DD

t

SU;STO

t

HD;DAT

HD;STA

SU;DAT

002aag332

Rise and fall times refer to V_ILand V_IH.

Fig 20. UFm I²C-bus timing diagram

15. Test information

V

or V

LED

DD

open

V

SS

V

DD

R

L

50 Ω

V

O

I

PULSE

GENERATOR

DUT

C

L

R

T

50 pF

002aag466

R_L= Load resistor for LEDn.

C_L= Load capacitance includes jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generators.

Fig 21. Test circuitry for switching times

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16. Package outline

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Fig 22. Package outline SOT1331-1 (HTSSOP38)

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17. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

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24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

18.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 23) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 24 and 25

Table 24. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 25. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 23.

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24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 23. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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19. Soldering: PCB footprints

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Fig 24. PCB footprint for SOT1331-1 (HTSSOP38); reflow soldering

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20. Abbreviations

Table 26. Abbreviations

Acronym

Description

ACK

Acknowledge

DUT

Device Under Test

ESD

ElectroStatic Discharge

Field-Effect Transistor

Human Body Model

FET

HBM

I²C-bus

LED

Inter-Integrated Circuit bus

Light Emitting Diode

LSB

Least Significant Bit

MSB

Most Significant Bit

NMOS

PCB

Negative-channel Metal-Oxide Semiconductor

Printed-Circuit Board

PMOS

PWM

RGB

Positive-channel Metal-Oxide Semiconductor

Pulse Width Modulation

Red/Green/Blue

RGBA

SMBus

Red/Green/Blue/Amber

System Management Bus

21. Revision history

Table 27. Revision history

Document ID

PCU9956A v.2.1

Modifications:

Release date

20150629

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCU9956A v.2

• Section 7.3.3 “LEDOUT0 to LEDOUT5, LED driver output state”: added remark.

• Table 8 “MODE1 - Mode register 1 (address 00h) bit description”: Added Table note [3].

PCU9956A v.2

Modifications:

PCU9956A v.1

20141014

• Section 7.5 “Power-on reset”: added remark.

20140124 Product data sheet

Product data sheet

-

PCU9956A v.1

-

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22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

22.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

22.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

PCU9956A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 June 2015

48 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

23. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCU9956A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 June 2015

49 of 50

PCU9956A

NXP Semiconductors

24-channel UFm 5 MHz I²C-bus 57 mA/20 V constant current LED driver

24. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.1.1

8.2

8.3

START and STOP conditions. . . . . . . . . . . . . 29

System configuration . . . . . . . . . . . . . . . . . . . 30

Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . 30

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3

9

Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 31

Application design-in information. . . . . . . . . 34

Thermal considerations . . . . . . . . . . . . . . . . . 35

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 37

Thermal characteristics . . . . . . . . . . . . . . . . . 37

Static characteristics . . . . . . . . . . . . . . . . . . . 38

Dynamic characteristics. . . . . . . . . . . . . . . . . 40

Test information . . . . . . . . . . . . . . . . . . . . . . . 41

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 42

Handling information . . . . . . . . . . . . . . . . . . . 43

4

4.1

5

10

10.1

11

12

13

14

15

16

17

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

7.1

7.1.1

7.1.2

7.1.3

7.2

Functional description . . . . . . . . . . . . . . . . . . . 7

Device addresses. . . . . . . . . . . . . . . . . . . . . . . 7

Regular I²C-bus slave address. . . . . . . . . . . . . 7

LED All Call I²C-bus address . . . . . . . . . . . . . 11

LED Sub Call I²C-bus addresses . . . . . . . . . . 12

Control register. . . . . . . . . . . . . . . . . . . . . . . . 12

Register definitions. . . . . . . . . . . . . . . . . . . . . 14

MODE1 — Mode register 1 . . . . . . . . . . . . . . 16

MODE2 — Mode register 2 . . . . . . . . . . . . . . 16

LEDOUT0 to LEDOUT5, LED driver output

18

Soldering of SMD packages. . . . . . . . . . . . . . 43

Introduction to soldering. . . . . . . . . . . . . . . . . 43

Wave and reflow soldering. . . . . . . . . . . . . . . 43

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 43

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 44

18.1

18.2

18.3

18.4

7.3

7.3.1

7.3.2

7.3.3

19

20

21

Soldering: PCB footprints . . . . . . . . . . . . . . . 46

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47

Revision history . . . . . . . . . . . . . . . . . . . . . . . 47

state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

GRPPWM, group duty cycle control. . . . . . . . 18

GRPFREQ, group frequency . . . . . . . . . . . . . 18

PWM0 to PWM23, individual brightness

control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

IREF0 to IREF23, LED output current value

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

OFFSET — LEDn output delay offset register 21

LED Sub Call I²C-bus addresses for

PCU9956A . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

ALLCALLADR, LED All Call I²C-bus address. 22

PWMALL — brightness control for all LEDn

outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

IREFALL register: output current value for all

LED outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 23

LED driver constant current outputs . . . . . . . . 23

7.3.4

7.3.5

7.3.6

22

Legal information . . . . . . . . . . . . . . . . . . . . . . 48

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 48

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 49

22.1

22.2

22.3

22.4

7.3.7

7.3.8

7.3.9

23

24

Contact information . . . . . . . . . . . . . . . . . . . . 49

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.3.10

7.3.11

7.3.12

7.3.13

7.3.13.1 Adjusting output current . . . . . . . . . . . . . . . . . 23

7.3.14

7.4

7.5

7.6

7.7

Overtemperature protection . . . . . . . . . . . . . . 25

Active LOW output enable input. . . . . . . . . . . 25

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 26

Hardware reset recovery . . . . . . . . . . . . . . . . 26

Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 26

Individual brightness control with group

7.8

dimming/blinking. . . . . . . . . . . . . . . . . . . . . . . 28

8

Characteristics of the PCU9956A Ultra

Fast-mode I²C-bus. . . . . . . . . . . . . . . . . . . . . . 29

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 June 2015

Document identifier: PCU9956A


型号：	PCU9956ATWY
厂家：	NXP
描述：	PCU9956A - 24-channel UFm 5 MHz I2C-bus 57 mA/20 V constant current LED driver TSSOP 38-Pin PC 驱动光电二极管接口集成电路
文件：	总50页 (文件大小：1244K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCU9956ATWY [NXP]

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