PDI1394P11_技术文档

INTEGRATED CIRCUITS

PDI1394P11

3-port physical layer interface

Product specification

1999 Apr 09

Supersedes data of 1998 Sep 24

Philips

Semiconductors

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

1.0 FEATURES

• 3 cable interface ports

2.0 DESCRIPTION

The Philips Semiconductors PDI1394P11 is an IEEE1394-1995

compliant Physical Layer interface. The PDI1394P11 provides the

analog physical layer functions needed to implement a three port

node in a cable-based IEEE 1394–1995 network. Additionally, the

device manages bus initialization and arbitration cycles, as well as

transmission and reception of data bits. The Link Layer Controller

interface is compatible with both 3V and 5V Link Controllers. While

providing a maximum transmission data rate of 200 Mb/s, the

PDI1394P11 is compatible with current 100 Mb/s Physical Layer

ICs. The PDI1394P11 is available in the LQFP64 package.

• Supports 100Mb/s and 200Mb/s transfers

• Interfaces to any 1394 standard Link Layer Controller

• 5V tolerant I/Os with Bus Holders

• Single 3.3V supply voltage

• Arbitrated (short) Bus Reset (1394a feature)

3.0 ORDERING INFORMATION

PACKAGE

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

PKG. DWG. #

64-pin plastic LQFP

0°C to +70°C

PDI1394P11 BD

SOT314-2

4.0 PIN CONFIGURATION

1

2

RESET–

LPS

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

TPBIAS3

TPBIAS2

TPBIAS1

TPA1+

TPA1–

TPB1+

TPB1–

AGND

LREQ

DVDD

PD

3

4

5

6

7

8

DGND

SYSCLK

DGND

CTL0

CTL1

D0

PDI1394P11

9

TPA2+

TPA2–

TPB2+

TPB2–

TPA3+

TPA3–

TPB3+

TPB3–

10

11

12

13

14

15

16

D1

D2

D3

SV00229

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1999 Apr 09

853–2150 21222

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

5.0 PIN DESCRIPTION

PIN NUMBER

PIN SYMBOL

RESET–

LPS

I/O

I*

NAME AND FUNCTION

Power up reset, active LOW

1

2

3

4

I*

Link Layer Controller (LLC) power status

Link request from controller

LREQ

DVDD

Should be connected to the LLC V supply when a 5V LLC is connected to the

DD

Phy, and should be connected to the Phy DVDD when a 3V LLC is used.

5, 6, 19, 20

DVDDD

PD

I

Digital circuit power

7

I*

Device power down input

8, 10, 17, 18, 63, 64

DGND

–

Digital circuit ground

9

SYSCLK

CTL[0:1]

D[0:3]

O*

I/O*

I*

49.152 MHz clock to link controller

Link interface bi-directional control signals

Link interface bi-directional data signals

11, 12

13, 14, 15, 16

22, 21

TESTM[1:2]

Test/Mode Control pins

11 =1394–1995 mode

10 = 1394a mode

00/01 = Reserved

23

CPS

I

Cable power status

24, 25, 51, 55

AVDD

–

Analog circuit power

26, 32, 41, 49, 50, 61

AGND

–

Analog circuit ground

27

C/LKON

PC[0:2]

CNA

I/O*

I*

Bus/Isochronous Resource Manager capable input, or LINK-ON signal output

Power class bits 0 through 2 inputs

Cable Not Active output

30, 29, 28

31

O*

I/O

O

36, 40, 45

35, 39, 44

34, 38, 43

33, 37, 42

46, 47, 48

52, 53

54

TPA[1:3]+

TPA[1:3]–

TPB[1:3]+

TPB[1:3]–

TPBIAS[1:3]

PLLGND

FILTER

XI

Port n cable pair A, positive signal

Port n cable pair A, negative signal

Port n cable pair B, positive signal

Port n cable pair B, negative signal

Cable termination voltage supplies

PLL circuit ground

–

I/O

I

PLL external filter capacitor

56

Crystal oscillator connection

PLL circuit power

57

XO

O

58

PLLVDD

R[0:1]

–

59, 60

62

–

External current setting resistor

Link interface isolation status input

ISO–

I*

NOTE:

* Indicates 5V tolerant structure.

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1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

6.0 BLOCK DIAGRAM

R0

R1

CPS

LPS

BIAS

VOLTAGE AND

CURRENT

RECEIVED

DATA

DECODER/

ISO–

CNA

TPBIAS1

TPBIAS2

TPBIAS3

GENERATOR

TIMER

SYSCLK

PORT 1

LREQ

LINK

INTERFACE

TPA1+

TPA1–

CTL0

CTL1

D0

D1

D2

D3

TPB1+

TPB1–

ARBITRATION

AND CONTROL

STATE

MACHINE

LOGIC

PC0

PC1

TPA2+

TPA2–

PC2

PORT 2

PORT 3

TPB2+

TPB2–

C/LKON

TPA3+

TPA3–

TESTM1

TESTM2

TPB3+

TPB3–

CRYSTAL

OSCILLATOR

PLL SYSTEM

& TRANSMIT

CLOCK

XI

XO

TRANSMIT

DATA

ENCODER

FILTER

GENERATOR

RESET–

PD

SV00228

monitor conditions on the cable to determine connection status, data

speed, and bus arbitration states.

7.0 FUNCTIONAL SPECIFICATION

The PDI1394P11 is an IEEE1394–1995 High Performance Serial

Bus Specification compliant physical layer interface device. It

provides an interface between an attached link layer controller and

three 1394 cable interface ports. In addition to the interface function,

the PDI1394P11 performs bus initialization and arbitration functions

as well as monitoring line conditions and connection status.

The PDI1394P11 receives data to be transmitted over the bus from

two or four parallel data paths to the Link Controller, D[0:3]. These

data paths are latched and synchronized with the 49.152 MHz clock.

The parallel bit paths are combined serially, encoded and

transmitted at either 98.304 Mb/s or 196.608 Mb/s, depending

whether the transaction is a 100 Mb/s or 200 Mb/s transfer,

respectively. The transmitted data is encoded as data-strobe

information, with the data information being transmitted on the TPB

cable pairs and the strobe information transmitted on the TPA cable

pairs.

7.1 Clocking

The PDI1394P11 utilizes a stable internal reference clock of

196.608 MHz. The reference clock is generated using an external

24.576 MHz crystal and an internal Phase Locked Loop (PLL). The

PLL clock is divided down to 49.152 MHz and 98.304 MHz clock

signals. The 49.152 MHz clock is used for internal logic and

provided as an output to clock a link layer controller. The 196.608

MHz and 98.304 MHz clocks are used for synchronization of the

transmitted strobe and data information.

During packet reception the TPA and TPB transmitters of the

receiving cable port are disabled, and the receivers for that port are

enabled. The encoded data information is received on the TPA cable

pair and the strobe information is received on the TPB cable pair.

The combination of the data and strobe signals is decoded to

recover the receive clock signal and the serial data stream. The

serial data stream is converted to two or four parallel bit streams,

resynchronized to the internal 49.152 MHz clock and sent to the

7.2 Port Interfaces

The PDI1394P11 provides the transceiver functions needed to

implement a three port node in a cable-based 1394 network. Each

cable port incorporates two differential line transceivers. In addition

to transmission and reception of packet data, the line transceivers

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1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

associated link controller. The received data is also transmitted out

the other active cable ports.

presence of the remotely supplied twisted-pair bias voltage,

indicating the cable connection status.

The cable status, bus initialization and arbitration states are

monitored through the cable interface using differential comparators.

The outputs of these comparators are used by internal logic to

determine cable and arbitration status. The TPA channel monitors

the incoming cable common-mode voltage value during arbitration to

determine the speed of the next packet transmission. The TPB

channel monitors the incoming cable common-mode voltage for the

The PDI1394P11 provides a nominal 1.85 V for driver load

termination. This bias voltage, when seen through a cable by a

remote receiver, is used to sense the presence of an active

connection. The value of this bias voltage has been chosen to allow

inter-operability between transceiver chips operating from either 5 V

nominal supplies, or 3.3 V nominal supplies. This bias voltage

source should be stabilized by using an external filter capacitor.

8.0 RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

CONDITION

UNIT

MIN

3.0

TYP

MAX

3.6

V

DD

DC supply voltage

Source/non-source power node

CMOS inputs

3.3

V

IH

High level input voltage

Low level input voltage

Differential input voltage

2.0

5.5

V

IL

CMOS inputs

0.8

V

Cable inputs, 100Mbit operation

Cable inputs, 200Mbit operation

Cable inputs, during arbitration

142

132

171

260

262

mV

ID–100

ID–200

ID–ARB

V

TPB cable inputs, 100Mbit or speed signaling OFF,

source power node

1.165

0.935

2.515

2.015

2.515

2.015

V

Common mode voltage

V

IC–100

TPB cable inputs, 100Mbit or speed signaling OFF,

non–source power node

TPB cable inputs, 200Mbit or speed signaling,

source power node

V

Common mode voltage

Receive input jitter

IC–200SP

TPB cable inputs, 200Mbit or speed signaling,

non–source power node

TPA, TPB cable inputs, 100Mbit operation

TPA, TPB cable inputs, 200Mbit operation

±1.08

±0.5

ns

Between TPA and TPB cable inputs, 100Mbit

operation

±0.8

ns

Receive input skew

Between TPA and TPB cable inputs, 200Mbit

operation

±0.55

SYSCLK

–16

–12

16

12

I

/I

Output current, I /I

mA

OL OH

Control, Data, CNA, C/LKON

TPBIAS outputs

I

O

Output current

–3

1.3

mA

f

Crystal frequency

Parallel resonant fundamental mode crystal

24.5735

24.576

24.5785

MHz

XTAL

Operating ambient

temperature range in free air

T

amb

0

+70

°C

5

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

1, 2

9.0 ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).

LIMITS

SYMBOL

PARAMETER

CONDITION

UNIT

MIN

–0.3

–0.5

MAX

V

I

DC supply voltage

4.6

V

DD

3

V

I

DC input voltage

Inputs CPS, TPAn, TPBn, FILTER, XI

V

+0.5

DD

5V tolerant digital inputs RESET–, LPS, LREQ, PD,

CTL[0:1], D[0:3], TESTM[2:1], C/LKON, PC[0:2], ISO–

DC input voltage

–0.5

5.5

+0.5

V

I,5t

3

V

O

DC output voltage

–0.5

–

V

DD

DC input diode current

DC output diode current

Storage temperature range

V < 0

I

–50

mA

°C

IK

I

V

O

< 0 or V > V

DD

–

±50

OK

O

T

stg

–65

+150

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output clamp current ratings are observed.

10.0 CABLE DRIVER

LIMITS

SYMBOL

PARAMETER

TEST CONDITION

UNIT

MIN

TYP

MAX

V

Differential output voltage

Difference current, TPA+, TPA–, TPB+, TPB–

Common mode speed signaling current, TPB+, TPB– 200Mbit speed signaling enabled

OFF state common mode voltage Drivers disabled

56 W load

172

265

mV

mA

mV

OD

1

2

1

I

Driver enabled, speed signaling OFF –1.05

1.05

O(diff)

2

I

SP

+2.53

+4.84

20

V

OFF

NOTES:

1. Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.

2. Limits defined as one half of the algebraic sum of currents flowing into TPB+ and TPB–.

11.0 CABLE RECEIVER

LIMITS

SYMBOL

PARAMETER

Common mode input current

TEST CONDITION

Driver disabled

UNIT

MIN

–20

15

TYP

MAX

I

IC

20

µA

kΩ

pF

kΩ

pF

mV

V

Z

Differential input impedance

Driver disabled

ID

IC

6

20

Z

Common mode input impedance

24

60

V

Receiver input threshold voltage

–60

0.6

TH

Cable bias detect threshold, TPBn cable inputs

Driver disabled

1.0

TH

6

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

12.0 OTHER DEVICE I/O

LIMITS

SYMBOL

PARAMETER

TEST CONDITION

One port transmitting

UNIT

MIN

TYP

MAX

One port receiving

V

DD

= 3.3 V

60

mA

One port not connected

I

Supply current

DD

V

= 3.6 V

175

5

mA

V

DD

= 3.6 V Power-down mode

1.5

4.7

2

DD

V

Cable Power Threshold Voltage

High-level output voltage

Low-level output voltage

R = 400 kΩ to CPS pin

7.5

P

L

V

OH

I

= Max., V = Min.

V – 0.55

DD

V

OH

OL

DD

V

OL

= Min., V = Max.

0.5

V

DD

Input current, LREQ, LPS, PD,

TESTM[1:2]

I

V = 5.5 V or 0 V, ISO– = 0

±1.0

µA

I

OFF-state output current, CTLn,

Dn, C/LKON I/Os, PC[0:2] inputs

I

V

O

= 5.5 V or 0 V, ISO– = 0

±5.0

OZ

PU

V = 1.5 V

I

–20

–22

–40

–45

–80

–90

µA

Pullup current, RESET– input

V = 0 V

I

V = V

I

DD

I

Pulldown current, RESET– input

100

260

450

µA

PD

PD = high

Power-up reset time, RESET– input

C = 0.1 µf

2

ms

Positive arbitration comparator threshold

voltage

+

V

89

168

mV

TH

Negative arbitration comparator threshold

voltage

–

–168

49

–89

131

mV

V

TH

V

Speed signal input threshold voltage

TH–SP

Positive going input threshold voltage,

LREQ, CTLn, Dn inputs

+

V

/2 + 0.12

V

/2 + 0.66

IT

DD

Negative going input threshold voltage,

LREQ, CTLn, Dn inputs

–

V

/2 – 0.66

/2 – 0.12

V

IT

DD

V

TPBIASn output voltage

1.665

1.85

190

2.015

O

Absolute value of bus holding current

LREQ, PD, CTLn, Dn inputs, LPS

I

b

ISO– = high, V = 0.5 V

DD

µA

I

13.0 THERMAL CHARACTERISTICS

LIMITS

TYP

SYMBOL

PARAMETER

TEST CONDITION

Board mounted, no air flow

UNIT

MIN

MAX

RΘjA

RΘjC

Junction-to-free-air thermal resistance

Junction-to-case thermal resistance

92.5

°C/W

10.4

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1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

14.0 AC SWITCHING CHARACTERISTICS

LIMITS

TYP

SYMBOL

PARAMETER

MEASURED

TEST CONDITION

UNIT

MIN

MAX

±0.25

±0.15

2.2

Transmit jitter

TPA, TPB

ns

Transmit skew

Between TPA and TPB

10% to 90%

t

r

Transmit rise time

Transmit fall time

R = 56Ω, C = 10 pF

L L

t

f

90% to 10%

R = 56Ω, C = 10 pF

2.2

L

Dn, CTLn, LREQ input setup time

to SYSCLK

t

su

50% to 50%

See Figure 1

5

ns

Dn, CTLn, LREQ input hold time

from SYSCLK

t

50% to 50%

See Figure 1

See Figure 2

2

ns

H

t

D

Delay time, SYSCLK to Dn, CTLn

13

15.0 SWITCHING WAVEFORMS

SYSCLK

50%

SYSCLK

50%

t

SU

t

H

t

D

Dn, CTLn, LREQ

50%

Dn, CTLn

50%

SV00238

SV00239

Figure 1. Dn, CTLn, LREQ input setup and hold times

Figure 2. Dn, CTLn, output delay relative to SYSCLK

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1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

16.0 INTERNAL REGISTER CONFIGURATION

The accessible internal registers of this device are listed in the following tables:

ADDRESS

0000

0001

0010

0011

0

1

2

3

4

5

6

7

Physical ID

R

CPS

RHB

IBR

GC

SPD

Reserved

BSTAT1

BSTAT2

BSTAT3

NP

AStat1

AStat2

AStat3

Ch1

Ch2

Ch3

Con1

Con2

Reserved

0100

0101

0110

Con3

Loopint

CPSint

CPS

IR

Reserved

PC1

C

0111

Reserved

PC2

PC0

1000

1001

Reserved

ISBR

The keys are listed as follows:

FIELD

Physical ID

R

SIZE TYPE

DESCRIPTION

6

Rd

The address of the local node determined during the Self-ID.

Indicates that the local node is the root.

1

6

2

4

2

CPS

Cable power Status (CPS input).

RHB

Rd/Wr Root hold-OFF bit. Instructs the local node to try to become the root during the next bus reset.

Rd/Wr Initiate Bus Reset. Instructs the PDI1394P11 to initiate Bus Reset at the next opportunity.

IBR

GC

Rd/Wr Gap count. Used to optimize the gap times based on the size of the network. See 1394 standard for details.

SPD

Rd

Indicates the top signaling speed of the local ports.

The number of ports on this device, set to 0011.

NP

AStat(n)

The line state of TPA of port n:

11 = Z

01 = 1

10 = 0

00 = invalid data state. Power up reset initializes to this line state. Also this line state is output during

transmit and receive operations. The line state outputs are generally valid during arbitration and idle

conditions on the bus.

BStat(n)

Ch(n)

2

1

2

1

Rd

The line state of TPB of port n. The encoding is the same as AStat(n).

If = 1, then port n is a child, otherwise it is a parent.

Con(n)

Loopint

If = 1, then port n is connected, otherwise it is disconnected.

Rd/Wr Indicates that the PDI1394P11 times out in tree ID, waiting for child signal from two or more ports. The

Loopint can be cleared by writing a ‘‘0’’ to this bit, but if the loop configuration has not been corrected, it will

promptly return to a ‘‘1’’.

CPSint

1

Rd/Wr Indicates that the cable power has dropped too low for guaranteed reliable operation. It can be cleared by

writing a ‘‘0’’ to the bit, but it will immediately return if CPS is still LOW.

CPS

IR

1

Rd/Wr Cable Power Status is also included in this register to expedite handling the CPSint.

Rd/Wr Indicates that the last bus reset was initiated in the PDI1394P11. This bit is also included in the self ID

packet.

C

1

Rd

If set, this node is a contender for the role of bus or Isochronous Resource Manager.

The least significant power class bit

PC2

PC1

PC0

ISBR

The middle power class bit

The most significant power class bit

Rd/Wr Initiate Short Bus Reset. Instructs the PDI1394P11 to initiate an arbitrated short bus reset.

See Section 17.1.

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1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

17.0 APPLICATION INFORMATION

TP CABLES

TPBIAS

TP CABLES

49

50

AGND

CNA

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

CNA OUT

51 AVDD

PC0

PC1

PC2

VDD

POWER-CLASS

PROGRAMMING

52

53

54

55

56

57

58

59

60

PLLGND

FILTER

AVDD

XI

CONTENDER

PROGRAMMING

C/LKON

AGND

AVDD

10K

V

0.1µF

DD

PDI1394P11

V

DD

12pF

XO

AVDD

CABLE POWER

V

400K

PLLVDD

R0

CPS

TESTM1

TESTM2

DVDD

DD

6.3K

R1

12pF

V

DD

61 AGND

ISO–

62

ISO–

DVDD

63

64

DGND

0.1µF

POWER

DOWN

LINK LAYER

CONTROLLER

INTERFACE

V

DD

V

DD

LINK LAYER

CONTROLLER

INTERFACE

SV00231

Figure 3. External Component Connections

400K

CPS

V

P

CABLE

POWER PAIR

PDI1394P11

1µF

TPBIAS

G

56Ω

TPAn+

TPAn–

CABLE

PAIR A

CABLE PORT

TPBn+

TPBn–

CABLE

PAIR B

56Ω

250pF

5KΩ

SV00236

Figure 4. Twisted pair cable interface connections

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1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

The external resistor (R) needed to set the CPS trip voltage (V

to a desired voltage can be calculated using the following equation:

)

17.1 Arbitrated (short) Bus Reset

cable

A 1394-1995 software initiated bus reset assumes that the state of

the bus is unknown when reset occurs and requires that the reset be

long enough to permit the longest transaction to finish and still

complete reset (167µs min. to 250µs max.). The total duration of bus

initialization is longer than the nominal isochronous cycle time

(125µs) and may disrupt two isochronous periods. This compels

device designers to add additional buffer depth to preserve the

smooth flow of isochronous data from the perspective of their

application. If a node that initiates a reset arbitrates for control of the

bus prior to asserting reset, arbitration time can be shortened

significantly (1.3µs min. to 80µs max.). This 1394a concept is known

as Arbitrated (short) Bus Reset, and is incorporated in the

PDI1394P11.

(V_cable* 1.85V)

R +

10mA

The external and internal circuitry associated with the CPS pin is

illustrated in Figure 5.

V

cable

R

COMPARATOR

CPS

The TESTM2 (pin 21) pins is used to enable Arbitrated (short) Bus

Reset mode. In 1394-1995 mode, this pin is tied high. In this mode,

an arbitrated bus reset cannot be initiated from this node and will be

treated as a “long” bus reset if initiated by another node. In

accordance with the 1394-1995 spec, all bus resets on the entire

bus will be “long”.

I

V

1.85V

comp

10µA

Phy

To enable Arbitrated (short) Bus Reset mode, set TESTM2 low.

With the part in this mode, writing a 1 to the ISBR (Initiate Short Bus

Reset) bit (bit 7) of Phy register 9 initiates an arbitrated bus reset.

This mode also allows the Phy to recognize arbitrated bus resets

initiated by other nodes. Non-arbitrated bus resets can still be

initiated from this node and are recognized and processed correctly

when initiated by another node.

SV00921

Figure 5.

Some typical threshold voltage values and their associated resistor

values are shown in Table 1.

17.2 Setting the CPS Trip Point

The Cable Power Status (CPS) pin (pin 23) is used to monitor the

cable power. When cable power voltage has dropped too low for

reliable operation, internal circuitry trips, which clears the CPS bits

in the Phy registers (bit 7 of register 0, and bit 2 of register 6). This

action causes a cable power status interrupt which sets the CPSint

bit in the Phy registers (bit 1 of register 6). This bit can be cleared by

a hardware reset or by writing a 0 to the CPSint bit. However, if the

CPS input is still low, another cable-power status interrupt

immediately occurs. The cable voltage at which these events occur

is adjustable on the PDI1394P11.

Table 1. Typical threshold voltage values

V

cable

DETECTOR

TOLERANCE % WITH:

V

cable

(V)

R (kΩ)

R of 5%

6.8

R of 2%

4.4

5

6

7

8

9

315

415

515

615

715

7.3

4.8

7.8

5.2

8.3

5.6

8.8

6.0

11

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

18.0 EXTERNAL COMPONENTS AND CONNECTIONS

18.1 Logic Reset input (RESET–, pin 1)

18.10 Bus or Isochronous Resource Manager

Forcing this pin low causes a Bus Reset condition on the active

cable ports, and resets the internal logic to the Reset Start state.

SYSCLK remains active. An internal pull-up resistor is provided that

Capable input or Link-On output (C/LKON, pin 27)

This is a bi-directional pin that is used as an input to specify, in the

Self-ID packet, that the node is Bus or Isochronous Resource

Manager Capable. As an output it signals the reception of a Link-On

message by supplying a 6.114 MHz signal. The bit value

is connected to V , so only an external delay capacitor is required.

DD

This input is a standard logic buffer and may also be driven by an

open drain logic output buffer. The RESET pin also has a n-channel

pull-down transistor activated by the PD (Power Down) pin.

programming is done by tying the pin through a 10kΩ resistor to a

high (V ) or low (GND). The use of the series resistor allows the

DD

Link-On to override the input value when necessary.

18.2 Link Power Status input (LPS, pin 2)

In a non-isolated implementation a 10kΩ resistor is connected to the

18.11 Power Class bits 0 through 2 inputs

(PC[0:2], pins [30,29,28])

Used as inputs to set the bit values of the three Power Class bits in

the self-ID packet (bits 21, 22 and 23). These bits can be

V

DD

supplying the link layer controller to monitor the link’s power

status. In an isolated implementation a square wave with a minimum

frequency of 500 kHz can be applied to the LPS pin to indicate the

pin is powered. If the link is not powered on the Control I/O’s (pins

11,12), Data I/O’s (pins 13 – 16) and SYSCLK output (pin 9) are

disabled, and the PDI1394P11 will perform only the basic repeater

functions required for network initialization and operation.

programmed by tying the pins high to V or low to GND.

DD

18.12 Cable Not Active output (CNA, pin 31)

This pin outputs the cable connection status. If all ports are

disconnected this pin outputs a high. If any port has a cable

connected then this pin outputs a low.

18.3 Link Request input (LREQ, pin 3)

LREQ is a signal from the link layer controller used to request the

PDI1394P11 to perform some service. This pin supports an optional

isolation barrier.

18.13 Twisted Pair I/O’s (TPA[1:3]+,

pins [45, 40, 36], TPA[1:3]–, pins [44,39,35],

TPB[1:3]+, pins [43,38,34], TPB[1:3]–,

18.4 Power Down input (PD, pin 7)

pins [42, 37, 33])

This input powers down all device functions with the exception of the

CNA circuit to conserve power in portable or battery powered

applications. It must be held high for at least 3.5ms to assure a

successful reset after power down. This pin supports an optional

isolation barrier.

These pins send and receive differential data over the twisted pair

cables. Two series connected external 56 Ω cable termination

resistors are required at each twisted pair. Each unused TPB pin

must be tied through a 5kΩ resistor to ground. The TPA pins can be

left floating.

18.5 System Clock output (SYSCLK, pin 9)

Provides a 49.152 MHz clock signal, synchronized with the data

transfers, to the link layer controller. This pin supports an optional

isolation barrier.

18.14 Twisted Pair Bias outputs (TPBIAS[1:3],

pins [46, 47, 48])

These outputs provide the 1.86 V nominal bias voltage needed for

proper operation of the twisted pair cable drivers, and for signaling

to the remote nodes that there is a valid cable connection. Three

TPBIAS outputs are provided for separate connection to each of the

three TPA twisted pairs to provide electrical isolation. A 1µF

capacitor to ground must be connected to each TPBIAS pin whether

it is used or not.

18.6 Control I/Os (CTL[0:1], pins[11,12])

These are bi-directional signals used in the communication between

the PDI1394P11 and the link layer controller that control passage of

information between the two devices. These pins support an

optional isolation barrier.

18.7 Data I/Os (D[0:3], pins [13,14,15,16])

These are bi-directional information signals used in the

communication between the PDI1394P11 and the link layer

controller. These pins support an optional isolation barrier.

18.15 PLL Filter (FILTER, pin 54)

This pin is connected to an external filter capacitor used in a

lag-lead filter for a PLL frequency multiplier running off of the crystal

oscillator.

18.8 Test Mode control and ISBR mode inputs

(TESTM[1:2], pins[22,21])

These two logic signals are used in manufacturing to enable

production line testing of the PDI1394P11. For normal use these

18.16 Oscillator crystal (Xl, pin 56 & XO, pin 57)

These pins connect to a 24.576 MHz parallel resonant fundamental

mode crystal. The optimum values for the external shunt capacitors

are dependent on the specifications of the crystal used, the

suggested values of 12 pF are appropriate for one specified for

15 pF loads.

should be tied to V . To enable ISBR (Arbitrated (short) bus reset)

DD

mode, set TESTM1 high and TESTM2 low. See section 17.1 for

more information on ISBR mode.

18.17 Current setting resistor (R[0:1],

pins [59,60])

An internal reference voltage is applied across the resistor

connected between these two pins to set the internal operating and

the cable driver output currents. A low TCR (<150ppm/°C

temperature coefficient) with a value of 6.34 kΩ ±1% should be used

to meet the 1394 standard output voltage limits.

18.9 Cable Power Status input (CPS, pin 23)

This is normally connected to the cable power through an external

resistor. The circuit drives an internal comparator which is used to

detect the presence of cable power. This information is maintained

in an internal register and is available to the link layer controller

through a register read. See section 17.2 for information on setting

the CPS trip point.

12

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

18.18 Isolation Barrier disable (ISO–, pin 62)

When ISO– is high, busholder circuits are enabled on the LREQ,

PD, and LPS input pins and on the CTL, and Data bidirectional pins.

This mode also allows isolation using a single 1nF capacitor per

signal line. When ISO– is low, busholder circuits are disabled and

isolation can be realized by using the scheme explained in Annex J

of the 1394–1995 spec.

19.2 Request

When the link layer controller wishes to request the bus, or access a

register that is located in the PDI1394P11, a serial stream of

information is sent across the LREQ line. The length of the stream

will vary depending on whether the transfer is a bus request, a read

command, or a write command. Regardless of the type of transfer, a

start bit of 1 is required at the beginning of the stream, and a stop bit

of 0 is required at the end of the stream. Bit 0 is the most significant,

and is transmitted first. The LREQ line will be required to idle low

(logic level 0).

18.19 Supply filters (AVDD, pins [24, 25, 51, 55],

DVDD, pins [5,6,19,20], and PLLVDD, pin 58)

A combination of decoupling capacitors is suggested for each

supply group, such as paralleled 10 µF and 0.1 µF. The high

frequency 0.1 µF capacitors should be mounted as close as

possible to the PDI1394P11 device supply leads. These supply lines

are separated on the IC to provide noise isolation. They should be

tied together at a low impedance point on the circuit board.

Individual filter networks are desirable.

19.2.1 Link Layer Controller Bus Request

For a Bus Request, the length of the LREQ data stream is 7 bits as

follows:

BIT(S) NAME

DESCRIPTION

0

Start Bit

Indicates the beginning of the transfer

(always 1)

1–3

Request Type

Indicates the type of bus request (see

the table below for the encoding of this

field)

Details of a phy-link Interface supporting an optional isolation barrier

are provided in Annex J of the 1394 standard.

4–5

6

Request Speed This should be 00 for PDI1394P11’s

100 Mbit/s speed and 01 for

19.0 PRINCIPLES OF OPERATION

The PDI1394P11 is designed to operate with a link layer controller.

These devices use an interface such as described in Annex J of the

1394 standard. The following describes the operation of the phy-link

interface.

200 Mbit/s speed.

Stop Bit

Indicates the end of the transfer

(always 0)

19.1 Data Transfer and Clock rates

19.2.2 Link Layer Controller Requests Read Register Access

For a Read Register Request, the length of the LREQ data stream is

9 bits as follows:

The PDI1394P11 supports 100/200 Mbit/s data transfer, and has

four bi-directional data lines D[0:3] crossing the interface. In 100

Mbit/s operation only D[0:1] pins are used, in 200 Mbit/s operations

all D[0:3] pins are used for data transfer. The unused D[n] pins are

driven low. In addition there are two bi-directional control lines CTL[0:1],

the 50 MHz SYSCLK line from the phy to the link, and the link request

line LREQ from the link to the phy. The PDI1394P11 has control of

all the bi-directional pins. The link is allowed to drive these pins only

after it has been given permission by the phy. The dedicated LREQ

request pin is used by the link for any activity which it wishes to

initiate.

BIT(S) NAME

DESCRIPTION

0

Start Bit

Indicates the beginning of the transfer

(always 1)

1–3

Request Type Always a 100 indicating that this is a

read register request

4–7

8

Address

Stop Bit

The address of the phy register to be read

Indicates the end of the transfer (always 0)

When the phy has control of the bus the CTL[0:1] lines are encoded

as follows:

19.2.3 Link Layer Controller Requests Write Register Access

For a Write Register Request, the length of the LREQ data stream is

17 bits. The details of bits are as shown below:

CTL [0:1] NAME

DESCRIPTION OF ACTIVITY

BIT(S) NAME

DESCRIPTION

00

01

10

11

Idle

No activity is occurring (this is the default

mode).

0

Start Bit

Indicates the beginning of the transfer

(always 1)

Status

Status information is being sent from the

phy to the link.

1–3

4–7

8–15

16

Request Type Always a 101 indicating that this is a

write register request

Receive An incoming packet is being sent from the

phy to the link.

Address

The address of the phy register to be

written to

Grant

The link has been given control of the bus

to send an outgoing packet.

Data

The data that is to be written to the

specified register address

When the link has control of the bus (phy permission) the CTL[0:1]

lines are encoded as follows:

Stop Bit

Indicates the end of the transfer (always 0)

CTL [0:1] NAME

DESCRIPTION OF ACTIVITY

00

Idle

The link releases the bus (transmission

has been completed).

01

Hold

The link is holding the bus while data is

being prepared for transmission or

sending another packet without arbitrating.

10

11

Transmit An outgoing packet is being sent from the

link to the phy.

NA

None

13

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

19.2.4 Other Requests and LREQ

The three bit Request Type field has the following possible values:

BIT(S)

000

NAME

DESCRIPTION

ImmReq

IsoReq

PriReq

Immediate request: Upon detection of an idle, take control of the bus immediately (no arbitration)

Isochronous request: Arbitrate for the bus, no gaps

Priority request: Arbitrate after a subaction gap, ignore fair protocol

Fair request: Arbitrate after a subaction gap, follow fair protocol

Return the specified register contents through a status transfer

Write to the specified register

001

010

011

FairReq

RdReg

WrReg

Reserved

100

101

110, 111

Reserved

19.3 Operation of LREQ

LR0

LR1

LR2

LR3

LR(n–2)

LR(n–1)

SV00232

Figure 6. LREQ Input Sequence (each cell represents one SYSCLK sample time)

For fair or priority access, the link requests control of the bus at least

one clock after the phy-link interface becomes idle. If the link senses

that the CTL pins are in a receive state (CTL[0:1] = 10), then it will

know that its request has been lost. This is true anytime during or

after the link sends the bus request transfer. Additionally, the phy will

ignore any fair or priority requests if it asserts the receive state while

the link is requesting the bus. The link will then reissue the request

one clock after the next interface idle.

removed. The only side effect would be the loss of the intended

acknowledgment packet (this will be handled by the higher-layer

protocol).

19.4 Read/Write Requests

When the link requests to read the specified register contents, the

phy will send the contents of the register to the link through a status

transfer. If an incoming packet is received while the phy is

transferring status information to the link, the phy will continue to

attempt to transfer the contents of the register until it is successful.

The cycle master uses a normal priority request to send a cycle start

message. After receiving a cycle start, the link can issue an

isochronous bus request. When arbitration is won, the link proceeds

with the isochronous transfer of data. The isochronous request will

be cleared by the phy once the link sends another type of request or

when the isochronous transfer has been completed.

For write requests, the phy will load the data field into the

appropriately addresses register as soon as the transfer has been

completed. The link will be allowed to request read or write

operations at any time.

The ImmReq request is issued when the link needs to send an

acknowledgment after reception of a packet address to it. This

request must be issued during packet reception. This is done to

minimize the delays that a phy would have to wait between the end

of a packet and the transmittal of an acknowledgment. As soon as

the packet ends, the phy immediately grants access of the bus to

the link. the link will send an acknowledgment to the sender unless

the header CRC of the packet turns out to be bad. In this case, the

link will release the bus immediately; it will not be allowed to send

another type of packet on this grant. To guarantee this, the link will

be forced to wait 160 ns after the end of the packet is received. The

phy then gains control of the bus and the ack with the CRC error is

sent. Then the bus is released and allowed to proceed with another

request.

19.5 Status

A status transfer is initiated by the phy when it has status

information to transfer to the link. The phy will wait until the interface

is idle before starting the transfer. The transfer is initiated by

asserting the following on the control pins: CTL[0:1] = 01 along with

the first two bits of status information on the D[0:1] pins. The phy

maintains CTL[0:1] = 01 for the duration of status transfer. The phy

may prematurely end a status transfer by asserting something other

than CTL[0:1] = 01 on the control pins. This could be caused by an

incoming packet from another node. The phy will continue to attempt

to complete the transfer until the information has been successfully

transmitted. There must be at least one idle cycle in between

consecutive status transfers.

The phy normally sends just the first four bits of status to the link.

These bits are status flags which are needed by the link state

machines. The phy sends an entire status packet to the link after a

request transfer which contains a read request, or when the phy has

pertinent information to send to the link or transaction layers. The

only defined condition when the phy automatically sends a register

to the link is after self-ID, when it sends the physical-ID register

which contains the new node address.

Although highly improbable, it is conceivable that the two separate

nodes will believe that an incoming packet is intended for them. The

nodes then issue a ImmReq request before checking the CRC of the

packet. Since both phys will seize control of the bus at the same

time, a temporary, localized collision of the bus will occur

somewhere between the competing nodes. This collision would be

interpreted by the other nodes on the network as being a ‘ZZ’ line

state, not a bus reset. As soon as the two nodes check the CRC, the

mistaken node will drop its request and the false line state will be

The definition of the bits in the status transfer are shown below.

14

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

20.0 STATUS REQUEST, LENGTH OF STREAM: 16 BITS

BIT(S)

NAME

DESCRIPTION

0

Arbitration reset gap

Indicates that the phy has detected that the bus has been idle for an arbitration reset gap time (this time is

defined in the P1394 standard). This bit is used by the link in its busy/retry state machine.

1

Subaction gap

Indicates that the phy has detected that the bus has been idle for a subaction gap time (this time is defined

in the P1394 standard). This bit is used by the link to detect the completion of an isochronous cycle.

2

3

Bus Reset

Indicates that the phy has entered the bus reset state.

State Time out or

CPS

Indicates that the phy stayed in a particular state for too long a period, which is usually the effect of a loop

in the cable topology, or that the cable power has dropped below the threshold for reliable operation.

4–7

Address

Data

These bits hold the address of the phy register whose contents will be transferred to the link.

The data that is to be sent to the link.

8–15

21.0 STATUS TRANSFER TIMING

PHY

CTL [0:1]

00

01

00

PHY

D [0:1]

00

S[0,1]

S[2,3]

S[14,15]

00

SV00233

Figure 7. Status Transfer Timing

15

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

assert ‘Idle’ on the CTL lines for one clock cycle after which it

releases control of the interface.

22.0 TRANSMIT

When the link wants to transmit information, it will first request

access to the bus through the LREQ pin. Once the phy receives this

request, it will arbitrate to gain control of the bus. When the phy wins

ownership of the serial bus, it will grant the bus to the link by

asserting the ‘transmit’ state on the CTL pins for at least one

SYSCLK cycle, followed by idle for one clock cycle.

However, there will be times when the link will need to send another

packet without releasing the bus. For example, the link may want to

send consecutive isochronous packets or it may want to attach a

response to an acknowledgment. To do this, the link will assert ‘hold’

instead of ‘Idle’ when the first packet of data has been completely

transmitted. ‘Hold’, in this case, informs the phy that the link needs

to send another packet without releasing control of the bus. The phy

will then wait a set amount of time before asserting ‘transmit’. The

link can then proceed with the transmittal of the second packet. After

all data has been transmitted and the link has asserted ‘Idle’ on the

CTL pins, the phy will assert its own ‘Idle’ state on the CTL lines.

When sending multiple packets in this fashion, it is required that all

data be transmitted at the same speed. This is required because the

transmission speed is set during arbitration and since the arbitration

step will be skipped, there will be no way of informing the network of

a change in speed.

The link will take control of the bus by asserting either ‘hold’ or

‘transmit’ on the CTL lines. ‘hold’ is used by the link to keep control

of the bus if it needs some time to prepare the data for transmission.

The phy will keep control of the bus for the link by asserting a

‘data-prefix’ state on the bus. It is not necessary for the link to use

‘hold’ if it is ready to transmit as soon as bus ownership is granted.

When the link is prepared to send data, it will assert ‘transmit’ on the

CTL lines as well as sending the first four bits of the packet on the

D[0:3] lines (assuming 200 Mb/s). The ‘transmit’ state is held on the

CTL pins until the last bits of data have been sent. The link will then

22.1 TRANSMIT TIMING WAVEFORMS

PHY

CTL [0:1]

00

0000

ZZ

11

0000

ZZ

00

0000

ZZ

ZZZZ

01

ZZ

ZZZZ

01

ZZ

ZZZZ

10

ZZ

ZZZZ

10

ZZ

ZZZZ

10

ZZ

ZZZZ

10

ZZ

ZZZZ

00

ZZ

ZZZZ

00

0000

ZZ

PHY

D [0:3]

LINK

CTL [0:1]

LINK

D [0:3]

ZZZZ

0000

P

n

0000

ZZZZ

0

1

2

PHY

CTL [0:1]

ZZ

ZZZZ

10

ZZ

ZZZZ

10

ZZ

ZZZZ

01

ZZ

ZZZZ

00

0000

ZZ

00

0000

ZZ

11

0000

ZZ

00

0000

ZZ

ZZZZ

01

ZZ

ZZZZ

01

ZZ

ZZZZ

10

ZZ

ZZZZ

10

PHY

D [0:3]

LINK

CTL [0:1]

LINK

CTL [0:1]

P

0000

ZZZZ

0000

P

1

n–1

n

0

NOTE:

ZZ = High Impedance State

= Packet Data

P

n

0

SV00235

NOTE:

ZZ = High Impedance State

P0 => Pn = Packet data

Figure 8. Transmit Timing Waveforms

16

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

23.0 RECEIVE

When data is received by the phy from the serial bus, it will transfer the data to the link for further processing. The phy will assert ‘Receive’ on

the CTL lines and ‘1’ on each D pin. The phy indicates the start of the packet by placing the speed code on the data bus. The phy will then

proceed with the transmittal of the packet to the link on the D lines while still keeping the ‘Receive’ status on the CTL pins. Once the packet has

been completely transferred, the phy will assert ‘Idle’ on the CTL pins which will complete the receive operation.

NOTE: The speed is a phy-link protocol and not included in the CRC.

23.1 RECEIVE TIMING WAVEFORMS

PHY

CTL [0:1]

00

10

00

PHY

D [0:3]

0000

1111

SPD

P

n

0000

0

1

NOTE:

SPD = Speed Code

P

P = Packet Data

n

0

SV00234

NOTE:

SPD = Speed Code

P

0

å Pn = packet data

Figure 9. Receive Timing Waveforms

The speed code for the receiver is as follows:

D [0:3]

DATA RATE

(Mbit/s)

00XX

100

200

0100

NOTE:

X transmitted as 0, ignored on receive.

24.0 POWER CLASS BITS IN SELF–ID PACKET

The settings of the PC[0:2] pins appear in the pwr field of the self–ID packet. Bit 21 is transmitted first, followed by bit 22 and then bit 23.

pwr[21:23]

000

DESCRIPTION

Node does not need power and does not repeat power.

001

Node is self powered, and provides a minimum of 15 W to the bus.

010

Node is self powered, and provides a minimum of 30 W to the bus.

011

Node is self powered, and provides a minimum of 45 W to the bus.

100

Node may be powered from the bus, and is using up to 1 W.

101

Node may be powered from the bus, and is using up to 1 W. An additional 2 W is needed to enable the LLC and higher layers.

Node may be powered from the bus, and is using up to 1 W. An additional 5 W is needed to enable the LLC and higher layers.

Node may be powered from the bus, and is using up to 1 W. An additional 9 W is needed to enable the LLC and higher layers.

110

111

17

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

18

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

NOTES

19

1999 Apr 09

Philips Semiconductors

Product specification

3-port physical layer interface

PDI1394P11

Data sheet status

[1]

Data sheet

status

Product

status

Definition

Objective

specification

Development

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

Preliminary

specification

Qualification

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make chages at any time without notice in order to

improve design and supply the best possible product.

Product

specification

Production

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 1999

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Date of release: 04-99

Document order number:

9397 750 05511

Philips

Semiconductors

20

1999 Apr 09


型号：	PDI1394P11
厂家：	NXP
描述：	3-port physical layer interface 3端口物理层接口
文件：	总20页 (文件大小：148K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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