PH4530L,115 [NXP]
PH4530L - N-channel TrenchMOS logic level FET SOIC 4-Pin;
| 型号： | PH4530L,115 |
| 厂家： | 
NXP |
| 描述： | PH4530L - N-channel TrenchMOS logic level FET SOIC 4-Pin 开关 晶体管 |
| 文件： | 总12页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PH4530L
N-channel TrenchMOS™ logic level FET
Rev. 02 — 26 January 2005
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode field effect transistor in a plastic package using
TrenchMOS™ technology.
1.2 Features
■ Low thermal resistance
■ Logic level gate drive
■ SO8 equivalent area footprint
■ Low on-state resistance.
1.3 Applications
■ DC-to-DC converters
■ Portable appliances
■ Switched-mode power supplies
■ Notebook computers.
1.4 Quick reference data
■ VDS ≤ 30 V
■ ID ≤ 80 A
■ Ptot ≤ 62.5 W
■ RDSon ≤ 5.7 mΩ.
2. Pinning information
Table 1:
Pin
Discrete pinning
Description
source
Simplified outline
Symbol
1,2,3
4
D
S
mb
gate
mb
mounting base;
connected to drain
G
mbb076
1
2
3
4
Top view
SOT669 (LFPAK)
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
plastic single-ended surface mounted package (LFPAK); 4 leads
Version
PH4530L
LFPAK
SOT669
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
VGS
ID
drain-source voltage (DC)
25 °C ≤ Tj ≤ 150 °C
-
30
V
gate-source voltage (DC)
drain current (DC)
-
±20
80
V
Tmb = 25 °C; VGS = 10 V; Figure 2 and 3
Tmb = 100 °C; VGS = 10 V; Figure 2
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tmb = 25 °C; Figure 1
-
A
-
240
50.7
62.5
+150
+150
A
IDM
Ptot
Tstg
Tj
peak drain current
-
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
−55
−55
Source-drain diode
IS
source (diode forward) current (DC) Tmb = 25 °C
-
-
52
A
A
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
150
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 36.2 A;
tp = 0.24 ms; VDD ≤ 30 V; VGS = 10 V;
starting Tj = 25 °C
-
130
mJ
9397 750 14031
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 26 January 2005
2 of 12
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa15
03aa23
120
120
Ider
Pder
(%)
(%)
80
40
0
80
40
0
200
mb (°C)
50
100
0
150
200
0
50
100
150
T
(°C)
Tmb
Ptot
ID
Pder
=
× 100%
Ider
=
× 100%
-----------------------
-------------------
P
I
°
°
tot(25 C)
D(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
003aaa525
103
ID
(A)
Limit RDSon = VDS / ID
t = 10
s
µ
p
102
10
1
100
s
µ
DC
1 ms
10 ms
100 ms
10-1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 14031
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 26 January 2005
3 of 12
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Min
Typ
Max Unit
2 K/W
Rth(j-mb) thermal resistance from junction to mounting base Figure 4
-
-
5.1 Transient thermal impedance
003aaa526
10
Zth(j-mb)
(K/W)
0.5
δ =
1
0.2
0.1
0.05
0.02
tp
δ =
P
10-1
T
single pulse
t
tp
T
10-2
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 14031
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 26 January 2005
4 of 12
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
ID = 1 mA; VDS = VGS; Figure 9
VDS = 30 V; VGS = 0 V
Tj = 25 °C
30
1
-
-
V
V
VGS(th)
IDSS
gate-source threshold voltage
drain-source leakage current
1.5
2
-
-
-
0.06
1
µA
Tj = 150 °C
-
500 µA
IGSS
gate-source leakage current
VGS = ±15 V; VDS = 0 V
VGS = 10 V; ID = 15 A; Figure 7 and 8
Tj = 25 °C
2
100 nA
RDSon
drain-source on-state resistance
-
-
-
4.8
8.2
5.8
5.7
9.7
7.2
mΩ
mΩ
mΩ
Tj = 150 °C
VGS = 5 V; ID = 15 A; Figure 7 and 8
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 25 A; VDS = 10 V; VGS = 5 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
23.5
5.8
6.5
1972
769
304
22
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
VGS = 0 V; VDS = 10 V; f = 1 MHz;
Figure 11
VDS = 10 V; ID = 25 A;
VGS = 5 V; RG = 4.7 Ω
40
td(off)
tf
turn-off delay time
fall time
48
18
Source-drain diode
VSD
trr
source-drain (diode forward) voltage IS = 15 A; VGS = 0 V; Figure 12
-
-
0.85 1.2
38
V
reverse recovery time
IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V
-
ns
9397 750 14031
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 26 January 2005
5 of 12
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
003aaa527
003aaa528
40
ID
40
30
20
10
0
3
VGS (V) = 2.9
10
ID
(A)
(A)
5
30
2.8
2.7
2.6
25
C
°
20
10
0
T = 150
C
°
j
2.5
2.4
2.2
0
1
2
3
4
0
0.5
1
1.5
2
V
DS (V)
V
GS (V)
Tj = 25 °C
Tj = 25 °C and 150 °C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
003aaa529
03al00
20
1.8
RDSon
(m
)
Ω
a
2.6
2.7
2.8
2.9
3
15
1.2
10
5
VGS (V) = 3.5
5
10
0.6
0
-60
0
0
10
20
30
40
0
60
120
180
Tj (°C)
ID (A)
Tj = 25 °C
RDSon
a =
----------------------------
RDSon(25 C)
°
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 14031
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 26 January 2005
6 of 12
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa33
03aa36
2.5
VGS(th)
(V)
10-1
ID
(A)
2
10-2
10-3
10-4
10-5
10-6
max
1.5
typ
min
typ
max
min
1
0.5
0
-60
0
60
120
180
0
1
2
3
T ( C)
VGS (V)
°
j
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
003aaa530
104
C
(pF)
Ciss
103
Coss
Crss
102
10-1
1
10
102
VDS (V)
VGS = 0 V; f = 1 MHz
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.
9397 750 14031
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 26 January 2005
7 of 12
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
003aaa531
003aaa532
40
10
VGS
(V)
IS
(A)
8
6
4
2
0
30
20
150
C
°
T = 25
C
°
j
10
0
0.2
0.4
0.6
0.8
1
0
10
20
30
40
QG (nC)
50
V
SD (V)
Tj = 25 °C and 150 °C; VGS = 0 V
ID = 25 A; VDD = 10 V
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 13. Gate-source voltage as a function of gate
charge; typical values.
9397 750 14031
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 26 January 2005
8 of 12
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
7. Package outline
Plastic single-ended surface mounted package (LFPAK); 4 leads
SOT669
A
2
E
A
C
c
E
1
b
2
2
b
3
L
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-09-15
04-10-13
SOT669
MO-235
Fig 14. SOT669 (LFPAK) package outline.
9397 750 14031
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 26 January 2005
9 of 12
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
8. Revision history
Table 6:
Revision history
Document ID
Release Data sheet Change
Doc. number
Supersedes
date
20050126 Product
data sheet
status
notice
PH4530L_2
-
9397 750 14031 PH4530L_1
Modifications:
• Section 1.4 “Quick reference data” ID and RDSon values updated
• Table 3 “Limiting values” ID and IDM values updated
• Figure 3, Figure 6, Figure 11 and Figure 13 updated
• Table 5 “Characteristics” RDSon, Qg(tot), Qgs, Qgd, Ciss, Coss and Crss values updated.
PH4530L_1
20040304 Preliminary
data sheet
-
9397 750 12813
-
9397 750 14031
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 26 January 2005
10 of 12
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
9. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
10. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
13. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14031
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 26 January 2005
11 of 12
PH4530L
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
14. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information . . . . . . . . . . . . . . . . . . . . 11
3
4
5
5.1
6
7
8
9
10
11
12
13
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 26 January 2005
Document number: 9397 750 14031
Published in The Netherlands
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