PHK28NQ03LT,118_技术文档

PHK28NQ03LT

N-channel TrenchMOS logic level FET

Rev. 03 — 8 December 2009

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

computing, communications, consumer and industrial applications only.

1.2 Features and benefits

Simple gate drive required due to low

Suitable for logic level gate drive

gate charge

sources

1.3 Applications

DC-to-DC convertors

Switched-mode power supplies

1.4 Quick reference data

Table 1.

Quick reference

Symbol Parameter

Conditions

drain-source voltage T_j≥ 25 °C; T_j≤ 150 °C

Min

Typ

Max Unit

V_DS

I_D

-

30

V

A

drain current

T_sp= 25 °C; V_GS= 10 V;

see Figure 1 and 3

23.7

P_tot

total power

dissipation

T_sp= 25 °C;

see Figure 2

-

6.25

-

W

Dynamic characteristics

Q_GDgate-drain charge

V_GS= 4.5 V; I_D= 14 A;

V_DS= 15 V; T_j= 25 °C;

see Figure 11

11.4

nC

Static characteristics

R_DSon

drain-source

V_GS= 10 V; I_D= 14 A;

-

5.5

6.5

mΩ

on-state resistance

T_j= 25 °C; see Figure 9 and 10

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

2. Pinning information

Table 2.

Pinning information

1

Symbol Description

Simplified outline

Graphic symbol

S

G

D

source

gate

8

5

4

D

2

3

G

4

mbb076

S

5

drain

1

6

drain

SOT96-1 (SO8)

7

drain

8

drain

3. Ordering information

Table 3.

Ordering information

Type number

Package

Name

SO8

Description

plastic small outline package; 8 leads; body width 3.9 mm

Version

PHK28NQ03LT

SOT96-1

4. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

Min

Max

30

Unit

drain-source voltage

drain-gate voltage

gate-source voltage

limiting drain current

drain current

T_j≥ 25 °C; T_j≤ 150 °C

T_j≤ 150 °C; T_j≥ 25 °C; R_GS= 20 kΩ

-

V

V_DGR

V_GS

-

30

V

-

20

V

I_D

T_sp= 100 °C; V_GS= 10 V; see Figure 1

T_sp= 25 °C; V_GS= 10 V; see Figure 1 and 3

T_sp= 25 °C; t_p≤ 10 µs; pulsed; see Figure 3

-

15

A

-

23.7

60

A

I_DM

P_tot

T_stg

T_j

peak drain current

-

A

total power dissipation T_sp= 25 °C; see Figure 2

storage temperature

-

6.25

150

W

°C

-55

junction temperature

Source-drain diode

I_S

source current

peak source current

T_sp= 25 °C

-

5.2

A

I_SM

T_sp= 25 °C; t_p≤ 10 µs; pulsed

20.8

PHK28NQ03LT_3

Product data sheet

Rev. 03 — 8 December 2009

2 of 12

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

03aa25

03aa17

120

I

P

der

(%)

80

40

0

50

100

150

200

0

50

100

150

200

T

sp

(°C)

T

sp

(°C)

Fig 1. Normalized continuous drain current as a

function of solder point temperature

Fig 2. Normalized total power dissipation as a

function of solder point temperature

03ak85

2

10

limit R

= V /I

DS D

DSon

t

p

= 10 μs

I

D

100 μs

(A)

10

1 ms

10 ms

DC

1

100 ms

−1

10

−1

2

1

10

V

DS

(V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

PHK28NQ03LT_3

Product data sheet

Rev. 03 — 8 December 2009

3 of 12

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5.

Symbol

R_th(j-sp)

Thermal characteristics

Parameter

Conditions

Min

Typ

Max

Unit

thermal resistance from junction to

solder point

see Figure 4

-

20

K/W

03ak84

2

10

Z

th(j-sp)

(K/W)

= 0.5

δ

10

0.2

0.1

t

p

P

0.05

δ =

1

T

0.02

t

single pulse

p

T

−1

10

−4

−3

−2

−1

10

1

10

t

p

(s)

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration

PHK28NQ03LT_3

Product data sheet

Rev. 03 — 8 December 2009

4 of 12

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

6. Characteristics

Table 6.

Symbol

Characteristics

Parameter

Conditions

Min

Typ

Max

Unit

Static characteristics

V_(BR)DSS

drain-source

breakdown voltage

I_D= 250 µA; V_GS= 0 V; T_j= 25 °C

I_D= 250 µA; V_GS= 0 V; T_j= -55 °C

30

27

0.6

-

V

V_GS(th)

gate-source threshold I_D= 1 mA; V_DS= V_GS; T_j= 150 °C;

voltage

see Figure 8

I_D= 1 mA; V_DS= V_GS; T_j= -55 °C;

see Figure 8

-

2.2

2

V

I_D= 1 mA; V_DS= V_GS; T_j= 25 °C;

see Figure 8

1

1.5

I_DSS

drain leakage current

gate leakage current

V_DS= 30 V; V_GS= 0 V; T_j= 150 °C

V_DS= 30 V; V_GS= 0 V; T_j= 25 °C

V_GS= 16 V; V_DS= 0 V; T_j= 25 °C

V_GS= -16 V; V_DS= 0 V; T_j= 25 °C

-

500

1

µA

nA

mΩ

0.05

10

I_GSS

100

13.1

10

R_DSon

drain-source on-state

resistance

V_GS= 4.5 V; I_D= 13 A; T_j= 150 °C;

see Figure 9 and 10

11.2

V_GS= 10 V; I_D= 14 A; T_j= 25 °C;

see Figure 9 and 10

-

5.5

6.6

6.5

7.7

mΩ

V_GS= 4.5 V; I_D= 13 A; T_j= 25 °C;

see Figure 9 and 10

Dynamic characteristics

Q_G(tot)

Q_GS

Q_GD

C_iss

total gate charge

gate-source charge

gate-drain charge

input capacitance

output capacitance

I_D= 14 A; V_DS= 15 V; V_GS= 4.5 V;

T_j= 25 °C; see Figure 11

-

30.3

7.8

-

nC

pF

11.4

2800

670

320

V_DS= 20 V; V_GS= 0 V; f = 1 MHz;

T_j= 25 °C; see Figure 12

C_oss

C_rss

reverse transfer

capacitance

t_d(on)

t_r

t_d(off)

t_f

turn-on delay time

rise time

V_DS= 15 V; R_L= 15 Ω; V_GS= 10 V;

R_G(ext)= 6 Ω; T_j= 25 °C

-

11

10

80

40

-

ns

turn-off delay time

fall time

Source-drain diode

V_SD

source-drain voltage

I_S= 2.3 A; V_GS= 0 V; T_j= 25 °C;

see Figure 13

-

0.72

1.2

V

PHK28NQ03LT_3

Product data sheet

Rev. 03 — 8 December 2009

5 of 12

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

03ak88

03ak86

30

10 V 4.5 V 3.5 V 3.2 V

3 V

V

> I x R

D DSon

DS

I

D

(A)

2.8 V

20

2.6 V

2.4 V

10

T = 150 °C

25 °C

j

V

= 2.2 V

GS

0

0.1

0.2

0.3

0.4

V

0.5

(V)

0

1

2

3

V

(V)

GS

DS

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

03aa36

03aa33

10^-1

2.5

I_D

(A)

V_GS(th)

(V)

10^-2

10^-3

2

max

1.5

typ

min

typ

max

10^-4

10^-5

10^-6

1

min

0.5

0

1

2

3

-60

0

60

120

180

V_GS(V)

T ( C)

°

j

Fig 7. Sub-threshold drain current as a function of

gate-source voltage

Fig 8. Gate-source threshold voltage as a function of

junction temperature

PHK28NQ03LT_3

Product data sheet

Rev. 03 — 8 December 2009

6 of 12

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

03al00

03ak87

1.8

1.2

0.6

0

30

V

= 2.6 V

GS

T = 25 °C

j

R

DSon

(mΩ)

a

2.8 V

20

3 V

3.2 V

3.5 V

4.5 V

10 V

10

0

10

20

30

−60

0

60

120

180

I

(A)

D

T (°C)

j

Fig 9. Drain-source on-state resistance as a function

of drain current; typical values

Fig 10. Normalized drain-source on-state resistance

factor as a function of junction temperature

03ak90

03ak91

4

10

I

= 14 A

V

D

GS

(V)

T = 25 °C

j

8

6

4

2

0

C

(pF)

V

= 15 V

DD

C

iss

3

10

C

oss

rss

2

10

−1

2

10

1

10

0

20

40

60

80

V

(V)

DS

Q

(nC)

G

Fig 11. Gate-source voltage as a function of gate

charge; typical values

Fig 12. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

PHK28NQ03LT_3

Product data sheet

Rev. 03 — 8 December 2009

7 of 12

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

03ak89

30

V

= 0 V

GS

I

S

(A)

20

10

T = 25 °C

150 °C

j

0

0.3

0.6

0.9

1.2

V

(V)

SD

Fig 13. Source current as a function of source-drain voltage; typical values

PHK28NQ03LT_3

Product data sheet

Rev. 03 — 8 December 2009

8 of 12

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

7. Package outline

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

D

E

A

X

v

c

y

H

M

A

E

Z

5

8

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

4

e

w

M

detail X

b

p

0

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT96-1

076E03

MS-012

Fig 14. Package outline SOT96-1 (SO8)

PHK28NQ03LT_3

Product data sheet

Rev. 03 — 8 December 2009

9 of 12

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

8. Revision history

Table 7.

Revision history

Document ID

PHK28NQ03LT_3

Modifications:

Release date

Data sheet status

Change notice

Supersedes

20091208

Product data sheet

-

PHK28NQ03LT-02

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

PHK28NQ03LT-02

(9397 750 11367)

20030410

Product data

-

PHK28NQ03LT-01

(9397 750 10743)

20021212

Product data

-

PHK28NQ03LT_3

Product data sheet

Rev. 03 — 8 December 2009

10 of 12

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term 'short data sheet' is explained in section "Definitions".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URLhttp://www.nxp.com.

Applications— Applications that are described herein for any of these

9.2 Definitions

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Draft— The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Quick reference data— The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Limiting values— Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet— A short data sheet is an extract from a full data sheet with

the same product type number(s) and title. A short data sheet is intended for

quick reference only and should not be relied upon to contain detailed and full

information. For detailed and full information see the relevant full data sheet,

which is available on request via the local NXP Semiconductors sales office.

In case of any inconsistency or conflict with the short data sheet, the full data

sheet shall prevail.

Terms and conditions of sale— NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

athttp://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such

terms and conditions, the latter will prevail.

9.3 Disclaimers

General— Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license— Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Right to make changes— NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control— This document as well as the item(s) described herein may

be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use— NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

TrenchMOS— is a trademark of NXP B.V.

10. Contact information

For more information, please visit:http://www.nxp.com

For sales office addresses, please send an email to:salesaddresses@nxp.com

PHK28NQ03LT_3

Product data sheet

Rev. 03 — 8 December 2009

11 of 12

PHK28NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

11. Contents

1

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1

1.2

1.3

1.4

General description . . . . . . . . . . . . . . . . . . . . . .1

Features and benefits. . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2

3

4

5

6

7

8

Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

Thermal characteristics . . . . . . . . . . . . . . . . . . .4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9

Legal information. . . . . . . . . . . . . . . . . . . . . . . .11

Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.1

9.2

9.3

9.4

10

Contact information. . . . . . . . . . . . . . . . . . . . . .11

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 December 2009

Document identifier: PHK28NQ03LT_3


型号：	PHK28NQ03LT,118
厂家：	NXP
描述：	N-channel TrenchMOS logic level FET SOIC 8-Pin
文件：	总12页 (文件大小：199K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PHK28NQ03LT,118 [NXP]

相关型号：

PHK28NQ03LT,518

PHK3

PHK31NQ03LT

PHK31NQ03LT,518

PHK4NQ10T

PHK4NQ10T,518

PHK4NQ10T/T3

PHK4NQ20T

PHK5NQ10T

PHK5NQ10T/T3

PHK5NQ15T

PHKD13N03LT