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PHP36N03LT,127 [NXP]

N-channel TrenchMOS logic level FET TO-220 3-Pin;
PHP36N03LT,127
型号： PHP36N03LT,127
厂家： NXP    NXP
描述：

N-channel TrenchMOS logic level FET TO-220 3-Pin

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PHD/PHP36N03LT  
N-channel TrenchMOS logic level FET  
Rev. 02 — 8 June 2006  
Product data sheet  
1. Product profile  
1.1 General description  
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic  
package using TrenchMOS technology.  
1.2 Features  
I Logic level compatible  
I Low gate charge  
1.3 Applications  
I DC-to-DC converters  
I Switched-mode power supplies  
1.4 Quick reference data  
I VDS ≤ 30 V  
I ID ≤ 43.4 A  
I RDSon ≤ 17 mΩ  
I Ptot ≤ 57.6 W  
2. Pinning information  
Table 1.  
Pinning  
Pin  
1
Description  
gate (G)  
Simplified outline  
Symbol  
mb  
[1]  
2
drain (D)  
3
source (S)  
mb  
D
mb  
mounting base;  
connected to drain  
G
mbb076  
2
S
1
3
1
2 3  
SOT428 (DPAK)  
SOT78 (3-lead TO-220AB)  
[1] It is not possible to make a connection to pin 2 of the SOT428 package.  
 
 
 
 
 
 
 
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
3. Ordering information  
Table 2.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
PHD36N03LT  
PHP36N03LT  
DPAK  
plastic single-ended surface-mounted package; 3 leads (one lead  
cropped)  
SOT428  
SC-46  
plastic single-ended package; heatsink mounted; 1 mounting hole;  
3-lead TO-220AB  
SOT78  
4. Limiting values  
Table 3.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
Max  
Unit  
VDS  
VDGR  
VGS  
ID  
drain-source voltage  
25 °C ≤ Tj ≤ 175 °C  
-
30  
V
drain-gate voltage (DC)  
gate-source voltage  
drain current  
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ  
-
30  
V
-
±20  
V
Tmb = 25 °C; VGS = 10 V; see Figure 2 and 3  
Tmb = 100 °C; VGS = 10 V; see Figure 2  
Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3  
Tmb = 25 °C; see Figure 1  
-
43.4  
30.7  
173.6  
57.6  
+175  
+175  
A
-
A
IDM  
Ptot  
Tstg  
Tj  
peak drain current  
-
A
total power dissipation  
storage temperature  
junction temperature  
-
W
°C  
°C  
−55  
−55  
Source-drain diode  
IS  
source current  
peak source current  
Tmb = 25 °C  
-
-
43.4  
A
A
ISM  
Tmb = 25 °C; pulsed; tp ≤ 10 µs  
173.6  
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
2 of 13  
 
 
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
03aa16  
03aa24  
120  
120  
Ider  
(%)  
Pder  
(%)  
80  
80  
40  
0
40  
0
0
50  
100  
150  
200  
mb (°C)  
0
50  
100  
150  
200  
Tmb ( C)  
°
T
Ptot  
ID  
Pder  
=
× 100 %  
Ider  
=
× 100 %  
-----------------------  
-------------------  
Ptot(25°C)  
ID(25°C)  
Fig 1. Normalized total power dissipation as a  
function of mounting base temperature  
Fig 2. Normalized continuous drain current as a  
function of mounting base temperature  
001aae811  
3
10  
I
D
(A)  
Limit R  
= V / I  
DS D  
DSon  
2
10  
t
= 10 µs  
p
100 µs  
10  
DC  
1 ms  
1
2
1
10  
10  
V
(V)  
DS  
Tmb = 25 °C; IDM is single pulse; VGS = 10 V  
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage  
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
3 of 13  
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
5. Thermal characteristics  
Table 4.  
Symbol Parameter  
Rth(j-mb) thermal resistance from junction to mounting base see Figure 4  
Thermal characteristics  
Conditions  
Min  
Typ  
Max Unit  
-
-
2.6  
K/W  
Rth(j-a)  
thermal resistance from junction to ambient  
SOT78  
vertical in free air  
-
-
-
60  
75  
50  
-
-
-
K/W  
K/W  
K/W  
[1]  
[1]  
SOT428  
minimum footprint  
SOT404 minimum footprint  
[1] Mounted on a printed-circuit board; vertical in still air.  
001aae810  
10  
Z
th(j−mb)  
(K/W)  
δ = 0.5  
1
0.2  
0.1  
0.05  
0.02  
t
p
P
−1  
δ =  
10  
T
single pulse  
t
t
p
T
−2  
10  
−5  
−4  
10  
−3  
10  
−2  
−1  
10  
10  
10  
1
t
(s)  
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration  
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
4 of 13  
 
 
 
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
6. Characteristics  
Table 5.  
Characteristics  
Tj = 25 °C unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max Unit  
Static characteristics  
V(BR)DSS drain-source breakdown  
voltage  
ID = 250 µA; VGS = 0 V  
Tj = 25 °C  
30  
27  
-
-
-
-
V
V
Tj = −55 °C  
VGS(th)  
gate-source threshold voltage  
ID = 250 µA; VDS = VGS; see Figure 9 and 10  
Tj = 25 °C  
1
1.5  
2
V
V
V
Tj = 175 °C  
0.5  
-
-
-
-
Tj = −55 °C  
2.2  
IDSS  
drain leakage current  
gate leakage current  
VDS = 24 V; VGS = 0 V  
Tj = 25 °C  
-
-
-
0.05  
-
1
µA  
µA  
nA  
Tj = 175 °C  
500  
100  
IGSS  
VGS = ±20 V; VDS = 0 V  
VGS = 4.5 V; ID = 12 A; see Figure 6 and 8  
Tj = 25 °C  
10  
RDSon  
drain-source on-state  
resistance  
-
-
-
-
18  
22  
mΩ  
Tj = 175 °C  
32.4 39.6 mΩ  
VGS = 10 V; ID = 25 A; see Figure 6 and 8  
VGS = 3.5 V; ID = 5.2 A; see Figure 6 and 8  
14  
22  
17  
40  
mΩ  
mΩ  
Dynamic characteristics  
QG(tot)  
QGS  
QGD  
Ciss  
Coss  
Crss  
td(on)  
tr  
total gate charge  
gate-source charge  
gate-drain charge  
input capacitance  
output capacitance  
reverse transfer capacitance  
turn-on delay time  
rise time  
ID = 36 A; VDS = 15 V; VGS = 10 V;  
see Figure 11 and 12  
-
-
-
-
-
-
-
-
-
-
18.5  
4.2  
2.9  
690  
160  
110  
6
-
-
-
-
-
-
-
-
-
-
nC  
nC  
nC  
pF  
pF  
pF  
ns  
ns  
ns  
ns  
VGS = 0 V; VDS = 25 V; f = 1 MHz;  
see Figure 14  
VDS = 15 V; RL = 0.6 Ω; VGS = 10 V;  
RG = 10 Ω  
10  
td(off)  
tf  
turn-off delay time  
fall time  
33  
19  
Source-drain diode  
VSD  
source-drain voltage  
IS = 25 A; VGS = 0 V; see Figure 13  
-
0.97 1.2  
V
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
5 of 13  
 
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
001aae812  
001aae813  
30  
40  
10  
4.5 3.8  
3.5  
3.4  
3.2  
3.0  
2.8  
R
DSon  
(mΩ)  
V
(V) = 3.4  
3.5  
GS  
I
D
(A)  
30  
3.8  
20  
4.5  
10  
20  
10  
0
10  
2.6  
V
(V) = 2.4  
GS  
0
0
0.2  
0.4  
0.6  
0.8  
V
1.0  
(V)  
0
10  
20  
30  
40  
I (A)  
D
DS  
Tj = 25 °C  
Tj = 25 °C  
Fig 5. Output characteristics: drain current as a  
function of drain-source voltage; typical values  
Fig 6. Drain-source on-state resistance as a function  
of drain current; typical values  
001aae814  
03af18  
40  
2
I
D
a
(A)  
30  
1.5  
20  
10  
0
1
0.5  
0
T = 25 °C  
175 °C  
j
-60  
0
60  
120  
180  
0
1
2
3
4
Tj (°C)  
V
(V)  
GS  
Tj = 25 °C and 175 °C; VDS > ID × RDSon  
RDSon  
a =  
-----------------------------  
RDSon(25°C)  
Fig 7. Transfer characteristics: drain current as a  
function of gate-source voltage; typical values  
Fig 8. Normalized drain-source on-state resistance  
factor as a function of junction temperature  
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
6 of 13  
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
03aa33  
03aa36  
2.5  
VGS(th)  
(V)  
10-1  
ID  
(A)  
2
10-2  
10-3  
10-4  
10-5  
10-6  
max  
1.5  
typ  
min  
typ  
max  
min  
1
0.5  
0
-60  
0
60  
120  
180  
0
1
2
3
T ( C)  
VGS (V)  
°
j
ID = 1 mA; VDS = VGS  
Tj = 25 °C; VDS = 5 V  
Fig 9. Gate-source threshold voltage as a function of  
junction temperature  
Fig 10. Sub-threshold drain current as a function of  
gate-source voltage  
001aae817  
10  
V
GS  
(V)  
8
6
4
2
0
V
DS  
I
D
V
GS(pl)  
V
GS(th)  
GS  
V
Q
Q
GS1  
GS2  
Q
Q
GD  
GS  
Q
G(tot)  
0
5
10  
15  
20  
Q
(nC)  
G
003aaa508  
ID = 36 A; VDS = 15 V  
Fig 11. Gate-source voltage as a function of gate  
charge; typical values  
Fig 12. Gate charge waveform definitions  
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
7 of 13  
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
001aae815  
001aae816  
4
3
2
40  
10  
I
S
C
(pF)  
(A)  
30  
10  
C
iss  
20  
10  
0
C
oss  
10  
C
rss  
T = 25 °C  
175 °C  
j
10  
10  
−1  
2
0
0.3  
0.6  
0.9  
1.2  
1
10  
10  
V
(V)  
V
(V)  
DS  
SD  
Tj = 25 °C and 175 °C; VGS = 0 V  
VGS = 0 V; f = 1 MHz  
Fig 13. Source current as a function of source-drain  
voltage; typical values  
Fig 14. Input, output and reverse transfer capacitances  
as a function of drain-source voltage; typical  
values  
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
8 of 13  
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
7. Package outline  
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)  
SOT428  
y
E
A
A
A
b
2
E
1
1
mounting  
base  
D
2
D
1
H
D
2
L
L
2
L
1
1
3
b
1
b
M
c
w
A
e
e
1
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
y
max  
D
min  
E
min  
L
1
min  
2
1
UNIT  
A
A
1
b
b
b
c
D
E
e
e
1
H
D
L
L
2
w
1
2
1
2.38  
2.22  
0.93  
0.46  
0.89  
0.71  
1.1  
0.9  
5.46  
5.00  
0.56  
0.20  
6.22  
5.98  
6.73  
6.47  
10.4  
9.6  
2.95  
2.55  
0.9  
0.5  
4.0  
4.45  
0.5  
mm  
2.285 4.57  
0.2  
0.2  
REFERENCES  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
JEDEC  
JEITA  
06-02-14  
06-03-16  
SOT428  
SC-63  
TO-252  
Fig 15. Package outline SOT428 (DPAK)  
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
9 of 13  
 
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB  
SOT78  
E
p
A
A
1
q
mounting  
base  
D
1
D
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
b
L
max.  
2
e
A
b
D
E
L
D
L
1
A
c
UNIT  
p
q
Q
1
1
1
4.7  
4.1  
1.40  
1.25  
0.9  
0.6  
1.45  
1.00  
0.7  
0.4  
16.0  
15.2  
6.6  
5.9  
10.3  
9.7  
15.0  
12.8  
3.30  
2.79  
3.8  
3.5  
3.0  
2.7  
2.6  
2.2  
mm  
3.0  
2.54  
REFERENCES  
JEDEC JEITA  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
05-03-22  
05-10-25  
SOT78  
3-lead TO-220AB  
SC-46  
Fig 16. Package outline SOT78 (3-lead TO-220AB)  
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
10 of 13  
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
8. Revision history  
Table 6.  
Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
PHD_PHP36N03LT_2  
Modifications:  
20060608  
Product data sheet  
-
PHD36N03LT-01  
• The format of this data sheet has been redesigned to comply with the new presentation  
and information standard of Philips Semiconductors.  
• Addition of PHP36N03LT  
PHD36N03LT-01  
(9397 750 11613)  
20030630  
Product data  
-
-
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
11 of 13  
 
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
9. Legal information  
9.1  
Data sheet status  
Document status[1][2]  
Product status[3]  
Definition  
Objective [short] data sheet  
Development  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.semiconductors.philips.com.  
to result in personal injury, death or severe property or environmental  
damage. Philips Semiconductors accepts no liability for inclusion and/or use  
of Philips Semiconductors products in such equipment or applications and  
9.2  
Definitions  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. Philips Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
therefore such inclusion and/or use is for the customer’s own risk.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. Philips Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local Philips Semiconductors  
sales office. In case of any inconsistency or conflict with the short data sheet,  
the full data sheet shall prevail.  
Terms and conditions of sale — Philips Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.semiconductors.philips.com/profile/terms, including those  
pertaining to warranty, intellectual property rights infringement and limitation  
of liability, unless explicitly otherwise agreed to in writing by Philips  
9.3  
Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, Philips Semiconductors does not give any representations  
or warranties, expressed or implied, as to the accuracy or completeness of  
such information and shall have no liability for the consequences of use of  
such information.  
Semiconductors. In case of any inconsistency or conflict between information  
in this document and such terms and conditions, the latter will prevail.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — Philips Semiconductors reserves the right to  
make changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
9.4  
Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use — Philips Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of a Philips Semiconductors product can reasonably be expected  
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.  
10. Contact information  
For additional information, please visit: http://www.semiconductors.philips.com  
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com  
PHD_PHP36N03LT_2  
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.  
Product data sheet  
Rev. 02 — 8 June 2006  
12 of 13  
 
 
 
 
 
 
PHD/PHP36N03LT  
Philips Semiconductors  
N-channel TrenchMOS logic level FET  
11. Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1  
1.1  
1.2  
1.3  
1.4  
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11  
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
9.1  
9.2  
9.3  
9.4  
10  
11  
Contact information. . . . . . . . . . . . . . . . . . . . . 12  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© Koninklijke Philips Electronics N.V. 2006.  
All rights reserved.  
For more information, please visit: http://www.semiconductors.philips.com.  
For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com.  
Date of release: 8 June 2006  
Document identifier: PHD_PHP36N03LT_2  
 

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