PHX3055L [NXP]
PowerMOS transistor Logic level FET; 功率MOS晶体管逻辑电平场效应管
| 型号： | PHX3055L |
| 厂家： | 
NXP |
| 描述： | PowerMOS transistor Logic level FET |
| 文件： | 总7页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
PHX3055L
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic full-pack envelope. The
device features high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermalcycling performance withlow
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
60
9.4
28
V
A
W
Ω
Ptot
RDS(ON)
0.18
general
purpose
switching
applications.
PINNING - SOT186A
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
case
gate
2
drain
g
3
source
case isolated
1
2 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
ID
Continuous drain current
Ths = 25 ˚C; VGS = 10 V
Ths = 100 ˚C; VGS = 10 V
Ths = 25 ˚C
-
-
-
-
-
-
-
9.4
5.9
A
A
IDM
PD
Pulsed drain current
Total dissipation
26
A
Ths = 25 ˚C
28
W
W/K
V
∆PD/∆Ths Linear derating factor
Ths > 25 ˚C
0.22
± 15
± 20
VGS
VGSM
Gate-source voltage
Non-repetitive gate source
voltage
Single pulse avalanche
energy
Peak avalanche current
tp≤50µs
V
EAS
V
DD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;
VGS = 10 V
DD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;
VGS = 10 V
-
-
25
6
mJ
A
IAS
V
Tj, Tstg
Operating junction and
storage temperature range
- 55
150
˚C
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Visol
Cisol
R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal
-
2500
V
three terminals to external
heatsink
waveform;
R.H. ≤ 65% ; clean and dustfree
Capacitance from T2 to external f = 1 MHz
heatsink
-
10
-
pF
October 1997
1
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
PHX3055L
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-hs
Thermal resistance junction to
-
-
4.5
K/W
heat sink.
Rth j-a
Thermal resistance junction to
ambient
-
55
-
K/W
ELECTRICAL CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V; ID = 0.25 mA
60
-
-
V
∆V(BR)DSS
∆Tj
/
Drain-source breakdown
voltage temperature coefficient
Drain-source on resistance
Gate threshold voltage
Forward transconductance
Drain-source leakage current
VDS = VGS; ID = 0.25 mA
-
0.06
-
V/K
RDS(ON)
VGS(TO)
gfs
VGS = 10 V; ID = 6 A
VDS = VGS; ID = 0.25 mA
VDS = 50 V; ID = 6 A
VDS = 60 V; VGS = 0 V
VDS = 48 V; VGS = 0 V; Tj = 150 ˚C
VGS = ±30 V; VDS = 0 V
-
1.0
3.5
-
-
-
0.13
1.5
5.5
0.1
1
0.18
2.0
-
25
250
100
Ω
V
S
µA
µA
nA
IDSS
IGSS
Gate-source leakage current
10
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 10 A; VDD = 48 V; VGS = 10 V
-
-
-
7.5
1.9
5.5
10
3
7
nC
nC
nC
td(on)
tr
td(off)
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 10 A;
RG = 24 Ω; RD = 2.7 Ω
-
-
-
-
12
105
26
-
-
-
-
ns
ns
ns
ns
35
Ld
Internal drain inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
4.5
-
nH
Ls
Internal source inductance
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
290
103
40
-
-
-
pF
pF
pF
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
-
-
-
-
9.4
48
A
A
(body diode)
ISM
Pulsed source current (body
diode)
Diode forward voltage
VSD
trr
IS = 10 A; VGS = 0 V
-
-
-
1.5
-
V
Reverse recovery time
IS = 10 A; VGS = 0 V;
dI/dt = 100 A/µs
40
ns
Qrr
Reverse recovery charge
-
0.1
-
µC
October 1997
2
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
PHX3055L
Normalised Power Derating
with heatsink compound
Transient Thermal Impedance (K/W)
Zth(j-hs)
0.5
PD%
120
10
1
110
100
90
80
70
60
50
40
30
20
10
0
0.2
0.1
0.05
0.1
0.02
t
p
t
p
P
D =
D
T
0.01
0.001
0
t
T
1us
10us 100us 1ms 10ms 0.1s
tp, pulse width (s)
1s
10s
0
20
40
60
80
Ths /
100
120
140
C
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Ths)
Fig.4. Transient thermal impedance.
Zth j-hs = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID, Drain current (Amps)
10 V
15
10
5
120
110
100
90
80
70
60
50
40
30
20
10
0
Tj = 25 C
with heatsink compound
7 V
6.5 V
6 V
5.5 V
5 V
VGS = 4.5 V
0
0
20
40
60
80
Ths /
100
120
140
0
5
10
15
20
25
30
VDS, Drain-Source voltage (Volts)
C
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Ths); conditions: VGS ≥ 10 V
Fig.5. Typical output characteristics.
ID = f(VDS); parameter VGS
ID, Drain current (Amps)
100
RDS(on), Drain-Source on resistance (Ohms)
0.4
0.3
0.2
0.1
0
6 V
7 V
5.5 V
6.5 V
tp = 10 us
100 us
10
1 ms
10 V
DC
1
10 ms
100 ms
VGS = 15 V
Tj = 25 C
0.1
0
5
10
15
20
1
10
100
1000
VDS, Drain-source voltage (Volts)
ID, Drain current (Amps)
Fig.3. Safe operating area. Ths = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance.
RDS(ON) = f(ID); parameter VGS
October 1997
3
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
PHX3055L
VGS(TO) / V
Tj = 175 C
ID, Drain current (Amps)
15
max.
VDS = 30 V
4
3
2
1
0
Tj = 25 C
typ.
10
min.
5
0
-60 -40 -20
0
20
40
60
80 100 120 140
0
2
4
6
8
10
VGS, Gate-source voltage (Volts)
Tj /
C
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
SUB-THRESHOLD CONDUCTION
ID / A
gfs, Transconductance (S)
VDD = 30 V
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
4
3
2
1
0
Tj = 25 C
Tj = 175 C
2 %
typ
98 %
0
1
2
3
4
0
5
10
15
ID, Drain current (Amps)
VGS / V
Fig.8. Typical transconductance.
gfs = f(ID); parameter Tj
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
a
Ciss, Coss, Crss, Junction capacitances (pF)
Normalised RDS(ON) = f(Tj)
1000
100
10
1.5
Ciss
Coss
1.0
0.5
0
Crss
-60 -40 -20
0
20 40 60 80 100 120 140
Tj /
1
10
100
VDS, Drain-source voltage (Volts)
C
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 10 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
October 1997
4
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
PHX3055L
VGS, Gate-Source voltage (Volts)
15
48 V
IF, Source-drain diode current (Amps)
VGS = 0 V
20
15
10
5
ID = 10 A
Tj = 25 C
VDS = 30 V
Tj = 25 C
Tj = 175 C
10
5
0
0
0
5
10
15
0
0.5
1
1.5
Qg, Gate charge (nC)
VSDS, Source-drain voltage (Volts)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Fig.16. Source-Drain diode characteristic.
IF = f(VSDS); parameter Tj
EAS, Normalised unclamped inductive energy (%)
120
Switching times (ns)
1000
100
10
VDD = 30 V
VGS = 10 V
RD = 2.7 Ohms
ID = 10 A
Tj = 25 C
110
100
90
80
70
60
50
40
30
20
10
0
tr
td(off)
tf
td(on)
1
0
20
40
60
80
100
20
40
60
80
100
120
140
RG, Gate resistance (Ohms)
Starting Tj ( C)
Fig.14. Typical switching times.
td(on), tr, td(off), tf = f(RG)
Fig.17. Normalised unclamped inductive energy.
EAS% = f(Tj)
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj
1.15
1.1
VDD
V(BR)DSS @ 25 C
+
L
1.05
1
VDS
-
VGS
-ID/100
T.U.T.
0
0.95
0.9
R 01
RGS
shunt
0.85
-100
-50
0
50
100
150
Tj, Junction temperature (C)
Fig.18. Unclamped inductive test circuit.
Fig.15. Normalised drain-source breakdown voltage.
V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj)
EAS = 0.5 LID2 V(BR)DSS/(V(BR)DSS − VDD
)
October 1997
5
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
PHX3055L
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
10.3
max
4.6
max
3.2
3.0
2.9 max
2.8
Recesses (2x)
6.4
2.5
0.8 max. depth
15.8
max
seating
plane
15.8
max.
19
max.
3 max.
not tinned
3
2.5
13.5
min.
1
2
3
M
0.4
1.0 (2x)
0.6
2.5
0.9
0.7
2.54
0.5
5.08
1.3
Fig.19. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
October 1997
6
Rev 1.000
Philips Semiconductors
Preliminary specification
PowerMOS transistor
Logic level FET
PHX3055L
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
October 1997
7
Rev 1.000
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