PIMXRT1167DVP8A [NXP]
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products;型号: | PIMXRT1167DVP8A |
厂家: | NXP |
描述: | i.MX RT1170 Crossover Processors Data Sheet for Industrial Products |
文件: | 总130页 (文件大小:2076K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: IMXRT1170IEC
Rev. 1, 05/2021
NXP Semiconductors
Data Sheet: Technical Data
MIMXRT1176CVM8A
MIMXRT1175CVM8A
MIMXRT1172CVM8A
MIMXRT117HCVM8A
MIMXRT1173CVM8A
MIMXRT1171CVM8A
MIMXRT117FCVM8A
i.MX RT1170 Crossover
Processors Data Sheet
for Industrial Products
Package Information
Plastic Package
289-pin MAPBGA, 14 x 14 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 6
1 i.MX RT1170 introduction
The i.MX RT1170 is a new high-end processor of i.MX
RT family, which features NXP’s advanced
implementation of a high performance Arm
1. i.MX RT1170 introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
1.3. Package marking information . . . . . . . . . . . . . . . 10
2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1. Special signal considerations . . . . . . . . . . . . . . . 21
3.2. Recommended connections for unused analog
®
Cortex -M7 core operating at speeds up to 800 MHz
®
and a power efficient Cortex -M4 core up to 400 MHz.
The i.MX RT1170 processor has 2 MB on-chip RAM in
total, including a 768 KB RAM which can be flexibly
configured as TCM (512 KB RAM shared with M7 TCM
and 256 KB RAM shared with M4 TCM) or
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 25
4.2. System power and clocks . . . . . . . . . . . . . . . . . . 37
4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.5. External memory interface . . . . . . . . . . . . . . . . . . 59
4.6. Display and graphics . . . . . . . . . . . . . . . . . . . . . . 69
4.7. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.8. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.9. Communication interfaces . . . . . . . . . . . . . . . . . . 86
4.10. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.11. SNVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . 105
5.1. Boot mode configuration pins . . . . . . . . . . . . . . 105
5.2. Boot device interface allocation . . . . . . . . . . . . . 105
6. Package information and contact assignments . . . . . . 111
6.1. 14 x 14 mm package information . . . . . . . . . . . . 111
7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
general-purpose on-chip RAM. The i.MX RT1170
integrates advanced power management module with
DCDC and LDO regulators that reduce complexity of
external power supply and simplifies power sequencing.
The i.MX RT1170 also provides various memory
interfaces, including SDRAM, RAW NAND FLASH,
NOR FLASH, SD/eMMC, Quad/Octal SPI, Hyper
RAM/Flash, and a wide range of other interfaces for
connecting peripherals, such as WLAN, Bluetooth™,
GPS, displays, and camera sensors. The i.MX RT1170
also has rich audio and video features, including MIPI
CSI/DSI, LCD display, graphic accelerator, camera
interface, SPDIF, and I2S audio interface.
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
© 2021 NXP B.V.
i.MX RT1170 introduction
The i.MX RT1170 is specifically useful for applications such as:
•
•
•
•
•
•
Industrial Human Machine Interfaces (HMI)
Motor Control
Home Appliance
High-end Audio Appliance
Low-end Instrument Cluster
Point-of-Sale (PoS)
1.1
Features
®
The i.MX RT1170 processors are based on Arm Cortex -M7 Core™ Platform, which has the following
features:
•
The Arm Cortex-M7 Core Platform:
— 32 KB L1 Instruction Cache and 32 KB L1 Data Cache
— Floating Point Unit (FPU) with single-precision and double-precision support of Armv7-M
Architecture FPv5
®
— Support the Arm v7-M Thumb instruction set, defined in the Armv7-M architecture
— Integrated Memory Protection Unit (MPU), up to 16 individual protection regions
— Up to 512 KB I-TCM and D-TCM in total
— Frequency of 800 MHz with Forward Body Biasing (FBB)
— ECC support for both cache and TCM
— Frequency of the core, as per Table 11, "Operating ranges," on page 28.
®
•
The Arm Cortex -M4 Core platform:
— Cortex-M4 processor with single-precision FPU defined by Armv7-M architecture FPv4-SP
— Integrated MPU with 8 individual protection regions
— 16 KB Instruction Cache, 16 KB Data Cache, and 256 KB TCM
— Frequency of 400 MHz without body biasing
— ECC support for TCM and parity check support for cache
The SoC-level memory system consists of the following additional components:
— Boot ROM (256 KB)
— On-chip RAM (2 MB in total)
– Configurable 512 KB RAM shared with M7 TCM
– 256 KB RAM shared with M4 TCM
– Dedicated 1.25 MB OCRAM
— Secure always-on RAM (4 KB)
•
External memory interfaces:
— 8/16/32-bit SDRAM, up to SDRAM-133/SDRAM-166/SDRAM-200
— 8/16-bit SLC NAND FLASH
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
2
NXP Semiconductors
i.MX RT1170 introduction
— SD/eMMC
— SPI NOR/NAND FLASH
— Parallel NOR FLASH with XIP support
— Single/Dual channel Quad SPI FLASH with XIP support
— Hyper RAM/FLASH
— OCT FLASH
— Synchronization mode for all devices
Timers and PWMs:
•
— Six General Programmable Timer (GPT) modules
– 4-channel generic 32-bit resolution timer for each
– Each supports standard capture and compare operation
— Two Periodical Interrupt Timer (PIT) modules
– Four timers for each module
– Generic 32-bit resolution timer
– Periodical interrupt generation
— Four Quad Timer (QTimer) modules
– 4-channel generic 16-bit resolution timer for each
– Each supports standard capture and compare operation
– Quadrature decoder integrated
— Four FlexPWMs
– Up to 8 individual PWM channels for each
– 16-bit resolution PWM suitable for Motor Control applications
— Four Quadrature Decoders
— Four Watch Dog (WDOG) modules
Each i.MX RT1170 processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
•
Display Interface:
— Parallel RGB LCD interface (eLCDIF)
– Support 8/16/24-bit interface
– Support up to WXGA resolution @60fps
– Support Index color with 256 entry x 24-bit color LUT
— Parallel RGB LCD Interface Version 2 (LCDIFv2)
– Enhanced based on LCDIF version
– Support up to 8 layers of alpha blending
— MIPI Display Serial Interface (MIPI DSI)
– PHY integrated
– 2 data lanes interface with up to 1.5 GHz bit rate clock
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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3
i.MX RT1170 introduction
— Smart LCD Display with 8080 interface through SEMC
Audio:
•
— SPDIF input and output
— Four Synchronous Audio Interface (SAI) modules supporting I2S, AC97, TDM, and
codec/DSP interfaces
— Medium Quality Sound (MQS) interface via GPIO pads
— PDM microphone interface with 4 pairs of inputs
— Asynchronous Sample Rate Converter (ASRC)
Graphics engine:
•
— Generic 2D (PXP)
– BitBlit
– Flexible image composition options—alpha, chroma key
– Porter-duff blending
– Image rotation (90, 180, 270)
– Image resize
– Color space conversion
– Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400)
– Standard 2D-DMA operation
— Vector Graphics Processing
– Real-time hardware curve tessellation of lines, quadratic, and cubic Bezier curves
– 16x Line Anti-aliasing
– OpenVG 1.1 support
– Vector Drawing
•
•
Camera Interface:
— Parallel Camera Sensor Interface (CSI)
– Support 24-bit, 16-bit, and 8-bit input
– Barcode binarization and histogram statistics
— MIPI Camera Serial Interface (MIPI CSI)
– PHY integrated
– 2 data lanes interface with up to 1.5 GHz bit rate clock
Connectivity:
— Two USB 2.0 OTG controllers with integrated PHY interfaces
— Two Ultra Secure Digital Host Controller (uSDHC) interfaces
– eMMC 5.0 compliance with HS400 support up to 400 MB/sec
– SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec
– Support for SDXC (extended capacity)
— One 10M/100M Ethernet controller with support for IEEE1588
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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NXP Semiconductors
i.MX RT1170 introduction
— One Gigabit Ethernet controller with support for AVB
— One Gigabit Ethernet controller with Time Sensitive Networking (TSN) Capability
— Twelve universal asynchronous receiver/transmitter (UARTs) modules
— Six I2C modules
— Six SPI modules
— Three FlexCAN (with Flexible Data-rate supported) modules
— Two EMV SIM modules
•
•
Analog:
— Two Analog-Digital-Converters (ADC), which supports both differential and single-end inputs
— One Digital-Analog-Converter (DAC)
— Four Analog Comparators (ACMP)
GPIO and Pin Multiplexing:
— General-purpose input/output (GPIO) modules with interrupt capability
— Input/output multiplexing controller (IOMUXC) to provide centralized pad control
— Two FlexIO modules
— 8 x 8 keypad
The i.MX RT1170 processors integrate advanced power management unit and controllers:
•
•
•
Full PMIC integration, including on-chip DCDC and LDOs
Temperature sensor with programmable trim points
Hardware power management controller (GPC)
The i.MX RT1170 processors support the following system debug:
•
•
•
•
Arm CoreSight debug and trace architecture
Trace Port Interface Unit (TPIU) to support off-chip real-time trace
Cross Triggering Interface (CTI)
Support for 5-pin (JTAG) and SWD debug interfaces
Security functions are enabled and accelerated by the following hardware:
•
•
High Assurance Boot (HAB)
Cryptographic Acceleration and Assurance (CAAM) module:
— Public Key Cryptography Engine (PKHA)
— Symmetric Engines
— Cryptographic Hash Engine
— Random Number Generation (RNG4)
— Four Job Rings for use by processors
— Secure Hardware-Only Cryptographic Key Management
— Encrypted Boot
— Revision control check based on fuse values
— DEK includes IV
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
5
i.MX RT1170 introduction
— Side channel attack countermeasures
— 64 KB secure RAM
•
•
•
Inline Encryption Engine (IEE):
— External memory encryption/decryption
— I/O direct encrypted storage and retrieval (Stream Support)
— FlexSPI decryption only
On-the-Fly AES Decryption (OTFAD):
— AES-128 Counter Mode On-the-Fly Decryption
— Hardware support for unwrapping “key blobs”
— Functionally acts as a slave sub-module to the FlexSPI
Secure Non-Volatile Storage (SNVS):
— Secure real-time clock (SRTC)
— Zero Master Key (ZMK)
— Tamper protection
— DryICE
•
•
Secure always-on RAM (4 KB)
Secure key management and protection
— Physical Unclonable Function (PUF)
— UnDocumented Function (UDF)
— Built-in Manufacturing Protection Hardware
Secure and trusted access control
•
NOTE
The actual feature set depends on the part numbers as described in Table 1.
Functions such as display and camera interfaces, connectivity interfaces,
and security features are not offered on all derivatives.
1.2
Ordering information
Table 1 provides examples of orderable part numbers covered by this Data Sheet.
Table 1. Order information
MIMXRT1176 MIMXRT1175 MIMXRT1173 MIMXRT1172 MIMXRT1171 MIMXRT117H MIMXRT117F
CVM8A
CVM8A
CVM8A
CVM8A
CVM8A
CVM8A
CVM8A
Qualification
tier
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
M7 core
M4 core
SRAM
800 MHz
400 MHz
800 MHz
400 MHz
800 MHz
400 MHz
800 MHz
800 MHz
800 MHz
400 MHz
800 MHz
—
—
—
2 MB without 2 MB without 2 MB without 2 MB without 2 MB without 2 MB without 2 MB without
ECC or 1.75 ECC or 1.75 ECC or 1.75 ECC or 1.75 ECC or 1.75 ECC or 1.75 ECC or 1.75
MB with ECC MB with ECC MB with ECC MB with ECC MB with ECC MB with ECC MB with ECC
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
6
NXP Semiconductors
i.MX RT1170 introduction
Table 1. Order information (continued)
MIMXRT1176 MIMXRT1175 MIMXRT1173 MIMXRT1172 MIMXRT1171 MIMXRT117H MIMXRT117F
CVM8A
CVM8A
CVM8A
CVM8A
CVM8A
CVM8A
CVM8A
Parallel LCD
and CSI
Yes
—
Yes
Yes
—
Yes
Yes
MIPI DSI and
CSI
Yes
—
Yes
Yes
—
Yes
Yes
GPU2D
PXP
Yes
Yes
x3
—
—
x3
x2
x1
x4
x1
Yes
Yes
x3
Yes
Yes
x3
—
—
x3
x2
x1
x4
x1
Yes
Yes
x3
Yes
Yes
x3
CAN-FD
ADC
x2
x2
x2
x2
x2
12-bit DAC
ACMP
x1
x1
x1
x1
x1
x4
x4
x4
x4
x4
1 Gb ENET
with AVB
x1
x1
x1
x1
x1
1 Gb ENET
with TSN
x1
x1
—
—
—
—
x1
x1
—
10/100 Mb
ENET with
1588
x1
x1
x1
x1
x1
USB 2.0 OTG
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
eMMC 5.0 / SD
3.0
EMV SIM
SAI
x2
x4
x8
x2
x12
x6
x6
x6
x2
x4
x4
x1
Yes
—
x2
x4
x8
x2
x12
x6
x6
x6
x2
x4
x4
x1
Yes
—
x2
x4
x2
x4
x8
x2
x12
x6
x6
x6
x2
x4
x4
x1
Yes
—
x2
x4
x8
x2
x12
x6
x6
x6
x2
x4
x4
x1
Yes
—
x2
x4
x8
x2
x12
x6
x6
x6
x2
x4
x4
x1
Yes
—
x2
x4
x8
x2
x12
x6
x6
x6
x2
x4
x4
x1
Yes
—
DMIC
x8
FlexSPI
UART
x2
x12
x6
I2C
SPI
x6
GPT
x6
PIT
x2
QTimer
FlexPWM
Temp Monitor
Security
Tamper
x4
x4
x1
Yes
x10 pins
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
7
i.MX RT1170 introduction
Table 1. Order information (continued)
MIMXRT1176 MIMXRT1175 MIMXRT1173 MIMXRT1172 MIMXRT1171 MIMXRT117H MIMXRT117F
CVM8A
CVM8A
CVM8A
CVM8A
CVM8A
CVM8A
CVM8A
Package
289
289
289
289
289
289
289
MAPBGA, 14 MAPBGA, 14 MAPBGA, 14 MAPBGA, 14 MAPBGA, 14 MAPBGA, 14 MAPBGA, 14
mm x14 mm, mm x14 mm, mm x14 mm, mm x14 mm, mm x14 mm, mm x14 mm, mm x14 mm,
0.8 mm pitch 0.8 mm pitch 0.8 mm pitch 0.8 mm pitch 0.8 mm pitch 0.8 mm pitch 0.8 mm pitch
Junction
temperature Tj
(C)
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be
identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The
primary characteristic which describes which data sheet applies to a specific part is the temperature grade
(junction) field.
•
The i.MX RT1170 Crossover Processors for Industrial Products Data Sheet (IMXRT1170IEC)
covers parts listed with a “C (Industrial temp)”
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/IMXRT or
contact an NXP representative for details.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
8
NXP Semiconductors
i.MX RT1170 introduction
M
IMX X X
@
##
%
+
VV
$
A
Qualification Level
M
Prototype Samples
Mass Production
Special
P
M
S
Silicon Rev
A
A0
A
Main Core Frequency
2xx MHz
$
2
5
6
8
A
Part # series
XX
i.MX RT
RT
500 MHz
@
1
Family
600 MHz
First Generation RT family
Reserved
800 MHz
2-8
1 GHz
Sub-Family
RT116x
##
Package Type
VV
VM
VJ
16
17
18
289MAPBGA, 14 x 14 mm, 0.8 mm pitch
196MAPBGA, 12 x 12 mm, 0.8 mm pitch
144MAPBGA, 10 x 10 mm, 0.8 mm pitch
RT117x
Tie
%
1
RT118x
Single Core Standard Feature
Single Core Enhanced Feature
Dual Core Enhanced Security
Dual Core Standard Feature
Dual Core Enhanced Feature
Dual Core Premium Feature
Dual Core Full Feature
2
VP
3
5
Temperature (Tj)
+
6
Consumer: 0 to + 95 °C
D
C
X
A
7
Industrial: -40 to +105 °C
9
Extended Industrial: -40 to + 125 eC
Automotive: -40 to + 125 eC
Facial Recognition
F
H
S
Hybrid Solution with Vision & Voice
Local Voice Control (text input models)
Figure 1. Part number nomenclature—i.MX RT11XX family
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
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i.MX RT1170 introduction
1.3
Package marking information
Figure 2 describes the package marking format about the i.MX RT1170 Crossover Processors.
Figure 2. MAPBGA289 14 x 14 mm package marking format
The 14 x 14 mm of i.MX RT1170 MAPBGA289 package has the following top-side marking:
•
•
•
First line: aaaaaaaaaaaaaaa
Second line: mmmmm
Third line: xxxyywwx
Table 2 lists the identifier decoder.
Table 2. Identifier decoder
Description
Identifier
a
m
y
Part number code, refer to Section 1.2, Ordering information
Mask set
Year
w
x
Work week
NXP internal use
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
10
Architectural overview
2 Architectural overview
The following subsections provide an architectural overview of the i.MX RT1170 processor system.
2.1
Block diagram
1
Figure 3 shows the functional modules in the i.MX RT1170 processor system .
.
Figure 3. i.MX RT1170 system block diagram
1. Some modules shown in this block diagram are not offered on all derivatives. See Table 1 for details.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
11
Modules list
3 Modules list
The i.MX RT1170 processors contain a variety of digital and analog modules. Table 3 describes these
modules in alphabetical order.
Table 3. i.MX RT1170 modules list
Block Mnemonic
Block Name
Subsystem
Brief Description
ACMP1
ACMP2
ACMP3
ACMP4
Analog Comparator
Analog
The comparator (CMP) provides a circuit for comparing
two analog input voltages. The comparator circuit is
designed to operate across the full range of the supply
voltage (rail-to-rail operation).
ADC_ETC
ADC External Trigger
Control
Analog
Analog
ADC_ETC enables multiple users shares a ADC
module in a Time-Division-Multiplexing (TDM).
ADC1
ADC2
Analog to Digital
Converter
The ADC is a 12-bit general purpose analog to digital
converter.
AOI
And-Or-Inverter
Arm Platform
Cross Trigger
The AOI provides a universal boolean function
generator using a four-term sum of products expression
with each product term containing true or complement
values of the four selected inputs (A, B, C, D).
Arm
Arm
The Arm Core Platform includes one Cortex-M7 core. It
includes associated sub-blocks, such as Nested
Vectored Interrupt Controller (NVIC), Floating-Point Unit
(FPU), Memory Protection Unit (MPU), and CoreSight
debug modules.
The Cortex-M4 platform has following features:
• Cortex-M4 processor with FPU
• Local memory
– 16 KB instruction cache and 16 KB data cache
– 256 KB TCM
ASRC
CAAM
Asynchronous Sample
Rate Converter
Multimedia
Peripherals
The ASRC can process groups of audio channels with
an independent time-based simultaneously.
Cryptographic
Accelerator and
Assurance Module
Security
CAAM supports a set of standard hardware
accelerators, boot time acceleration of the hashing
function, crypto key protection, HDCP 2.x authentication
and protected video path support, manufacturing
protection and public key cryptographic acceleration,
and inter-operate with TrustZone, Resource Domain,
and system virtualization access controls.
CANFD1
CANFD2
CANFD3
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN with Flexible Data rate (CAN FD) module is a
communication controller implementing the CAN
protocol according to the ISO11898-1 and CAN 2.0B
protocol specification.
CCM
GPC
PGMC
PMU
SRC
Clock Control Module,
GeneralPowerController,
Power Manage Unit,
Power Gating and
Clocks, Resets, and These modules are responsible for clock and reset
Power Control
distribution in the system, and also for the system power
management.
Memory Controller,
System Reset Controller
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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12
Modules list
Table 3. i.MX RT1170 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
The CSI IP provides parallel CSI standard camera
interface port. The CSI parallel data ports are up to 24
bits. It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB,
and 8-bit/10-bit/16-bit/24-bit Bayer data input.
CSI
Parallel CSI
Multimedia
Peripherals
CWT
Code Watchdog Timer
Timer peripherals The CWT provides mechanisms for detecting
side-channel attacks and the execution of unexpected
instruction sequences.
DAC
DAP
Digital-Analog-Converter
Debug Access Port
Analog
The DAC is a 12-bit general purpose digital to analog
converter.
System Control
Peripherals
The DAP provides real-time access for the debugger
without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-M7
Core Platform.
DCDC
DCDC Converter
Analog
The DCDC module is used for generating power supply
for core logic. Main features are:
• Adjustable high efficiency regulator
• Two outputs: 1.0 V and 1.8 V
• Over current and over voltage detection
eDMA
eDMA_LPSR
enhanced Direct Memory
Access
System Control
Peripherals
There are two enhanced DMAs (eDMA).
• The eDMA is a 32-channel DMA engine, which is
capable of performing complex data transfers with
minimal intervention from a host processor.
• The DMA_MUX is capable of multiplexing up to 128
DMA request sources to the 32 DMA channels of
eDMA.
eLCDIF
LCD interface
Multimedia
Peripherals
The enhanced LCD controller provides flexible display
options and to drive a wide range of display devices
varying in size and capability. Major features are:
• Up to WXGA 60 Hz
• 8/16/18/24 bit LCD data bus support available
depending on I/O mux options.
• Programmable timing and parameters for LCD
interfaces to support a wide variety of displays.
• Index color with 256 entry x 24-bit color LUT
EMV SIM1
EMV SIM2
Europay, Master and Visa
Subscriber Identification
Module
Connectivity
Peripherals
EMV SIM is designed to facilitate communication to
Smart Cards compatible to the EMV version 4.3
standard (Book 1) and Smart Cards compatible with
ISO/IEC 7816-3 standard.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Modules list
Table 3. i.MX RT1170 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
ENET
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is
designed to support 10/100 Mbit/s Ethernet/IEEE 802.3
networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the reference manual for details.
ENET 1G
Ethernet Controller
Connectivity
Peripherals
One 1G Ethernet is also integrated, which has following
features:
• RGMII/RMII/MII operation
• Support IEEE1588
• Support AVB
ENET_QOS
Ethernet
Quality-of-Service
Connectivity
Peripherals
The ENET_QOS is compliant with the IEEE 802.3–2015
specification and can be used in applications, such as
AV bridges, AV nodes, switches, data center bridges
and nodes, and network interface cards. It enables a
host to transmit and receive data over Ethernet in
compliance with the IEEE802.1AS and IEEE802.1-Qav
for audio/video traffic.
EWM
External Watchdog
Monitor
Timer Peripherals The EWM modules is designed to monitor external
circuits, as well as the software flow. This provides a
back-up mechanism to the internal WDOG that can
reset the system. The EWM differs from the internal
WDOG in that it does not reset the system. The EWM, if
allowed to time-out, provides an independent trigger pin
that when asserted resets or places an external circuit
into a safe mode.
FlexIO1
FlexIO2
Flexible Input/output
Pulse Width Modulation
RAM
Connectivity and
The FlexIO is capable of supporting a wide range of
Communications protocols including, but not limited to: UART, I2C, SPI,
I2S, camera interface, display interface, PWM
waveform generation, etc. The module can remain
functional when the chip is in a low power mode
provided the clock it is using remain active.
FlexPWM1
FlexPWM2
FlexPWM3
FlexPWM4
Timer Peripherals The pulse-width modulator (PWM) contains four PWM
sub-modules, each of which is set up to control a single
half-bridge power stage. Fault channel support is
provided. The PWM module can generate various
switching patterns, including highly sophisticated
waveforms.
FlexRAM
Memories
The i.MX RT1170 has 512 KB of on-chip RAM which
could be flexible allocated to I-TCM, D-TCM, and
on-chip RAM (OCRAM) in a 32 KB granularity. The
FlexRAM is the manager of the 512 KB on-chip RAM
array. Major functions of this blocks are: interfacing to
I-TCM and D-TCM of CM7 and OCRAM controller;
dynamic RAM arrays allocation for I-TCM, D-TCM, and
OCRAM.
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Modules list
Table 3. i.MX RT1170 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
FlexSPI1
FlexSPI2
Flexible Serial Peripheral
Interface
Connectivity and
FlexSPI acts as an interface to one or two external serial
Communications memory devices, FlexSPI2 has 8 bi-directional data
lines.
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
General Purpose I/O
Modules
System Control
Peripherals
Used for general purpose input/output to external ICs.
Each GPIO module supports up to 32 bits of I/O.
Note: GPIO13 register access takes a long time (about
50s due to clocked by 32 KHz clock source). During the
period of registers access, the LPSR domain bus would
be on hold.
GPT1
GPT2
GPT3
GPT4
GPT5
GPT6
General Purpose Timer
Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
GPU2D
Graphics Processing
Multimedia
Peripherals
The vector graphics processing supports following
features:
• Real-time hardware curve tessellation of lines,
quadratic, and cubic Bezier curves
• 16x line anti-aliasing
• OpenVG 1.1 support
• Vector drawing
IOMUXC
IOMUX Control
Mux control
This module enables flexible I/O multiplexing. Each IO
pad has a default as well as several alternate functions.
The alternate functions are software configurable.
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Modules list
Table 3. i.MX RT1170 modules list (continued)
Block Mnemonic
Block Name
JTAG Controller
Subsystem
Brief Description
JTAGC
System Control
Peripherals
The JTAG interface complies with JTAG TAP standards
to internal logic. The i.MX RT1170 processors use JTAG
port for production, testing, and system debugging. In
addition, the JTAG provides BSR (Boundary Scan
Register) standard support, which complies with IEEE
1149.1 and IEEE 1149.6 standards.
The JTAG port must be accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX RT1170 JTAG
incorporates two security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
KPP
Keypad Port
Human Machine
Interfaces
The KPP is a 16-bit peripheral that can be used as a
keypad matrix interface or as general purpose
input/output (I/O). It supports 8 x 8 external key pad
matrix. Main features are:
• Multiple-key detection
• Long key-press detection
• Standby key-press detection
• Supports a 2-point and 3-point contact key matrix
LCDIFv2
Parallel RGB LCD
interface version 2
Multimedia
Peripherals
The LCDIFv2 is an enhanced version of LCDIF.
Main features are:
• Eight layers of alpha blending
• CRC check for configurable region on the final
display output after alpha blending
• Write-back channel to save the final output into
memory
LPI2C1
LPI2C2
LPI2C3
LPI2C4
LPI2C5
LPI2C6
Low Power
Inter-integrated Circuit
Connectivity and
The LPI2C is a low power Inter-Integrated Circuit (I2C)
Communications module that supports an efficient interface to an I2C bus
as a master.
The I2C provides a method of communication between
a number of external devices. More detailed information,
see Section 4.9.2, LPI2C module timing parameters.
LPSPI1
LPSPI2
LPSPI3
LPSPI4
LPSPI5
LPSPI6
Low Power Serial
Peripheral Interface
Connectivity and
The LPSPI is a low power Serial Peripheral Interface
Communications (SPI) module that support an efficient interface to an SPI
bus as a master and/or a slave.
• It can continue operating while the chip is in stop
modes, if an appropriate clock is available
• Designed for low CPU overhead, with DMA off
loading of FIFO register access
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Modules list
Table 3. i.MX RT1170 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
LPUART1
LPUART2
LPUART3
LPUART4
LPUART5
LPUART6
LPUART7
LPUART8
LPUART9
LPUART10
LPUART11
LPUART12
UART Interface
Connectivity
Peripherals
Each of the UART modules support the following serial
data transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 20 Mbps.
MECC64
Error Correcting Code
MIPI CSI Interface
Memories and
MECC64 module supports Single Error Correction and
Memory Controllers Double Error Detection (SECDED) ECC function to
provide reliability for 4 banks On-Chip RAM (OCRAM)
access. When ECC function is disabled, ECC OCRAM
can be also used to store data.
MIPI-CSI
Multimedia
Peripherals
Key features of MIPI CSI controller are listed as
following:
• Implements all three MIPI CSI-2 layers
• Supports CSI-2 Unidirectional Master operation
• Virtual Channel support
• Flexible pixel-based user interface
MIPI-DSI
MIPI DSI Interface
Multimedia
Peripherals
Key features of MIPI DSI controller are listed as
following:
• Implements all three DSI layers
• Supports Command and Video Modes
• Virtual Channel support
• Flexible packet based user interface
MQS
MU
Medium Quality Sound
Messaging Unit
Multimedia
Peripherals
MQS is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
System Control
The Messaging Unit module enables two processors
within the SoC to communicate and coordinate by
passing messages (e.g. data, status, and control)
through the MU interface.
The MU also provides the ability for one processor to
signal the other processor using interrupts.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Modules list
Table 3. i.MX RT1170 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
OCOTP_CTRL
OTP Controller
Security
The On-Chip OTP controller (OCOTP_CTRL) provides
an interface for reading, programming, and/or overriding
identification and control information stored in on-chip
fuse elements. The module supports electrically
programmable poly fuses (eFUSEs). The
OCOTP_CTRL also provides a set of volatile
software-accessible signals that can be used for
software control of hardware elements, not requiring
non volatility. The OCOTP_CTRL provides the primary
user-visible mechanism for interfacing with on-chip fuse
elements. Among the uses for the fuses are unique chip
identifiers, mask revision numbers, cryptographic keys,
JTAG secure mode, boot characteristics, and various
control signals requiring permanent non volatility.
OCRAM
On-Chip Memory
controller
Memories and
The On-Chip Memory controller (OCRAM) module is
Memory Controllers designed as an interface between the system’s AXI bus
and the internal (on-chip) SRAM memory module.
OSC
Oscillator
Clock Sources and Two crystal oscillators:
Control
• 48 MHz crystal oscillator: it is used as primary clock
source for all the PLLs to generate the clock for CPU,
BUS, and high-speed interfaces.
• 32 kHz crystal oscillator: it is the primary clock source
for RTC as well as low speed clock source for
CCM/SRC/GPC.
PDM
Pulse Density Modulation
Multimedia
Peripherals
The PDM supports up to 8-channels (4 lanes) digital
MIC inputs.
PIT1
PIT2
Periodical Interrupt Timer Timer Peripherals The PIT features 32-bit counter timer, programmable
count modules, clock division features, interrupt
generation, and a slave mode to synchronize count
enable for multiple PITs.
PXP
Pixel Processing Pipeline
Multimedia
Peripherals
A high-performance pixel processor capable of 1
pixel/clock performance for combined operations, such
as color-space conversion, alpha blending, and rotation.
The PXP is enhanced
with features specifically for gray scale applications. In
addition, the PXP supports traditional pixel/frame
processing paths for still-image and video processing
applications.
Quadrature DEC1
Quadrature DEC2
Quadrature DEC3
Quadrature DEC4
Quadrature Decoder
Timer Peripherals The enhanced quadrature decoder module provides
interfacing capability to position/speed sensors. There
are five input signals: PHASEA, PHASEB, INDEX,
TRIGGER, and HOME. This module is used to decode
shaft position, revolution count, and speed.
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Modules list
Table 3. i.MX RT1170 modules list (continued)
Block Name Subsystem Brief Description
Block Mnemonic
QuadTimer1
QuadTimer2
QuadTimer3
QuadTimer4
QuadTimer
Timer Peripherals The quad-timer provides four time channels with a
variety of controls affecting both individual and
multi-channel features.Specific features include
up/down count, cascading of counters, programmable
module, count once/repeated, counter preload,
compare registers with preload, shared use of input
signals, prescaler controls, independent
capture/compare, fault input control, programmable
input filters, and multi-channel synchronization.
RDC
Resource Domain
Controller
Security
The RDC provides robust support for the isolation of
processing domain to prevent one core from accessing
another’s peripherals, to control access rights to
common memory and provide hardware enforcement of
semaphore based locking of shared peripherals.
For single system use case, RDC can be disabled and
AIPS-TZ/DEXSC can be bypassed. For dual system
case, RDC can be configured and locked each core
starts their own image.
ROMCP
ROM Controller with
Patch
Memories and
The ROMCP acts as an interface between the Arm
Memory Controllers advanced high-performance bus and the ROM. The
on-chip ROM is only used by the Cortex-M7 core during
boot up. Size of the ROM is 256 KB.
RTC OSC
Real Time Clock
Oscillator
Clock Sources and The RTC OSC provides the clock source for the
Control
Real-Time Clock module. The RTC OSC module, in
conjunction with an external crystal, generates a 32.768
kHz reference clock for the RTC.
SAI1
SAI2
SAI3
SAI4
Synchronous Audio
Interface
Multimedia
Peripherals
The SAI module provides a synchronous audio interface
(SAI) that supports full duplex serial interfaces with
frame synchronization, such as I2S, AC97, TDM, and
codec/DSP interfaces.
SEMA4
Semaphores
System Control
The SEMA4 module implements hardware-enforced
semaphores as an IPS-mapped slave peripheral device
and provides 16 hardware-enforced gates in a
dual-processor configuration.
SEMC
Smart External Memory
Controller
Memory and
The SEMC is a multi-standard memory controller
Memory Controller optimized for both high-performance and low pin-count.
It can support multiple external memories in the same
application with shared address and data pins. The
interface supported includes SDRAM, NOR Flash,
SRAM, and NAND Flash, as well as 8080 display
interface.
SNVS
SPDIF
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, Master Key
Control, and Violation/Tamper Detection and reporting.
Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
A standard audio file transfer format, developed jointly
by the Sony and Phillips corporations. Has Transmitter
and Receiver functionality.
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Modules list
Table 3. i.MX RT1170 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
The SSARC saves the registers of functional modules in
SSARC
State Save and Restore
Controller
Memories and
Memory Controllers memory before power down, and restores registers from
memory after the module is powered up.
TEMP SENSE
Temperature Sensor
Analog
The temperature sensor implements a temperature
sensor/conversion function based on a
temperature-dependent voltage to time conversion.
USB1
USB2
Universal Serial Bus 2.0
Connectivity
Peripherals
USB 2.0 OTG modules (USB OTG1 and USB OTG2)
contains:
• Two high-speed OTG 2.0 modules with integrated HS
USB PHYs
• Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0
uSDHC1
uSDHC2
SD/MMC and SDXC
Enhanced Multi-Media
Card / Secure Digital Host
Controller
Connectivity
Peripherals
i.MX RT1170 specific SoC characteristics:
All four MMC/SD/SDIO controllers are identical and are
based on the uSDHC. They are:
• Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia Card
System Specification.
• Fully compliant with SD command/response sets and
Physical Layer as defined in the SD Memory Card
Specifications, v3.0 including high-capacity SDXC
cards up to 2 TB.
• Fully compliant with SDIO command/response sets
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC
chips up to 200 MHz in HS200 mode (200 MB/s max)
VIDMUX
Video mux
Mux control
Video mux are mux control for Parallel CSI (IO PADs),
MIPI CSI-2, MIPI DSI, Parallel LCDIF (IO PADs) and
CSI, LCDIF-V2, eLCDIF control. It also includes the
DCIC of MIPI DSI and Parallel DSI.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Modules list
Table 3. i.MX RT1170 modules list (continued)
Block Name Subsystem Brief Description
Block Mnemonic
WDOG1
WDOG2
WDOG3
WDOG4
Watch Dog
Timer Peripherals WDOG1 and WDOG2 Timer support two comparison
points during each counting period. Each of the
comparison points is configurable to evoke an interrupt
to the Arm core, and a second point evokes an external
event on the WDOG line.
WDOG3 and WDOG4 modules are high reliability
independent timers that are available for system to use.
They provide a safety feature to ensure software is
executing as planned and the CPU is not stuck in an
infinite loop or executing unintended code. If the WDOG
module is not serviced (refreshed) within a certain
period, it resets the MCU. Windowed refresh mode is
supported as well.
XBARA
XBARB
Cross BAR
Cross Trigger
Memories and
Each crossbar switch is an array of muxes with shared
inputs. Each mux output provides one output of the
crossbar. The number of inputs and the number of
muxes/outputs are user configurable and registers are
provided to select which of the shared inputs are routed
to each output.
XECC
XRDC
External ECC Controller
XECC can be used as a gasket module on AXI bus to
Memory Controllers support ECC function for external memory.
Extended Resource
Domain Controller
Security
The XRDC provides an integrated, scalable
architectural framework for access control, system
memory protection, and peripheral isolation. It allows
software to assign chip resources including processor
cores, non-core bus masters, memory regions, and
slave peripherals to processing domains to support
enforcement of robust operational environments.
3.1
Special signal considerations
Table 4 lists special signal considerations for the i.MX RT1170 processors. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 6, Package information and contact
assignments.” Signal descriptions are provided in the i.MX RT1170 Reference Manual
(IMXRT1170RM).
Table 4. Special signal considerations
Signal Name
Remarks
CLK1_P/ CLK1_N
This differential output is reserved for NXP internal use. For users, this output must be a no
connect.
DCDC_PSWITCH
PAD is in DCDC_IN domain and connected to ground to bypass DCDC.
To enable DCDC function, assert DCDC_PSWITCH with at least 1 ms delay after the DCDC_IN
rising edge.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Modules list
Table 4. Special signal considerations (continued)
Remarks
Signal Name
RTC_XTALI/RTC_XTALO To hit the exact oscillation frequency, the board capacitors must be reduced to account for the
board and chip parasitics. The integrated oscillation amplifier is self-biasing, but relatively weak.
Care must be taken to limit the parasitic leakage from RTC_XTALI and RTC_XTALO to either the
power or the ground (> 100 M). This de-biases the amplifier and reduces the start-up margin.
If you want to feed an external low-frequency clock into RTC_XTALI, the RTC_XTALO pin must
remain unconnected or driven by a complementary signal. The logic level of this forcing clock must
not exceed the VDD_SNVS_DIG level and the frequency shall be < 100 kHz under the typical
conditions.
It is recommended to tie RTC_XTALI to GND if external crystal is not used. When a high-accuracy
real-time clock is not required, the system may use the on-chip 32 kHz oscillator. The tolerance is
10%. The ring oscillator starts faster than the external crystal and is used until the external crystal
reaches a stable oscillation. The ring oscillator also starts automatically if no clock is detected at
RTC_XTALI.
XTALI/XTALO
The SDK software requires 24 MHz on XTALI/XTALO. The crystal can be eliminated if an external
24 MHz oscillator is available in the system. In this case, refer to section of Bypass Configuration
(24 MHz) from the reference manual. There are three configurations that can be utilized, but
configuration 2 is recommended.
The logic level of this forcing clock must not exceed the VDD_LPSR_ANA level.
If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter
requirements. See Section 4.2.6, On-chip oscillators and relevant interface specifications chapters
for details.
JTAG_nnnn
External resistors can be used with all JTAG signals except for JTAG_TDO, but they are not
required. See Table 5 for a summary of the JTAG interface.
JTAG_TDO is configured with an on-chip keeper circuit, such that the floating condition is actively
eliminated if an external pull resistor is not present. An external pull resistor on JTAG_TDO is
detrimental. See Table 5 for a summary of the JTAG interface.
When JTAG_MOD is low, the JTAG interface is configured for a common software debug, adding
all the system TAPs to the chain.
When JTAG_MOD is high, the JTAG interface is configured to a mode compliant with the IEEE
1149.1 standard.
NC
These signals are No Connect (NC) and should not be connected by the user.
POR_B
See the System Boot chapter in the reference manual for the correct boot configuration. Note that
an incorrect setting may result from an improper boot sequence.
POR_B signal has internal 100 k pull up to SNVS domain, should pull up to VDD_SNVS_ANA if
need to add external pull up resistor, otherwise it will cause additional leakage during SNVS mode.
It is recommended to add the external reset IC to the circuit to guarantee POR_B is properly
processed during power up/down, please refer to the EVK design for details.
Note:
• As the Low DCDC_IN detection threshold is 2.6 V, the reset IC’s reset threshold must be higher
than 2.6 V, then the whole chip is reset before the internal DCDC module reset to guarantee the
chip safety during power down.
• For power on reset, on any conditions ones need to make sure the voltage on DCDC_PSWITCH
pin is below 0.5 V before power up.
ONOFF
Abrief connection to GND in the OFF mode causes the internal power management state machine
to change the state to ON. In the ON mode, a brief connection to GND generates an interrupt
(intended to be a software-controllable power-down). Approximately five seconds (or more) to GND
causes a forced OFF. Both boot mode inputs can be disconnected.
TEST_MODE
This input is reserved for NXP manufacturing use. The user must tie this pin directly to GND.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Modules list
Table 4. Special signal considerations (continued)
Remarks
Signal Name
WAKEUP
A GPIO powered by SNVS domain power supply which can be configured as wakeup source in
SNVS mode.
Table 5. JTAG controller interface summary
JTAG
I/O Type
On-chip Termination
JTAG_TCK
JTAG_TMS
JTAG_TDI
Input
Input
20–50 kpull-down
20–50 kpull-up
20–50 kpull-up
High-impedance
Input
JTAG_TDO
JTAG_TRSTB
JTAG_MOD
3-state output
Input
20–50 kpull-up
20–50 kpull-down
Input
3.2
Recommended connections for unused analog interfaces
Table 6 shows the recommended connections for unused analog interfaces.
hi
Table 6. Recommended connections for unused analog interfaces
Recommendations
if Unused
Module
Pad Name
32 kHz RTC_XTALI, RTC_XTALO
OSC
Not connected
It is recommended that
RTC_XTALI ties to GND if
external crystal is not
connected.
ADC
ADC_VREFH
10 K resistor to ground
10 K resistor to ground
10 K resistor to ground
Not connected
VDDA_ADC_1P8
VDDA_ADC_3P3
CLK1_N, CLK1_P
DAC_OUT
CCM
DAC
MIPI
Not connected
VDD_MIPI_1P0
VDD_MIPI_1P8
10 K resistor to ground
10 K resistor to ground
Not connected
MIPI_DSI_CKN, MIPI_DSI_CKP, MIPI_DSI_DN0, MIPI_DSI_DP0,
MIPI_DSI_DN1, MIPI_DSI_DP1
MIPI_CSI_CKN, MIPI_CSI_CKP, MIPI_CSI_DN0, MIPI_CSI_DP0,
MIPI_CSI_DN1, MIPI_CSI_DP1
Not connected
DCDC
DCDC_IN, DCDC_IN_Q, DCDC_DIG, DCDC_ANA
DCDC_DIG_SENSE, DCDC_ANA_SENSE, DCDC_LP, DCDC_LN
DCDC_PSWITCH, DCDC_MODE
Not connected
Not connected
To ground
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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23
Modules list
Table 6. Recommended connections for unused analog interfaces (continued)
Recommendations
Module
Pad Name
if Unused
USB
USB1_DN, USB1_DP, USB1_VBUS, USB2_DN, USB2_DP, USB2_VBUS
Not connected
Powered with 1.8 V
Powered with 3.3 V
Not connected
VDD_USB_1P8
VDD_USB_3P3
SYS OSC XTALI, XTALO
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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24
Electrical characteristics
4 Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX RT1170
processors.
4.1
Chip-level conditions
This section provides the device-level electrical characteristics for the IC. See Table 7 for a quick reference
to the individual tables and sections.
Table 7. i.MX RT1170 chip-Level conditions
For these characteristics
Topic appears
Absolute maximum ratings
Thermal characteristics
Operating ranges
on page 25
on page 27
on page 27
on page 30
on page 31
on page 37
Maximum supply currents
Typical power mode supply currents
System power and clocks
4.1.1
Absolute maximum ratings
CAUTION
Stress beyond those listed under Table 8 may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
Table 8 shows the absolute maximum operating ratings.
Table 8. Absolute maximum ratings
Parameter Description
Core supplies input voltage
Symbol
Min
Max
Unit
VDD_SOC_IN
VDD_LPSR_IN
DCDC_IN
-0.3
-0.3
-0.3
-0.3
-0.3
1.2
V
V
V
V
V
Power for LPSR domain
Power for DCDC
3.96
3.96
1.98
3.96
Power for PLL, OSC, and LDOs
VDDA_1P8_IN
VDD_SNVS_IN
Supply input voltage to Secure Non-Volatile Storage
and Real Time Clock
USB VBUS supply
USB1_VBUS
USB2_VBUS
-0.3
5.6
V
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
25
Electrical characteristics
Table 8. Absolute maximum ratings (continued)
Power for USB OTG PHYs
VDD_USB_1P8
VDD_USB_3P3
VDDA_ADC_1P8
VDDA_ADC_3P3
VDD_MIPI_1P8
VDD_MIPI_1P0
NVCC_SD1
-0.3
1.98
3.96
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
o C
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.5
-40
Power for ADC, DAC, and ACMP
Power for MIPI CSI/DSI PHY
1.98
3.96
1.98
1.2
IO supply for GPIO in SDIO1 bank (3.3 V mode)
IO supply for GPIO in SDIO1 bank (1.8 V mode)
IO supply for GPIO in SDIO2 bank (3.3 V mode)
IO supply for GPIO in SDIO2 bank (1.8 V mode)
IO supply for GPIO in EMC bank1 (3.3 V mode)
IO supply for GPIO in EMC bank1 (1.8 V mode)
IO supply for GPIO in EMC bank2 (3.3 V mode)
IO supply for GPIO in EMC bank2 (1.8 V mode)
IO power for GPIO in GPIO AD bank (3.3 V mode)
IO power for GPIO in GPIO AD bank (1.8 V mode)
IO supply for GPIO in DISP1 bank (3.3 V mode)
IO supply for GPIO in DISP1 bank1 (1.8 V mode)
IO supply for GPIO in DISP2 bank (3.3 V mode)
IO supply for GPIO in DISP2 bank1 (1.8 V mode)
IO power for GPIO in LPSR bank (3.3 V mode)
IO power for GPIO in LPSR bank (1.8 V mode)
IO power for GPIO in SNVS bank (1.8 V mode)
Input/Output Voltage range
3.96
1.98
NVCC_SD2
NVCC_EMC1
NVCC_EMC2
NVCC_GPIO
NVCC_DISP1
NVCC_DISP2
NVCC_LPSR
3.96
1.98
3.96
1.98
3.96
1.98
3.96
1.98
3.96
1.98
3.96
1.98
3.96
1.98
NVCC_SNVS
Vin/Vout
1.98
NVCC + 0.31
150
Storage Temperature range
TSTORAGE
1
NVCC is the I/O supply voltage.
Table 9. Electrostatic discharge and latch-up characteristics
Symbol
Description
Min
Max
Unit
Notes
1
VHBM
VESD
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
All pins except the corner pins
-2000
+2000
V
2
-500
+500
V
3
ILAT
Immunity level
-100
+100
mA
• Class II @105 oC ambient temperature
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
26
Electrical characteristics
1
2
3
Determined according to JEDEC Standard JS001, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model
(HBM).
Determined according to JEDEC Standard JS002, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
Determined according o JEDEC Standard JESD78, IC Latch-up Test.
4.1.2
Thermal characteristics
Table 10 displays the 14 x 14 mm package thermal characteristics.
Table 10. 14 x 14 mm thermal characteristics
Rating
Board Type1
JESD51-9, 2s2p
Symbol
Value
Unit
3
Junction to Ambient Thermal Resistance2
RJA
31.6
1.4
oC/W
oC/W
4
Junction to Top of Package
JESD51-9, 2s2p
JT
Thermal Characterization Parameter2
Junction to Case Thermal Resistance5
JESD51-9, 1s
RJC
10
oC/W
6
1
Thermal test board meets JEDEC specification for this package (JESD51-9).
2
Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not
meant to predict the performance of a package in an application-specific environment.
3
4
5
RJA = (Tj - Ta)/P [unit: oC/W], where Tj = junction temperature, Ta = ambient temperature, P = device power.
Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature is taken at the package top
side centre surface temperature.
RJC = (Tj - Tc)/P [unit: oC/W], where Tj = junction temperature, Tc = case temperature, P = device power.
JT = (Tj - Tt)/P [unit: oC/W], where Tj = junction temperature, Tt = temperature at top of package, P = device power.
6
4.1.3
Operating ranges
Table 11 provides the operating ranges of the i.MX RT1170 processors. For details on the chip's power
structure, see the “Power Management Unit (PMU)” chapter of the i.MX RT1170 Reference Manual
(IMXRT1170RM).
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
27
Electrical characteristics
Table 11. Operating ranges
Operating
Parameter
Description
Symbol
VDD_SOC_IN
Min
Max1 Unit
Comment
Conditions
Run Mode
Overdrive M7 core at
800MHz
1.1
1.15
V
The FBB_DISABLE fuse bit must be
checked on each device to determine
if FBB must be enabled along with
overdrive to operate the M7 core at
frequencies above 600 MHz. If
FBB_DISABLE = 0, then FBB must
be enabled when the SOC domain is
in overdrive mode. If FBB_DISABLE
= 1, then FBB should not be enabled
when the SOC domain is in overdrive
mode.
M7 core at 600 MHz
M7 core at 240 MHz
1.0
0.9
1.1
1.0
0.9
0.8
0.8
3.0
1.71
1.15
1.15
1.15
1.15
1.15
1.15
1.15
3.6
V
V
V
V
V
V
V
V
V
—
—
—
—
—
—
—
—
—
VDD_LPSR_DIG M4 core at 400 MHz
M4 core at 240 MHz
M4 core at 120 MHz
STANDBY Mode
Power for DCDC
VDD_SOC_IN
VDD_LPSR_DIG
DCDC_IN
M7 core
M4 core
—
Power for PLL,
OSC, and LDOs
VDDA_1P8_IN
—
1.89
Power for LPSR
domain
VDD_LPSR_IN
VDD_SNVS_IN
—
—
3.0
2.4
3.6
3.6
V
V
—
—
Power for SNVS
and RTC
Power for USB
OTG PHYs
VDD_USB_1P8
VDD_USB_3P3
VDDA_ADC_1P8
VDDA_ADC_3P3
ADC_VREFH
—
—
—
—
—
—
—
1.65
3.0
1.95
3.6
V
V
V
V
V
V
V
—
—
—
—
—
—
—
Power for ADC,
DAC, and ACMP
1.65
3.0
1.95
3.6
1.0
1.89
1.95
1.1
Power for MIPI
CSI/DSI PHY
VDD_MIPI_1P8
VDD_MIPI_1P0
1.65
0.9
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
28
Electrical characteristics
Table 11. Operating ranges (continued)
GPIO supplies
NVCC_SD1
NVCC_SD2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.0
1.65
3.0
3.6
1.95
3.6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IO power for GPIO in SDIO1 bank
(3.3 V mode)
IO power for GPIO in SDIO1 bank
(1.8 V mode)
IO power for GPIO in SDIO2 bank
(3.3 V mode)
1.65
3.0
1.95
3.6
IO power for GPIO in SDIO2 bank
(1.8 V mode)
NVCC_EMC1
NVCC_EMC2
NVCC_GPIO
NVCC_DISP1
NVCC_DISP2
NVCC_LPSR
IO power for GPIO in EMC bank1 (3.3
V mode)
1.65
3.0
1.95
3.6
IO power for GPIO in EMC bank1 (1.8
V mode)
IO power for GPIO in EMC bank2 (3.3
V mode)
1.65
3.0
1.95
3.6
IO power for GPIO in EMC bank2 (1.8
V mode)
IO power for GPIO in GPIO AD bank
(3.3 V mode)
1.65
3.0
1.95
3.6
IO power for GPIO in GPIO AD bank
(1.8 V mode)
IO power for GPIO in DISP1 bank
(3.3 V mode)
1.65
3.0
1.95
3.6
IO power for GPIO in DISP1 bank
(1.8 V mode)
IO power for GPIO in DISP2 bank
(3.3 V mode)
1.65
3.0
1.95
3.6
IO power for GPIO in DISP2 bank
(1.8 V mode)
IO power for GPIO in LPSR bank (3.3
V mode)
1.65
1.65
1.95
1.95
IO power for GPIO in LPSR bank (1.8
V mode)
NVCC_SNVS
Tj
IO power for GPIO in SNVS bank (1.8
V mode)
Temperature Operating Ranges
Standard Industrial -40 105
Junction
temperature
oC See the application note, i.MX
RT1170 Product Lifetime Usage
Estimates for information on product
lifetime (power-on years) for this
processor.
1
Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set
point = (Vmin + the supply tolerance). This results in an optimized power/speed ratio.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
29
Electrical characteristics
4.1.4
Maximum supply currents
The data shown in Table 12 represent a use case designed specifically to show the maximum current
consumption possible. All cores are running at the defined maximum frequency and are limited to L1
cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited
practical use case, if at all, and be limited to an extremely low duty cycle unless the intention were to
specifically show the worst case power consumption.
Table 12. Maximum supply currents
Power Rail
Comments
Max Current
Unit
DCDC_IN
Max power for chip at 125 oC
500
100
mA
mA
VDDA_1P8_IN
1.8 V power supply for PLL, OSC, and
LDOs
VDD_SOC_IN
VDD_LPSR_IN
VDD_SNVS_IN
VDD_USB_1P8
VDD_USB_3P3
VDDA_ADC_1P8
Power supply for digital logic
850
75
1
mA
mA
mA
mA
mA
mA
3.3 V power supply for LPSR domain
Power supply for SNVS domain
1.8 V power supply for USB OTG PHYs
3.3 V power supply for USB OTG PHYs
50
60
10
1.8 V power supply for ADC, DAC, and
ACMP
VDDA_ADC_3P3
ADC_VREFH
3.3 V power supply for ADC, DAC, and
ACMP
2
mA
VDD_MIPI_1P8
VDD_MIPI_1P0
1.8 V power supply for MIPI CSI/DSI PHY
1.0 V power supply for MIPI CSI/DSI PHY
100
30
mA
mA
NVCC_SD1
NVCC_SD2
Imax = N x C x V x (0.5 x F)
Where:
NVCC_EMC1
NVCC_EMC2
NVCC_GPIO
NVCC_DISP1
NVCC_DISP2
NVCC_LPSR
NVCC_SNVS
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 x F)—Data change rate. Up to 0.5 of the clock rate (F)
In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
30
Electrical characteristics
4.1.5
Typical power mode supply currents
Table 13 and Table 14 show the current and power consumption (not including I/O) of i.MX RT1170
processors in selected power modes.
Table 13. Typical power modes current and power consumption (Dual core)
Power supplies at 3.3 V (Typical)1
Modes
Test conditions
Units
25 oC Tj 105 oC Tj
Set Point #1 • CM7 runs at 800 MHz, Overdrive voltage to 1.1 V
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
144.3
36.1
348
40.5
mA
A
Active
with FBB mode; CM4 runs at 400 MHz, overdrive
voltage to 1.1 V
• CM7 domain bus frequency at 240 MHz; CM4
domain bus frequency at 160 MHz
• Enables ECC for cache, TCM, and OCRAM
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
4
11.8
A
476.322
1148.573
mW
• 16 MHz, 400 MHz, external 24 MHz crystal, and
external 32 kHz crystal are enabled
• All PLLs are enabled
• All peripherals are enabled and run at their
maximum clock root frequency under overdrive
mode
Set Point #0 • CM7 runs at 600 MHz, drive voltage to 1.0 V; CM4
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
84.8
36.1
131.9
40.3
mA
A
Active
runs at 240 MHz, drive voltage to 1.0 V
• CM7 domain bus frequency at 200 MHz; CM4
domain bus frequency at 120 MHz
• Enables ECC for cache, TCM, and OCRAM
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
3.9
11.5
A
279.972
435.441
mW
• 16 MHz, 400 MHz, external 24 MHz crystal, and
external 32 kHz crystal are enabled
• All PLLs are enabled
• All peripherals are enabled and run at their
maximum clock root frequency under normal drive
mode
Set Point #5 • CM7 runs at 240 MHz, lower voltage to 0.9 V;
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
43.4
36
70.9
40.7
mA
A
Active
CM4 runs at 120 MHz, lower voltage to 0.9 V
• CM7 domain bus frequency at 100 MHz; CM4
domain bus frequency at 60 MHz
• Enables ECC for cache, TCM, and OCRAM
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
3.9
10.8
A
143.352
234.140
mW
• 16 MHz, 400 MHz, external 24 MHz crystal, and
external 32 kHz crystal are enabled
• All PLLs are enabled
• All peripherals are enabled and run at their
maximum clock root frequency under underdrive
mode
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
31
Electrical characteristics
Table 13. Typical power modes current and power consumption (Dual core) (continued)
Set Point #7 • CM7 runs at 200 MHz, lower voltage to 0.9 V;
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
24.9
36.1
49
40.4
mA
A
Active
CM4 is clock gated, lower voltage to 0.9 V
• CM7 domain bus frequency at 100 MHz
• Enables ECC for cache, TCM, and OCRAM
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
3.9
10.6
A
82.302
161.868
mW
• 16 MHz, 400 MHz, and external 32 kHz crystal are
enabled
• All PLLs are power gated
• All peripherals controlled by CM4 core are clock
gated, but remain powered
Set Point #9 • CM7 is clock gated, lower voltage to 0.9 V; CM4
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
13.3
36.1
34.4
40.5
mA
A
Active
runs at 100 MHz, lower voltage to 0.9 V
• CM4 domain bus frequency at 50 MHz
• Enables ECC for cache, TCM, and OCRAM
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
3.9
10.5
A
44.022
113.688
mW
• 16 MHz, 400 MHz, and external 32 kHz crystal are
enabled
• All PLLs are power gated
• All peripherals controlled by CM7 core are clock
gated, but remain powered
Set Point #11 • CM7 is power off; CM4 runs at 200 MHz, drive
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
25.9
38.4
45.7
45.8
A
mA
A
Active
voltage to 1.0 V
• CM4 domain bus frequency at 100 MHz
• Enables ECC for CM4 TCM and OCRAM
• DCDC is off, LDO_LPSR_ANA and
LDO_LPSR_DIG are active
3.9
10.3
126.818
151.325
mW
• 16 MHz, 400 MHz, and external 32 kHz crystal are
enabled
• All PLLs are power gated
• The WAKEUPMIX domain, MEGAMIX domain,
and DISPLAYMIX domain are power gated
• All peripherals in LPSRMIX domain are clocked
Set Point #12 • CM7 is power off; CM4 runs at 100 MHz, lower
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
25.7
23
45.2
28
A
mA
A
Active
voltage to 0.9 V
• CM4 domain bus frequency at 50 MHz
• Enables ECC for CM4 TCM and OCRAM
• DCDC is off, LDO_LPSR_ANA and
LDO_LPSR_DIG are active
3.8
10.2
75.997
92.583
mW
• 16 MHz, 400 MHz, and external 32 kHz crystal are
enabled
• All PLLs are power gated
• The WAKEUPMIX domain, MEGAMIX domain,
and DISPLAYMIX domain are power gated
• All peripherals in LPSRMIX domain are clocked
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
32
Electrical characteristics
Table 13. Typical power modes current and power consumption (Dual core) (continued)
Set Point #1 • System is on STANDBY mode
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
4.1
27.6
22.6
30.5
mA
A
Standby
Suspend
• Both CM7 and CM4 are on SUSPEND mode
• TCM with ECC is on retention
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
3.8
10.4
A
13.634
74.715
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• All peripherals are clock gated, but remain
powered
Set Point #0 • System is on STANDBY mode
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
3
17
29.4
mA
A
Standby
Suspend
• Both CM7 and CM4 are on SUSPEND mode
27.5
3.8
• TCM with ECC is on retention
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
10.3
A
10.003
56.231
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• All peripherals are clock gated, but remain
powered
Set Point #5 • System is on STANDBY mode
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
2.4
27.6
3.8
13.1
29.3
mA
A
Standby
Suspend
• Both CM7 and CM4 are on SUSPEND mode
• TCM with ECC is on retention
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
10.3
A
8.024
43.361
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• All peripherals are clock gated, but remain
powered
Set Point #7 • System is on STANDBY mode
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
2.4
27.6
3.8
13.1
29.3
mA
A
Standby
Suspend
• Both CM7 and CM4 are on SUSPEND mode
• TCM with ECC is on retention
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
10.3
A
8.024
43.361
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• All peripherals are clock gated, but remain
powered
Set Point #10 • Lower voltage to 0.8 V with RBB mode for both
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
1.9
27.6
3.8
8.7
29.2
mA
A
Standby
Suspend
SOC and LPSR domains
• System is on STANDBY mode
• Both CM7 and CM4 are on SUSPEND mode
• TCM with ECC is on retention
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
10.2
A
6.374
28.840
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• All peripherals are clock gated, but remain
powered
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
33
Electrical characteristics
Table 13. Typical power modes current and power consumption (Dual core) (continued)
Set Point #11 • System is on STANDBY mode
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
25.6
0.759
3.8
44.8
6
A
mA
A
Standby
Suspend
• CM7 is power off, CM4 is on SUSPEND mode
• CM4 TCM with ECC is on retention
• DCDC is off, LDO_LPSR_ANA and
LDO_LPSR_DIG are active
10.1
19.981
2.602
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• The WAKEUPMIX domain, MEGAMIX domain,
and DISPLAYMIX domain are power gated
• All peripherals in LPSRMIX domain are clock
gated, but remain powered
Set Point #15 • Lower voltage to 0.8 V with RBB mode for LPSR
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
25.5
0.408
3.8
44.6
3.5
A
mA
A
Standby
Suspend
domain
• System is on STANDBY mode
• CM7 is power off, CM4 is on SUSPEND mode
• CM4 TCM with ECC is on retention
• DCDC is off, LDO_LPSR_ANA and
LDO_LPSR_DIG are active
10.1
1.443
11.731
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• The WAKEUPMIX domain, MEGAMIX domain,
and DISPLAYMIX domain are power gated
• All peripherals in LPSRMIX domain are clock
gated, but remain powered
SNVS
• Only SNVS domain is powered
• 32 kHz RTC is alive
• DCDC_IN and VDD_LPSR_IN are power gated
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
0
0
0
0
A
A
A
W
3.8
12.54
10.2
33.66
1
Code runs in the ITCM; typical values are the average values on typical process wafers.
Table 14. Typical power modes current and power consumption (Single core)
Power supplies at 3.3 V (Typical)1
Modes
Test conditions
Units
25 oC Tj 105 oC Tj
Set Point #1 • CM7 runs at 800 MHz, overdrive voltage to 1.1 V
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
123
36.3
319.8
40.8
mA
A
Active
with FBB mode
• CM7 domain bus frequency at 240 MHz
• Enables ECC for cache, TCM, and OCRAM
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
4
12
A
406.033
1055.514
mW
• 16 MHz, 400 MHz, external 24 MHz crystal, and
external 32 kHz crystal are enabled
• All PLLs are enabled
• All peripherals are enabled and run at their
maximum clock root frequency under overdrive
mode
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
34
Electrical characteristics
Table 14. Typical power modes current and power consumption (Single core) (continued)
Set Point #0 • CM7 runs at 600 MHz, drive voltage to 1.0 V
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
75.9
36.3
120.8
40.7
mA
A
Active
• CM7 domain bus frequency at 200 MHz
• Enables ECC for cache, TCM, and OCRAM
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
3.9
11.6
A
250.603
398.813
mW
• 16 MHz, 400 MHz, external 24 MHz crystal, and
external 32 kHz crystal are enabled
• All PLLs are enabled
• All peripherals are enabled and run at their
maximum clock root frequency under normal drive
mode
Set Point #5 • CM7 runs at 240 MHz, lower voltage to 0.9 V
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
41.5
36.1
67.5
40.7
mA
A
Active
• CM7 domain bus frequency at 100 MHz
• Enables ECC for cache, TCM, and OCRAM
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
3.9
10.8
A
137.082
222.920
mW
• 16 MHz, 400 MHz, external 24 MHz crystal, and
external 32 kHz crystal are enabled
• All PLLs are enabled
• All peripherals are enabled and run at their
maximum clock root frequency under underdrive
mode
Set Point #7 • CM7 runs at 200 MHz, lower voltage to 0.9 V
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
24.3
36.1
48.2
40.6
mA
A
Active
• CM7 domain bus frequency at 100 MHz
• Enables ECC for cache, TCM, and OCRAM
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
3.9
10.5
A
80.322
159.229
mW
• 16 MHz, 400 MHz, and external 32 kHz crystal are
enabled
• All PLLs are power gated
• All peripherals are clocked
Set Point #1 • System is on STANDBY mode
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
4.2
27.4
22.2
30.4
mA
A
Standby
Suspend
• CM7 is on SUSPEND mode
• TCM with ECC is on retention
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
3.9
10.3
A
13.963
73.394
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• All peripherals are clock gated, but remain
powered
Set Point #0 • System is on STANDBY mode
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
3.1
27.3
16.8
29.6
mA
A
Standby
Suspend
• CM7 is on SUSPEND mode
• TCM with ECC is on retention
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
3.9
10.3
A
10.333
55.572
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• All peripherals are clock gated, but remain
powered
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 14. Typical power modes current and power consumption (Single core) (continued)
Set Point #5 • System is on STANDBY mode
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
2.4
27.3
3.9
12.9
29.3
mA
A
Standby
Suspend
• CM7 is on SUSPEND mode
• TCM with ECC is on retention
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
10.2
A
8.023
42.700
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• All peripherals are clock gated, but remain
powered
Set Point #10 • Lower voltage to 0.8 V with RBB mode for both
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
1.9
27.1
3.9
8.6
29.2
mA
A
Standby
Suspend
SOC and LPSR domains
• System is on STANDBY mode
• CM7 is on SUSPEND mode
• TCM with ECC is on retention
• LDO_LPSR_ANA and LDO_LPSR_DIG are
bypassed
10.2
A
6.372
28.510
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• All peripherals are clock gated, but remain
powered
Set Point #15 • Lower voltage to 0.8 V with RBB mode for LPSR
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
26.3
0.423
3.8
44.2
3.5
A
mA
A
Standby
Suspend
domain
• System is on STANDBY mode
• CM7 is power off
10.1
• LMEM is on retention
• DCDC is off, LDO_LPSR_ANA and
LDO_LPSR_DIG are active
1.495
11.729
mW
• All clock sources are turned off except for 32 kHz
RTC
• All PLLs are power gated
• The WAKEUPMIX domain, MEGAMIX domain,
and DISPLAYMIX domain are power gated
• All peripherals in LPSRMIX domain are clock
gated, but remain powered
SNVS
• Only SNVS domain is powered
• 32 kHz RTC is alive
• DCDC_IN and VDD_LPSR_IN are power gated
DCDC_IN
VDD_LPSR_IN
VDD_SNVS_IN
Total
0
0
0
0
A
A
A
W
3.9
12.87
10.2
33.66
1
Code runs in the ITCM; typical values are the average values on typical process wafers.
Table 15 shows the typical wakeup time.
1
Table 15. Typical wakeup time
Description
Typical wakeup time
Unit
From Set Point #1 Standby Suspend to Set Point #1 Overdrive RUN
From Set Point #0 Standby Suspend to Set Point #1 Overdrive RUN
4.76
6.4
ms
ms
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Electrical characteristics
1
Table 15. Typical wakeup time (continued)
Description
Typical wakeup time
Unit
From Set Point #5 Standby Suspend to Set Point #1 Overdrive RUN
From Set Point #10 Standby Suspend to Set Point #1 Overdrive RUN
From Set Point #15 Standby Stop to Set Point #1 Overdrive RUN
From SNVS mode to ROM exit
6.96
6.74
8.07
8.54
ms
ms
ms
ms
1
Please refer to Table 13 and Table 14 for Set Point modes definition, and the only difference between Set Point #15 Standby
Suspend mode and Set Point #15 Standby Stop mode is the Suspend mode versus Stop mode on CM4 core.
4.2
System power and clocks
This section provides the information about the system power and clocks.
4.2.1
Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
•
•
•
Excessive current during power-up phase
Prevention of the device from booting
Irreversible damage to the processor (worst-case scenario)
Figure 4 shows the power sequence.
VDD_SNVS_IN
VDD_SNVS_ANA
VDD_SNVS_DIG
VDD_LPSR_IN
VDD_LPSR_ANA
VDD_LPSR_DIG
DCDC_IN
1ms
DCDC_PSWITCH
VDDA_1P8
VDD_SOC_IN
ONOFF
POR_B
Figure 4. Power sequence
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Electrical characteristics
4.2.1.1
Power-up sequence
The below restrictions must be followed:
•
•
•
•
•
VDD_SNVS_IN supply must be turned on before any other power supply or be connected
(shorted) with VDD_LPSR_IN and DCDC_IN supply.
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other
supply is switched on.
When internal DCDC is enabled, external delay circuit is required to delay the
“DCDC_PSWITCH” signal at least 1 ms after DCDC_IN is stable.
Need to ensure DCDC_IN ramps to 3.0 V within 0.2 x RC, RC is from external delay circuit used
for DCDC_PSWITCH and must be longer than 1 ms.
POR_B (if used) must be held low during the entire power up sequence.
NOTE
The POR_B input (if used) must be immediately asserted at power-up and
remain asserted until after the last power rail reaches its working voltage. In
the absence of an external reset feeding the POR_B input, the internal POR
module takes control. See the i.MX RT1170 Reference Manual
(IMXRT1170RM) for further details and to ensure that all necessary
requirements are being met.
NOTE
The voltage on DCDC_PSWITCH pin should be below 0.5 V before
ramping up the voltage on DCDC_PSWITCH.
NOTE
The power rail VDD_SNVS_DIG is controlled by software.
NOTE
Need to ensure that there is no back voltage (leakage) from any supply on
the board towards the 3.3 V supply (for example, from the external
components that use both the 1.8 V and 3.3 V supplies).
NOTE
USB1_VBUS, USB2_VBUS, and VDDA_ADC_3P3 are not part of the
power supply sequence and may be powered at any time.
4.2.1.2
Power-down sequence
The following restrictions must be followed:
•
•
VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted)
with VDD_LPSR_IN and DCDC_IN supply.
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply
is switched off.
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NXP Semiconductors
Electrical characteristics
4.2.1.3
Power supplies usage
I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_XXXX) is OFF.
This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O
power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, Package information
and contact assignments.”
4.2.2
Internal POR and power detect
Internal detector monitors VDD_SOC_IN and VDD_LPSR_DIG. Internal POR will be asserted whenever
VDD_SOC_IN or VDD_LPSR_DIG are lower than the valid voltage values shown in the Table 16.
Table 16. Internal POR and power detect
Symbol
Description
Value
Unit
Vdetlpsr1p0_H
Vdetsoc1p0_H
Hystdet1p0
1.0 V supply valid
1.0 V supply valid
0.75
0.75
100
V
V
The detector hysteresis
mV
4.2.3
Integrated LDO voltage regulator parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. The on-chip LDOs
are intended for internal use only and should not be used to power any external circuitry. See the i.MX
RT1170 Reference Manual (IMXRT1170RM) for details on the power tree scheme.
4.2.3.1
LDO_SNVS_ANA
Table 17 shows the parameters of LDO_SNVS_ANA.
Table 17. LDO_SNVS_ANA specification
Specification
Min
Typ
Max
Unit
VDD_SNVS_IN
VDD_SNVS_ANA
I_out
2.4
1.65
—
3
3.6
1.95
1
V
V
1.75
—
mA
F
External decoupling capacitor
—
2.2
—
4.2.3.2
LDO_SNVS_DIG
Table 18 shows the parameters of LDO_SNVS_DIG.
Table 18. LDO_SNVS_DIG specification
Specification
Min
Typ
Max
Unit
VDD_SNVS_ANA
VDD_SNVS_DIG
1.65
0.65
1.75
0.85
1.95
0.95
V
V
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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39
Electrical characteristics
Table 18. LDO_SNVS_DIG specification (continued)
Specification
Min
Typ
Max
Unit
I_out
—
—
—
1
mA
External decoupling capacitor
0.22
—
F
4.2.3.3
LDO_PLL
Table 19 shows the parameters of LDO_PLL.
Table 19. LDO_PLL specification
Min
Specification
Typ
Max
Unit
VDDA_1P8_IN
VDDA_1P0
I_out
1.71
0.9
—
1.8
1
1.89
1.2
70
V
V
—
2.2
mA
F
External decoupling capacitor
—
—
4.2.3.4
LPSR_LDO_DIG
LPSR_LDO_DIG provides 1.0 V power source (VDD_LPSR_DIG) from 1.8V power domain
(VDD_LPSR_ANA). The trim voltage range of LDO output is from 0.7 V to 1.15 V. There are two work
modes: Low Power mode and High Power mode. In typical PVT case, the static current consumption is
less than 3 A in Low Power mode. The maximum drive strength of this LDO regulator is 50 mA in High
Power mode.
Table 20. LPSR_LDO_DIG specification
Specification
Min
Typ
Max
Unit
VDD_LPSR_ANA
VDD_LPSR_DIG
I_out
1.71
0.7
—
1.8
1
1.89
1.15
50
V
V
—
2.2
mA
F
External decoupling capacitor
—
—
4.2.3.5
LPSR_LDO_ANA
LPSR_LDO_ANA provides 1.8 V power source (VDD_LPSR_ANA) from 3.3 V power domain
(VDD_LPSR_IN). Its default output value is 1.8 V. Two work modes are supported by this LDO: Low
Power mode and High Power mode. In Low Power mode, the LDO provides 2 mA (maximum value) by
consuming only 4 A current. In High Power mode, the LDO provides 75 mA current capacity with 40 A
static power dissipation.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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NXP Semiconductors
Electrical characteristics
Table 21. LPSR_LDO_ANA specification
Specification
Min
Typ
Max
Unit
VDD_LPSR_IN
VDD_LPSR_ANA
I_out
3
3.3
1.8
—
3.6
—
V
V
—
—
—
75
—
mA
F
External decoupling capacitor
4.7
4.2.4
DCDC
DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During
the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a
minimum quiescent current to maintain high efficiency.
DCDC can detect the peak current in the P-channel switch. When the peak current exceeds the threshold,
DCDC will give an alert signal, and the threshold can be configured. By this way, DCDC can roughly
detect the current loading.
DCDC also includes the following protection functions:
•
Over current protection. In run mode, DCDC shuts down when detecting abnormal large current in
the P-type power switch.
•
•
Over voltage protection. DCDC shuts down when detecting the output voltage is too high.
Low voltage detection. DCDC shuts down when detecting the input voltage is too low.
Table 22 shows DCDC characteristics.
Table 22. DCDC characteristics
Description
Input voltage
Min Typ Max
Unit
Comments
3
3.3
3.6
V
—
Output voltage
• 1.0 V output
• 1.8 V output
Loading
0.6
1.5
1
1.375
2.275
V
V
25 mV per step
25 mV per step
1.8
• 1.0 V output
• 1.8 V output
Efficiency
—
—
150
80
850
150
mA
mA
—
——
• DCDC run mode
—
—
80%
80%
—
—
—
—
150 mA@vdd1p0
80 mA@vdd1p8
• DCDC low power mode
Output voltage accuracy
300 A@vdd1p0
300 A@vdd1p8
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 22. DCDC characteristics
Min Typ Max
-2.5%
Description
Unit
Comments
• DCDC Run mode
—
2.5%
—
Maximum 50 mV
Vp-p@vdd1p0
• DCDC Low power mode
Over current detection
-6%
—
—
6%
—
—
A
—
1.5
The typical value can be
configured as 1.5 A and
2 A by register.
Over voltage detection
• Output 1.8 V
—
—
—
—
2.5
1.5
2.6
3
2.75
1.65
2.8
V
—
• Output 1.0 V
V
—
• Low DCDC_IN detection
Leakage current
V
—
—
A
DCDC off
Quiescent current
• DCDC Run mode
• DCDC Low power mode
Capacitor value
—
—
—
150
5
—
—
—
A
A
F
—
—
33
High frequency
capacitor are also
required.
(DCDC_ANA)
66
(DCDC_DIG)
Inductor value
—
—
4.7
1
—
—
H
—
—
• Saturation current
A
For additional information, see the i.MX RT1170 Reference Manual (IMXRT1170RM).
4.2.5
PLL’s electrical characteristics
This section provides PLL electrical characteristics.
4.2.5.1 Audio/Video PLL’s electrical parameters
Table 23. Audio/Video PLL’s electrical parameters
Parameter
Min
Typ
Max
Unit
Clock output range
Reference clock
Lock time
650
—
—
24
—
1300
—
MHz
MHz
—
11250
reference cycles
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Unit
Table 23. Audio/Video PLL’s electrical parameters (continued)
Parameter
Min
Typ
Max
Period jitter (p2p)
Duty cycle
—
50
—
—
ps
%
48.5
51.5
4.2.5.2
528 MHz PLL
Table 24. 528 MHz PLL’s electrical parameters
Parameter
Min
Typ
Max
Unit
Clock output range
Reference clock
Lock time
—
—
—
—
—
45
—
24
—
528
—
MHz
MHz
11250
—
reference cycles
Period jitter (p2p)
PFD period jitter (p2p)
Duty cycle
50
100
—
ps
ps
%
—
55
4.2.5.3
Ethernet PLL
Table 25. Ethernet PLL’s electrical parameters
Parameter
Min
Typ
Max
Unit
Clock output range
Reference clock
Lock time
—
—
—
24
—
50
—
1000
—
MHz
MHz
—
11250
—
reference cycles
Period jitter (p2p)
Duty cycle
—
ps
%
47.5
52.5
4.2.5.4
480 MHz PLL
Table 26. 480 MHz PLL’s electrical parameters
Parameter
Min
Typ
Max
Unit
Clock output range
Reference clock
Lock time
—
—
—
—
—
24
—
40
480
—
MHz
MHz
383
—
reference cycles
ps
Period jitter (p2p)
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Parameter
Table 26. 480 MHz PLL’s electrical parameters (continued)
Min
Typ
Max
Unit
PFD period jitter (p2p)
Duty cycle
—
125
—
—
ps
%
45
55
4.2.5.5
Arm PLL
Table 27. Arm PLL’s electrical parameters
Parameter
Min
Typ
Max
Unit
Clock output range
Reference clock
Lock time
624
—
—
24
—
15
—
1248
—
MHz
MHz
—
2250
—
reference cycles
Period jitter (p2p)
Duty cycle
—
ps
%
45
55
4.2.6
On-chip oscillators
The system oscillator (SYS OSC) is a crystal oscillator. The SYS OSC, in conjunction with an external
crystal or resonator, generates a reference clock for this chip. It also provides the option for an external
input clock to XTALI signal directly.
Table 28. System oscillator frequency specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IVDDA (Low power mode) Analog supply current
IVDDA (High gain mode) Analog supply current
24 MHz
24 MHz
—
—
0.5
1.3
—
—
mA
mA
RF
Feedback resistor
Low-power mode
High-gain mode
—
No need
—
—
1
0
—
—
M
k
RS
Series resistor1
CXCY
Cpara
XTALI/XTALO load capacitance
See crystal or resonator manufacture’s recommendation
Parasitically capacitance of
XTALI and XTALO
—
—
1.5
2.0
pF
Clock output
FOSC
Oscillator crystal or resonator
frequency
—
—
—
24
50
—
MHz
%
tdcy
Duty-cycle of the output clock
40
60
Dynamic parameters
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 28. System oscillator frequency specifications (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VPP
Peak-peak amplitude of
oscillation
Low-power mode
High gain mode
—
0.8
—
—
V
V
0.75x
0.8 x
VDDA_ VDDA_
1P8_IN 1P8_IN
tstart
Start-up time
24 MHz low-power
mode
—
250
—
—
s
s
24 MHz high-gain
mode
—
250
1
Depends on the drive level of external crystal device
Each i.MX RT1170 processor has two external input system clocks: a low frequency (RTC_XTALI) and
a high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, and slow system and watch-dog counters. The clock input can be
connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is
an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either external oscillator or a crystal using internal
oscillator amplifier.
Table 29. 32 kHz oscillator DC electrical specifications
Symbol
Description
Min
Typ
Max
Unit
Note
Cpara
Parasitically capacitance of RTC_XTALI
and RTC_XTALO
—
1.5
2.0
pF
—
1
Vpp
fosc_lo
Peak-to-peak amplitude of oscillator
Oscillator crystal
—
—
0.6
32.768
500
—
—
—
V
kHz
ms
V
—
1
tstart
Crystal startup time
—
2,3
Vec_extal32
Externally provided input clock amplitude
0.7
—
VDD_SNVS
_ANA
1
2
Proper PCB layout procedures must be followed to achieve specifications.
This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3
The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock
must be within the range of VSS to VDD_SNVS_ANA.
The RTC OSC module provides the clock source for the Real-Time Clock module. The RTC OSC module,
in conjunction with an external crystal, generates a 32.768 kHz reference clock for the RTC.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 30. RC oscillator with 16 MHz internal reference frequency
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Clock output
Fclkout_16M
Clock frequency
—
—
—
15.1
—
16
50
2
16.9
—
MHz
s
Dynamic parameters
Tstart_16M
Power-down mode
IVDDA
Start-up time
Supply current in power-down
1
95
nA
Table 31. RC oscillator with 48 MHz internal reference frequency
Symbol
Parameter
Condition
Min
Typ
Max
Unit
General
IVDDA
Analog supply current
Clock frequency
—
—
—
—
—
—
—
-2
350
48
500
—
—
2
A
MHz
s
Clock output
Fclkout
Dynamic parameters
Tstart Start-up time
Accuracy
2.5
—
Ttarget
Trimmed
%
Table 32. RC oscillator with 400 MHz internal reference frequency
Symbol
Parameter
Condition
Min
Typ
Max
Unit
General
IVDD_1P8V_ON
IVDD_ON
Analog supply current
Digital supply current
—
—
—
—
60
80
—
—
A
A
Clock output
F_tuned
Tuned clock frequency
—
—
—
—
400
0.1
—
—
MHz
%
ΔF/F
Frequency error after tuning
Dynamic parameters
JPP-CC Peak-peak, period jitter
tstart
—
—
—
—
—
1
50
1
—
—
ns
s
s
Start-up time
Tuning time
ttune
—
256
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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46
Electrical characteristics
Table 33. RC oscillator with 32 kHz internal reference frequency
Symbol
Description
Min
Typ
Max
Unit
Note
firc32k
Internal reference frequency
Deviation of IRC32K frequency
—
32
—
—
kHz
—
—
Δfirc32k
-25%
25%
%firc32k
4.3
I/O parameters
This section provides parameters on I/O interfaces.
4.3.1
I/O DC parameters
This section includes the DC parameters of the following I/O types:
•
•
XTALI and RTC_XTALI (Clock Inputs) DC Parameters
General Purpose I/O (GPIO)
NOTE
The term ‘NVCC_XXXX’in this section refers to the associated supply rail
of an input or output.
NOTE
When enable the open drain for I/O pad, the external pull-up voltage cannot
exceed the associated supply rail.
Figure 5. Circuit for parameters Voh and Vol for I/O cells
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Electrical characteristics
4.3.1.1
XTALI and RTC_XTALI (clock inputs) DC parameters
Table 34 shows the DC parameters for the clock inputs.
1
Table 34. XTALI and RTC_XTALI DC parameters
Symbol Test Conditions Min
Parameter
Max
Unit
XTALI high-level DC input voltage
XTALI low-level DC input voltage
Vih
Vil
—
—
—
—
VDDA_1P8_IN - 0.5
0
VDDA_1P8_IN
0.5
V
V
V
V
RTC_XTALI high-level DC input voltage
RTC_XTALI low-level DC input voltage
Vih
Vil
VDD_SNVS_ANA - 0.5 VDD_SNVS_ANA
0.5
0
1
The DC parameters are for external clock input only.
4.3.1.2
General purpose I/O (GPIO) DC parameters
Following section introduces the GPIO DC parameters, respectively, for GPIO pads. These parameters are
guaranteed per the operating ranges in Table 11 unless otherwise noted.
Table 35. DC specification for GPIO_EMC_B1/GPIO_EMC_B2/GPIO_SD_B1/GPIO_SD_B2/GPIO_DISP_B1
bank
Value
Parameter
Symbol
Unit
Condition
Min
Typ
Max
Receiver 3.3 V
High level input voltage
Low level input voltage
VIH
VIL
0.625 x NVCC
-0.3
—
—
NVCC + 0.3
0.25 x NVCC
V
V
—
—
Receiver 1.8 V
High level input voltage
Low level input voltage
VIH
VIL
0.65 x NVCC
-0.3
—
—
NVCC + 0.3
0.35 x NVCC
V
V
—
—
Driver 3.3 V and driver 1.8 V for PDRV = L and PDRV = H
Output high current
Output low current
IOH
IOL
-6
6
—
—
—
—
—
mA
mA
mA
VOH = 0.8 x NVCC
VOL = 0.2 x NVCC
—
Output low/high current total
for each IO bank
IOCT
—
100
Weak pull-up and pull-down
Pull-up / pull-down resistance
Pull-up / pull-down resistance
RHigh
10
—
100
50
k
k
High voltage range
(2.7 V - 3.6 V)
RLow
20
—
Low voltage range
(1.65 V - 1.95 V)
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Electrical characteristics
Table 36. DC specification for GPIO_SNVS bank
Parameter
Symbol
Min
Typ
Max
Unit
Condition
High level input voltage
VIH
0.7 x
NVCC_SNVS
—
NVCC_SNVS+
0.1
V
V
—
Low level input voltage
Output high current
Output low current
VIL
-0.3
170
—
—
0.3 x
NVCC_SNVS
—
IOH
—
A
VOH =
NVCC_SNVS - 0.3
IOL
270
—
—
—
—
A
VOL = 0.3
—
Output low/high current total for
each IO bank
IOCT
100
mA
Weak pull-up and pull-down
Pull-up resistance
RHigh
RLow
—
—
1000
850
3500
3500
—
—
Pull-down resistance
Table 37. DC specification for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2 bank
NO.
Characteristics
Test Conditions
Min
Max
Units
1
Input high voltage (VIH)
Normal voltage range
Derated voltage range
Derated2 voltage range
Low voltage range
0.7 x NVCC
0.75 x NVCC
0.75 x NVCC
0.7 x NVCC
0.7 x NVCC
- 0.3
NVCC + 0.1
NVCC + 0.1
NVCC + 0.1
NVCC + 0.1
NVCC + 0.1
0.3 x NVCC
0.25 x NVCC
0.25 x NVCC
0.3 x NVCC
0.3 x NVCC
—
V
V
V
V
V
V
V
V
V
V
V
V
High voltage range
Normal voltage range
Derated voltage range
Derated2 voltage range
Low voltage range
2
Input low voltage (VIL)
- 0.3
- 0.3
- 0.3
High voltage range
All voltage range
- 0.3
3
4
Input Hysteresis (VHYSN)
0.06 x NVCC
NVCC - 0.5
Output high voltage (VOH
)
Normal voltage range
IOH = -10 mA
—
DSE = 1
Derated voltage range
IOH = -6 mA
NVCC - 0.5
NVCC - 0.5
NVCC - 0.5
NVCC - 0.5
—
—
—
—
V
V
V
V
Derated2 voltage range
IOH = -5 mA
Low voltage range
IOH = -10 mA
High voltage range
IOH = -10 mA
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Electrical characteristics
Table 37. DC specification for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2 bank (continued)
NO.
Characteristics
Test Conditions
Min
Max
Units
5
Output high voltage (VOH
)
Normal voltage range
IOH = -5 mA
NVCC - 0.5
—
V
DSE = 0
Derated voltage range
NVCC - 0.5
—
—
V
V
V
V
V
V
V
V
V
V
V
V
V
V
I
OH = -3 mA
Derated2 voltage range
IOH = -2.5 mA
NVCC - 0.5
Low voltage range
IOH = -5 mA
NVCC - 0.5
—
High voltage range
NVCC - 0.5
—
I
OH = -5 mA
6
7
8
Output low voltage (VOL
)
Normal voltage range
IOL = 10 mA
—
—
—
—
—
—
—
—
—
—
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
DSE = 1
Derated voltage range
IOL = 6 mA
Derated2 voltage range
IOL = 5 mA
Low voltage range
IOL = 10 mA
High voltage range
IOL = 10 mA
Output low voltage (VOL
)
Normal voltage range
IOL = 5 mA
DSE = 0
Derated voltage range
IOL = 3 mA
Derated2 voltage range
IOL = 2.5 mA
Low voltage range
IOL = 5 mA
High voltage range
IOL = 5 mA
NVCC
Normal voltage range
Derated voltage range
Derated2 voltage range
Low voltage range
2.7
1.98
1.71
1.71
3
3.6
2.7
V
V
1.98
1.98
3.6
V
V
High voltage range
All voltage range
V
11
12
Pull-up resistor range (RPU
)
25
50
k
Measure @VDD
Pull-down resistor range
All voltage range
25
50
k
(RPD
)
Measure @VSS
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Electrical characteristics
Table 37. DC specification for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2 bank (continued)
NO.
Characteristics
Test Conditions
Min
Max
Units
13
14
15
16
Input leakage current
Output capacitance (CL)
Input capacitance (Cin)
All voltage range
All voltage range
All voltage range
All voltage range
—
—
—
—
400
15
nA
pF
5
pF
Output low/high current
100
mA
total for each IO bank (IOCT
)
4.3.2
I/O AC parameters
The GPIO and DDR I/O load circuit and output transition time waveform are shown in Figure 6 and
Figure 7.
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 6. Load circuit for output
OVDD
0 V
80%
20%
80%
20%
tr
Output (at pad)
tf
Figure 7. Output transition time waveform
4.3.2.1
General purpose I/O (GPIO) AC parameters
The I/O AC parameters for GPIO are presented in the Table 38 and Table 39, respectively.
Table 38. AC specification for GPIO_EMC_B1/GPIO_EMC_B2/GPIO_SD_B1/GPIO_SD_B2/GPIO_DISP_B1
bank
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
Driver 1.8 V application
fmax
Maximum frequency
Load = 21 pF (PDRV = L, high drive,
208
MHz
33
—
—
Load = 15 pF (PDRV = H, low drive,
50
tr
tf
Rise time
Fall time
Measured between VOL and VOH
Measured between VOH and VOL
Driver 3.3 V application
0.4
0.4
—
—
1.32
1.32
ns
ns
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Electrical characteristics
Table 38. AC specification for GPIO_EMC_B1/GPIO_EMC_B2/GPIO_SD_B1/GPIO_SD_B2/GPIO_DISP_B1
bank (continued)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
fmax
tr
Maximum frequency
Rise time
Load = 20 pF
—
—
—
—
—
—
200
3
MHz
ns
Measured between VOL and VOH
Measured between VOH and VOL
tf
Fall time
3
ns
Table 39. Dynamic input characteristics for
GPIO_EMC_B1/GPIO_EMC_B2/GPIO_SD_B1/GPIO_SD_B2/GPIO_DISP_B1 bank
Symbol
Parameter
Test Condition1, 2
Min
Max
Unit
Dynamic Input Characteristics for 3.3 V Application
fop
Input frequency of operation
—
—
—
200
3.5
MHz
ns
INPSL Slope of input signal at I/O
Measured between 10% to 90% of the I/O swing
Dynamic Input Characteristics for 1.8 V Application
fop
Input frequency of operation
—
—
—
208
1.5
MHz
ns
INPSL Slope of input signal at I/O
For all supply ranges of operation.
Measured between 10% to 90% of the I/O swing
1
2
The dynamic input characteristic specifications are applicable for the digital bidirectional cells.
Table 40. AC specifications for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2 bank
NO.
Characteristic
Condition
Max
Unit
1
Pad rise/fall time (DSE = 0, SRE = 0)
Normal voltage range
(Cload = 15 pF)
—
—
—
—
—
3
ns
Derated voltage range
(Cload = 15 pF)
5
6
3
3
ns
ns
ns
ns
Derated2 voltage range
(Cload = 15 pF)
Low voltage range
(Cload = 15 pF)
High voltage range
(Cload = 15 pF)
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Electrical characteristics
Table 40. AC specifications for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2 bank (continued)
NO.
Characteristic
Condition
Max
Unit
2
Pad rise/fall time (DSE = 0, SRE = 1)
Normal voltage range
(Cload = 15 pF)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
ns
Derated voltage range
(Cload = 15 pF)
10
12
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Derated2 voltage range
(Cload = 15 pF)
Low voltage range
(Cload = 15 pF)
High voltage range
(Cload = 15 pF)
6
3
4
5
Pad rise/fall time (DSE = 1, SRE = 0)
Normal voltage range
(Cload = 15 pF)
2.5
4.5
5
Derated voltage range
(Cload = 15 pF)
Derated2 voltage range
(Cload = 15 pF)
Low voltage range
(Cload = 15 pF)
2.5
2.5
5
High voltage range
(Cload = 15 pF)
Pad rise/fall time (DSE = 1, SRE = 1)
Normal voltage range
(Cload = 15 pF)
Derated voltage range
(Cload = 15 pF)
9
Derated2 voltage range
(Cload = 15 pF)
10
5
Low voltage range
(Cload = 15 pF)
High voltage range
(Cload = 15 pF)
5
IPP_DO to pad propagation delay:
(DSE = 0, SRE = 0)
Normal voltage range
(Cload = 15 pF)
2.5
4.5
5
Derated voltage range
(Cload = 15 pF)
Derated2 voltage range
(Cload = 15 pF)
Low voltage range
(Cload = 15 pF)
2.5
4
High voltage range
(Cload = 15 pF)
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Electrical characteristics
Table 40. AC specifications for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2 bank (continued)
NO.
Characteristic
Condition
Max
Unit
6
IPP_DO to pad propagation delay:
(DSE = 0, SRE = 1)
Normal voltage range
(Cload = 15 pF)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7
ns
Derated voltage range
(Cload = 15 pF)
12
14
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Derated2 voltage range
(Cload = 15 pF)
Low voltage range
(Cload = 15 pF)
High voltage range
(Cload = 15 pF)
8.5
2
7
8
9
IPP_DO to pad propagation delay:
(DSE = 1, SRE = 0)
Normal voltage range
(Cload = 15 pF)
Derated voltage range
(Cload = 15 pF)
3.6
4
Derated2 voltage range
(Cload = 15 pF)
Low voltage range
(Cload = 15 pF)
2
High voltage range
(Cload = 15 pF)
4
IPP_DO to pad propagation delay:
(DSE = 1, SRE = 1)
Normal voltage range
(Cload = 15 pF)
6
Derated voltage range
(Cload = 15 pF)
11
12
6
Derated2 voltage range
(Cload = 15 pF)
Low voltage range
(Cload = 15 pF)
High voltage range
(Cload = 15 pF)
7.5
2
Pad to IPP_IND propagation delay
Normal voltage range
(100 F load on IPP_IND)
Derated voltage range
(100 F load on IPP_IND)
3.5
4
Derated2 voltage range
(100 F load on IPP_IND)
Low voltage range
(100 F load on IPP_IND)
4
High voltage range
2
(100 F load on IPP_IND)
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 40. AC specifications for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2 bank (continued)
NO.
Characteristic
IPP_IND rise/fall time
Condition
Max
Unit
10
Normal voltage range
(100 F load on IPP_IND)
—
—
—
—
—
0.3
ns
Derated voltage range
(100 F load on IPP_IND)
0.4
0.5
0.3
0.3
ns
ns
ns
ns
Derated2 voltage range
(100 F load on IPP_IND)
Low voltage range
(100 F load on IPP_IND)
High voltage range
(100 F load on IPP_IND)
Figure 8 is the GPIO block diagram.
IPP_OBE
IPP_DSE
IPP_DO
IPP_SRE
Pad
IPP_PUE
IPP_PUS
IOMUX/IOMUXC
PU/PD logic
PU/PD device
IPP_IBE
IPP_IND
IPP_HYS
INPUT RECEIVER
Figure 8. GPIO block diagram
4.4
System modules
This section contains the timing and electrical parameters for the modules in the i.MX RT1170 processor.
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Electrical characteristics
4.4.1
Reset timing parameters
Figure 9 shows the POR reset timing and Table 41 lists the timing parameters.
POR_B
(Input)
CC1
Figure 9. POR reset timing diagram
Table 41. POR reset timing parameters
ID
Parameter
Min Max
Unit
CC1
Duration of POR_B to be qualified as valid.
1
—
RTC_XTALI cycle
4.4.2
WDOG reset timing parameters
Figure 10 shows the WDOG reset timing and Table 42 lists the timing parameters.
WDOGn_B
(Output)
CC3
Figure 10. WDOGn_B timing diagram
Table 42. WDOGn_B timing parameters
ID
Parameter
Duration of WDOGn_B Assertion
Min
Max
Unit
CC3
1
—
RTC_XTALI cycle
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 s.
NOTE
WDOGn_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
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Electrical characteristics
4.4.3
JTAG Controller timing parameters
Figure 11 depicts the JTAG controller timing. Figure 12 depicts the JTAG TRST_B timing.
J1
J2
J2
TCK (input)
J4
J3
TDI / TMS (input)
J5
TDO (output)
TDO (output)
J6
Figure 11. JTAG controller timing
TCK (input)
J7
J8
TRST_B (input)
TRST_B (input)
J8
Figure 12. JTAG_TRST_B timing
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 43. JTAG timing parameters
Parameter
Value
ID
Unit
Min
Max
J0
J1
J2
J3
J4
J5
J6
J7
J8
TCK frequency
—
40
20
5
25
—
MHz
ns
TCK cycle time
TCK pulse width
—
ns
Input data setup time
Input data hold time
Output data valid time
Output high impedance time
TRST_B assert time
—
ns
5
—
ns
—
—
100
18
15.2
15.2
—
ns
ns
ns
TRST_B setup time to TCK edge
—
ns
4.4.4
SWD timing parameters
Figure 13 depicts the SWD timing.
S1
S2
S2
SWD_CLK (input)
SWD_DIO
S4
S3
S5
S6
SWD_DIO
SWD_DIO
Figure 13. SWD timing
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 44. SWD timing parameters
Description
Symbol
Min
Max
Unit
S0
S1
S2
S3
S4
S5
S6
SWD_CLK frequency
SWD_CLK cycle time
SWD_CLK pulse width
Input data setup time
Input data hold time
Output data valid time
—
20
10
5
50
—
MHz
ns
—
ns
—
ns
1
—
ns
—
—
14.4
14.4
ns
Output high impedance time
ns
4.4.5
Trace timing parameters
Figure 14 depicts the trace timing.
T1
T2
T2
TRACE_CLK (output)
TRACE0-3 (output)
T4
T4
T3
T3
Figure 14. Trace timing
Table 45. Trace timing parameters
Description
Symbol
Min
Max
Unit
T0
T1
T2
T3
T4
TRACE_CLK frequency
TRACE_CLK cycle time
TRACE_CLK pulse width
TRACE data setup time
TRACE data hold time
—
1/T0
6
70
—
—
—
—
MHz
ns
ns
2
ns
0.7
ns
4.5
External memory interface
The following sections provide information about external memory interfaces.
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Electrical characteristics
4.5.1
SEMC specifications
The following sections provide information on SEMC interface.
Measurements are with a load of 15 pf and an input slew rate of 1 V/ns.
4.5.1.1
SEMC output timing
There are ASYNC and SYNC modes for SEMC output timing.
4.5.1.1.1
SEMC output timing in ASYNC mode
Table 46 shows SEMC output timing in ASYNC mode.
Table 46. SEMC output timing in ASYNC mode
Symbol
Parameter
Min.
Max.
Unit
Comment
Frequency of operation
Internal clock period
Address output valid time
Address output hold time
Active low time
—
5
200
—
2
MHz
ns
TCK
TAVO
TAHO
TADVL
TDVO
TDHO
TWEL
—
ns
These timing parameters
apply to Address and ADV#
for NOR/PSRAM in ASYNC
mode.
(TCK - 2) 1
(TCK - 1) 2
—
—
ns
Data output valid time
Data output hold time
WE# low time
2
ns
ns
ns
These timing parameters
apply to Data/CLE/ALE and
WE# for NAND, apply to
Data/DM/CRE for
NOR/PSRAM, apply to
Data/DCX and WRX for DBI
interface.
(TCK - 2) 3
(TCK - 1) 4
—
1
2
3
4
Address output hold time is configurable by SEMC_*CR0.AH. AH field setting value is 0x0 in above table. When AH is set
with value N, TAHO min time should be ((N + 1) x TCK). See the i.MX RT1170 Reference Manual (IMXRT1170RM) for more
detail about SEMC_*CR0.AH register field.
ADV# low time is configurable by SEMC_*CR0.AS. AS field setting value is 0x0 in above table. When AS is set with value N,
TADL min time should be ((N + 1) x TCK - 1). See the i.MX RT1170 Reference Manual (IMXRT1170RM) for more detail about
SEMC_*CR0.AS register field.
Data output hold time is configurable by SEMC_*CR0.WEH. WEH field setting value is 0x0 in above table. When WEH is set
with value N, TDHO min time should be ((N + 1) x TCK). See the i.MX RT1170 Reference Manual (IMXRT1170RM) for more
detail about SEMC_*CR0.WEH register field.
WE# low time is configurable by SEMC_*CR0.WEL. WEL field setting value is 0x0 in above table. When WEL is set with value
N, TWEL min time should be ((N + 1) x TCK - 1). See the i.MX RT1170 Reference Manual (IMXRT1170RM) for more detail
about SEMC_*CR0.WEL register field.
Figure 15 shows the output timing in ASYNC mode.
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Electrical characteristics
4#+
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Figure 15. SEMC output timing in ASYNC mode
4.5.1.1.2
SEMC output timing in SYNC mode
Table 47 shows SEMC output timing in SYNC mode.
Table 47. SEMC output timing in SYNC mode
Symbol
Parameter
Min.
Max.
Unit
Comment
Frequency of operation
Internal clock period
Data output valid time
Data output hold time
—
5
200
—
MHz
ns
—
—
TCK
TDVO
TDHO
—
0.6
—
ns
These timing parameters apply to
Address/Data/DM/CKE/control
signals with SEMC_CLK for
SDRAM.
-0.7
ns
Figure 16 shows the output timing in SYNC mode.
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Electrical characteristics
3%-#?#,+
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Figure 16. SEMC output timing in SYNC mode
4.5.1.2
SEMC input timing
There are ASYNC and SYNC modes for SEMC input timing.
4.5.1.2.1
SEMC input timing in ASYNC mode
Table 48 shows SEMC input timing in ASYNC mode.
Table 48. SEMC input timing in ASYNC mode
Symbol
Parameter
Min.
Max.
Unit
Comment
TIS
TIH
Data input setup
Data input hold
7.1
0
—
—
ns
ns
ForNAND/NOR/PSRAM/DBI,
thesetimingparametersapply
to RE# and Read Data.
Figure 17 shows the input timing in ASYNC mode.
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Figure 17. SEMC input timing in ASYNC mode
4.5.1.2.2
SEMC input timing in SYNC mode
Table 49 and Table 50 show SEMC input timing in SYNC mode.
Table 49. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x0)
Symbol
Parameter
Min.
Max.
Unit
Comment
TIS
TIH
Data input setup
Data input hold
8.67
0
—
—
ns
ns
—
Table 50. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x1)
Symbol
Parameter
Min.
Max.
Unit
Comment
TIS
TIH
Data input setup
Data input hold
2
1
—
—
ns
ns
—
Figure 18 shows the input timing in SYNC mode.
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Figure 18. SEMC input timing in SYNC mode
4.5.2
FlexSPI parameters
Measurements are with a load 15 pf and input slew rate of 1 V/ns.
4.5.2.1 FlexSPI input/read timing
There are three sources for the internal sample clock for FlexSPI read data:
• Dummy read strobe generated by FlexSPI controller and looped back internally
(FlexSPIn_MCR0[RXCLKSRC] = 0x0)
• Dummy read strobe generated by FlexSPI controller and looped back through the
DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)
• Read strobe provided by memory device and input from DQS pad
(FlexSPIn_MCR0[RXCLKSRC] = 0x3)
The following sections describe input signal timing for each of these three internal sample clock sources.
4.5.2.1.1
SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 51. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
8.67
0
60
—
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
ns
Table 52. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X1
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
2
133
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
1
—
ns
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SCK
TIS
TIH
TIS
TIH
SIO[0:7]
Internal Sample Clock
Figure 19. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge, and FlexSPI controller sampling read data on the falling edge.
4.5.2.1.2
SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in SDR mode:
• A1—Memory generates both read data and read strobe on SCK rising edge (or falling
edge)
• A2—Memory generates read data on SCK falling edge and generates read strobe on
SCK rising edge
Table 53. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A1)
Value
Symbol
Parameter
Unit
Min
Max
Frequency of operation
Time delta between TSCKD and TSCKDQS
—
-2
166
2
MHz
ns
TSCKD - TSCKDQS
SCK
TSCKD
TSCKD
SIO[0:7]
TSCKDQS
TSCKDQS
DQS
Figure 20. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A1)
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NOTE
Timing shown is based on the memory generating read data and read strobe
on the SCK rising edge. The FlexSPI controller samples read data on the
DQS falling edge.
Table 54. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A2)
Value
Symbol
Parameter
Unit
Min
Max
Frequency of operation
Time delta between TSCKD and TSCKDQS
—
-2
166
2
MHz
ns
TSCKD - TSCKDQS
SCK
TSCKD
TSCKD
TSCKD
SIO[0:7]
TSCKDQS
TSCKDQS
TSCKDQS
DQS
Internal Sample Clock
Figure 21. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A2)
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge and read strobe on the SCK rising edge. The FlexSPI controller
samples read data on a half cycle delayed DQS falling edge.
4.5.2.1.3
DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 55. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
8.67
0
30
—
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
ns
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Table 56. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
2
66
—
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
1
ns
SCLK
TIS
TIH
TIS
TIH
SIO[0:7]
Internal Sample Clock
Figure 22. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
4.5.2.1.4
DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in DDR mode:
• B1—Memory generates both read data and read strobe on SCK edges
• B2—Memory generates read data on SCK edges and generates read strobe on SCK2
edges
Table 57. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)
Symbol
Parameter
Min
Max
Unit
Frequency of operation
Time delta between TSCKD and TSCKDQS
—
-1
166
1
MHz
ns
TSCKD - TSCKDQS
SCK
TSCKD
SIO[0:7]
TSCKDQS
DQS
Figure 23. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)
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Table 58. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)
Symbol
Parameter
Min
Max
Unit
Frequency of operation
Time delta between TSCKD and TSCKDQS
—
-1
166
1
MHz
ns
TSCKD - TSCKDQS
SCK
SIO[0:7]
SCK2
TSCKD
TSCK2DQS
DQS
Figure 24. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)
4.5.2.2
FlexSPI output/write timing
The following sections describe output signal timing for the FlexSPI controller including control signals
and data outputs.
4.5.2.2.1
SDR mode
Table 59. FlexSPI output timing in SDR mode
Parameter Min
Frequency of operation
Symbol
Max
Unit
—
6.0
—
1
1661
—
MHz
ns
Tck
SCK clock period
TDVO
TDHO
TCSS
TCSH
Output data valid time
Output data hold time
Chip select output setup time
Chip select output hold time
1
ns
—
ns
3 x TCK - 1
3 x TCK + 2
—
ns
—
ns
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
NOTE
T
and T
are configured by the FlexSPIn_FLSHAxCR1 register, the
CSS
CSH
default values are shown above. Please refer to the i.MXRT1170 Reference
Manual (IMXRT1170RM) for more details.
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SCK
CS
TCSH
T
CSS
T
CK
TDVO
TDVO
SIO[0:7]
TDHO
TDHO
Figure 25. FlexSPI output timing in SDR mode
4.5.2.2.2
DDR mode
Table 60. FlexSPI output timing in DDR mode
Symbol
Parameter
Min
Max
Unit
MHz
Frequency of operation1
—
166
—
Tck
SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
Output data valid time
6.0
—
ns
ns
ns
ns
ns
TDVO
TDHO
TCSS
2.2
—
Output data hold time
0.8
Chip select output setup time
Chip select output hold time
3 x TCK / 2 - 0.7
—
TCSH
3 x TCK / 2 + 0.8 —
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
NOTE
T
and T
are configured by the FlexSPIn_FLSHAxCR1 register, the
CSS
CSH
default values are shown above. Please refer to the i.MXRT1170 Reference
Manual (IMXRT1170RM) for more details.
SCK
CS
T
CSS
T
CK
TCSH
TDVO
TDVO
SIO[0:7]
TDHO
TDHO
Figure 26. FlexSPI output timing in DDR mode
4.6
Display and graphics
The following sections provide information about display and graphic interfaces.
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4.6.1
MIPI D-PHY electrical characteristics
The i.MX RT1170 conforms to the MIPI CSI-2 and D-PHY standards for protocol and electrical
specifications.
Compliant with standards:
•
•
•
MIPI Alliance Specification for Display Serial Interface Version 1.1 (MIPI DSI controller)
MIPI Standard 1.1 for D-PHY (MIPI DSI D-PHY)
Compatible with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) Version 1.1
4.6.1.1
MIPI HS-TX specifications
Table 61. MIPI high-speed transmitter DC specifications
Symbol
Parameter
Min
Typ
Max
Unit
1
VCMTX
High Speed Transmit Static Common Mode Voltage
VCMTX mismatch when Output is Differential-1 or Differential-0
High Speed Transmit Differential Voltage
150
—
200
—
250
5
mV
mV
mV
mV
mV
|VCMTX (1,0)
|
1
|VOD
|
140
—
200
—
270
14
|VOD
|
VOD mismatch when Output is Differential-1 or Differential-0
High Speed Output High Voltage
1
VOHHS
ZOS
—
—
360
62.5
10
Single Ended Output Impedance
40
—
50
—
ZOS
Single Ended Output Impedance Mismatch
%
1
Value when driving into load impedance anywhere in the ZID (Differential input impedance) range.
Table 62. MIPI high-speed transmitter AC specifications
Symbol
Parameter
Min
Typ
Max
Unit
VCMTX(HF)
VCMTX(LF)
Common-level variations above 450 MHz
Common-level variation between 50-450 MHz
Rise Time and Fall Time (20% to 80%)
—
—
—
—
—
15
25
mVRMS
mVPEAK
ps
1
tR and tF
150
0.3 x UI
1
UI is the long-term average unit interval.
4.6.1.2
MIPI LP-TX specifications
Table 63. MIPI low-power transmitter DC specifications
Symbol
Parameter
Thevenin Output High Level
Min
Typ
Max
Unit
1
VOH
1.1
-50
110
1.2
—
1.3
50
—
V
mV
VOL
Thevenin Output Low Level
2
ZOLP
Output Impedance of Low Power Transmitter
—
1
This specification can only be met when limiting the core supply variation from 1.1 V to 1.3 V.
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2
Though there is no specified maximum for ZOLP, the LP transmitter output impedance ensures the TRLP/TFLP specification is
met.
Table 64. MIPI low-power transmitter AC specifications
Symbol
Parameter
Min
Typ
Max
Unit
1
TRLP /TFLP
15% to 85% Rise Time and Fall Time
30% to 85% Rise Time and Fall Time
—
—
40
—
—
—
25
35
—
ns
ns
ns
1,2,3
TREOT
TLP-PULSE-TX
4
Pulse width of the LP exclusive-OR clock: First LP exclusive-OR
clock pulse after Stop state or last pulse before Stop state
Pulse width of the LP exclusive-OR clock: All other pulses
Period of the LP exclusive-OR clock
Slew Rate @ CLOAD = 0 pF
20
90
30
30
30
30
0
—
—
—
—
—
—
—
—
—
ns
TLP-PER-TX
ns
1,5,6,7
V/tSR
500
200
150
100
70
mV/ns
mV/ns
mV/ns
mV/ns
pF
Slew Rate @ CLOAD = 5 pF
Slew Rate @ CLOAD = 20 pF
Slew Rate @ CLOAD = 70 pF
1
CLOAD
Load Capacitance
1
2
CLOAD includes the low equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be
< 10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2 ns delay.
The rise-time of TREOT starts from the HS common-level at the moment of the differential amplitude drops below 70 mV, due
to stopping of the differential drive.
3
4
With an additional load capacitance CCM between 0 to 60 pF on the termination center tap at RX side of the lane.
This parameter value can be lower than TLPX (MIPI D-PHY low power states), due to differences in rise vs. fall signal slopes,
trip levels, and mismatches between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT
(transition from HS level to LP-11) is glitch behavior as described in Low-Power Receiver section.
5
6
7
When the output voltage is between 15% and 85% of the fully settled LP signal levels.
Measured as average across any 50 mV segment of the output signal transition.
This value represents a corner point in a piecewise linear curve.
4.6.1.3
MIPI LP-RX specifications
Table 65. MIPI low power receiver DC specifications
Symbol
Parameter
Min
Typ
Max
Unit
VIH
VIL
Logic 1 input voltage
880
—
—
—
—
—
1300
550
300
—
mV
mV
mV
mV
Logic 0 input voltage, not in ULP state
Logic 0 input voltage, ULP state
Input hysteresis
VIL-ULPS
VHYST
—
25
Table 66. MIPI low power receiver AC specifications
Symbol
Parameter
Min
Typ
Max
Unit
1,2
eSPIKE
Input pulse rejection
—
—
300
V.ps
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Table 66. MIPI low power receiver AC specifications (continued)
3
TMIN-RX
VINT
Minimum pulse width response
20
—
—
—
—
—
200
—
ns
mV
Peak Interference amplitude
Interference frequency
fINT
450
MHz
1
2
3
Time-voltage integration of a spike above VIL when being in LP-0 state or below VIH when being in LP-1 state.
An impulse below this value will not change the receiver state.
An input pulse greater than this value will toggle the output.
4.6.1.4
MIPI LP-CD specifications
Table 67. MIPI contention detector DC specifications
Symbol
Parameter
Min
Typ
Max
Unit
VIHCD
VILCD
Logic 1 contention threshold
Logic 0 contention threshold
450
—
—
—
—
mV
mV
200
4.6.1.5
MIPI DC specifications
Table 68. MIPI input characteristics DC specifications
Symbol
Parameter
Min
Typ
Max
Unit
VPIN
Pad signal voltage range
Pin leakage current
Ground shift
-50
-10
—
—
—
—
—
1350
10
mV
A
mV
V
1
ILEAK
VGNDSH
-50
50
2
VPIN(absmax)
Maximum pin voltage level
-0.15
—
1.45
20
3
TVPIN(absmax)
Maximum transient time above VPIN(max) or below VPIN(min)
ns
1
When the pad voltage is within the signal voltage range between VGNDSH(min) to VOH + VGNDSH(max) and the Lane Module is
in LP receive mode.
2
3
This value includes ground shift.
The voltage overshoot and undershoot beyond the VPIN is only allowed during a single 20 ns window after any LP-0 to LP-1
transition or vice versa. For all other situations it must stay within the VPIN range.
4.6.2
CMOS Sensor Interface (CSI) timing parameters
The following sections describe the CSI timing in gated and ungated clock modes.
4.6.2.1 Gated clock mode timing
Figure 27 and Figure 28 shows the gated clock mode timings for CSI, and Table 69 describes the timing
parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC
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(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,
CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P5 P6
CSI_PIXCLK
P3 P4
CSI_DATA[23:00]
Figure 27. CSI Gated clock mode—sensor data at falling edge, latch data at rising edge
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P6 P5
CSI_PIXCLK
P3 P4
CSI_DATA[23:00]
Figure 28. CSI Gated clock mode—sensor data at rising edge, latch data at falling edge
Table 69. CSI gated clock mode timing parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
P2
P3
CSI_VSYNC to CSI_HSYNC time
CSI_HSYNC setup time
CSI DATA setup time
tV2H
tHsu
tDsu
33.5
2.6
—
—
—
ns
ns
ns
2.6
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Table 69. CSI gated clock mode timing parameters (continued)
ID
Parameter
CSI DATA hold time
CSI pixel clock high time
Symbol
Min.
Max.
Units
P4
P5
P6
P7
tDh
0
—
—
—
80
ns
ns
tCLKh
tCLKl
fCLK
3.75
3.75
—
CSI pixel clock low time
CSI pixel clock frequency
ns
MHz
4.6.2.2
Ungated clock mode timing
Figure 29 shows the ungated clock mode timings of CSI, and Table 70 describes the timing parameters
(P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are
used, and the CSI_HSYNC signal is ignored.
CSI_VSYNC
P1
P6
P4 P5
CSI_PIXCLK
P2 P3
CSI_DATA[23:00]
Figure 29. CSI ungated clock mode—sensor data at falling edge, latch data at rising edge
Table 70. CSI ungated clock mode timing parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
P2
P3
P4
P5
P6
CSI_VSYNC to pixel clock time
CSI DATA setup time
tVSYNC
tDsu
33.5
2.6
0
—
—
—
—
—
80
ns
ns
CSI DATA hold time
tDh
ns
CSI pixel clock high time
CSI pixel clock low time
CSI pixel clock frequency
tCLKh
tCLKl
fCLK
3.75
3.75
—
ns
ns
MHz
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
•
Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
•
Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
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4.6.3
LCD Controller timing parameters
Figure 30 shows the LCD timing and Table 71 lists the timing parameters.
L1
L2
L3
LCDn_CLK
(falling edge capture)
LCDn_CLK
(rising edge capture)
LCDn_DATA[23:00]
LCDn Control Signals
L4
L5
L6
L7
Figure 30. LCD timing
Table 71. LCD timing parameters
Parameter
ID
Symbol
Min
Max
Unit
L1
L2
L3
L4
L5
L6
L7
LCD pixel clock frequency
tCLK(LCD)
tCLKH(LCD)
tCLKL(LCD)
td(CLKH-DV)
td(CLKL-DV)
—
3
75/1501 MHz
LCD pixel clock high (falling edge capture)
—
—
1
ns
ns
ns
ns
ns
ns
LCD pixel clock low (rising edge capture)
3
LCD pixel clock high to data valid (falling edge capture)
LCD pixel clock low to data valid (rising edge capture)
-1
-1
-1
-1
1
LCD pixel clock high to control signal valid (falling edge capture) td(CLKH-CTRLV)
LCD pixel clock low to control signal valid (rising edge capture) td(CLKL-CTRLV)
1
1
1
For eLCDIF or LCDIFv2, the maximum pixel clock frequency of parallel IO interface is 75 MHz, while it is 150 MHz for MIPI
DSI interface.
4.7
Audio
This section provides information about SAI/I2S.
4.7.1
SAI/I2S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
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Num
Table 72. Master mode SAI timing
Characteristic Min
Max
Unit
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
SAI_MCLK cycle time
15
40%
40
40%
—
—
ns
SAI_MCLK pulse width high/low
SAI_BCLK cycle time
60%
—
MCLK period
ns
SAI_BCLK pulse width high/low
SAI_BCLK to SAI_FS output valid
SAI_BCLK to SAI_FS output invalid
SAI_BCLK to SAI_TXD valid
60%
8.4
—
BCLK period
ns
ns
ns
ns
ns
ns
0
—
10
SAI_BCLK to SAI_TXD invalid
1
—
SAI_RXD/SAI_FS input setup before SAI_BCLK
SAI_RXD/SAI_FS input hold after SAI_BCLK
14
0
—
—
Figure 31. SAI timing—Master modes
Table 73. Slave mode SAI timing
Num
Characteristic
SAI_BCLK cycle time (input)
Min
Max
Unit
S11
S12
S13
S14
S15
S16
40
40%
6
—
ns
SAI_BCLK pulse width high/low (input)
SAI_FS input setup before SAI_BCLK
SAI_FA input hold after SAI_BCLK
60%
—
BCLK period
ns
ns
ns
ns
2
—
SAI_BCLK to SAI_TXD/SAI_FS output valid
SAI_BCLK to SAI_TXD/SAI_FS output invalid
—
20
—
-1.5
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Electrical characteristics
Table 73. Slave mode SAI timing
Characteristic Min
Num
Max
Unit
S17
S18
SAI_RXD setup before SAI_BCLK
SAI_RXD hold after SAI_BCLK
6
2
—
—
ns
ns
Figure 32. SAI timing—Slave mode
4.8
Analog
The following sections provide information about analog interfaces.
4.8.1
12-bit ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
1
Table 74. ADC electrical specifications (VREFH = VDD_ANA_18 and VADIN
≤ VREFH)
max
Symbol
VADIN
Description
Input voltage
Min
VREFL
Typ
Max
VREFH
Unit
Notes
—
V
V
—
—
VREFH
ADC high reference supply
input
1.0
1.8
1.89
CADIN
RADIN
RAS
Input capacitance
—
—
—
8
4.5
500
—
—
—
5
pF
—
Input resistance
—
2
Analog source resistance
K
MHz
fADCK
ADC conversion clock
frequency
—
88
—
3
Csample
Sample cycles
3.5
—
—
131.5
—
Cycles
Cycles
Cycles
Ccompare
Cconversion
Fixed compare cycles
Conversion cycles
17.5
—
—
Cconversion = Csample + Ccompare
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Electrical characteristics
Table 74. ADC electrical specifications (VREFH = VDD_ANA_18 and VADIN
1
≤ VREFH) (continued)
max
Symbol
TUE
Description
Min
Typ
Max
Unit
Notes
4
Total unadjusted Error
Differential nonlinearity
Integral nonlinearity
Effective number of bits
Single-ended mode
Avg = 1
—
—
—
-14 to -2
±1.2
—
—
—
LSB
4,5
4,5
6
DNL
INL
LSB
LSB
±1.2
ENOB
—
—
—
10.3
10.6
11.3
—
—
—
—
—
—
Avg = 2
Avg = 16
Differential mode
Avg = 1
—
—
—
11.2
—
—
—
—
—
Avg = 2
—
Avg = 16
—
—
SINAD
EFS
Signal to noise plus distortion SINAD = 6.02 x ENOB + 1.76
dB
LSB
LSB
nA
—
4
Full-scale error
Zero-scale error
—
—
—
-4
—
4
EZS
0.05
30
—
lin_ext_leak
External channel leakage
current
500
—
EIL
Input leakage error
Setup time
RAS * lin_ext_leak
—
mV
—
—
tADCSETUP
5
—
s
1
The range is from 1.71 V to 1.89 V.
2
This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS and
CAS time constant should be kept to < 1 ns.
3
4
5
6
See Figure 33, "Sample time VS. RAS".
1 LSB = (VREFH - VREFL) / 2^N, N = 12
ADC conversion clock at max frequency and using linear histogram.
Input data used for test is 1 kHz sine wave.
Table 75. ADC electrical specifications (VREFFH = 1.68 V and VADIN
≤ NVCC_GPIO
)
max
max
Symbol
VADIN
Description
Input voltage
Min
VREFL
Typ1
Max
Unit
Notes
—
NVCC_GPIOmax
1.89
V
V
—
—
VREFH
ADC high reference supply
input
1.0
1.8
CADIN
RADIN
RAS
Input capacitance
—
—
—
4.5
1
—
—
5
pF
—
Input resistance
K
K
—
2
Analog source resistance
—
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 75. ADC electrical specifications (VREFFH = 1.68 V and VADIN
≤ NVCC_GPIO
) (continued)
max
max
Symbol
fADCK
Description
Min
Typ1
Max
Unit
Notes
ADC conversion clock
frequency
8
—
88
MHz
—
3
Csample
Ccompare
Cconversion
TUE
Sample cycles
Fixed compare cycles
Conversion cycles
Total unadjusted Error
Differential nonlinearity
Integral nonlinearity
Effective number of bits
Single-ended mode
Avg = 1
3.5
—
—
131.5
—
Cycles
Cycles
Cycles
LSB
17.5
—
Cconversion = Csample + Ccompare
—
4
—
—
—
-14 to -2
±1.2
—
—
—
4,5
4,5
6
DNL
LSB
INL
±1.2
LSB
ENOB
—
—
—
10.3
10.6
11.3
—
—
—
—
—
—
Avg = 2
Avg = 16
Differential mode
Avg = 1
—
—
—
11.2
—
—
—
—
—
Avg = 2
—
Avg = 16
—
—
SINAD
EFS
Signal to noise plus distortion SINAD = 6.02 x ENOB + 1.76
dB
LSB
LSB
nA
—
4
Full-scale error
Zero-scale error
—
—
—
-4
—
4
EZS
0.05
30
—
lin_ext_leak
External channel leakage
current
500
—
EIL
Input leakage error
Setup time
RAS * lin_ext_leak
—
mV
—
—
tADCSETUP
5
—
s
1
Typical values assume Temp = 25 °C and fACLK = Max, unless otherwise stated. Typical values are for reference only, and are
not tested in production.
2
This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS and
CAS time constant should be kept to < 1 ns.
3
4
5
6
See Figure 33, "Sample time VS. RAS".
1 LSB = (VREFH - VREFL) / 2^N, N = 12
ADC conversion clock at max frequency and using linear histogram.
Input data used for test is 1 kHz sine wave.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
1
2
Table 76. ADC electrical specifications (1 V ≤ VREFFH < VDD_ANA_18
and VADIN
≤ VREFH)
max
min
Symbol
VADIN
Description
Input voltage
Min
VREFL
Typ3
Max
VREFH
Unit
Notes
—
V
V
—
—
VREFH
ADC high reference supply
input
1.0
1.8
1.89
CADIN
RADIN
RAS
Input capacitance
—
—
—
8
4.5
500
—
—
—
5
pF
—
Input resistance
—
4
Analog source resistance
K
MHz
fADCK
ADC conversion clock
frequency
—
88
—
5
Csample
Ccompare
Cconversion
TUE
Sample cycles
Fixed compare cycles
Conversion cycles
Total unadjusted Error
Differential nonlinearity
Integral nonlinearity
Effective number of bits
Single-ended mode
Avg = 1
3.5
—
—
131.5
—
Cycles
Cycles
Cycles
LSB
17.5
—
Cconversion = Csample + Ccompare
—
6
—
—
—
-14 to -2
±1.2
—
—
—
6,7
6,7
8
DNL
LSB
INL
±1.2
LSB
ENOB
—
—
—
10.3
10.6
11.3
—
—
—
—
—
—
Avg = 2
Avg = 16
Differential mode
Avg = 1
—
—
—
11.2
—
—
—
—
—
Avg = 2
—
Avg = 16
—
—
SINAD
EFS
Signal to noise plus distortion SINAD = 6.02 x ENOB + 1.76
dB
LSB
LSB
nA
—
6
Full-scale error
Zero-scale error
—
—
—
-4
—
6
EZS
0.05
30
—
lin_ext_leak
External channel leakage
current
500
—
EIL
Input leakage error
Setup time
RAS * lin_ext_leak
—
mV
—
—
tADCSETUP
5
—
s
1
VDD_ANA_18min = 1.71 V
2
3
Values in this table are based on design simulations.
Typical values assume Temp = 25 °C and fACLK = Max, unless otherwise stated. Typical values are for reference only, and are
not tested in production.
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Electrical characteristics
4
This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS and
C
AS time constant should be kept to < 1 ns.
5
6
7
8
See Figure 33, "Sample time VS. RAS".
1 LSB = (VREFH - VREFL) / 2^N, N = 12
ADC conversion clock at max frequency and using linear histogram.
Input data used for test is 1 kHz sine wave.
The following figure shows a plot of the ADC sample time versus R .
AS
Figure 33. Sample time VS. R
AS
4.8.1.1
12-bit ADC input impedance equivalent circuit diagram
The following figure shows 12-bit ADC input impedance equivalent circuit diagram.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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81
Electrical characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
ADC SAR
ENGINE
R
AS
R
ADIN
VADIN
C
AS
VAS
R
R
R
ADIN
ADIN
ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C
ADIN
Figure 34. ADC input impedance equivalent circuit diagram
4.8.2
12-bit DAC electrical characteristics
12-bit DAC operating requirements
4.8.2.1
Table 77. 12-bit DAC operating conditions
Symbol
Description
Min Typ Max
Unit
Notes
1
2
CL
IL
Output load capacitance
Output load current
—
—
50
—
100
1
pF
mA
1
The DAC output can drive R and C loading. The user should consider both DC and dynamic application requirements. 50 pF
CL provides the best dynamic performance, while 100 pF provides the best DC performance.
2
Sink or source current ability.
Table 78. DAC characteristics
Symbol
Description
Test Conditions
Min
VSS
Typ
Max
0.15
Unit
Notes
1
VDACOUTL DAC low level output
voltage
ADC_VREFH selected,
Rload = 18 k, Cload = 50
pF
—
V
V
VDACOUTH DAC high level output
voltage
VDDA_AD —
C_1P8 -
0.15
VDDA_AD
C_1P8
DNL
Differential nonlinearity
error
Code 100h — F00h best fit —
curve
±0.5
±1
LSB
—
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 78. DAC characteristics (continued)
Test Conditions Min Typ
Symbol
INL
Description
Max
Unit
LSB
Notes
2
Integral nonlinearity error Code 100h — F00h best fit
curve
—
—
—
±1
±2
—
—
—
3
LSB
EO
Offset error
Code 100h
±0.6
%FSR
(Full-sc
ale
—
range)
TEO
Offset error temperature Code 100h
coefficient
—
±30
—
V/oC
—
EG
Gain error
Code F00h
Code F00h
—
—
±0.4
±10
—
—
%FSR
—
—
TEG
Gain error temperature
coefficient
ppm of
FSR/oC
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 78. DAC characteristics (continued)
Symbol
TFS_LS
Description
Test Conditions
Min
Typ
Max
Unit
s
Notes
4
Full scale setting time in Code 100h — F00h or
Low Speed mode
—
—
—
—
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
—
—
—
—
—
F00h — 100h @ZTC
current
Code 100h — F00h or
F00h —100h @PTAT
current
5
TFS_MS
TFS_HS
TCC_LS
TCC_MS
TCC_HS
Full scale setting time in Code 100h — F00h or
Middle Speed mode
1
F00h — 100h @ZTC
current
Code 100h — F00h or
F00h — 100h @PTAT
current
1
Full scale setting time in Code 100h — F00h or
High Speed mode
0.5
0.5
1
F00h — 100h @ZTC
current
Code 100h — F00h or
F00h — 100h @PTAT
current
Code to code setting
time in Low Speed mode 807h — 7F7h @ZTC
current
Code 7F7h — 807h or
Code 7F7h — 807h or
807h — 7F7h @PTAT
current
1
Code to code setting
time in Middle Speed
mode
Code 7F7h — 807h or
807h — 7F7h @ZTC
current
0.5
0.5
0.3
0.3
Code 7F7h — 807h or
807h — 7F7h @PTAT
current
Code to code setting
time in Middle Speed
mode
Code 7F7h — 807h or
807h — 7F7h @ZTC
current
Code 7F7h — 807h or
807h — 7F7h @PTAT
current
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Electrical characteristics
Table 78. DAC characteristics (continued)
Test Conditions Min Typ
Slew rate in Low Speed Code 100h — F00h or 0.24
Symbol
SR_LS
Description
Max
Unit
V/s
Notes
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
mode
F00h — 100h @ZTC
current
Code 100h — F00h or
F00h —100h @PTAT
current
0.24
1.2
1.2
2.4
2.4
70
SR_MS
SR_HS
Slew rate in Middle
Speed mode
Code 100h — F00h or
F00h — 100h @ZTC
current
Code 100h — F00h or
F00h —100h @PTAT
current
Slew rate in High Speed Code 100h — F00h or
mode
F00h — 100h @ZTC
current
Code 100h — F00h or
F00h —100h @PTAT
current
6
PSRR
Glitch
Power supply rejection
ratio
Code 800h,
ΔVDD_ANA18 = 100 mV,
VREFH_ANA12 selected
dB
Glitch energy
Code 100h — F00h —
100h
—
—
—
—
30
30
—
—
nV-s
—
Code 7FFh — 800h —
7FFh
—
7
8
CT
Channel to channel
crosstalk
—
-80
—
dB
ROP
Output resistance
Code 100h — F00h and
200
Rload = 18 k
1
It is recommended to operate the DAC in the output voltage range between 0.15 V and (VDDA_ADC_1P8 - 0.15 V) for best
accuracy. Linearity of the output voltage outside this range will be affected as current load increases.
2
3
4
When ADC_VREFH is selected as the reference (DAC_CR[DACRFS] = 0b).
When the internal 1.2 V source is selected as the reference (DAC_CR[DACRFS] = 1b).
The DAC output remains within ±0.5 LSB of the final measured value for digital input code change. Noise on the power supply
can cause this performance to degrade to ±1 LSB. This parameter represents both rising edge and falling edge settling time.
5
6
7
8
Time for the DAC output to transition from 10% to 90% signal amplitude (rising edge or falling edge).
PSRR = 20 x log{ΔVDD_ANA18 /ΔVDAC_OUT}
If two DACs are used and sharing the same VREFH.
Based on design simulation.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
4.8.3
ACMP electrical specifications
Table 79. ACMP operating conditions
Symbol
Description
Min
Typ
Max
Unit
VREFH_EXT
VREFH_INT1
External reference voltage
Internal reference voltage
1
—
1.98
—
V
V
—
1.3
1
This is an internal reference voltage generated by PMC0.
Table 80. ACMP characteristics
Condition Min
Symbol
VAIN
Description
Typ
Max
Unit
Analog input voltage
—
—
0
—
—
NVCC_GPIO1
20
V
VAIO
Analog input offset
voltage
—
mV
VH
Analog comparator
hysteresis
Hystrl[1:0] = 00
Hystrl[1:0] = 01
Hystrl[1:0] = 10
Hystrl[1:0] = 11
Normal supply
—
—
—
—
—
5
—
—
—
—
50
mV
mV
mV
mV
ns
10
20
30
—
TDHS
TDHS
—
Propagation delay,
high-speed mode
Propagation delay,
low-speed mode
—
—
—
—
—
—
-1
-1
—
—
—
—
5
s
Analog comparator
initialization delay
20
1
s
INL
8-bit DAC integral
non-linearity
LSB
LSB
DNL
8-bit DAC differential
non-linearity
1
1
The maximum input voltage for CMP analog inputs associated with GPIO_AD bank is NVCC_GPIO.
4.8.4
Temperature sensor
Table 81 lists the parameters of temperature sensor.
Table 81. Temperature sensor parameters
Parameter
Min
Max
Unit
C
Temperature range1
-40
125
1
Accuracy of measurement: ± 5C for 25C and above, while ± 10C for below 25C.
4.9
Communication interfaces
The following sections provide the information about communication interfaces.
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Electrical characteristics
4.9.1
LPSPI timing parameters
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables provide timing
characteristics for classic LPSPI timing modes.
All timing is shown with respect to 20% V and 80% V thresholds, unless noted, as well as input
DD
DD
signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.
Table 82. LPSPI Master mode timing
Number
Symbol
Description
Frequency of operation
Min.
Max.
Units
Note
1
1
2
3
4
5
6
7
8
9
fSCK
tSCK
tLead
tLag
tWSCK
tSU
—
fperiph / 2
MHz
ns
2
SCK period
2 x tperiph
—
—
—
—
—
—
8
Enable lead time
1
tperiph
tperiph
ns
—
—
—
—
—
—
—
Enable lag time
1
Clock (SCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SCK edge)
Data hold time (outputs)
tSCK / 2 - 3
10
2
ns
tHI
ns
tV
—
0
ns
tHO
—
ns
1
2
Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must guaranteed
this limit is not exceeded.
tperiph = 1000 / fperiph
1
PCS
(OUTPUT)
3
2
4
SCK
(CPOL=0)
(OUTPUT)
5
5
SCK
(CPOL=1)
(OUTPUT)
6
7
SIN
(INPUT)
2
LSB IN
BIT 6 . . . 1
MSB IN
8
9
SOUT
(OUTPUT)
2
MSB OUT
BIT 6 . . . 1
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 35. LPSPI Master mode timing (CPHA = 0)
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Electrical characteristics
1
PCS
(OUTPUT)
2
4
3
SCK
(CPOL=0)
(OUTPUT)
5
5
SCK
(CPOL=1)
(OUTPUT)
6
7
SIN
(INPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
9
8
SOUT
(OUTPUT)
PORT DATA
BIT 6 . . . 1
PORT DATA
MASTER MSB OUT
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 36. LPSPI Master mode timing (CPHA = 1)
s
Table 83. LPSPI Slave mode timing
Number
Symbol
Description
Frequency of operation
Min.
Max.
Units
Note
1
1
2
fSCK
tSCK
tLead
tLag
tWSCK
tSU
0
fperiph / 2
—
MHz
ns
2
SCK period
2 x tperiph
3
Enable lead time
1
—
tperiph
tperiph
ns
—
—
—
—
4
Enable lag time
1
—
5
Clock (SCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time
tSCK / 2 - 5
—
6
2.7
3.8
—
—
—
0
—
ns
7
tHI
—
ns
—
3
8
ta
tperiph
tperiph
14.5
—
ns
4
9
tdis
Slave MISO disable time
Data valid (after SCK edge)
Data hold time (outputs)
ns
10
11
tV
ns
—
—
tHO
ns
1
Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be
guaranteed this limit is not exceeded.
2
3
4
tperiph = 1000 / fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
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Electrical characteristics
PCS
(INPUT)
2
4
SCK
(CPOL=0)
(INPUT)
5
5
3
SCK
(CPOL=1)
(INPUT)
9
8
10
BIT 6 . . . 1
11
11
see
note
SEE
NOTE
SIN
(OUTPUT)
SLAVE MSB
7
SLAVE LSB OUT
6
SOUT
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 37. LPSPI Slave mode timing (CPHA = 0)
PCS
(INPUT)
4
2
3
SCK
(CPOL=0)
(INPUT)
5
5
SCK
(CPOL=1)
(INPUT)
11
BIT 6 . . . 1
9
10
see
SIN
SLAVE MSB OUT
SLAVE LSB OUT
LSB IN
note
(OUTPUT)
8
6
7
SOUT
(INPUT)
BIT 6 . . . 1
MSB IN
Figure 38. LPSPI Slave mode timing (CPHA = 1)
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89
Electrical characteristics
4.9.2
LPI2C module timing parameters
This section describes the timing parameters of the LPI2C module.
Table 84. LPI2C module timing parameters
Symbol
Description
Standard mode (Sm)
Min
Max
100
Unit
Notes
1
fSCL
SCL clock frequency
0
0
0
0
0
kHz
Fast mode (Fm)
400
Fast mode Plus (Fm+)
High speed mode (Hs-mode)
Ultra Fast mode (UFm)
1000
3400
5000
1
Hs-mode and Ultra Fast mode are supported in slave mode.
4.9.3
Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD3.0 (Single Data Rate)
timing and eMMC5.0 (up to 200 MHz) timing.
4.9.3.1
SD3.0/eMMC4.3 (Single Data Rate) specifications
Figure 39 depicts the timing of SD3.0/eMMC4.3, and Table 85 lists the SD/eMMC4.3 timing
characteristics.
SD4
SD2
SD1
SD5
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure 39. SD/eMMC4.3 timing
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Electrical characteristics
Table 85. SD/eMMC4.3 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
1
SD1 Clock Frequency (Low Speed)
fPP
0
0
400
25/50
20/52
400
—
kHz
MHz
MHz
kHz
ns
2
Clock Frequency (SD/SDIO Full Speed/High Speed)
Clock Frequency (MMC Full Speed/High Speed)
Clock Frequency (Identification Mode)
fPP
3
fPP
0
fOD
tWL
100
7
SD2 Clock Low Time
SD3 Clock High Time
SD4 Clock Rise Time
SD5 Clock Fall Time
tWH
tTLH
tTHL
7
—
ns
—
—
3
ns
3
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6 uSDHC Output Delay tOD -6.6
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
3.6
ns
SD7 uSDHC Input Setup Time
SD8 uSDHC Input Hold Time4
tISU
tIH
2.5
1.5
—
—
ns
ns
1
2
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3
4
In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4.9.3.2
eMMC4.4/4.41/SD3.0 (Dual Data Rate) AC timing)
Figure 40 depicts the timing of eMMC4.4/4.41/SD3.0. Table 86 lists the eMMC4.4/4.41/SD3.0 timing
characteristics. Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).
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Electrical characteristics
SD1
SDx_CLK
SD2
SD2
Output from eSDHCv3 to card
SDx_DATA[7:0]
......
......
SD3
SD4
Input from card to eSDHCv3
SDx_DATA[7:0]
Figure 40. eMMC4.4/4.41/SD3.0 timing
Table 86. eMMC4.4/4.41/SD3.0 interface timing specification
ID
Parameter
Symbols
Card Input Clock
Min
Max
Unit
SD1
SD1
Clock Frequency (eMMC4.4/4.41 DDR)
Clock Frequency (SD3.0 DDR)
fPP
fPP
0
0
52
50
MHz
MHz
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
uSDHC Output Delay tOD 2.8
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2
6.8
ns
SD3
SD4
uSDHC Input Setup Time
uSDHC Input Hold Time
tISU
tIH
2.4
1.2
—
—
ns
ns
4.9.3.3
SDR50/SDR104 AC timing
Figure 41 depicts the timing of SDR50/SDR104, and Table 87 lists the SDR50/SDR104 timing
characteristics.
SD1
SD2
SD3
SCK
4-bit output from uSDHC to card
4-bit input from card to uSDHC
SD4/SD5
SD6
SD7
SD8
Figure 41. SDR50/SDR104 timing
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Electrical characteristics
Table 87. SDR50/SDR104 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
SD2
SD3
Clock Frequency Period
tCLK
tCL
5.0
—
ns
ns
ns
Clock Low Time
Clock High Time
0.46 x tCLK
0.46 x tCLK
0.54 x tCLK
0.54 x tCLK
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
uSDHC Output Delay tOD –3
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
uSDHC Output Delay tOD –1.6
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4
SD5
1
ns
ns
1
uSDHC Input Setup Time
uSDHC Input Hold Time
tISU
tIH
2.5
1.5
—
—
ns
ns
SD6
SD7
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
Card Output Data Window tODW 0.5 x tCLK
—
ns
SD8
1Data window in SDR104 mode is variable.
4.9.3.4
HS200 mode timing
Figure 42 depicts the timing of HS200 mode, and Table 88 lists the HS200 timing characteristics.
SD1
SD2
SD3
SCK
SD5
8-bit output from uSDHC to eMMC
8-bit input from eMMC to uSDHC
SD8
Figure 42. HS200 mode timing
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Electrical characteristics
Table 88. HS200 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
SD2
SD3
Clock Frequency Period
tCLK
tCL
5.0
—
ns
ns
ns
Clock Low Time
Clock High Time
0.46 x tCLK
0.46 x tCLK
0.54 x tCLK
0.54 x tCLK
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
uSDHC Output Delay tOD –1.6 0.74
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
Card Output Data Window tODW 0.5 x tCLK
ns
ns
SD5
—
SD8
1HS200 is for 8 bits while SDR104 is for 4 bits.
4.9.3.5
HS400 specifications - eMMC 5.0 only
Be aware that only data are sampled on both edges of the clock (not applicable to CMD). The CMD
input/output timing for HS400 mode is the same as CMD input/output timing for HS200 mode. Check SD5
and SD8 parameters in the HS200 interface timing specifications table for CMD input/output timing of
HS400 mode.
Table 88 lists the HS400 timing characteristics.
Table 89. HS400 interface timing specification
Symbol
Description
Min
Max
Unit
Operating voltage
1.71
1.95
V
Card input clock
Clock frequency
Clock period
0
200
—
MHz
ns
SD1
SD2
SD3
5.0
Clock Low time
Clock High time
0.46 x SD1
0.46 x SD1
0.54 x SD1
0.54 x SD1
ns
ns
SDHC output / card Inputs SDHC_CMD, SDHC_Dn (reference to SDHC_CLK)
Output skew from data to edge of SCK
Output skew from edge of SCK to data
0.45
0.45
—
—
ns
ns
SD4
SD5
SDHC input / card outputs (reference to strobe)
SDHC input skew
SDHC hold skew
—
—
0.45
0.45
ns
ns
SD6
SD7
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Electrical characteristics
Figure 42 depicts the timing of HS400.
SD1
SD3
SD2
SCK
SD4
SD5
SD5
SD4
DAT0
Output from
uSDHC to eMMC
DAT1
...
DAT7
Strobe
DAT0
SD6
SD7
Input from
eMMC to uSDHC
DAT1
...
DAT7
Figure 43. HS400 timing
4.9.3.6
Bus operation condition for 3.3 V and 1.8 V signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of
SDR104/SDR50/HS200/HS400 mode is 1.8 V.
4.9.4
Ethernet controller (ENET) AC electrical specifications
ENET MII mode timing
4.9.4.1
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
4.9.4.1.1
MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER, and ENET_RX_CLK)
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET_RX_CLK frequency.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Figure 44 shows MII receive signal timings. Table 90 describes the timing parameters (M1–M4) shown in
the figure.
M3
ENET_RX_CLK (input)
M4
ENET_RX_DATA3,2,1,0
(inputs)
ENET_RX_EN
ENET_RX_ER
M1
M2
Figure 44. MII receive signal timing diagram
Table 90. MII receive signal timing
ID
Characteristic1
Min.
Max.
Unit
M1
M2
ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
5
—
ns
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
5
—
ns
M3
M4
ENET_RX_CLK pulse width high
ENET_RX_CLK pulse width low
35%
35%
65%
65%
ENET_RX_CLK period
ENET_RX_CLK period
1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
4.9.4.1.2
MII transmit signal timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET_TX_CLK frequency.
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96
NXP Semiconductors
Electrical characteristics
Figure 45 shows MII transmit signal timings. Table 91 describes the timing parameters (M5–M8) shown
in the figure.
M7
ENET_TX_CLK (input)
M5
M8
ENET_TX_DATA3,2,1,0
(outputs)
ENET_TX_EN
ENET_TX_ER
M6
Figure 45. MII transmit signal timing diagram
Table 91. MII transmit signal timing
ID
Characteristic1
Min.
Max.
Unit
M5
M6
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER invalid
5
—
ns
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER valid
—
20
ns
M7
M8
ENET_TX_CLK pulse width high
ENET_TX_CLK pulse width low
35%
35%
65%
65%
ENET_TX_CLK period
ENET_TX_CLK period
1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
4.9.4.1.3
MII asynchronous inputs signal timing (ENET_CRS and ENET_COL)
Figure 46 shows MII asynchronous input timings. Table 92 describes the timing parameter (M9) shown in
the figure.
ENET_CRS, ENET_COL
M9
Figure 46. MII asynchronous inputs timing diagram
Table 92. MII asynchronous inputs signal timing
ID
M91
Characteristic
Min.
Max.
Unit
ENET_CRS to ENET_COL minimum pulse width
1.5
—
ENET_TX_CLK period
1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
97
Electrical characteristics
4.9.4.1.4
MII serial management channel timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 47 shows MII asynchronous input timings. Table 93 describes the timing parameters (M10–M15)
shown in the figure.
M14
M15
ENET_MDC (output)
M10
ENET_MDIO (output)
M11
ENET_MDIO (input)
M12
M13
Figure 47. MII serial management channel timing diagram
Table 93. MII serial management channel timing
ID
M10
Characteristic
Min.
Max.
Unit
ENET_MDC falling edge to ENET_MDIO output invalid (min.
propagation delay)
0
—
ns
M11
ENET_MDC falling edge to ENET_MDIO output valid (max.
propagation delay)
—
5
ns
M12
M13
M14
M15
ENET_MDIO (input) to ENET_MDC rising edge setup
ENET_MDIO (input) to ENET_MDC rising edge hold
ENET_MDC pulse width high
18
0
—
—
ns
ns
40%
40%
60%
60%
ENET_MDC period
ENET_MDC period
ENET_MDC pulse width low
4.9.4.2
RMII mode timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock.
Figure 48 shows RMII mode timings. Table 94 describes the timing parameters (M16–M21) shown in the
figure.
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NXP Semiconductors
Electrical characteristics
M16
M17
ENET_CLK (input)
M18
ENET_TX_DATA (output)
ENET_TX_EN
M19
ENET_RX_EN (input)
ENET_RX_DATA[1:0]
ENET_RX_ER
M20
M21
Figure 48. RMII mode signal timing diagram
Table 94. RMII signal timing
ID
Characteristic
Min.
Max.
Unit
M16
M17
M18
M19
M20
ENET_CLK pulse width high
ENET_CLK pulse width low
35%
35%
4
65%
65%
—
ENET_CLK period
ENET_CLK period
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid
ns
ns
ns
—
13
ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER
to ENET_CLK setup
2
—
M21
ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER
hold
2
—
ns
4.9.4.3
RGMII signal switching specifications
The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver
devices.
1
Table 95. RGMII signal switching specifications
Symbol
Description
Min.
Max.
Unit
2
Tcyc
Clock cycle duration
Data to clock output skew at transmitter
7.2
8.8
ns
ps
3
TskewT
-500
500
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
99
Electrical characteristics
1
Table 95. RGMII signal switching specifications (continued)
Symbol
Description
Data to clock input skew at receiver
Min.
Max.
Unit
3
TskewR
Duty_G4
Duty_T4
Tr/Tf
1
2.6
85
ns
%
%
ns
Duty cycle for Gigabit
Duty cycle for 10/100T
Rise/fall time (20–80%)
45
40
—
90
0.98
1
The timings assume the following configuration:
DDR_SEL = (11)b
DSE (drive-strength) = (111)b
2
3
For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns 40 ns and 40 ns 4 ns respectively.
For all versions of RGMII prior to 2.0; this implies that PC board design will require clocks to be routed such that an additional
trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value
is unspecified.
4
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long
as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned
between.
2'-))?48# ꢆAT TRANSMITTERꢇ
4SKEW4
2'-))?48$N ꢆN ꢈ ꢁ TO ꢉ ꢇ
2'-))?48?#4,
48%.
48%22
4SKEW2
2'-))?48# ꢆAT RECEIVERꢇ
Figure 49. RGMII transmit signal timing diagram
2'-))?28# ꢆAT TRANSMITTERꢇ
4SKEW4
2'-))?28$N ꢆN ꢈ ꢁ TO ꢉ ꢇ
2'-))?28?#4,
28$6
28%22
4SKEW2
2'-))?28# ꢆAT RECEIVERꢇ
Figure 50. RGMII receive signal timing diagram
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
100
NXP Semiconductors
Electrical characteristics
)NTERNAL DELAY
2'-))?28# ꢆSOURCE OF DATAꢇ
2'-))?28$N ꢆN ꢈ ꢁ TO ꢉ ꢇ
4SETUP 4
4 HOLD 4
28$6
28%22
2'-))?28?#4,
4 SETUP 2
4 HOLD 2
2'-))?28# ꢆAT RECEIVERꢇ
Figure 51. RGMII receive signal timing diagram with internal delay
4.9.4.4
Ethernet Quality-of-Service (QOS) electrical specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the physical interface.
It also supports the following Time Sensitive Networking (TSN) features:
•
•
•
802.1Qbv Enhancements to Scheduling Traffic
802.1Qbu Frame preemption
Time based Scheduling
Please refer to RGMII, RMII, and MII specifications in Section 4.9.4, Ethernet controller (ENET) AC
electrical specifications
4.9.5
Controller Area Network (CAN) AC electrical specifications
The Controller Area Network (CAN) module is a communication controller implementing the CAN
protocol according to the CAN with Flexible Data rate (CAN FD) protocol and the CAN 2.0B protocol
specification. The processor has three CAN modules available. Tx and Rx ports are multiplexed with other
I/O pins. See the IOMUXC chapter of the device reference manual to see which pins expose Tx and Rx
pins; these ports are named CAN_TX and CAN_RX, respectively.
Please refer to Section 4.3.2.1, General purpose I/O (GPIO) AC parameters.
4.9.6
LPUART electrical specifications
Please refer to Section 4.3.2.1, General purpose I/O (GPIO) AC parameters.
4.9.7
USB PHY parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
2.0 OTG with the following amendments.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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101
Electrical characteristics
•
USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0 plus errata and ecn June 4, 2010
Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
•
•
— Portable device only
4.10 Timers
This section provides information on timers.
4.10.1 Pulse Width Modulator (PWM) characteristics
This section describes the electrical information of the PWM.
Table 96. PWM timing parameters
Parameter
PWM Clock Frequency
Symbol
Typ
Max
Unit
—
—
—
—
240
2
MHz
ns
Output skew
4.10.2 Quad timer timing
Table 97 lists the quad timer parameters.
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 97. Quad timer timing
Characteristic
Timer input period
Symbo
Min1
Max
Unit
See Figure
TIN
2T + 6
1T + 3
33
—
—
—
—
ns
ns
ns
ns
Timer input high/low period
Timer output period
TINHL
TOUT
Timer output high/low period
TOUTHL
16.7
1
T = clock cycle. For 60 MHz operation, T = 16.7 ns.
4IMER )NPUTS
4
4
).(,
).(,
4
).
4IMER /UTPUTS
4
4
/54(,
/54(,
4
/54
Figure 52. Quad timer timing
4.11 SNVS
This section provides parameters of SNVS.
4.11.1 SNVS tamper
Table 98 lists the SNVS tamper specifications.
Table 98. SNVS tamper specifications
Parameters
Min Typ
Max
Unit
High Temp Tamper
Low Temp Tamper
125
-40
130
-30
135
C
C
C
V
-20
-40
2.4
4.5
1.68
2.06
25
Low Temp Tamper (Shelf mode)
Vbat LVD tamper
-60
-50
2.25
4.25
1.48
1.86
15
2.325
4.375
1.58
1.96
20
Vbat HVD tamper
V
Regulator LVD tamper
Regulator HVD tamper
V
V
kHz
kHz
Clock low freq tamper
Clock high freq tamper
40
52.5
80
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Electrical characteristics
Table 99 lists DC specifications for Tamper pin.
Table 99. DC specification for Tamper pin
Value
Parameter
Symbol
Units
Condition
Min
Typ
Max
Pull-up / pull-down resistance
RPU / RPD
—
300
—
k
—
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104
Boot mode configuration
5 Boot mode configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot mode configuration pins
Table 100 provides boot options, functionality, fuse values, and associated pins. Several input pins are
also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL
fuse. The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX RT1170
Fuse Map and the System Boot chapter in i.MX RT1170 Reference Manual (IMXRT1170RM).
Table 100. Fuses and associated pins used for boot
Pad
Default setting on reset
eFuse name
Details
GPIO_LPSR_02
35 K pull-down
35 K pull-down
HighZ
BOOT_MODE[0]
BOOT_MODE[1]
BT_CFG[0]
BT_CFG[1]
BT_CFG[2]
BT_CFG[3]
BT_CFG[4]
BT_CFG[5]
BT_CFG[6]
BT_CFG[7]
BT_CFG[8]
BT_CFG[9]
BT_CFG[10]
BT_CFG[11]
GPIO_LPSR_03
GPIO_DISP_B1_06
GPIO_DISP_B1_07
GPIO_DISP_B1_08
GPIO_DISP_B1_09
GPIO_DISP_B1_10
GPIO_DISP_B1_11
GPIO_DISP_B2_00
GPIO_DISP_B2_01
GPIO_DISP_B2_02
GPIO_DISP_B2_03
GPIO_DISP_B2_04
GPIO_DISP_B2_05
Boot Options, Pin value overrides
fuse settings for BT_FUSE_SEL = ‘0’.
Signal Configuration as Fuse
Override Input at Power Up.
These are special I/O lines that
control the boot up configuration
during product development. In
production, the boot configuration can
be controlled by fuses.
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ
5.2
Boot device interface allocation
The following tables list the interfaces that can be used by the boot process in accordance with the specific
boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 101. Boot through NAND
PAD Name
IO Function
ALT
Comments
GPIO_EMC_B1_00
GPIO_EMC_B1_01
GPIO_EMC_B2_02
semc.DATA[0]
semc.DATA[1]
semc.DATA[2]
ALT 0
ALT 0
ALT 0
—
—
—
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
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Boot mode configuration
Table 101. Boot through NAND
GPIO_EMC_B1_03
GPIO_EMC_B1_04
GPIO_EMC_B1_05
GPIO_EMC_B1_06
GPIO_EMC_B1_07
GPIO_EMC_B1_30
GPIO_EMC_B1_31
GPIO_EMC_B1_32
GPIO_EMC_B1_33
GPIO_EMC_B1_34
GPIO_EMC_B1_35
GPIO_EMC_B1_36
GPIO_EMC_B1_37
GPIO_EMC_B1_18
GPIO_EMC_B1_19
GPIO_EMC_B1_20
GPIO_EMC_B1_22
GPIO_EMC_B1_41
semc.DATA[3]
semc.DATA[4]
semc.DATA[5]
semc.DATA[6]
semc.DATA[7]
semc.DATA[8]
semc.DATA[9]
semc.DATA[10]
semc.DATA[11]
semc.DATA[12]
semc.DATA[13]
semc.DATA[14]
semc.DATA[15]
semc.ADDR[9]
semc.ADDR[11]
semc.ADDR[12]
semc.BA1
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
semc.CSX[0]
Table 102. Boot through FlexSPI1
IO Function
PAD Name
Mux Mode
Comments
GPIO_SD_B2_00
GPIO_SD_B2_01
GPIO_SD_B2_02
GPIO_SD_B2_03
GPIO_SD_B2_04
GPIO_SD_B1_05
GPIO_SD_B1_04
GPIO_SD_B1_03
GPIO_SD_B2_05
GPIO_EMC_B2_18
flexspi1.B_DATA[3]
flexspi1.B_DATA[2]
flexspi1.B_DATA[1]
flexspi1.B_DATA[0]
flexspi1.B_SCLK
flexspi1.B_DQS
ALT 1
ALT 1
ALT 1
ALT 1
ALT 1
ALT 8
ALT 8
ALT 9
ALT 1
ALT 6
—
—
—
—
—
—
—
—
—
flexspi1.B_SS0_B
flexspi1.B_SS1_B
flexspi1.A_DQS
flexspi1.A_DQS
Secondary
option for DQS
GPIO_SD_B2_06
GPIO_SD_B1_02
flexspi1.A_SS0_B
flexspi1.A_SS1_B
ALT 1
ALT 9
—
—
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
106
Boot mode configuration
Mux Mode Comments
Table 102. Boot through FlexSPI1 (continued)
PAD Name
IO Function
GPIO_SD_B2_07
GPIO_SD_B2_08
GPIO_SD_B2_09
GPIO_SD_B2_10
GPIO_SD_B2_11
flexspi1.A_SCLK
flexspi1.A_DATA[0]
flexspi1.A_DATA[1]
flexspi1.A_DATA[2]
flexspi1.A_DATA[3]
ALT 1
ALT 1
ALT 1
ALT 1
ALT 1
—
—
—
—
—
Table 103. Boot through FlexSPI2 (QSPI/HyperFLASH)
PAD Name
IO Function
ALT
Comments
GPIO_EMC_B1_41
GPIO_EMC_B2_00
GPIO_EMC_B2_01
GPIO_EMC_B2_02
GPIO_EMC_B2_03
GPIO_EMC_B2_04
GPIO_EMC_B2_05
GPIO_EMC_B2_06
GPIO_EMC_B2_07
GPIO_EMC_B2_08
GPIO_EMC_B2_09
GPIO_EMC_B2_10
GPIO_EMC_B2_11
GPIO_EMC_B2_12
GPIO_EMC_B2_13
GPIO_EMC_B2_14
GPIO_EMC_B2_15
GPIO_EMC_B2_16
GPIO_EMC_B2_17
GPIO_EMC_B2_18
GPIO_EMC_B2_19
GPIO_EMC_B2_20
flexspi2.B_DATA[7]
flexspi2.B_DATA[6]
flexspi2.B_DATA[5]
flexspi2.B_DATA[4]
flexspi2.B_DATA[3]
flexspi2.B_DATA[2]
flexspi2.B_DATA[1]
flexspi2.B_DATA[0]
flexspi2.B_DQS
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
ALT 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
flexspi2.B_SS0_B
flexspi2.B_SCLK
flexspi2.A_SCLK
flexspi2.A_SS0_B
flexspi2.A_DQS
flexspi2.A_DATA[0]
flexspi2.A_DATA[1]
flexspi2.A_DATA[2]
flexspi2.A_DATA[3]
flexspi2.A_DATA[4]
flexspi2.A_DATA[5]
flexspi2.A_DATA[6]
flexspi2.A_DATA[7]
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
107
Boot mode configuration
PAD Name
Table 104. FlexSPI reset
IO Function
Mux Mode
Comments
GPIO_SD_B1_00
gpio_mux4.IO[3]
gpio_mux2.IO[8]
ALT 5
ALT 5
—
GPIO_EMC_B1_40
Secondary
option
Table 105. Boot through SAI1
IO Function
PAD Name
Mux Mode
Comments
GPIO_AD_17
GPIO_AD_18
GPIO_AD_19
GPIO_AD_20
GPIO_AD_21
GPIO_AD_22
GPIO_AD_23
sai1.MCLK
sai1.RX_SYNC
sai1.RX_BCLK
sai1.RX_DATA[0]
sai1.TX_DATA[0]
sai1.TX_BCLK
sai1.TX_SYNC
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
—
Table 106. Boot through SD1
IO Function
PAD Name
Mux Mode
Comments
GPIO_AD_32
GPIO_AD_33
usdhc1.CD_B
usdhc1.WP
ALT 4
ALT 4
ALT 4
ALT 4
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
—
—
—
—
GPIO_AD_34
usdhc1.VSELECT
usdhc1.RESET_B
usdhc1.CMD
GPIO_AD_35
GPIO_SD_B1_00
GPIO_SD_B1_01
GPIO_SD_B1_02
GPIO_SD_B1_03
GPIO_SD_B1_04
GPIO_SD_B1_05
usdhc1.CLK
usdhc1.DATA0
usdhc1.DATA1
usdhc1.DATA2
usdhc1.DATA3
Table 107. Boot through SD2
IO Function
PAD Name
Mux Mode
Comments
GPIO_AD_26
GPIO_AD_27
usdhc2.CD_B
usdhc2.WP
ALT 11
ALT 11
ALT 11
ALT 0
—
—
—
—
—
GPIO_AD_28
usdhc2.VSELECT
usdhc2.DATA3
usdhc2.DATA2
GPIO_SD_B2_00
GPIO_SD_B2_01
ALT 0
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
108
Boot mode configuration
Mux Mode Comments
Table 107. Boot through SD2 (continued)
PAD Name
IO Function
GPIO_SD_B2_02
GPIO_SD_B2_03
GPIO_SD_B2_04
GPIO_SD_B2_05
GPIO_SD_B2_06
GPIO_SD_B2_08
GPIO_SD_B2_09
GPIO_SD_B2_10
GPIO_SD_B2_11
usdhc2.DATA1
usdhc2.DATA0
usdhc2.CLK
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
—
—
—
usdhc2.CMD
usdhc2.RESET_B
usdhc2.DATA4
usdhc2.DATA5
usdhc2.DATA6
usdhc2.DATA7
Table 108. Boot through SPI1
IO Function
PAD Name
Mux Mode
Comments
GPIO_AD_28
GPIO_AD_29
GPIO_AD_30
GPIO_AD_31
lpspi1.SCK
lpspi1.PCS0
lpspi1.SDO
lpspi1.SDI
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
Table 109. Boot through SPI2
IO Function
PAD Name
Mux Mode
Comments
GPIO_SD_B2_07
GPIO_SD_B2_08
GPIO_SD_B2_09
GPIO_SD_B2_10
lpspi2.SCK
lpspi2.PCS0
lpspi2.SDO
lpspi2.SDI
ALT 6
ALT 6
ALT 6
ALT 6
—
—
—
—
Table 110. Boot through SPI3
IO Function
PAD Name
Mux Mode
Comments
GPIO_DISP_B1_04
GPIO_DISP_B1_07
GPIO_DISP_B1_06
GPIO_DISP_B1_05
lpspi3.SCK
lpspi3.PCS0
lpspi3.SDO
lpspi3.SDI
ALT 9
ALT 9
ALT 9
ALT 9
—
—
—
—
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
109
Boot mode configuration
PAD Name
Table 111. Boot through SPI4
IO Function
Mux Mode
Comments
GPIO_DISP_B2_12
GPIO_DISP_B2_15
GPIO_DISP_B2_14
GPIO_DISP_B2_13
lpspi4.SCK
lpspi4.PCS0
lpspi4.SDO
lpspi4.SDI
ALT 9
ALT 9
ALT 9
ALT 9
—
—
—
—
Table 112. Boot through UART1
IO Function
PAD Name
Mux Mode
Comments
GPIO_AD_24
GPIO_AD_25
GPIO_AD_26
GPIO_AD_27
lpuart1.TX
lpuart1.RX
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
lpuart1.CTS_B
lpuart1.RTS_B
Table 113. Boot through UART12
IO Function
PAD Name
Mux Mode
Comments
GPIO_LPSR_04
GPIO_LPSR_05
GPIO_LPSR_06
GPIO_LPSR_07
lpuart12.RTS_B
lpuart12.CTS_B
lpuart12.TX
ALT 3
ALT 3
ALT 3
ALT 3
—
—
—
—
lpuart12.RX
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
110
Package information and contact assignments
6 Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
14 x 14 mm package information
14 x 14 mm, 0.8 mm pitch, ball matrix
6.1.1
Figure 53 shows the top, bottom, and side views of the 14 x 14 mm MAPBGA package.
Figure 53. 14 x 14 mm BGA, case x package top, bottom, and side Views
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
111
Package information and contact assignments
6.1.2
14 x 14 mm supplies contact assignments and functional contact
assignments
Table 114 shows the device connection list for ground, sense, and reference contact signals.
Table 114. 14 x 14 mm supplies contact assignment
Supply Rail Name
Ball(s) Position(s)
Remark
G16
H16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADC_VREFH
DAC_OUT
DCDC_ANA
M7, M8
M6
DCDC_ANA_SENSE
DCDC_DIG
K8, K9, L8
L7
DCDC_DIG_SENSE
DCDC_GND
K6, K7, L6
M5, N5
L5
DCDC_IN
DCDC_IN_Q
DCDC_LN
T4, U4
T3, U3
DCDC_LP
DCDC_MODE
DCDC_PSWITCH
NVCC_DISP1
NVCC_DISP2
NVCC_EMC1
NVCC_EMC2
NVCC_GPIO
NVCC_LPSR
NVCC_SNVS
NVCC_SD1
N4
P3
D12
E7
F6, F7, G6
H6, J6
M12
P7
U11
D14
G13
P12
P11
R12
F10
F9
NVCC_SD2
VDD_LPSR_ANA
VDD_LPSR_DIG
VDD_LPSR_IN
VDD_MIPI_1P0
VDD_MIPI_1P8
VDD_USB_1P8
VDD_USB_3P3
H12
G12
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
112
Package information and contact assignments
Table 114. 14 x 14 mm supplies contact assignment (continued)
Supply Rail Name
Ball(s) Position(s)
Remark
H8, H9, H10, J8, J9, J10, K10
VDD_SOC_IN
VDD_SNVS_ANA
VDD_SNVS_DIG
VDD_SNVS_IN
VDDA_1P0
U14
T14
U12
N11
M11
K15
J13
—
—
—
—
—
VDDA_1P8_IN
VDDA_ADC_1P8
VDDA_ADC_3P3
VSS
—
—
A1, A17, B7, C8, C10, C12, C14, D4, F11, F12, F13, G3, G7, G8, G9,
G10, G11, G15, H7, H11, J7, J11, K11, L3, L10, L11, L15, P4, P14, R4,
R7, T12, U1, U17
Table 115 shows an alpha-sorted list of functional contact assignments of the 14 x 14 mm package.
Table 115. 14 x 14 mm functional contact assignment
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
CLK1_N
CLK1_P
T15
U15
N12
—
—
—
—
—
—
—
—
—
—
GPIO_AD_00
GPIO_AD_01
GPIO_AD_02
GPIO_AD_03
GPIO_AD_04
GPIO_AD_05
GPIO_AD_06
GPIO_AD_07
GPIO_AD_08
NVCC_GPIO
Digital
GPIO
ALT 5
GPIO_MUX2_IO31
GPIO_MUX3_IO0
GPIO_MUX3_IO1
GPIO_MUX3_IO2
GPIO_MUX3_IO3
GPIO_MUX3_IO4
GPIO_MUX3_IO5
GPIO_MUX3_IO6
GPIO_MUX3_IO7
Input
35K PU1
R14
R13
P15
M13
P13
N13
T17
R15
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
Digital
GPIO
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
Input
Input
Input
Input
Input
Input
Input
Input
35K PU
35K PD2
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
113
Package information and contact assignments
Table 115. 14 x 14 mm functional contact assignment (continued)
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
GPIO_AD_09
R16
R17
P16
P17
L12
N14
M14
N17
N15
M16
L16
K13
K14
K12
J12
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
Digital
GPIO
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
GPIO_MUX3_IO8
GPIO_MUX3_IO9
GPIO_MUX3_IO10
GPIO_MUX3_IO11
GPIO_MUX3_IO12
GPIO_MUX3_IO13
GPIO_MUX3_IO14
GPIO_MUX3_IO15
GPIO_MUX3_IO16
GPIO_MUX3_IO17
GPIO_MUX3_IO18
GPIO_MUX3_IO19
GPIO_MUX3_IO20
GPIO_MUX3_IO21
GPIO_MUX3_IO22
GPIO_MUX3_IO23
GPIO_MUX3_IO24
GPIO_MUX3_IO25
GPIO_MUX3_IO26
Input
35K PD
GPIO_AD_10
GPIO_AD_11
GPIO_AD_12
GPIO_AD_13
GPIO_AD_14
GPIO_AD_15
GPIO_AD_16
GPIO_AD_17
GPIO_AD_18
GPIO_AD_19
GPIO_AD_20
GPIO_AD_21
GPIO_AD_22
GPIO_AD_23
GPIO_AD_24
GPIO_AD_25
GPIO_AD_26
GPIO_AD_27
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PU
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PU
35K PU
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
L13
M15
L14
N16
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
114
Package information and contact assignments
Table 115. 14 x 14 mm functional contact assignment (continued)
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
GPIO_AD_28
L17
M17
K17
J17
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_DISP1
NVCC_DISP1
NVCC_DISP1
NVCC_DISP1
NVCC_DISP1
NVCC_DISP1
NVCC_DISP1
NVCC_DISP1
NVCC_DISP1
NVCC_DISP1
NVCC_DISP1
Digital
GPIO
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
GPIO_MUX3_IO27
GPIO_MUX3_IO28
GPIO_MUX3_IO29
GPIO_MUX3_IO30
GPIO_MUX3_IO31
GPIO_MUX4_IO0
GPIO_MUX4_IO1
GPIO_MUX4_IO2
GPIO_MUX4_IO21
GPIO_MUX4_IO22
GPIO_MUX4_IO23
GPIO_MUX4_IO24
GPIO_MUX4_IO25
GPIO_MUX4_IO26
GPIO_MUX4_IO27
GPIO_MUX4_IO28
GPIO_MUX4_IO29
GPIO_MUX4_IO30
GPIO_MUX4_IO31
Input
35K PD
GPIO_AD_29
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PU
GPIO_AD_30
Digital
GPIO
GPIO_AD_31
Digital
GPIO
GPIO_AD_32
K16
H17
J16
Digital
GPIO
GPIO_AD_33
Digital
GPIO
GPIO_AD_34
Digital
GPIO
GPIO_AD_35
G17
E13
D13
D11
E11
E10
C11
D10
E12
A15
C13
B14
Digital
GPIO
GPIO_DISP_B1_00
GPIO_DISP_B1_01
GPIO_DISP_B1_02
GPIO_DISP_B1_03
GPIO_DISP_B1_04
GPIO_DISP_B1_05
GPIO_DISP_B1_06
GPIO_DISP_B1_07
GPIO_DISP_B1_08
GPIO_DISP_B1_09
GPIO_DISP_B1_10
Digital
GPIO
50/35K
PD3
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
Highz
Highz
Highz
Highz
Highz
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
115
Package information and contact assignments
Table 115. 14 x 14 mm functional contact assignment (continued)
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
Highz
GPIO_DISP_B1_11
GPIO_DISP_B2_00
GPIO_DISP_B2_01
GPIO_DISP_B2_02
GPIO_DISP_B2_03
GPIO_DISP_B2_04
GPIO_DISP_B2_05
GPIO_DISP_B2_06
GPIO_DISP_B2_07
GPIO_DISP_B2_08
GPIO_DISP_B2_09
GPIO_DISP_B2_10
GPIO_DISP_B2_11
GPIO_DISP_B2_12
GPIO_DISP_B2_13
GPIO_DISP_B2_14
GPIO_DISP_B2_15
GPIO_EMC_B1_00
GPIO_EMC_B1_01
A14
E8
F8
E9
D7
C7
C9
C6
D6
B5
D8
D9
A6
B6
A5
A7
A4
F3
F2
NVCC_DISP1
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_DISP2
NVCC_EMC1
NVCC_EMC1
Digital
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
GPIO_MUX5_IO0
GPIO_MUX5_IO1
GPIO_MUX5_IO2
GPIO_MUX5_IO3
GPIO_MUX5_IO4
GPIO_MUX5_IO5
GPIO_MUX5_IO6
GPIO_MUX5_IO7
GPIO_MUX5_IO8
GPIO_MUX5_IO9
GPIO_MUX5_IO10
GPIO_MUX5_IO11
GPIO_MUX5_IO12
GPIO_MUX5_IO13
GPIO_MUX5_IO14
GPIO_MUX5_IO15
GPIO_MUX5_IO16
GPIO_MUX1_IO0
GPIO_MUX1_IO1
Input
GPIO
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Highz
Digital
GPIO
Highz
Digital
GPIO
Highz
Digital
GPIO
Highz
Digital
GPIO
Highz
Digital
GPIO
Highz
Digital
GPIO
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PU
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
116
Package information and contact assignments
Table 115. 14 x 14 mm functional contact assignment (continued)
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
GPIO_EMC_B1_02
GPIO_EMC_B1_03
GPIO_EMC_B1_04
GPIO_EMC_B1_05
GPIO_EMC_B1_06
GPIO_EMC_B1_07
GPIO_EMC_B1_08
GPIO_EMC_B1_09
GPIO_EMC_B1_10
GPIO_EMC_B1_11
GPIO_EMC_B1_12
GPIO_EMC_B1_13
GPIO_EMC_B1_14
GPIO_EMC_B1_15
GPIO_EMC_B1_16
GPIO_EMC_B1_17
GPIO_EMC_B1_18
GPIO_EMC_B1_19
GPIO_EMC_B1_20
G4
E4
H5
F4
H4
H3
F5
A3
A2
C2
C5
D5
B1
C1
D3
B3
B4
C4
C3
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
Digital
GPIO
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
GPIO_MUX1_IO2
GPIO_MUX1_IO3
GPIO_MUX1_IO4
GPIO_MUX1_IO5
GPIO_MUX1_IO6
GPIO_MUX1_IO7
GPIO_MUX1_IO8
GPIO_MUX1_IO9
GPIO_MUX1_IO10
GPIO_MUX1_IO11
GPIO_MUX1_IO12
GPIO_MUX1_IO13
GPIO_MUX1_IO14
GPIO_MUX1_IO15
GPIO_MUX1_IO16
GPIO_MUX1_IO17
GPIO_MUX1_IO18
GPIO_MUX1_IO19
GPIO_MUX1_IO20
Input
50/35K
PD
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
117
Package information and contact assignments
Table 115. 14 x 14 mm functional contact assignment (continued)
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
GPIO_EMC_B1_21
GPIO_EMC_B1_22
GPIO_EMC_B1_23
GPIO_EMC_B1_24
GPIO_EMC_B1_25
GPIO_EMC_B1_26
GPIO_EMC_B1_27
GPIO_EMC_B1_28
GPIO_EMC_B1_29
GPIO_EMC_B1_30
GPIO_EMC_B1_31
GPIO_EMC_B1_32
GPIO_EMC_B1_33
GPIO_EMC_B1_34
GPIO_EMC_B1_35
GPIO_EMC_B1_36
GPIO_EMC_B1_37
GPIO_EMC_B1_38
GPIO_EMC_B1_39
G2
H2
B2
J5
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC1
Digital
GPIO
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
GPIO_MUX1_IO21
GPIO_MUX1_IO22
GPIO_MUX1_IO23
GPIO_MUX1_IO24
GPIO_MUX1_IO25
GPIO_MUX1_IO26
GPIO_MUX1_IO27
GPIO_MUX1_IO28
GPIO_MUX1_IO29
GPIO_MUX1_IO30
GPIO_MUX1_IO31
GPIO_MUX2_IO0
GPIO_MUX2_IO1
GPIO_MUX2_IO2
GPIO_MUX2_IO3
GPIO_MUX2_IO4
GPIO_MUX2_IO5
GPIO_MUX2_IO6
GPIO_MUX2_IO7
Input
50/35K
PD
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
J4
Digital
GPIO
50/35K
PD
J3
Digital
GPIO
50/35K
PD
G5
E5
E6
E3
D2
D1
E2
E1
F1
G1
H1
J1
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
J2
Digital
GPIO
50/35K
PD
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
118
Package information and contact assignments
Table 115. 14 x 14 mm functional contact assignment (continued)
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
GPIO_EMC_B1_40
GPIO_EMC_B1_41
GPIO_EMC_B2_00
GPIO_EMC_B2_01
GPIO_EMC_B2_02
GPIO_EMC_B2_03
GPIO_EMC_B2_04
GPIO_EMC_B2_05
GPIO_EMC_B2_06
GPIO_EMC_B2_07
GPIO_EMC_B2_08
GPIO_EMC_B2_09
GPIO_EMC_B2_10
GPIO_EMC_B2_11
GPIO_EMC_B2_12
GPIO_EMC_B2_13
GPIO_EMC_B2_14
GPIO_EMC_B2_15
GPIO_EMC_B2_16
K1
L1
NVCC_EMC1
NVCC_EMC1
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
Digital
GPIO
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
GPIO_MUX2_IO8
GPIO_MUX2_IO9
GPIO_MUX2_IO10
GPIO_MUX2_IO11
GPIO_MUX2_IO12
GPIO_MUX2_IO13
GPIO_MUX2_IO14
GPIO_MUX2_IO15
GPIO_MUX2_IO16
GPIO_MUX2_IO17
GPIO_MUX2_IO18
GPIO_MUX2_IO19
GPIO_MUX2_IO20
GPIO_MUX2_IO21
GPIO_MUX2_IO22
GPIO_MUX2_IO23
GPIO_MUX2_IO24
GPIO_MUX2_IO25
GPIO_MUX2_IO26
Input
50/35K
PD
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
50/35K
PD
K2
K4
K3
R1
M1
N1
T1
M3
P1
N2
R2
L4
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PU
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PU
M2
K5
M4
L2
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
P2
Digital
GPIO
50/35K
PD
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
119
Package information and contact assignments
Table 115. 14 x 14 mm functional contact assignment (continued)
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
GPIO_EMC_B2_17
GPIO_EMC_B2_18
GPIO_EMC_B2_19
GPIO_EMC_B2_20
GPIO_LPSR_00
GPIO_LPSR_01
GPIO_LPSR_02
GPIO_LPSR_03
GPIO_LPSR_04
GPIO_LPSR_05
GPIO_LPSR_06
GPIO_LPSR_07
GPIO_LPSR_08
GPIO_LPSR_09
GPIO_LPSR_10
GPIO_LPSR_11
GPIO_LPSR_12
GPIO_LPSR_13
GPIO_LPSR_14
T2
N3
U2
R3
N6
R6
P6
T7
N7
N8
P8
R8
U8
P5
R5
T5
U5
U6
T6
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_EMC2
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
NVCC_LPSR
Digital
GPIO
ALT 5
ALT 5
ALT 5
ALT 5
GPIO_MUX2_IO27
GPIO_MUX2_IO28
GPIO_MUX2_IO29
GPIO_MUX2_IO30
Input
50/35K
PD
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
ALT 10 GPIO12_IO0
ALT 10 GPIO12_IO1
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PD
35K PU
Highz
Digital
GPIO
Digital
GPIO
ALT 0
ALT 0
BOOT_MODE0
BOOT_MODE1
Digital
GPIO
Digital
GPIO
ALT 10 GPIO12_IO4
ALT 10 GPIO12_IO5
ALT 10 GPIO12_IO6
ALT 10 GPIO12_IO7
ALT 10 GPIO12_IO8
ALT 10 GPIO12_IO9
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
JTAG_MUX_TRSTB
Digital
GPIO
JTAG_MUX_TDO
JTAG_MUX_TDI
JTAG_MUX_MOD
JTAG_MUX_TCK
Digital
GPIO
35K PU
35K PD
35K PD
Digital
GPIO
Digital
GPIO
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
120
Package information and contact assignments
Table 115. 14 x 14 mm functional contact assignment (continued)
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
GPIO_LPSR_15
U7
NVCC_LPSR
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
Digital
GPIO
ALT 0
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
ALT 5
JTAG_MUX_TMS
GPIO_MUX4_IO3
GPIO_MUX4_IO4
GPIO_MUX4_IO5
GPIO_MUX4_IO6
GPIO_MUX4_IO7
GPIO_MUX4_IO8
GPIO_MUX4_IO9
GPIO_MUX4_IO10
GPIO_MUX4_IO11
GPIO_MUX4_IO12
GPIO_MUX4_IO13
GPIO_MUX4_IO14
GPIO_MUX4_IO15
GPIO_MUX4_IO16
GPIO_MUX4_IO17
GPIO_MUX4_IO18
GPIO_MUX4_IO19
GPIO_MUX4_IO20
Input
35K PU
GPIO_SD_B1_00
GPIO_SD_B1_01
GPIO_SD_B1_02
GPIO_SD_B1_03
GPIO_SD_B1_04
GPIO_SD_B1_05
GPIO_SD_B2_00
GPIO_SD_B2_01
GPIO_SD_B2_02
GPIO_SD_B2_03
GPIO_SD_B2_04
GPIO_SD_B2_05
GPIO_SD_B2_06
GPIO_SD_B2_07
GPIO_SD_B2_08
GPIO_SD_B2_09
GPIO_SD_B2_10
GPIO_SD_B2_11
B16
D15
C15
B17
B15
A16
J15
J14
H13
E15
F14
E14
F17
G14
F15
H15
H14
F16
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
50/35K
PU
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PU
Digital
GPIO
50/35K
PU
Digital
GPIO
50/35K
PU
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PU
Digital
GPIO
50/35K
PU
Digital
GPIO
50/35K
PU
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
Digital
GPIO
50/35K
PD
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
121
Package information and contact assignments
Table 115. 14 x 14 mm functional contact assignment (continued)
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
PD
GPIO_SNVS_00
R10
P10
L9
NVCC_SNVS
NVCC_SNVS
NVCC_SNVS
NVCC_SNVS
NVCC_SNVS
NVCC_SNVS
NVCC_SNVS
NVCC_SNVS
NVCC_SNVS
NVCC_SNVS
ANALOG ALT 5
GPIO
GPIO13_IO3
GPIO13_IO4
GPIO13_IO5
GPIO13_IO6
GPIO13_IO7
GPIO13_IO8
GPIO13_IO9
GPIO13_IO10
GPIO13_IO11
GPIO13_IO12
Input
GPIO_SNVS_01
GPIO_SNVS_02
GPIO_SNVS_03
GPIO_SNVS_04
GPIO_SNVS_05
GPIO_SNVS_06
GPIO_SNVS_07
GPIO_SNVS_08
GPIO_SNVS_09
ANALOG ALT 5
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
PD
PD
PD
PD
PD
PD
PD
PD
PD
ANALOG ALT 5
GPIO
M10
N10
P9
ANALOG ALT 5
GPIO
ANALOG ALT 5
GPIO
ANALOG ALT 5
GPIO
M9
ANALOG ALT 5
GPIO
R9
ANALOG ALT 5
GPIO
N9
ANALOG ALT 5
GPIO
R11
ANALOG ALT 5
GPIO
MIPI_CSI_CKP
MIPI_CSI_CKN
MIPI_CSI_DN0
MIPI_CSI_DN1
MIPI_CSI_DP0
MIPI_CSI_DP1
MIPI_DSI_CKP
MIPI_DSI_CKN
MIPI_DSI_DN0
MIPI_DSI_DN1
MIPI_DSI_DP0
MIPI_DSI_DP1
ONOFF
B12
A12
A11
A13
B11
B13
B9
VDD_MIPI_1P8
VDD_MIPI_1P8
VDD_MIPI_1P8
VDD_MIPI_1P8
VDD_MIPI_1P8
VDD_MIPI_1P8
VDD_MIPI_1P8
VDD_MIPI_1P8
VDD_MIPI_1P8
VDD_MIPI_1P8
VDD_MIPI_1P8
VDD_MIPI_1P8
NVCC_SNVS
CSI
CSI
CSI
CSI
CSI
CSI
DSI
DSI
DSI
DSI
DSI
DSI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A9
—
A8
—
A10
B8
—
—
—
B10
U10
ANALOG ALT 0
GPIO
RESET_B
Input
PU
PMIC_ON_REQ
U9
NVCC_SNVS
ANALOG ALT 0
GPIO
SNVS_LP_PMIC_ON Output
_REQ
Output
high
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
122
Package information and contact assignments
Table 115. 14 x 14 mm functional contact assignment (continued)
Default setting
14x14
ball
Ball
Ball name
Power group
Types Default
modes
Input/
output
Default function
Value
PMIC_STBY_REQ
POR_B
T9
NVCC_SNVS
NVCC_SNVS
ANALOG ALT 0
GPIO
CCM_PMIC_VSTBY_ Output
REQ
Output
low
T10
ANALOG ALT 0
GPIO
POR_B
—
PU
RTC_XTALI
RTC_XTALO
TEST_MODE
T13
U13
T11
—
—
—
—
—
—
—
—
—
—
—
—
NVCC_SNVS
ANALOG ALT 0
GPIO
TEST_MODE
Input
PD
USB1_DN
USB1_DP
USB2_DN
USB2_DP
USB1_VBUS
USB2_VBUS
XTALI
E16
E17
C16
C17
D17
D16
U16
T16
T8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XTALO
—
—
WAKEUP
NVCC_SNVS
ANALOG ALT 5
GPIO
GPIO13_IO0
Input
PU
1
Pull-up
2
3
Pull-down
Typical resistance value is 50 k for 3.3 V and 35 k for 1.8 V. The range is from 10 k to 100 k (3.3 V) and 20 k to 50 k
(1.8 V).
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
123
Package information and contact assignments
6.1.3
14 x 14 mm, 0.8 mm pitch, ball map
Table 116 shows the 14 x 14 mm, 0.8 mm pitch ball map for the i.MX RT1170.
Table 116. 14 x 14 mm, 0.8 mm pitch, ball map
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GPIO_
EMC_
B1_10
GPIO_
EMC_
B1_09
GPIO_
DISP_
B2_15
GPIO_
DISP_
B2_13
GPIO_
DISP_
B2_11
GPIO_
DISP_
B2_14
MIPI_
DSI_
DN0
MIPI_
DSI_
CKN
MIPI_
DSI_
DN1
MIPI_
CSI_
DN0
MIPI_
CSI_
CKN
MIPI_
CSI_
DN1
GPIO_
DISP_
B1_11
GPIO_
DISP_
B1_08
GPIO_
SD_
B1_05
VSS
VSS
A
B
C
D
E
F
GPIO_
EMC_
B1_14
GPIO_
EMC_
B1_23
GPIO_
EMC_
B1_17
GPIO_
EMC_
B1_18
GPIO_
DISP_
B2_08
GPIO_
DISP_
B2_12
VSS
MIPI_
DSI_
DP0
MIPI_
DSI_
CKP
MIPI_
DSI_
DP1
MIPI_
CSI_
DP0
MIPI_
CSI_
CKP
MIPI_
CSI_
DP1
GPIO_
DISP_
B1_10
GPIO_
SD_
B1_04
GPIO_
SD_
B1_00
GPIO_
SD_
B1_03
GPIO_
EMC_
B1_15
GPIO_
EMC_
B1_11
GPIO_
EMC_
B1_20
GPIO_
EMC_
B1_19
GPIO_
EMC_
B1_12
GPIO_
DISP_
B2_06
GPIO_
DISP_
B2_04
VSS
GPIO_
DISP_
B2_05
VSS
GPIO_
DISP_
B1_05
VSS
GPIO_
DISP_
B1_09
VSS
GPIO_
SD_
B1_02
USB2_
DN
USB2_
DP
GPIO_
EMC_
B1_32
GPIO_
EMC_
B1_31
GPIO_
EMC_
B1_16
VSS
GPIO_
EMC_
B1_13
GPIO_
DISP_
B2_07
GPIO_
DISP_
B2_03
GPIO_
DISP_
B2_09
GPIO_
DISP_
B2_10
GPIO_
DISP_
B1_06
GPIO_
DISP_
B1_02
NVCC_
DISP1
GPIO_
DISP_
B1_01
NVCC_
SD1
GPIO_
SD_
B1_01
USB2_
VBUS
USB1_
VBUS
GPIO_
EMC_
B1_34
GPIO_
EMC_
B1_33
GPIO_
EMC_
B1_30
GPIO_
EMC_
B1_03
GPIO_
EMC_
B1_28
GPIO_
EMC_
B1_29
NVCC_
DISP2
GPIO_
DISP_
B2_00
GPIO_
DISP_
B2_02
GPIO_
DISP_
B1_04
GPIO_
DISP_
B1_03
GPIO_
DISP_
B1_07
GPIO_
DISP_
B1_00
GPIO_
SD_
B2_05
GPIO_
SD_
B2_03
USB1_
DN
USB1_
DP
GPIO_
EMC_
B1_35
GPIO_
EMC_
B1_01
GPIO_
EMC_
B1_00
GPIO_
EMC_
B1_05
GPIO_
EMC_
B1_08
NVCC_ NVCC_
EMC1
GPIO_
DISP_
B2_01
VDD_
MIPI_
1P8
VDD_M
IPI_
1P0
VSS
VSS
VSS
VSS
VSS
VSS
GPIO_
SD_
B2_04
GPIO_
SD_
B2_08
GPIO_
SD_
B2_11
GPIO_
SD_
B2_06
EMC1
GPIO_
EMC_
B1_36
GPIO_
EMC_
B1_21
VSS
GPIO_
EMC_
B1_02
GPIO_
EMC_
B1_27
NVCC_
EMC1
VSS
VSS
VSS
VSS
VDD_
USB_
3P3
NVCC_
SD2
GPIO_
SD_
B2_07
VSS
ADC_
VREFH
GPIO_
AD_35
G
H
J
GPIO_
EMC_
B1_37
GPIO_
EMC_
B1_22
GPIO_
EMC_
B1_07
GPIO_
EMC_
B1_06
GPIO_
EMC_
B1_04
NVCC_
EMC2
VSS
VSS
VDD_
SOC_
IN
VDD_
SOC_
IN
VDD_
SOC_
IN
VDD_
USB_
1P8
GPIO_
SD_
B2_02
GPIO_
SD_
B2_10
GPIO_
SD_
B2_09
DAC_
OUT
GPIO_
AD_33
GPIO_
EMC_
B1_38
GPIO_
EMC_
B1_39
GPIO_
EMC_
B1_26
GPIO_
EMC_
B1_25
GPIO_
EMC_
B1_24
NVCC_
EMC2
VDD_
SOC_
IN
VDD_
SOC_
IN
VDD_
SOC_
IN
GPIO_
AD_23
VDDA_
ADC_
3P3
GPIO_
SD_
B2_01
GPIO_
SD_
B2_00
GPIO_
AD_34
GPIO_
AD_31
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
124
NXP Semiconductors
Package information and contact assignments
Table 116. 14 x 14 mm, 0.8 mm pitch, ball map (continued)
GPIO_
EMC_
B1_40
GPIO_
EMC_
B2_00
GPIO_
EMC_
B2_02
GPIO_
EMC_
B2_01
GPIO_
EMC_
B2_13
DCDC
_GND
DCDC
_GND
DCDC
_DIG
DCDC
_DIG
VDD_
SOC_
IN
VSS
GPIO_
AD_22
GPIO_
AD_20
GPIO_
AD_21
VDDA_
ADC_
1P8
GPIO_
AD_32
GPIO_
AD_30
K
L
GPIO_
EMC_
B1_41
GPIO_
EMC_
B2_15
VSS
GPIO_
EMC_
B2_11
DCDC
_IN_Q
DCDC
_GND
DCDC
_DIG_
SENSE
DCDC
_DIG
GPIO_
SNVS_
02
VSS
VSS
GPIO_
AD_13
GPIO_
AD_24
GPIO_
AD_26
VSS
GPIO_
AD_19
GPIO_
AD_28
GPIO_
EMC_
B2_04
GPIO_
EMC_
B2_12
GPIO_
EMC_
B2_07
GPIO_
EMC_
B2_14
DCDC
_IN
DCDC
_ANA_
SENSE
DCDC
_ANA
DCDC
_ANA
GPIO_
SNVS_
06
GPIO_
SNVS_
03
VDDA_ NVCC_
GPIO_
AD_04
GPIO_
AD_15
GPIO_
AD_25
GPIO_
AD_18
GPIO_
AD_29
M
N
P
R
T
1P8_IN
GPIO
GPIO_
EMC_
B2_05
GPIO_
EMC_
B2_09
GPIO_
EMC_
B2_18
DCDC_
MODE
DCDC
_IN
GPIO_
LPSR_
00
GPIO_
LPSR_
04
GPIO_
LPSR_
05
GPIO_
SNVS_
08
GPIO_
SNVS_
04
VDDA_
1P0
GPIO_
AD_00
GPIO_
AD_06
GPIO_
AD_14
GPIO_
AD_17
GPIO_
AD_27
GPIO_
AD_16
GPIO_
EMC_
B2_08
GPIO_
EMC_
B2_16
DCDC
_PSWI
TCH
VSS
VSS
GPIO_
LPSR_
09
GPIO_
LPSR_
02
NVCC_
LPSR
GPIO_
LPSR_
06
GPIO_
SNVS_
05
GPIO_
SNVS_
01
VDD_
LPSR_
DIG
VDD_
LPSR_
ANA
GPIO_
AD_05
VSS
GPIO_
AD_03
GPIO_
AD_11
GPIO_
AD_12
GPIO_
EMC_
B2_03
GPIO_
EMC_
B2_10
GPIO_
EMC_
B2_20
GPIO_
LPSR_
10
GPIO_
LPSR_
01
VSS
GPIO_
LPSR_
07
GPIO_
SNVS_
07
GPIO_
SNVS_
00
GPIO_
SNVS_
09
VDD_
LPSR_
IN
GPIO_
AD_02
GPIO_
AD_01
GPIO_
AD_08
GPIO_
AD_09
GPIO_
AD_10
GPIO_
EMC_
B2_06
GPIO_
EMC_
B2_17
DCDC
_LP
DCDC_
LN
GPIO_
LPSR_
11
GPIO_
LPSR_
14
GPIO_
LPSR_
03
WAKE
UP
PMIC_
STBY_
REQ
POR_B
TEST_
MODE
VSS
RTC_
XTALI
VDD_
SNVS_
DIG
CLK1_
N
XTALO
XTALI
GPIO_
AD_07
VSS
GPIO_
EMC_
B2_19
DCDC
_LP
DCDC_
LN
GPIO_
LPSR_
12
GPIO_
LPSR_
13
GPIO_
LPSR_
15
GPIO_
LPSR_
08
PMIC_
ON_
REQ
ONOFF NVCC_
SNVS
VDD_
RTC_
VDD_
CLK1_
P
VSS
U
SNVS_ XTALO SNVS_
IN
ANA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
125
Revision history
7 Revision history
Table 117 provides a revision history for this data sheet.
Table 117. i.MX RT1170 Data Sheet document revision history (continued)
Rev.
Number
Date
Substantive Change(s)
Rev. 1
05/2021
• Added new part numbers in the Table 1. Order information
• Updated the Figure 1, "Part number nomenclature—i.MX RT11XX family"
• Updated OCRAM and uSHDC descriptions in the Table 3. i.MX RT1170 modules list
• Updated the CLK1_P/CLK1_N, DCDC_PSWITCH, RTC_XTALI/RTC_XTALO, and NC
descriptions in the Table 4. Special signal considerations
• Updated the Table 9. Electrostatic discharge and latch-up characteristics
• Updated the comment for VDD_SOC_IN in the Table 11. Operating ranges
• Updated the test condition of Set Point #7 in the Table 14. Typical power modes current and
power consumption (Single core)
• Updated the DCDC_PSWITCH note in the Section 4.2.1.1, Power-up sequence
• Updated the descriptions of the Section 4.2.2, Internal POR and power detect
• Updated the maximum value of loading 1.0 V output in the Table 22. DCDC characteristics
• Updated the compliant information in the Section 4.6.1, MIPI D-PHY electrical
characteristics
• Removed a footnote from the Table 75. ADC electrical specifications (VREFFH = 1.68 V and
VADINmax ≤ NVCC_GPIOmax)
• Added tADCSETUP time in the Table 75. ADC electrical specifications (VREFFH = 1.68 V and
VADINmax ≤ NVCC_GPIOmax) and Table 76. ADC electrical specifications (1 V ≤ VREFFH
< VDD_ANA_18min and VADINmax ≤ VREFH)
• Updated the note in the Table 81. Temperature sensor parameters
Rev. 0
02/2021
• Initial version
i.MX RT1170 Crossover Processors Data Sheet for Industrial Products, Rev. 1, 05/2021
NXP Semiconductors
126
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eIQ, and Immersive3D are trademarks of NXP B.V. All other product or service names are the property of their
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For more information, please visit: http://www.nxp.com
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Date of release: 28 May 2021
Document identifier: IMXRT1170IEC
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