PIP213-12M,518 [NXP]
IC 40 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PQCC56, 8 X 8 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT684-4, HVQFN-56, Switching Regulator or Controller;
| 型号： | PIP213-12M,518 |
| 厂家： | 
NXP |
| 描述： | IC 40 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PQCC56, 8 X 8 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT684-4, HVQFN-56, Switching Regulator or Controller 开关 |
| 文件： | 总21页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIP213-12M
DC-to-DC converter power train
Rev. 01 — 25 September 2007
Product data sheet
1. General description
The PIP213-12M is a fully optimized power train for high-current high-frequency
synchronous buck DC-to-DC converter applications. The PIP213-12M replaces two power
MOSFETs, a Schottky diode and a driver IC, resulting in a significant increase in power
density. The integrated solution allows for optimization of individual components and
greatly reduces the parasitics associated with conventional discrete solutions, resulting in
higher system efficiencies at higher operating frequencies.
2. Features
I Input voltage range from 3.3 V to 16 V
I Output voltages from 0.8 V to 6 V
I Capable of up to 25 A maximum output current at 1 MHz
I Operating frequency up to 1 MHz
I Peak system efficiency > 85 % at 1 MHz
I Automatic Dead-time Reduction (ADR) for maximum efficiency
I Internal thermal shutdown
I Auxiliary 5 V output
I Power ready output flag
I Power sequencing functions
I Internal 6.5 V regulator for efficient gate drive
I Compatible with single and multi-phase Pulse Width Modulation (PWM) controllers
I Low-profile, surface-mounted package (8 mm × 8 mm × 0.85 mm)
3. Applications
I High-current DC-to-DC point-of-load converters
I Small form-factor voltage regulator modules
I Microprocessor and memory voltage regulators
I Intel DriverMOS (DrMOS) compatible
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PIP213-12M
HVQFN56 plastic thermal enhanced very thin quad flat package; no leads; 56
SOT684-4
terminals; body 8 × 8 × 0.85 mm
5. Block diagram
V
CBP CBN
DDO
5
10
8, 11
to 20
PIP213-12M
4
2
V
DDC
6.5 V
REG
INTERNAL
5 V REG
BOOST
SWITCH
VDDG_EN
UVLO
3
V
DDG
54
upper
driver
REG5V
5 V REG
5 V
42 to 50
56
VO
VI
CONTROL LOGIC
AND
DEAD-TIME
CONTROL
5 V
OTP
30 kΩ
55
53
DISABLE
PRDY
V
DDG
lower
driver
1, 7, 51
22 to 41
V
V
SSO
003aac025
SSC
signal ground
power ground
A bootstrap switch is integrated into the design of the PIP213-12M between VDDC and CBN
Fig 1. Block diagram
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
2 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
6. Functional diagram
conversion supply
control circuit supply
V
V
V
DDC
DDO
DDG
100 nF
CBP
CBN
REG5V
VI
PWM input
PIP213-12M
L
o(ext)
DISABLE
output
VO
C
o(ext)
V
V
SSC
SSO
003aac027
signal ground
power ground
Fig 2. Simplified functional block diagram of a synchronous DC-to-DC converter output
stage
7. Pinning information
7.1 Pinning
terminal 1
index area
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
VO
SSC
VDDG_EN
V
V
V
V
V
V
V
V
V
V
V
V
V
SSO
SSO
SSO
SSO
SSO
SSO
SSO
SSO
SSO
SSO
SSO
SSO
SSO
3
V
DDG
V
SSC
4
V
DDC
PAD 1
5
CBP
n.c
6
7
V
SSC
PIP213-12M
8
V
DDO
n.c.
9
VO
PAD 3
10
11
12
13
14
CBN
V
DDO
V
DDO
DDO
DDO
DDO
PAD 2
V
V
V
003aac026
Transparent top view
Fig 3. Pin configuration
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
3 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
7.2 Pin description
Table 2.
Symbol
VDDC
Pin description
Pin
Type
Description
4
-
control circuit supply voltage
output stage supply voltage
control circuit ground
VDDO
8, 11 to 20, pad 2
I
VSSC
1, 7, 51, pad 1
22 to 41
56
-
VSSO
-
output stage ground supply voltage
pulse width modulation input
output voltage
VI
I
VO
42 to 50, pad 3
21
O
O
VO_SENSE
sense connection to VO often required for remote
current sensing
CBP
5
-
connection to bootstrap capacitor
connection to bootstrap capacitor
enables internal 6.5 V regulator for VDDG
gate driver supply voltage
CBN
10
2
-
VDDG_EN
VDDG
I
3
-
PRDY
53
O
indicates that VDDC is above the UVLO
(UnderVoltage Lockout) level (open drain)
REG5V
DISABLE
n.c.
54
O
I/O
-
5 V regulated supply output
55
disable driver function (active LOW)
6, 9, 52
not connected - leave open or connected to GND
on PCB (Printed-Circuit Board) layout
8. Functional description
8.1 Basic operation
The PIP213-12M combines two MOSFET’s and a MOSFET driver in a thermally
enhanced low inductance package for use in high frequency and high efficiency
synchronous buck DC-to-DC converters; see Figure 2. The two MOSFETs are connected
in a half bridge configuration between VDDO and VSSO. The mid point of the two transistors
is VO which is connected to the output of DC-to-DC converter via an inductor. A logic
HIGH signal on the VI pin causes the lower MOSFET to be switched off and the upper
MOSFET to be switched on. Current will then flow from the supply (VDDO), through the
upper MOSFET and the inductor (Lo(ext)) to the output.
A logic LOW signal on the VI pin causes the upper MOSFET to be turned off and the lower
MOSFET to be switched on. Current then flows from the power ground (VSSO), through
the lower MOSFET and the inductor (Lo(ext)), to the output. The output voltage is
determined by the ratio of the times that the upper and lower MOSFETs conduct.
8.2 UnderVoltage Lockout (UVLO)
The UVLO function ensures the correct operation of the control circuit during a power-up
and power-down sequence. Power to the control circuit is provided by the VDDC pin. This
voltage is internally monitored to ensure that if VDDC is below the UVLO threshold, the
DISABLE pin is internally pulled LOW and both MOSFETs are off. This is indicated by the
power ready (PRDY) flag, an open drain output that is pulled LOW whenever VDDC is
below the UVLO threshold.
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
4 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
8.3 Upper driver operation
The gate drive to the upper MOSFET is provided by a bootstrap capacitor (typically
100 nF) that is placed between the CBP and CBN pins. This capacitor is charged via an
internal boost switch to a voltage within a few millivolts of VDDC up to a maximum of 12 V
(this is to prevent excessive gate charge losses when VDDC > 12 V). The upper MOSFET
will be switched according to PWM input once the boost capacitor voltage is above
Vth(CBP-CBN) on. When ever the voltage is below Vth(CBP-CBN) off the upper MOSFET will
remain off.
8.4 VDDG regulator
The gate drive voltage level to the lower MOSFET is set by the voltage on the VDDG pin. A
1 µF capacitor must be connected between this pin and VSSC. For minimum power loss
within the PIP213-12M, an external power supply of between 5 V and 12 V must be
connected to this pin. The optimum value for this voltage is dependent on the application
but in the majority of cases a 5 V supply is recommended; see Figure 11. In cases where
the VDDG maximum voltage will not be exceeded, the VDDG pin can be connected to the
V
DDC pin and the VDDG capacitor can be omitted; see Figure 13.
When VDDC is connected to a supply greater than 9 V, an internal 6.5 V regulator
connected to VDDG can be used to provide the gate drive for the lower MOSFET;
see Figure 12. The VDDG regulator is enabled by leaving the VDDG_EN pin open resulting
in this pin being pulled internally to 5 V. If an external supply is to be connected to VDDG
then the VDDG_EN pin must be pulled low by connecting to VSSC to disable the internal
VDDG regulator.
Table 3.
VDDG biasing
VDDG
VDDG_EN
Open circuit
VSSC
internal 6.5 V regulator used (VDDC > 9 V)
connection to external supply required
8.5 3-state function
If the input to VI from the PWM controller becomes high impedance, then the VI input is
driven to 2.5 V by an internal voltage divider. A voltage on the VI pin that is in-between the
VIH and VIL levels and present for longer than td(3-state), causes both MOSFETs to be
turned off. Normal operation commences once the VI input is outside this window for
longer than td(3-state)
.
8.6 Automatic Dead-time Reduction (ADR)
Protection against cross-conduction (shoot-through) is achieved via by a delay (or
dead-time) between the switching off of one MOSFET and the switching on of the other
MOSFET. The automatic dead-time reduction feature continuously monitors the body
diode of the lower MOSFET adjusting the dead-time to minimize body diode conduction.
This reduces power loss in both the upper and lower MOSFETs due to the reduction in
body diode conduction and reverse recovery charge. The lower power dissipation leads to
higher system efficiency and enables higher frequency operation.
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
5 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
8.7 Overtemperature Protection (OTP)
Protection against over temperature is provided by an internal thermal shutdown
incorporated into the control circuit. When the control circuit die temperature exceeds the
upper thermal trip level, both MOSFETs are switched off and the internal VDDG regulator
disabled. This state continues until the die temperature falls below the lower trip
temperature. This function is only operational when VDDC is above the UVLO level.
8.8 Disable
This is the disable or enable function of the driver. Pulling the DISABLE pin LOW switches
off both MOSFETs and disables the REG5V output. This pin is internally pulled LOW
whilst VDDC remains below the UVLO threshold. Once VDDC exceeds the UVLO threshold,
this pin is pulled HIGH by an internal resistor. In this way the driver will enable itself unless
there is an external pull down. In multiphase applications, connecting the DISABLE pins of
multiple PIP213-12M devices together will ensure that all devices will only become
enabled when the voltage on the VDDC pins of all of the devices has exceeded the UVLO
threshold; see Figure 10.
8.9 Reg5V
This function provides a low current regulated 5 V output voltage suitable for providing
power to a PWM controller. It is operational when both PRDY and DISABLE are HIGH.
Operation as a 5 V power supply is only guaranteed when VDDC is > 7 V. This pin can also
be used as part of an enable function for a PWM controller; this ensures that the PWM is
enabled only when the PIP213-12M is fully operational (i.e. both PRDY and DISABLE are
HIGH).
9. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDC
VDDO
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−0.5
−0.5
−0.5
-
Max
+15
Unit
V
control circuit supply voltage
output stage supply voltage
input voltage
+24
V
+12.6
+12.6
V
VDDG
VO
gate driver supply voltage
output voltage
V
VDDO + 0.5 V
Vc(bs)
IO(AV)
bootstrap capacitance voltage
average output current
VO + 15
25
V
A
VDDC = 12 V; Tpcb ≤ 90 °C;
fi = 1 MHz
[1]
IORM
repetitive peak output current
voltage on pin PRDY
VDDC = 12 V; tp ≤ 10 µs
-
40
A
VPRDY
VDISABLE
VREG5V
Ptot
−0.5
−0.5
−0.5
-
+12.6
+12.6
+12.6
21
V
voltage on pin DISABLE
voltage on pin REG5V
total power dissipation
V
V
Tmb = 25 °C
Tmb = 90 °C
W
W
°C
°C
[2]
-
10
Tstg
Tj
storage temperature
junction temperature
−55
−55
+150
+150
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
6 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
[1] Pulse width and repetition rate limited by maximum value of Tj.
[2] Assumes a thermal resistance from junction to mounting base of 6 K/W.
10. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max Unit
6 K/W
thermal resistance from junction device tested with upper and
-
3
to mounting base
lower MOSFETs in series
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
7 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
11. Characteristics
Table 6.
Characteristics
VDDC = 12 V; Tj = 25 °C unless otherwise specified.
Symbol Parameter
Static characteristics
Conditions
Min
Typ
Max Unit
VDDC
control circuit supply voltage
25 °C ≤ Tj ≤ 150 °C
4.5
12
14
4.45
4.1
4.35
2.85
3.7
1.6
-
V
Vth(UVLO)
undervoltage lockout threshold voltage turn on
4.05 4.2
3.7 3.9
V
turn off
turn on
turn off
V
Vth(CBP-CBN) threshold voltage between pin CBP
and pin CBN
3.85 4.1
2.35 2.6
V
V
[1]
[1]
VIH
VIL
ILI
HIGH-level input voltage
LOW-level input voltage
input leakage current
3.3
3.5
1.5
180
8.2
40
V
1.4
V
0 V ≤ VI ≤ 5 V
-
-
-
-
µA
mA
mA
mA
V
IDDC
control circuit supply current
fi = 0 Hz, VI = 0 V
-
fi = 500 kHz, VDDG_EN = open
fi = 500 kHz, VDDG_EN = ground
IL = 65 mA
-
12
-
VDDG
gate driver supply voltage
voltage on pin REG5V
current on pin REG5V
enable threshold voltage
disable threshold voltage
5.75 6.5
7.25
5.5
-
VREG5V
IREG5V
Vth(en)
Vth(dis)
Ttrip(otp)
IL ≤ IREG5V minimum, VDDC > 7 V
VREG5V = 4.5 V
4.5
18
2.9
1.4
-
5.0
-
V
mA
V
on pin DISABLE, VDDC > 4.5 V
on pin DISABLE, VDDC > 4.5 V
3.2
1.6
160
3.5
1.8
-
V
over-temperature protection trip
temperature
°C
Ttrip(otp)hys
Ptot
hysteresis of over-temperature
protection trip temperature
-
40
-
°C
total power dissipation
VDDO = 12 V; IO(AV) = 20 A;
VO = 1.3 V; Tpcb = 90 °C;
fi = 500 kHz
fi = 1 MHz
-
-
4.7
5.5
-
-
W
W
Upper MOSFET
RDSon
drain-source on-state resistance
IO = 10 A; VCBP = 12 V
-
6.5
-
mΩ
Lower MOSFET
RDSon
drain-source on-state resistance
IO = 10 A; VDDG = 12 V
IO = 10 A; VDDG = 6.5 V
-
-
3.8
4.5
-
-
mΩ
mΩ
Dynamic characteristics
td(on)(IH-OH) turn-on delay time from input HIGH to VDDO = 12 V; IO(AV) = 12.5 A
output HIGH
-
-
-
-
80
75
-
ns
ns
ns
td(off)(IL-OL)
turn-off delay time from input LOW to
output LOW
-
td(3-state)
3-state delay time
90
[1] If the input voltage remains between VIH and VIL (2.5 V typ) for longer than td(3-state), then both MOSFETs are turned off.
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
8 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
003aab957
003aab958
10
1.3
1.2
1.1
1
P
tot
(W)
a
8
6
4
2
0
1 MHz
500 kHz
0.9
0
10
20
30
0
6
12
18
I
(A)
V
(V)
DDO
O
VDDC = 12 V; VDDO = 12 V; VO = 1.3 V; fi = 1 Mhz
VDDC = 12 V; VO = 1.3 V; fi = 1 MHz; IO(AV) = 20 A
Ptot
a =
----------------------------------------
Ptot(V
= 12 V)
DDO
Fig 4. Total power dissipation as a function of average
output current; typical values
Fig 5. Normalized power dissipation as a function of
output stage supply voltage; typical values
003aab959
003aab960
1.6
1.2
b
c
1.4
1
1.2
1
0.8
0.8
0.6
200
0
2
4
6
400
600
800
1000
V
(V)
f (kHz)
out
VDDC = 12 V; VDDO = 12 V; fi = 1 MHz; IO(AV) = 20 A
VDDC = 12 V; VDDO = 12 V; VO = 1.3 V; IO(AV) = 20 A
Ptot
Ptot
b =
c =
------------------------------------
-----------------------------------
Ptot(V
= 1.3 V)
O
Ptot( f
= 1 MHz)
i
Fig 6. Normalized power dissipation as a function of
output voltage; typical values
Fig 7. Normalized power dissipation as a function of
input frequency; typical values
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
9 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
003aab961
003aab962
1.2
d
1.2
1.1
1
e
1.1
1
0.9
0.8
0.9
6
8
10
12
14
4
6
8
10
12
V
(V)
V
(V)
DDC
DDG
VDDC = 12 V; VO = 1.3 V; fi = 1 MHz; IO(AV) = 20 A
VDDC = 12 V; VDDO = 12 V; f = 1 MHz; IO(AV) = 20 A
Ptot
Ptot
d =
e =
--------------------------------------
----------------------------------------
Ptot(V
= 12 V)
DDC
Ptot(V
= 5 V)
DDG
Fig 8. Normalized power dissipation as a function of
control circuit supply voltage; typical values
Fig 9. Normalized power dissipation as a function of
gate driver supply voltage; typical values
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
10 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
12. Application information
12.1 Typical application
conversion supply
control circuit supply
22 µF
(4×)
10 Ω
1 µF
1 µF
1 µF
1 µF
1 µF
V
V
V
DDG
DDC
DDO
CBP
100 nF
REG5V
VI
CBN
VO
PIP213-12M
360 nH
100 nF
DISABLE
V
SSC
V
SSO
100 µF
(2×)
22 µF
(4×)
10 Ω
1 µF
V
V
DDC
V
DDG
DDO
CBP
100 nF
REG5V
CBN
VO
VI
PIP213-12M
360 nH
DISABLE
V
CC
V
SSC
V
SSO
100 µF
(2×)
PWM 1
PWM 1
PWM 1
PWM 1
PWM
CONTROLLER
22 µF
(4×)
10 Ω
1 µF
V
V
DDC
V
DDG
DDO
CBP
100 nF
REG5V
VI
CBN
VO
PIP213-12M
360 nH
DISABLE
V
SSC
V
SSO
100 µF
(2×)
22 µF
(4×)
10 Ω
1 µF
V
V
V
DDG
DDC
DDO
CBP
100 nF
signal ground
power ground
REG5V
VI
voltage
output
CBN
VO
PIP213-12M
360 nH
DISABLE
V
SSC
V
SSO
100 µF
(2×)
003aac028
Fig 10. Typical application circuit using the PIP213-12M in a four-phase converter
A typical four-phase buck converter is shown in Figure 10. This system uses four
PIP213-12M devices to deliver a continuous output current of 100 A at an operating
frequency of 500 kHz.
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
11 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
12.2 VDDG supply options
The following options can be used for the lower MOSFET driver supply (VDDG).
conversion supply
control circuit supply
V
5 V external gate drive
PWM input
V
V
DDC
DDO
DDG
100 nF
CBP
CBN
VI
PIP213-12M
L
o(ext)
VDDG_EN
output
VO
C
o(ext)
V
V
SSC
SSO
003aac030
signal ground
power ground
Fig 11. Dual supply operation using 5 V external supply for VDDG
conversion supply
control circuit supply
V
V
V
DDC
DDO
DDG
100 nF
CBP
CBN
PWM input
open circuit
VI
PIP213-12M
L
o(ext)
VDDG_EN
output
VO
C
o(ext)
V
V
SSC
SSO
003aac031
signal ground
power ground
Fig 12. Single supply operation using internal supply for VDDG
conversion supply
control circuit supply
V
V
V
DDC
DDO
DDG
100 nF
CBP
CBN
PWM input
VI
PIP213-12M
L
o(ext)
VDDG_EN
output
VO
C
o(ext)
V
V
SSC
SSO
003aac029
signal ground
power ground
Fig 13. Single supply operation using external supply for VDDG
12.3 DrMOS compatibility
The PIP213-12M can be configured to be compatible with the Intel DrMOS specification.
Conformance to the Intel DrMOS specification requires that an external power supply to
the VDDG pin is used and hence the internal VDDG regulator must be disabled by
connecting the VDDG_EN pin to VSSC
.
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
12 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
The PRDY flag is not used and should be left unconnected on the PCB. The external
boost capacitor should also be connected between CBP and VO and not CBP and CBN
with the CBN pin being left unconnected on the PCB. In addition, VSSC pin 7 and VSSO pin
39 to pin 41 should be left unconnected on the PCB. Note that the sizes of PAD 1, PAD 2
and PAD 3 can vary between different DrMOS vendors. The PCB footprint must be
modified to take the pinning modifications and pad size differences into account.
To ensure footprint compatibility with other DrMOS products, it is recommended that the
latest multiple vendor compatibility PCB footprint contained within the Intel DrMOS
specification is used and that the relevant DrMOS product data sheet is checked for
compatibility.
13. Marking
terminal 1
index area
TYPE No.
RoHS compliant
Mask code
G = RoHS indicator
N1I = Mask layout version
DIFFUSION LOT No.
Diffusion centre
h = Hazel Grove,
UK
hfGYYWWN1I
MANUFACTURING CODE
COUNTRY OF ORIGIN
Assembly centre
f = Amkor Korea
Date code
YY = last two digits of year
WW = week number
03ao89
03ai72
TYPE No: PIP213-12M_NN (NN is revision number)
DIFFUSION LOT No: 7 characters
MANUFACTURING CODE; see Figure 15
COUNTRY OF ORIGIN: Korea
Fig 14. SOT684-4 marking
Fig 15. Interpretation of manufacturing code
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
13 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
14. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm
SOT684-4
D
B
D
A
1
terminal 1
index area
A
4
A
E
E
c
1
A
1
detail X
C
e
1
y
y
v
M
M
C
C
A
B
C
1
e
1/2 e
b
w
15
28
L
29
14
e
E
h1
e
E
2
h
1/2 e
E
h2
1
42
terminal 1
index area
56
43
X
D
D
h2
h1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
E
UNIT
A
A
b
c
D
D
D
E
E
E
E
D
e
e
e
2
v
w
y
y
1
L
h2
1
4
1
h1
h2
1
h
h1
1
max.
0.05 0.70 0.30
0.00 0.65 0.18
8.1 7.8 2.65 3.55 8.1 7.8 6.45 3.25 2.85
7.9 7.7 2.35 3.25 7.9 7.7 6.15 2.95 2.55
0.5
0.3
mm
0.2
0.5 6.5 6.5
0.05 0.1
0.9
0.1 0.05
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
03-10-23
04-09-14
SOT684-4
- - -
MO-220
- - -
Fig 16. Package outline SOT684-4 (HVQFN56)
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
14 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
15. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
15 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 17) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 7 and 8
Table 7.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
220
< 2.5
235
220
≥ 2.5
220
Table 8.
Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 17.
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
16 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 17. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Mounting
16.1 PCB design guidelines
The terminals on the underside of the package are rectangular in shape with a rounded
edge on the inside. Electrical connection between the package and the printed-circuit
board is made by printing solder paste onto the PCB footprint followed by component
placement and reflow soldering. The PCB footprint shown in Figure 18 is designed to form
reliable solder joints.
The use of solder resist between each solder land is recommended. PCB tracks should
not be routed through the corner areas shown in Figure 18. This is because there is a
small, exposed remnant of the lead frame in each corner of the package, left over from the
cropping process.
Good surface flatness of the PCB lands is desirable to ensure accuracy of placement after
soldering. Printed-circuit boards that are finished with a roller tin process tend to leave
small lumps of tin in the corners of each land. Levelling with a hot air knife improves
flatness. Alternatively, an electro-less silver or silver immersion process produces
completely flat PCB lands.
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
17 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
9.25 (2×)
8.30 (2×)
6.20 (2×)
0.475
1.40
0.50
0.25
0.30
1.60
0.40
0.70 (3×)
0.45
0.525
7.04
(4×)
e = 0.50
0.615
0.05
0.80 (2×)
1.90
0.50
0.29 (56×)
solder lands
Cu pattern
0.50
2.00
0.425
0.075
0.150
7.20 (2×)
9.00 (2×)
001aaa064
clearance
solder paste
placement area
occupied area
0.025
All dimensions in mm
Fig 18. PCB footprint for SOT684-4 package (reflow soldering)
16.2 Solder paste printing
The process of printing the solder paste requires care because of the fine pitch and small
size of the solder lands. A stencil thickness of 0.125 mm is recommended. The stencil
apertures can be made the same size as the solder lands in Figure 18.
The type of solder paste recommended for MLF (Micro Lead-Frame) packages is “No
clean”, Type 3, due to the difficulty of cleaning flux residues from beneath the MLF
package.
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
18 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
17. Revision history
Table 9.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PIP213-12M_1
20070925
Product data sheet
-
-
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
19 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
result in personal injury, death or severe property or environmental damage.
18.2 Definitions
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
TrenchMOS — is a trademark of NXP B.V.
19. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
PIP213-12M_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 September 2007
20 of 21
PIP213-12M
NXP Semiconductors
DC-to-DC converter powertrain
20. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Basic operation. . . . . . . . . . . . . . . . . . . . . . . . . 4
UnderVoltage Lockout (UVLO) . . . . . . . . . . . . . 4
Upper driver operation . . . . . . . . . . . . . . . . . . . 5
VDDG regulator . . . . . . . . . . . . . . . . . . . . . . . . . 5
3-state function . . . . . . . . . . . . . . . . . . . . . . . . . 5
Automatic Dead-time Reduction (ADR) . . . . . . 5
Overtemperature Protection (OTP). . . . . . . . . . 6
Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Reg5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal characteristics. . . . . . . . . . . . . . . . . . . 7
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . 11
Typical application. . . . . . . . . . . . . . . . . . . . . . 11
10
11
12
12.1
12.2
12.3
VDDG supply options . . . . . . . . . . . . . . . . . . . . 12
DrMOS compatibility. . . . . . . . . . . . . . . . . . . . 12
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13
14
15
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Introduction to soldering . . . . . . . . . . . . . . . . . 15
Wave and reflow soldering . . . . . . . . . . . . . . . 15
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
16.1
16.2
Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PCB design guidelines . . . . . . . . . . . . . . . . . . 17
Solder paste printing. . . . . . . . . . . . . . . . . . . . 18
17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 September 2007
Document identifier: PIP213-12M_1
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