PLC42VA12A [NXP]
CMOS programmable multi-function PLD 42 】 105 】 12; CMOS可编程的多功能PLD 42 】 105 】 12
| 型号： | PLC42VA12A |
| 厂家： | 
NXP |
| 描述： | CMOS programmable multi-function PLD 42 】 105 】 12 |
| 文件： | 总20页 (文件大小：437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
DESCRIPTION
FEATURES
PIN CONFIGURATIONS
The new PLC42VA12 CMOS PLD from
Philips Semiconductors exhibits a unique
combination of the two architectural concepts
that revolutionized the PLD marketplace.
• High-speed EPROM-based CMOS
Multi-Function PLD
FA and N Pack-
ages
– Super set of 22V10, 32VX10 and
20RA10 PAL ICs
1
2
24
V
I0/CLK
I1
CC
The Philips Semiconductors unique Output
Macro Cell (OMC) embodies all the
23
22
21
20
19
18
17
16
15
14
13
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
I9/OE
• Two fully programmable arrays eliminate
“P-term Depletion”
3
I2
advantages and none of the disadvantages
associated with the “V” type Output Macro
Cell devices. This new design, combined with
added functionality of two programmable
arrays, represents a significant advancement
in the configurability and efficiency of
multi-function PLDs.
– Up to 64 P-terms per OR function
4
I3
5
I4
• Improved Output Macro Cell Structure
– Individually programmable as:
* Registered Output with feedback
* Registered Input
6
I5
7
I6
8
I7
* Combinatorial I/O with Buried Register
* Dedicated I/O with feedback
* Dedicated Input (combinatorial)
9
I8
The most significant improvement in the
Output Macro Cell structure is the
10
11
B0
B1
implementation of the register bypass
function. Any of the 10 J-K/D registers can be
individually bypassed, thus creating a
combinatorial I/O path from the AND array to
the output pin. Unlike other “V” type devices,
the register in the PLC42VA12 Macro Cell
remains fully functional as a buried register.
Both the combinatorial I/O and buried register
have separate input paths (from the AND
array). In most V-type architectures, the
register is lost as a resource when the cell is
configured as a combinatorial I/O. This
feature provides the capability to operate the
buried register independently from the
combinatorial I/O.
– Bypassed Registers are 100% functional
with separate input and feedback paths
GND 12
– Individual Output Enable control
functions
N = Plastic DIP (300mil-wide)
FA = Ceramic DIP with Quartz Window (300mil-wide)
* From pin or AND array
• Reprogrammable – 100% tested for
programmability
• Eleven clock sources
• Register Preload and Diagnostic Test Mode
A Package
Features
I0/
I2 I1 CLK N/C
M9 M8
V
• Security fuse
CC
28 27 26
4
3
2
1
5
6
25
24
23
I3
I4
M7
M6
M5
APPLICATIONS
The PLC42VA12 is an EPROM-based CMOS
device. Designs can be generated using
Philips Semiconductors SNAP PLD design
software packages or one of several other
commercially available JEDEC standard PLD
design software packages.
• Mealy or Moore State Machines
– Synchronous
7
I5
N/C
8
22 N/C
– Asynchronous
9
21
20
19
I6
I7
I8
M4
M3
M2
• Multiple, independent State Machines
• 10-bit ripple cascade
• Sequence recognition
• Bus Protocol generation
• Industrial control
10
11
12 13 14 15 16 17 18
B0 B1 GND N/C I9/ M0 M1
OE
A = Plastic Leaded Chip Carrier (450mil-square)
• A/D Scanning
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
DRAWING NUMBER
24-Pin Ceramic Dual In-Line with window,
Reprogrammable (300mil-wide)
PLC42VA12FA
1478A
24-Pin Plastic Dual In-Line,
One Time Programmable (300mil-wide)
PLC42VA12N
PLC42VA12A
0410D
0401F
28-Pin Plastic Leaded Chip Carrier,
One Time Programmable (450mil-wide)
PAL is a registered trademark of Advanced Micro Devices, Inc.
73
October 22, 1993
853–1414 11164
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
LOGIC DIAGRAM
R R R R C
P
A
MMMM K
8 7 6 5
8
63
56 55
48 47
40 39
32 31
24 23
16 15
8
7
0 F
C
I1
I2
I3
I4
I5
I6
I7
I8
2
3
4
5
6
7
8
9
PR
J
K
CK
Q
PR
J
CK
K
Q
PR
J
CK
K
Q
PR
J
CK
K
Q
NOTE:
Programmable
Connection
74
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
LOGIC DIAGRAM (Continued)
C C C
K K K
7 6 5
R R R R C
MMMM K
C C C
K K K
3 2 1
P R P R
MMMM
9 9 0 0
C
K
9
C
K
0
L
L D D D D D D D D
M MMMMM MMMM
0 1 2 3 4 5 6 7 8
D D
MM
0 9
L
A
P
B
L
B
D D
1 0
4 3 2 1
4
9
13 I9/OE
I0/CLK
1
CK
CK
22 M8
21 M7
20 M6
19 M5
CK
CK
PR
CK
J
CK
K
Q
18 M4
17 M3
16 M2
15 M1
CK
CK
CK
PR
J
CK
K
Q
PR
J
CK
K
Q
PR
J
CK
K
Q
CK
PR
J
CK
K
Q
23 M9
CK
PR
J
CK
K
Q
14 M0
11 B1
10 B0
75
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
FUNCTIONAL DIAGRAM
P
P
F
L
P
R
CK
LM
PM
RM
CK
DM
DM
DB
n
63
0
C
n
n
n
n
n
n
n
n
n
n
I
/OE
9
I1 – I8
X8
I
/CLK
0
X1
X2
X2
X8
X8
X2
X2
X2
X2
X8
X2
X2
CLK
CONTROL
P
J
R
X8
X8
CK
X8
X8
E
(X2)
n
OE
n
K
Q
X8
OMC
CONFIG.
POLARITY
M1 – M8
CLK
CONTROL
P
J
R
X2
X2
CK
X2
E
(X2)
n
OE
n
K
Q
X2
OMC
CONFIG.
M0, M9
X2
X2
POLARITY
POLARITY
B0 – B1
76
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
1
ABSOLUTE MAXIMUM RATINGS
THERMAL RATINGS
TEMPERATURE
Maximum junction
SYMBOL
PARAMETER
Supply voltage
RATINGS
UNIT
150°C
75°C
V
V
V
–0.5 to +7
V
DC
V
DC
V
DC
CC
IN
Maximum ambient
Input voltage
–0.5 to V +0.5
CC
Output voltage
–0.5 to V +0.5
Allowable thermal
rise ambient to
junction
OUT
CC
75°C
I
Input currents
–10 to +10
+24
mA
mA
°C
IN
OUT
I
Output currents
T
amb
Operating temperature range
Storage temperature range
0 to +75
–65 to +150
T
stg
°C
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.
AC TEST CONDITIONS
VOLTAGE WAVEFORMS
+5V
OE
V
S
+3.0V
CC
1
90%
C
C
2
R
10%
90%
1
1
0V
M
I
I
Z
n
t
t
F
5ns
5ns
R
C
R
L
2
+3.0V
0V
INPUTS
DUT
n
M
B
10%
B
M
M
Z
GND
OUTPUTS
CK
5ns
5ns
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
NOTE:
and C are to bypass V to GND.
CC
C
1
2
Test Load Circuit
Input Pulses
77
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
DC ELECTRICAL CHARACTERISTICS
0°C ≤ T
≤ +75°C, 4.75V ≤ V ≤ 5.25V
amb
CC
LIMITS
1
SYMBOL
Input voltage
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
2
V
V
Low
V
= MIN
–0.3
2.0
0.8
V
V
IL
CC
High
V
CC
= MAX
V
+ 0.3
IH
CC
2
Output voltage
V
Low
V
= MIN; I = 16mA
0.3
4.3
0.5
V
V
OL
CC
OL
V
OH
High
V
CC
= MIN; I = –3.2mA
2.4
OH
Input current
I
I
Low
V
= GND
–1
+1
–10
10
µA
µA
IL
IN
High
V
= V
IN CC
IH
Output current
V
= V
= GND
10
–10
OUT
CC
1
–1
µA
µA
I
Hi-Z state
O(OFF)
V
OUT
3,7
I
I
I
Short-circuit
V
= GND
–130
120
mA
mA
mA
OS
OUT
4
5
6
V
CC
CC
supply current (Active)
supply current (Active)
I
I
= 0mA, f = 15MHz , V = MAX
90
70
CC1
CC2
OUT
CC
6
V
= 0mA, f = 15MHz , V = MAX
100
OUT
CC
Capacitance
C
C
Input
I/O
V
CC
= 5V; V = 2.0V
12
15
pF
pF
I
IN
V
B
= 2.0V
B
NOTES:
1. All typical values are at V = 5V. T
= +25°C.
amb
CC
2. All voltage values are with respect to network ground terminal.
3. Duration of short–circuit should not exceed one second. Test one at a time.
4. Tested with V = 0.45V, V = 2.4V.
IL
IH
5. Tested with V = 0V, V = V .
IL
IH
CC
6. Refer to Figure 1, ∆I vs Frequency (worst case). (Referenced from 15MHz)
CC
The I increases by 1.5mA per MHz for the frequency range of 16MHz up to 25MHz.
CC
The I remains at a worst case for the frequency range of 26MHz up to 37MHz.
CC
The I decreases by 1.0mA per MHz for the frequency range of 14MHz down to 1MHz.
CC
The worst case I is calculated as follows:
CC
–
–
–
–
All dedicated inputs are switching.
All OMCs are configured as JK flip-flops in the toggle mode. . .all are toggling.
All 12 outputs are disabled.
The number of product terms connected does not impact the I
.
CC
7. Refer to Figure 2 for ∆t vs output capacitance loading.
PD
+30
+25
+20
+15
+10
+5
6
5
4
3
2
1
0
0
–5
–1
–2
–10
–15
0
20 40 60 80 100 120 140 160 180 200
OUTPUT CAPACITANCE LOADING (pF)
1
5
10
15
f(MHz)
20
25
30
35
40
Figure 1. ∆I vs Frequency
Figure 2. ∆t vs Output
PD
CC
(Worst Case) (Referenced from 15MHz)
Capacitance Loading (Typical)
78
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
AC ELECTRICAL CHARACTERISTICS
0°C ≤ T
≤ +75°C, 4.75V ≤ V ≤ 5.25V; R = 238Ω, R = 170Ω
amb
CC 1 2
2
TEST
CONDITION
PLC42VA12
1
SYMBOL
PARAMETER
FROM
TO
MIN
TYP
MAX
UNIT
(C (pF))
L
Set-up Time
t
t
t
t
Input; dedicated clock
(I, B, M) +/–
(I, B, M) +/–
(M) +/–
CK+
50
50
50
50
23
20
10
2
16
13
ns
ns
ns
ns
IS1
IS2
IS3
IS4
Input; P-term clock
(I, B, M) +/–
CK+
3
3
Preload; dedicated clock
Preload; P-term clock
3.5
(M) +/–
(I, B, M) +/–
–1.0
Input through complement array;
dedicated clock
3
3
t
(I, B, M) +/–
(I, B, M) +/–
CK+
50
50
50
40
34
ns
ns
IS5
IS6
Input through complement array;
P-term clock
t
(I, B, M) +/–
30
Propagation Delay
t
Propagation Delay
(I, B, M) +/–
(I, B,) +/–
(I, B, M) +/–
(I, B, M) +/–
50
50
20
36
35
55
ns
ns
PD1
PD2
Propagation Delay with complement
array (2 passes)
t
t
t
Clock to Output; Dedicated clock
Clock to output; P-term clock
Registered operating period;
CK+
(M) +/–
(M) +/–
50
50
13
18
17
27
ns
ns
CKO1
(I, B, M) +/–
CKO2
t
t
t
t
(I, B, M) +/–
(I, B, M) +/–
(M) +/–
(M) +/–
(M) +/–
(M) +/–
(M) +/–
50
50
50
50
29
31
40
47
27
29
ns
ns
ns
ns
RP1
Dedicated clock (t + t
)
IS1
CKO1
Registered operating period;
P-term clock (t + t
RP2
)
CKO2
IS2
Register preload operating period;
Dedicated clock (t + t
3
16.5
17
RP3
)
CKO1
IS3
Register preload operating period;
P-term clock (t + t
3
(M) +/–
RP4
)
CKO2
IS4
Registered operating period with comple-
ment array; dedicated clock (t
3
+
t
(I, B, M) +/–
(I, B, M) +/–
(M) +/–
(M) +/–
50
50
47
48
67
67
ns
ns
IS5
RP5
t
)
CKO1
Registered operating period with
complement array; P-term clock
3
t
RP6
(t
IS6
+ t
CKO2
)
4
t
t
Output Enable; from /OE pin
/OE –
(M) +/–
50
50
10
20
25
ns
ns
OE1
4
Output Enable; from P-term
(I, B, M) +/–
(B, M) +/–
12.5
OE2
Outputs dis-
abled
4
t
t
Output Disable; from /OE pin
/OE +
5
5
10
20
25
ns
ns
OD1
Outputs dis-
abled
4
Output Disable; from P-term
(I, B, M) +/–
(I, B, M) +/–
14.5
25
OD2
3
t
t
Preset to Output
(M) +/–
(M) +/–
50
50
35
15
ns
ns
PRO
3
Power-on Reset (Mn = 1)
V
CC
+
PPR
Hold Time
t
t
t
t
Input (Dedicated clock)
CK+
(I, B, M) +/–
(I, B, M) +/–
(M) +/–
50
50
50
50
0
5
–13
–7.5
–1.5
3.5
ns
ns
ns
ns
IH1
IH2
IH3
IH4
Input (P-term clock)
(I, B, M) +/–
CK+
3
3
Input; from Mn (Dedicated clock)
Input; from Mn (P-term clock)
5
(I, B, M) +/–
(M) +/–
10
Pulse Width
t
t
t
t
t
Clock High; Dedicated clock
Clock Low; Dedicated clock
Clock High; P-term clock
CK+
CK–
CK–
CK+
50
50
50
50
50
10
10
15
15
30
5
5
7
7
7
ns
ns
ns
ns
ns
CKH1
CKL1
CKH2
CKL2
CK+
CK–
Clock Low; P-term clock
CK–
CK+
3
Width of preset/reset input pulse
(I, B, M) +/–
(I, B, M) +/–
PRH
Notes on page 80.
79
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
AC ELECTRICAL CHARACTERISTICS (Continued)
0°C ≤ T
≤ +75°C, 4.75V ≤ V ≤ 5.25V; R = 238Ω, R = 170Ω
amb
CC
1
2
2
TEST
CONDITION
PLC42VA12
1
SYMBOL
PARAMETER
FROM
TO
MIN
TYP
MAX
UNIT
(C (pF))
L
Frequency of Operation
f
f
Dedicated clock frequency
P-term clock frequency
C+
C+
C+
C+
50
50
50
33
100
MHz
MHz
CK1
CK2
71.4
Registered operating frequency;
Dedicated clock (t + t
f
(I, B, M) +/–
(I, B, M) +/–
(M) +/–
(M) +/–
50
50
25
34.5
32.3
MHz
MHz
MAX1
MAX2
)
CKO1
IS1
Registered operating frequency;
P-term clock (t + t
f
21.3
)
CKO2
IS2
Register preload operating
frequency; Dedicated clock
3
3
3
3
f
f
f
f
(M) +/–
(M) +/–
(M) +/–
(M) +/–
(M) +/–
(M) +/–
50
50
50
50
37
60.6
58.8
21.3
20.8
MHz
MHz
MHz
MHz
MAX3
MAX4
MAX5
MAX6
(t
IS3
+ t
CKO1
)
Register preload operating
frequency; P-term clock
34.5
14.9
14.9
(t
IS4
+ t
CKO2
)
Registered operating frequency
with complement array;
(I, B, M) +/–
(I, B, M) +/–
Dedicated clock (t + t
)
IS5
CKO1
Registered operating frequency
with complement array;
P-term clock (t + t
)
IS6
CKO2
NOTES:
1. All typical values are at V = 5V, T
2. Refer also to AC Test Conditions (Test Load Circuit).
= +25°C. These limits are not tested/guaranteed.
amb
CC
3. These limits are not tested, but are characterized periodically and are guaranteed by design.
4. For 3-State output; output enable times are tested with C = 50pF to the 1.5V level, and S is open for high-impedance to High tests and
L
1
closed for high-impedance to Low tests. Output disable times are tested with C = 5pF. High-to-High impedance tests are made to an output
L
voltage of V = (V – 0.5V) with S open, and Low-to-High impedance tests are made to the V = (V + 0.5V) level with S closed.
T
OH
1
T
OL
1
BLOCK DIAGRAM
65 X 105 PROGRAMMABLE AND ARRAY
I1
64 LOGIC TERMS
41 CONTROL TERMS
I8
CK
I0/CLK
I9/OE
J
P
R L D
MUX
COMPLEMENT
JK/D
OMC OE
MUX
(10)
Q
64 X 32
PROGRAMMABLE
OR ARRAY
K
MUX
Q
M0 – M9
B0 – B1
BYPASS
80
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
OUTPUT MACRO CELL (OMC)
FROM AND ARRAY
O
E
LOAD PRESET RESET
CK
OE
F
CONTROL
C
0
1
OUTPUT ENABLE
SELECT MUX
0
P
J
R
CK
CLOCK
FROM OR ARRAY
SELECT
MUX
1
CLK
M
JK/D
MUX
1
M
FROM OR ARRAY
TO AND ARRAY
K
Q
OUTPUT
SELECT
MUX
FROM OR ARRAY
(REGISTER BYPASS)
TO AND ARRAY
These 14 configurations, combined with the
fully programmable OR array, make the
PLC42VA12 the most versatile and silicon
efficient of all the Output Macro Cell-type
PLDs.
source – make it possible to design
synchronous state machine functions,
event-driven state machine functions and
combinatorial (asynchronous) functions all on
the same chip.
Output Macro Cell Configuration
Philips Semiconductors unique Output Macro
Cell design represents a significant
advancement in the configurability of
multi-function Programmable Logic Devices.
The most significant Output Macro Cell
(OMC) feature is the implementation of the
register bypass function. Any of the 10 J-K/D
registers can be individually bypassed, thus
creating a combinatorial I/O path from the
AND array to the output pin. Unlike other
Output Macro Cell-type devices, the register
in the OMC is fully functional as a buried
register. Furthermore, both the combinatorial
I/O and the buried register have separate
input paths (from the AND array) and
separate feedback paths (to the AND array).
This feature provides the capability to operate
the buried register independently from the
combinatorial I/O.
Sophisticated control functions support
individual OE control and Reset functions
from the AND array. OE control is also
available from the I9/OE pin. Register Preset
and Load functions are controlled from the
AND array, in 2 banks of 4 for OMCs M1 –
M8. Output Macro Cells M0 and M9 have
individual Preset and Load Control terms.
The PLC42VA12 has 10 programmable
Output Macro Cells. Each can be individually
programmed in any of 5 basic configurations:
• Dedicated I/O (combinatorial) with
feedback to AND array
• Dedicated Input
• Combinatorial I/O with feedback and
Buried Register with feedback (register
bypass)
Output Polarity for the combinatorial I/O
paths is configurable via 12 programmable
EX-OR gates. The output of each register
can be configured as inverting (active Low) or
non-inverting (active High) via manipulation
of the logic equations.
• Registered Input
• Registered Output with feedback
Each of the registered options can be further
customized as J-K type or D-type, with either
an internally derived clock (from the AND
array) or clocked from an external source.
With these additional programmable options,
it is possible to program each Output Macro
Cell in any one of 14 different configurations.
The output of each buried register can also
be configured as inverting or non-inverting via
the input buffer which feeds back to the AND
array.
The PLC42VA12 is ideally suited for both
synchronous and asynchronous logic
functions. Eleven clock sources – 10 driven
from the AND array and one from an external
81
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
OUTPUT MACRO CELL PROGRAMMABLE OPTIONS
OMC Programmable Options
For purposes of programming, the Output
Macro Cell should be considered to be
partitioned into five separate blocks. As
shown in the drawing titled “Output Macro Cell
Programmable Options”, the programmable
blocks are: Register Select Options, Polarity
Options, Clock Options, OMC Configuration
Options and Output Enable Control Options.
OUTPUT MACRO CELL
REGISTER
SELECT
OPTIONS
CLOCK OPTIONS
OUTPUT
M
OMC
CONFIGURATION
OPTIONS
OUTPUT ENABLE
CONTROL
There is one programmable location
associated with each block except the Output
Enable Control block which has two
programmable fuse locations per OMC.
OPTIONS
POLARITY
OPTIONS
The following drawings detail the options
associated with each programmable block.
The associated programming codes are also
included. The table titled “Output Macro Cell
Configurations” (page 87) lists all the possible
combinations of the five programmable
options.
ARCHITECTURAL OPTIONS
REGISTER SELECT OPTIONS
Register Select Options
Each OMC Register can be configured either
as a dedicated D-type or a J-K flip-flop. The
Flip-Flop Control term, Fc, provides the
option to control each Register
P
R
dynamically—switching from D-type to J-K
type, based on the Fc control signal.
P
R
CK
CLOCK
OPTIONS
FROM
OR ARRAY
D
Register Preset and Reset are controlled
from the AND array. Each OMC has an
individual Reset Control term (RMn). The
Register Preset function is controlled in two
banks of 4 for OMCs M1 – M3 and M4 – M8
(via the control terms PA and PB). OMCs M0
and M9 have individual control terms (PM0
and PM9 respectively).
OMC
CONFIG.
OPTIONS
OUTPUT
CONTROL
OPTIONS
Q
FROM
AND ARRAY
CODE
REGISTER MODE (D or JK)
D-TYPE
A
L
F
CONTROL P-TERM
C
P
P
R
R
CK
CLOCK
OPTIONS
J
FROM
OR ARRAY
OMC
CONFIG.
OPTIONS
OUTPUT
CONTROL
OPTIONS
K
Q
FROM
AND ARRAY
CODE
REGISTER MODE (D or JK)
JK-TYPE
•
F
CONTROL P-TERM
–
C
Notes on page 87.
82
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
REGISTER SELECT OPTIONS (Continued)
P
P
R
P
R
F
C
R
CK
P
R
CK
CLOCK
OPTIONS
CLOCK
OPTIONS
FROM
OR ARRAY
J
D
FROM
OR ARRAY
OMC
CONFIG.
OPTIONS
OUTPUT
CONTROL
OPTIONS
OMC
CONFIG.
OPTIONS
OUTPUT
CONTROL
OPTIONS
K
Q
Q
FROM
AND ARRAY
FROM
AND ARRAY
REGISTER MODE (D or JK)
CODE
DYNAMICALLY CONTROLLABLE
CONTROL P-TERM
A
L or H
F
C
F
= LOW
F
= HIGH
C
C
1
POLARITY OPTIONS (for Combinatorial I/O Configurations Only )
Polarity Options
When an OMC is configured as a
FROM
OR ARRAY
Combinatorial I/O with Buried Register, the
polarity of the combinatorial path can be
programmed as Active-High or Active-Low. A
configurable EX-OR gate provides polarity
control.
OMC CONFIG.
OPTIONS
OUTPUT SELECT
OPTIONS
M
POLARITY
CODE
4
ACTIVE-HIGH (NON-INVERTING)
H
If an OMC is configured as a Registered
Output, /Q is propagated to the output pin.
Note that either Q or /Q can be fedback to
the AND array by manipulating the feedback
logic equations. (TRUE or COMPLEMENT).
FROM
OR ARRAY
OMC CONFIG.
OPTIONS
OUTPUT CONTROL
OPTIONS
M
POLARITY
CODE
4
L
ACTIVE-LOW (INVERTING)
CLOCK OPTIONS
Clock Options
In the unprogrammed state, all Output Macro
Cell clock sources are connected to the
External Clock pin (I /CLK pin 1). Each OMC
can be individually programmed such that its
CLK OPTIONS
CODE
A
REGISTER SELECT OPTIONS
EXTERNAL CLOCK
(FROM PIN 1)
0
P-term Clock (CK ) is enabled, thus disabling
it from the External Clock and providing
event-driven clocking capability.
n
D (OR J) CK
CLK
FROM
OR ARRAY
This feature supports multiple state machines,
clocked at several different rates, all on one
chip, or the ability to collect large amounts of
random logic, including 10 separately clocked
flip-flops.
OMC
CONFIG.
OPTIONS
OUTPUT
CONTROL
OPTIONS
(K)
Q
TO
AND ARRAY
CLK OPTIONS
CODE
REGISTER SELECT OPTIONS
CK
•
P-TERM CLOCK
D (OR J) CK
FROM
OR ARRAY
OMC
CONFIG.
OPTIONS
OUTPUT
CONTROL
OPTIONS
(K)
Q
TO
AND ARRAY
Notes on page 87.
October 22, 1993
83
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
OUTPUT MACRO CELL CONFIGURATION OPTIONS
REGISTER SELECT OPTIONS
CLOCK
OPTIONS
D (OR J) CK
REGISTER SELECT OPTIONS
FROM
OR ARRAY
CLOCK
D (OR J) CK
(K)
Q
OPTIONS
TO
FROM
OR ARRAY
OMC
AND ARRAY
M
(K)
Q
CONFIG.
OPTIONS
COMBINATORIAL OPTIONS
TO
FROM
OR
ARRAY
OUTPUT
CONTROL
OPTIONS
AND ARRAY
M
CODE
OMC CONFIGURATION
CODE
A
OMC CONFIGURATION
COMBINATORIAL OUTPUT
WITH BURIED REGISTER
(D or JK)
•
REGISTERED OUTPUT
(D or JK)
OMC Configuration Options
L
Each OMC can be configured as a Registered
Output with feedback, a Registered Input or a
Combinatorial I/O with Buried Register.
Dedicated Input and dedicated I/O
Note that an OMC can be configured as
either a Combinatorial I/O (with Buried
Register) or a Registered Output with
feedback and it can still be used as a
Registered Input. By disabling the outputs via
any OE control function, the M pin can be
used as an input. When the Load Control
P-term is asserted HIGH, the register is
preloaded from the M pin(s). When the L
P-term is Active-Low and the output is
enabled, the OMC will again function as
configured (either a combinatorial I/O or a
registered output with feedback). This feature
is suited for synchronizing input signals prior
to commencing a state sequence.
M
configurations are also possible.
When the Combinatorial I/O option is
selected, (the Register Bypass option), the
Buried Register remains 100% functional, with
its own inputs from the AND array and a
separate feedback path. This unique feature is
ideal for designing any type of state machine;
synchronous Mealy-types that require both
Buried and Output Registers, or asynchronous
Mealy-types that require buried registers and
combinatorial output functions. Both
CLOCK
OPTIONS
D
CK
Q
C
OUTPUT
CONTROL
OPTIONS
TO AND
ARRAY
CODE
OMC CONFIGURATION
REGISTERED INPUT
synchronous and asynchronous Moore-type
state machines can also be easily
A or •5
accommodated with the flexible OMC
structure.
6
LOAD CONTROL P-TERM
H
Notes on page 87.
84
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
OUTPUT CONTROL OPTIONS
Output Enable Control Options
Similar to the Clock Options, the Output
Enable Control for each OMC can be
connected either to an external source
(I9/OE, pin 13) or controlled from the AND
OE
OMC
CONFIG.
OPTIONS
M
array (P-terms DM ). Each Output can also
n
be permanently enabled.
Output Enable control for the two
bi-directional I/O (B pins 10 and 11) is from
the AND array only (P-terms DB0 and DB1
respectively).
TO
AND ARRAY
CODE
A
CODE
A
OE CONTROL FUSE
FROM OE PIN
E
FUSE
n
FROM OE PIN
DM
OMC
CONFIG.
OPTIONS
M
OMC
CONFIG.
OPTIONS
M
TO
TO
AND ARRAY
AND ARRAY
CODE
CODE
A or 0
CODE
A
CODE
0
OE FUSE
OE CONTROL FUSE
ALWAYS ENABLED
E
FUSE
E FUSE
n
n
•
FROM P-TERM CONTROL
ALWAYS ENABLED
FROM P-TERM CONTROL
COMPLEMENT ARRAY DETAIL
Complement Array Detail
The complement array is a special sequencer
feature that is often used for detecting illegal
states. It is also ideal for generating
IF-THEN-ELSE logic statements with a
minimum number of product terms.
P
P
P
P
P
F
C
LM
PM
RM
n
63
62
61
1
0
n
n
The concept is deceptively simple. If you
subscribe to the theory that the expressions
(/A * /B * /C) and (A + B + C) are equivalent,
you will begin to see the value of this single
term NOR array.
The complement array is a single OR gate
with inputs from the AND array. The output of
the complement array is inverted and fedback
to the AND array (NOR function). The output
of the array will be LOW if any one or more of
the AND terms connected to it are active
(HIGH). If, however, all the connected terms
are inactive (LOW), which is a classic
unknown state, the output of the complement
array will be HIGH.
C0
A
B
D
E
Consider the product terms A, B and D that
represent defined states. They are also
connected to the input of the complement
array. When the condition (not A and not B
and not D) exists, the Complement Array will
detect this and propagate an Active-High
signal to the AND array. This signal can be
connected to product term E, which could be
used in turn to preset the state machine to
known state. Without the complement array,
one would have to generate product terms for
all unknown or illegal states. With very
complex state machines, such an approach
can be prohibitive, both in terms of time and
wasted resources.
C0
TO OR ARRAY
TO OMCs AND BIDIRECTIONAL I/O
Notes on page 87.
October 22, 1993
85
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
PLC42VA12 logic designs can also be
configuration have been previously defined in
the Architectural Options section.
LOGIC PROGRAMMING
generated using the program table entry
format, which is detailed on the following
pages. This program table entry format is
supported by SNAP only.
The PLC42VA12 is fully supported by
industry standard (JEDEC compatible) PLD
CAD tools, including Philips Semiconductors
SNAP design software package. ABEL and
CUPL design software packages also
support the PLC42VA12 architecture.
PROGRAMMING AND
SOFTWARE SUPPORT
Refer to Section 9 (Development Software)
and Section 10 (Third-party Programmer/
Software Support) of this data handbook for
additional information.
To implement the desired logic functions, the
state of each logic variable from logic
equations (I, B, O, P, etc.) is assigned a
symbol. The symbols for TRUE,
COMPLEMENT, INACTIVE, PRESET, etc.,
are defined below. Symbols for OMC
All packages allow Boolean and state
equation entry formats. SNAP, ABEL and
CUPL also accept, as input, schematic
capture format.
LOGIC IMPLEMENTATION
“AND” ARRAY – (I), (B), (Qp)
I, B, Q
I, B, Q
I, B, Q
I, B, Q
I, B, Q
I, B, Q
I, B, Q
I, B, Q
I, B, Q
I, B, Q
I, B, Q
I, B, Q
(T, F , L, P, R, D)
(T, F , L, P, R, D)
C
(T, F , L, P, R, D)
(T, F , L, P, R, D)
C n
C
n
n
C
n
CODE
O
CODE
H
CODE
L
CODE
–
STATE
STATE
I, B, Q
STATE
I, B, Q
STATE
1
DON’T CARE
INACTIVE
“COMPLEMENT” ARRAY – (C)
C
C
C
C
C
C
C
C
(T , F
)
(T , F
)
(T , F
)
(T , F )
n C
n
C
n
C
n
C
CODE
O
CODE
A
CODE
CODE
–
ACTION
1, 3
ACTION
ACTION
ACTION
•
PROPAGATE
TRANSPARENT
GENERATE
INACTIVE
“OR” ARRAY – (J-K Type)
T
n
T
T
T
n
n
n
J
Q
J
Q
J
Q
J
Q
M = DISABLED
M = DISABLED
M = DISABLED
M = DISABLED
K
K
K
K
CODE
CODE
CODE
CODE
ACTION
TOGGLE
ACTION
SET
ACTION
RESET
ACTION
HOLD
O
H
L
–
“OR” ARRAY
“OR” ARRAY – (D-Type)
T
T
n
n
T
n
T
n
J
Q
J
Q
P, R, L
(OR B)
P, R, L
(OR B)
M = ENABLED
M = ENABLED
K
K
CODE
CODE
CODE
CODE
T
STATUS
1
T
STATUS
T
STATUS
T STATUS
n
n
n
n
A
INACTIVE
A
INACTIVE (RESET)
•
ACTIVE (SET)
•
ACTIVE
Notes on page 87.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
86
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
LOGIC IMPLEMENTATION (Continued)
OUTPUT MACRO CELL CONFIGURATIONS
PROGRAMMING CODES
OMC CONFIGURATION POLARITY
OUTPUT MACRO CELL
CONFIGURATION
REGISTER SELECT
FUSE
CLOCK
FUSE
FUSE
FUSE
Combinatorial I/O with Buried D-type register
•
•
External clock source
P-term clock source
A
A
H or L
H or L
A
•
Combinatorial I/O with Buried J-K type register
•
•
•
•
External clock source
P-term clock source
H or L
H or L
A
•
Registered Output (D-type) with feedback
External clock source
A
A
A
A
N/A
N/A
A
•
P-term clock source
Registered Output (J-K type) with feedback
•
•
External clock source
P-term clock source
A
A
N/A
N/A
A
•
Registered Input (Clocked Preload) with feedback
A or •5
A or •5
5
5
External clock source
P-term clock source
A
Optional
Optional
A
•
A
OUTPUT CONTROL FUSES
8
OUTPUT ENABLE CONTROL
CONFIGURATION
OE CONTROL FUSE
En FUSES
CONTROL SIGNAL
OMC controlled by /OE pin
Output Enabled
A
A
Low
Output Disabled
High
•
OMC controlled by P-term
Output Enabled
A or 0
High
Low
Output Disabled
Output always Enabled
A
0
Not Applicable
NOTES:
1. This is the initial (unprogrammed) state of the device.
2. Any gate will be unconditionally inhibited if both the TRUE and COMPLEMENT fuses are left intact.
3. To prevent oscillations, this state is not allowed for Complement Array fuse pairs that are coupled to active product terms.
4. The OMC Configuration fuse must be programmed as Combinatorial I/O in order to make use of the Polarity Option.
5. Regardless of the programmed state of the OMC Configuration fuse, an OMC can be used as a Registered Input. Note that the Load Control
P-term must be asserted Active-High.
6. Output must be disabled.
7. Program code definitions:
A
= Active (unprogrammed fuse)
0, • = Inactive (programmed fuse)
–
H
L
= Don’t Care (both TRUE and COMPLEMENT fuses unprogrammed)
= Active-High connection
= Active-Low connection
8. OE control for B0 and B1 (Pins 10 and 11) is from the AND array only.
87
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
TIMING DIAGRAMS
TIMING DEFINITIONS
SYMBOL PARAMETER
+3V
0V
f
f
Clock Frequency; External Clock
Clock Frequency; P-term Clock
CK1
I, B, M
(INPUTS)
1.5V
1.5V
CK2
Width of Input Clock Pulse;
External Clock
t
t
t
t
t
t
CKH1
CKH2
CKL1
CKL2
IH2
IS2,6
+3V
Width of Input Clock Pulse;
P-term Clock
P-TERM CK
(I, B, M)
1.5V
1.5V
1.5V
0V
V
Interval between Clock pulses;
External Clock
t
t
t
IS2,6
CKH2
CKL2
OH
Interval between Clock Pulses;
P-term Clock
M
V
1.5V
T
(OUTPUTS)
V
Delay between the Positive
Transition of External Clock and
when M Outputs become valid.
OL
t
CKO2
t
OD1,2
t
CKO1
CKO2
t
RP2,6
+3V
0V
I, B, M, OE TERM OR
OE PIN
(OUTPUT ENABLE)
Delay between the Positive
Transition of P-term Clock and
when M Outputs become valid.
1.5V
1.5V
t
t
OE1,2
Delay between beginning of Valid
Input and when the M outputs
become Valid when using
External Clock.
t
RP1
RP2
Flip-Flop Outputs with P-term Clock
Delay between beginning of Valid
Input and when the M outputs
become Valid when using P-term
Clock.
t
+3V
0V
I, B, M
(INPUTS)
1.5V
1.5V
Delay between beginning of Valid
Input and when the M outputs
become Valid when using
Preload Inputs (from M pins) and
External Clock.
t
RP3
RP4
t
t
IS1,5
IH1
+3V
1.5V
1.5V
1.5V
EXTERNAL CK
Delay between beginning of Valid
Input and when the M outputs
become valid when using
Preload inputs (from M pins) and
P-term Clock.
0V
V
t
t
t
IS1,5
CKH1
CKL1
t
OH
M
V
1.5V
T
(OUTPUTS)
Delay between beginning of Valid
Input and when the M outputs
become Valid when using Com-
plement Array and External
clock.
V
OL
t
CKO1
t
OD1,2
t
RP1,5
t
t
RP5
+3V
0V
I, B, M, OE TERM
OR OE PIN
(OUTPUT ENABLE)
1.5V
1.5V
Delay between beginning of Valid
Input and when the M outputs
become Valid when using Com-
plement Array and P-term Clock.
t
OE1,2
RP6
Flip-Flop Outputs with External Clock
Minimum guaranteed Operating
Frequency; Dedicated Clock
f
f
MAX1
Minimum guaranteed Operating
Frequency; P-term Clock
MAX2
+3V
0V
V
Minimum guaranteed Operating
Frequency using Preload;
Dedicated Clock (M pin to M pin)
I, B
(INPUTS)
f
f
f
f
t
1.5V
MAX3
MAX4
MAX5
MAX6
IH1
Minimum guaranteed Operating
Frequency using Preload; P-term
Clock (M pin to M pin)
t
PD
OH
B, M
(COMBINATORIAL
OUTPUTS)
1.5V
V
T
Minimum guaranteed Operating
Frequency using Complement
Array; Dedicated Clock
V
OL
t
t
OD2
OE2
+3V
0V
I, B, M, OE TERM
OR OE PIN
(OUTPUT ENABLE)
Minimum Operating Frequency
using Complement Array; P-term
Clock
+1.5V
+1.5V
Required delay between positive
transition of External Clock and
end of valid input data.
Gated Outputs
88
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
TIMING DIAGRAMS (Continued)
TIMING DEFINITIONS (Continued)
SYMBOL PARAMETER
+3V
0V
I, B
1.5V
1.5V
(LOAD SELECT)
Required delay between positive
transition of P-term Clock and
end of valid input data.
t
IH2
IH3
+3V
0V
I, B, OE TERM OR OE PIN
(OUTPUT ENABLE)
1.5V
1.5V
t
Required delay between positive
transition of External Clock and
end of valid input data when us-
ing Preload Inputs (from M pins).
t
OE1,2
L
Required delay between positive
transition of P-term Clock and
end of valid input data when us-
ing Preload Inputs (from M pins).
t
IH4
+3V
0V
M
1.5V
V
(FORCED D
t t
IS3,4
)
IN
T
(INPUT)
Required delay between begin-
ning of valid input and positive
transition of External Clock.
t
OD1,2
IH3,4
t
t
t
IS1
CKL
+3V
0V
P-TERM OR
EXTERNAL CK
Required delay between begin-
ning of valid input and positive
transition of P-term Clock input.
t
CKH
t
IS2
IH3,4
Q
(D
)
IN
Required delay between
beginning of valid Preload input
(from M pins) and positive
transition of External Clock.
t
t
t
t
t
t
t
t
IS3
Flip-Flop Input Mode (Preload)
Required delay between
+3V
0V
beginning of valid Preload input
(from M pins) and positive
transition of P-term Clock input.
I, B, M
(INPUTS)
1.5V
IS4
+3V
0V
Required delay between
P-TERM OR
EXTERNAL CK
1.5V
beginning of valid input through
Complement Array and positive
transition of External Clock.
IS5
t
*
t
t
CKO
IS
IS
+3V
0V
Required delay between
PRESET/RESET
(I, B, M INPUTS)
1.5V
1.5V
beginning of valid input through
Complement Array and positive
transition of P-term Clock input.
IS6
t
PRH
(PRESET)
(RESET)
Q
Delay between beginning of
Output Enable signal (Low) from
/OE pin and when Outputs
become valid.
t
OE1
OE2
OD1
OD2
PRO
V
OH
(RESET)
(PRESET)
M
1.5V
1.5V
(OUTPUTS)
Delay between beginning of
Output Enable signal (High or
Low) from OE P-term and when
Outputs become valid.
V
OL
*Preset and Reset functions override Clock. However, M outputs may glitch with
the first positive Clock Edge if t cannot be guaranteed by the user.
IS
Delay between beginning of
Output Enable signal (HIGH) from
/OE pin and when Outputs
become disabled.
Asynchronous Preset/Reset
+5V
4.5V
Delay between beginning of
Output Enable signal (High or
Low) from OE P-term and when
Outputs become disabled.
V
CC
0V
V
t
PPR
M
OH
Delay between beginning of valid
input and when the Outputs be-
come valid (Combinatorial Path).
(OUTPUTS)
1.5V
1.5V
1.5V
t
t
PD
V
t
OL
CKO1,2
Width of Preset/Reset Pulse.
PRH
+3V
0V
I, B, M
(INPUTS)
1.5V
Delay between beginning of valid
Preset/Reset Input and when the
registered Outputs become
Preset (“1”) or Reset (“0”).
t
PRO
t
t
IH
IS
+3V
0V
1.5V
t
1.5V
t
1.5V
P-TERM OR
EXTERNAL CK
Delay between V (after
CC
power-up) and when flip-flops
become Reset to “0”. Note:
Signal at Output (M pin) will be
inverted.
t
IS
CKH
CKL
t
PPR
t
CK1,2
Power-On Reset
89
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
LOGIC FUNCTION
PLC42VA12 UNPROGRAMMED
STATE
A factory shipped unprogrammed device is
configured such that all cells are in a
conductive state.
ERASURE CHARACTERISTICS
(For Quartz Window Packages
Q3 Q2 Q1 Q0
Only)
1
0
1
0
PRESENT STATE
. . .
NEXT STATE
S
R
The erasure characteristics of the
PLC42VA12 devices are such that erasure
begins to occur upon exposure to light with
wavelength shorter than approximately 4000
Angstroms (Å). It should be noted that
sunlight and certain types of fluorescent
lamps have wavelengths in the 3000 – 4000Å
range. Data shows that constant exposure to
room level fluorescent lighting could erase a
typical PLC42VA12 in approximately three
years, while it would take approximately one
week to cause erasure when exposed to
direct sunlight. If the PLC42VA12 is to be
exposed to these types of lighting conditions
for extended periods of time, opaque labels
should be placed over the window to prevent
unintentional erasure.
A
B C
STATE REGISTER
The following are:
0
0
0
1
2
S
n + 1
ACTIVE:
– OR array logic terms
SET Q : J = (Q
Q
Q ) A B C . . .
0
0
1 0
– Output Macro Cells M1 – M8;
K
= 0
0
• D-type registered outputs (D = 0)
– External clock path
RESET Q : J = 0
1
1
K
= (Q
Q
Q
Q
Q )
0
A
B
C . . .
1
3
2
1
– Inputs: B0, B1, M0, M9
HOLD Q : J = 0
2
2
2
K
= 0
INACTIVE:
– AND array logic and control terms (except
RESET Q : J = (Q
Q
Q
)
0
A
A
B
B
C . . .
C . . .
3
3
3
3
2
2
1
K
= (Q
Q
Q
Q )
flip-flop mode control term, F )
3
1 0
C
– Bidirectional I/O (B0, B1);
NOTE:
• Inputs are active. Outputs are 3-Stated
via the OE P-terms, D0 and D1.
Similar logic functions are applicable for D
mode flip-flops.
The recommended erasure procedure for the
PLC42VA12 is exposure to shortwave
ultraviolet light which has a wavelength of
2537 Angstroms (Å). The integrated dose
(i.e., UV intensity × exposure time) for
erasure should be a minimum of
• D-type registers (D = 0).
– Output Macro Cells M0 and M9;
• Bidirectional I/O, 3-Stated via the OE
P-terms, DM0 and DM9. The inputs are
active.
FLIP-FLOP TRUTH TABLE
OE
H
L
L
CK
P
R
n
J
K
Q
M
Hi-Z
H
n
n
n
2
15Wsec/cm . The erasure time with this
– P-term clocks
dosage is approximately 30 to 35 minutes
using an ultraviolet lamp with a
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
– Complement Array
– J-K Flip-Flop mode
L
X
X
H
L
L
L
2
12,000µW/cm power rating. The device
should be placed within one inch of the lamp
tubes during erasure. The maximum
integrated dose a CMOS EPLD can be
exposed to without damage is
L
H
H
L
L
L
L
L
L
L
L
↑
↑
↑
↑
L
L
L
L
L
L
L
L
L
L
L
H
L
Q
L
Q
H
L
PROGRAMMING AND
SOFTWARE SUPPORT
Refer to Section 9 (Development Software)
and Section 10 (Third-party Programmer/
Software Support) in this data handbook for
additional information.
2
2
7258Wsec/cm (1 week @ 12000µW/cm ).
Exposure of these CMOS EPLDs to high
intensity UV light for longer periods may
cause permanent damage.
H
H
H
Q
H
Q
H
H
H
H
↑
↑
↑
↑
L
L
L
L
L
H
L
L
H*
L*
H
H
The maximum number of guaranteed
erase/write cycles is 50. Data retentions
exceeds 20 years.
+10V
X
X
X
X
X
X
L
H
L
L
H**
L**
H
H
NOTES:
1. Positive Logic:
J-K = T + T + T + ... + T
0
1
2
31
T = C (I0 I1 I2...) (Q0 Q1...)
n
(B0 B1...)
2. ↑ denotes transition for Low to High level.
3. X = Don’t care
4. * = Forced at M pin for loading the J-K
n
flip-flop in the Input mode. The load
control term, L must be enabled (HIGH)
n
and the p-terms that are connected to the
associated flip-flop must be forced LOW
(disabled) during Preload.
5. At P = R = H, Q = H. The final state of Q
depends on which is released first.
6. ** = Forced at F pin to load J/K flip-flop
n
(Diagnostic mode).
90
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
PROGRAM TABLE
91
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42 × 105 × 12)
PLC42VA12
SNAP RESOURCE SUMMARY DESIGNATIONS
P
P
F
L
P
R
CK
LM
PM
RM
CK
DM
DM
DB
n
63
0
C
n
n
n
n
n
n
n
n
n
n
I9/OE
I1 – I8
DIN42
NIN42
X8
I0/CK
NOR
AND
ANDFC
CAND
X2
X1
X2
X2
X8
X8
X2
X2
X2
X8
X2
X2
NTIM42
CLK
CONTROL
DTIM42
OR
X8
P
J
R
CK42
CK
X8
E
(X2)
n
OE
n
X8
OR
K
Q
X8
OMC
CONFIG.
OENAND
OEBUFF
JKFFPR42
X8
POLARITY
M1 – M8
TNOO42
EXOR42
CLK
CONTROL
OR
P
J
R
X2
CK42
CK
X2
E
(X2)
X2
n
OE
n
X2
K
Q
OENAND
OMC
OR
CONFIG.
JKFFPR42
OEBUFF
M0, M9
X2
POLARITY
POLARITY
TNOU42
EXOR42
B0 – B1
X2
TNOU42
EXOR42
92
October 22, 1993
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