PLS100 [NXP]
Programmable logic arrays 16 】 48 】 8; 可编程逻辑阵列16 】 48 】 8型号: | PLS100 |
厂家: | NXP |
描述: | Programmable logic arrays 16 】 48 】 8 |
文件: | 总8页 (文件大小:131K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16 × 48 × 8)
PLS100/PLS101
DESCRIPTION
FEATURES
PIN CONFIGURATIONS
The PLS100 (3-State) and PLS101 (Open
Collector) are bipolar, fuse Programmable
Logic Arrays (PLAs). Each device utilizes the
standard AND/OR/Invert architecture to
directly implement custom sum of product
equations.
• Field-programmable (Ni-Cr link)
• Input variables: 16
N Package
1
2
28
V
FE*
I7
CC
• Output functions: 8
27 I8
• Product terms: 48
3
26 I9
I6
Each device consists of 16 dedicated inputs
and 8 dedicated outputs. Each output is
capable of being actively controlled by any or
all of the 48 product terms. The True,
Complement, or Don’t Care condition of each
of the 16 inputs and be ANDed together to
comprise one P-term. All 48 P-terms can be
selectively ORed to each output.
• I/O propagation delay: 50ns (max.)
• Power dissipation: 600mW (typ.)
• Input loading: –100µA (max.)
• Chip Enable input
4
25 I10
24 I11
23 I12
I5
5
I4
6
I3
7
22
I2
I13
21 I14
I15
8
I1
• Output option:
– PLS100: 3-State
9
20
I0
10
11
12
13
19 CE
18 F0
17 F1
16 F2
15 F3
F7
F6
F5
F4
The PLS100 and PLS101 are fully TTL
compatible, and chip enable control for
expansion of input variables and output
inhibit. They feature either Open Collector or
3-State outputs for ease of expansion of
product terms and application in
– PLS101: Open-Collector
• Output disable function:
– 3-State: Hi-Z
– Open-Collector: High
GND 14
bus-organized systems.
*
Fuse Enable Pin: It is recommended that this pin
be left open or connected to ground during normal
operation.
Order codes are listed in the Ordering
Information Table.
APPLICATIONS
• CRT display systems
N = Plastic DIP (600mil-wide)
• Code conversion
• Peripheral controllers
• Function generators
• Look-up and decision tables
• Microprogramming
A Package
FE
1
I5 I6 I7
I8 I9
V
CC
28 27 26
4
3
2
5
6
25
24
23
22
21
20
19
I4
I3
I2
I1
I0
I10
I11
I12
• Address mapping
7
• Character generators
• Data security encoders
• Fault detectors
8
I13
I14
I15
CE
9
10
11
F7
F6
• Frequency synthesizers
• 16-bit to 8-bit bus interface
• Random logic replacement
12 13 14 15 16 17 18
GND
F1 F0
F5 F4
F3 F2
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
3-STATE
PLS100N
PLS100A
OPEN COLLECTOR
PLS101N
DRAWING NUMBER
0413D
28-Pin Plastic Dual In-Line 600mil-wide
28-Pin Plastic Leaded Chip Carrier
PLS101A
0401F
49
October 22, 1993
853–0308 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16 × 48 × 8)
PLS100/PLS101
LOGIC DIAGRAM
(LOGIC TERMS–P)
I0
I1
I2
I3
I4
I5
I6
I7
9
8
7
6
5
4
3
2
I8 27
I9 26
I10 25
I11 24
I12 23
I13 22
I14 21
I15
20
S
0
F0
F1
F2
F3
F4
F5
F6
F7
CE
18
17
16
15
13
12
11
10
19
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
S
S
S
S
S
S
S
1
2
3
4
5
6
7
47
40 39
32 31
24 23
1615
8
7
0
NOTES:
1. All AND gate inputs with a blown link float to a logic “1”.
2. All OR gate inputs with a blown fuse float to logic “0”.
3.
Programmable connection.
50
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16 × 48 × 8)
PLS100/PLS101
FUNCTIONAL DIAGRAM
I0
I1
TYPICAL CONNECTION
I15
TYPICAL CONNECTION
S
0
6
7
F0
F6
F7
S
S
P
P
P
47
0
1
CE
1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Supply voltage
RATINGS
+7.0
UNIT
V
CC
V
IN
V
O
V
DC
V
DC
V
DC
Input voltage
Output voltage
Input current
Output current
+5.5
+5.5
I
I
±30
mA
mA
°C
IN
OUT
+100
T
amb
Operating temperature range
Storage temperature range
0 to +75
–65 to +150
T
stg
°C
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other conditions above
those indicated in the operational and programming specification of the device is not
implied.
The PLS100 device is also processed to
military requirements for operation over the
military temperature range. For specifications
THERMAL RATINGS
TEMPERATURE
and ordering information consult the Philips
Semiconductors Military Data Handbook.
Maximum junction
Maximum ambient
150°C
75°C
Allowable thermal rise
ambient to junction
75°C
51
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16 × 48 × 8)
PLS100/PLS101
DC ELECTRICAL CHARACTERISTICS
0°C ≤ T
≤ +75°C, 4.75V ≤ V ≤ 5.25V
amb
CC
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2
Input voltage
V
V
V
High
Low
V
= MAX
= MIN
2.0
V
V
V
IH
CC
V
0.8
IL
CC
3
Clamp
V
CC
= MIN, I = –12mA
–0.8
0.35
–1.2
IC
IN
2
Output voltage
V
= MIN
CC
4
V
V
High (PLS100)
I
= –2mA
= 9.6mA
2.4
V
V
OH
OH
OL
5
Low
I
0.45
OL
Input current
I
IH
I
IL
High
Low
V
= 5.5V
< 1
25
µA
µA
IN
V
IN
= 0.45V
–10
–100
Output current
I
Hi-Z state (PLS100)
CE = High, V = MAX
CC
O(OFF)
V
= 5.5V
1
40
µA
µA
OUT
V
OUT
= 0.45V
–1
–40
–70
170
3, 6
I
I
Short circuit (PLS100)
CE = Low, V
= 0V
–15
mA
mA
OS
OUT
7
V
CC
supply current
V
= MAX
120
CC
CC
Capacitance
CE = High, V = 5.0V
CC
C
C
Input
Output
V
= 2.0V
8
pF
pF
IN
IN
V
OUT
= 2.0V
17
OUT
NOTES:
1. All typical values are at V = 5V, T
= +25°C.
amb
CC
2. All voltage values are with respect to network ground terminal.
3. Test one pin at a time.
4. Measured with V applied to CE and a logic high stored.
IL
5. Measured with a programmed logic condition for which the output test is at a low logic level. Output sink current is applied through a resistor
to V
.
CC
6. Duration of short circuit should not exceed 1 second.
7. I is measured with the Chip Enable input grounded, all other inputs at 4.5V and the outputs open.
CC
52
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16 × 48 × 8)
PLS100/PLS101
AC ELECTRICAL CHARACTERISTICS
0°C < T
< +75°C, 4.75 < V < 5.25V, R = 470Ω, R = 1kΩ
amb
CC
1
2
LIMITS
1
SYMBOL
Propagation delay
PARAMETER
TO
FROM
MIN
TYP
MAX
UNIT
2
t
t
Input
Output
Output
Input
35
15
50
30
ns
ns
PD
CE
3
Chip Enable
Chip Enable
Disable time
3
t
Chip Disable
Output
Chip Enable
15
30
ns
CD
NOTES:
1. All typical values are at V = 5V. T
= +25°C.
amb
CC
2. All propagation delays are measured and specified under worst case conditions.
3. For 3-State output; output enable times are tested with C = 30pF to the 1.5V level, and S is open for high-impedance to High tests and
L
1
closed for high-impedance to Low tests. Output disable times are tested with C = 5pF. High-to-High impedance tests are made to an output
L
voltage of V = (V – 0.5V) with S open, and Low-to-High impedance tests are made to the V = (V + 0.5V) level with S closed.
T
OH
1
T
OL
1
VOLTAGE WAVEFORMS
TEST LOAD CIRCUIT
+3.0V
90%
+5V
V
S
CC
1
10%
90%
0V
C
C
2
R
1
1
t
t
F
5ns
5ns
R
F
0
I
0
+3.0V
C
R
L
2
INPUTS
DUT
GND
I
15
10%
0V
CE
F
7
5ns
MEASUREMENTS:
5ns
OUTPUTS
All circuit delays are measured at the +1.5V level of in-
puts and outputs, unless otherwise specified.
NOTE:
and C are to bypass V to GND.
CC
C
1
2
Input Pulses
TIMING DEFINITIONS
TIMING DIAGRAM
+3.0V
0V
SYMBOL
PARAMETER
INPUT
1.5V
t
t
t
Delay between beginning of
Chip Enable Low (with Input
valid) and when Data Output
becomes valid.
CE
CD
PD
+3.0V
0V
1.5V
t
1.5V
t
CE
Delay between when Chip
Enable becomes High and
Data Output is in off state
(Hi-Z or High).
CE
CD
V
OH
1.5V
1.5V
F0 – F7
Delay between beginning of
valid Input (with Chip Enable
Low) and when Data Output
becomes valid.
V
OL
t
PD
Read Cycle
53
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16 × 48 × 8)
PLS100/PLS101
PLS100/PLS101 logic designs can also be
COMPLEMENT, INACTIVE, PRESET, etc.,
are defined below.
LOGIC PROGRAMMING
generated using the program table entry
format detailed on the following pages. This
program table entry format is supported by
the Philips Semiconductors’ SNAP PLD
design software package.
PLS100/PLS101 is fully supported by
industry standard (JEDEC compatible) PLD
CAD tools, including Philips Semiconductors’
SNAP, Data I/O Corporation’s ABEL and
Logical Devices Inc.’s CUPL design
software packages.
PROGRAMMING AND
SOFTWARE SUPPORT
Refer to Section 9 (Development Software)
and Section 10 (Third-party Programmer/
Software Support) of this dat handbook for
additional informational.
To implement the desired logic functions, the
state of each logic variable from logic
equations (I, B, O, P, etc.) is assigned a
symbol. The sumbols for TRUE,
All packages allow Boolean and state
equation entry formats. SNAP, ABEL and
CUPL also accept, as input, schematic
capture format.
OUTPUT POLARITY – (F)
S
S
F
O, B
X
ACTIVE LEVEL
CODE
L
ACTIVE LEVEL
CODE
H
1
HIGH
LOW
(INVERTING)
(NON-INVERTING)
“AND” ARRAY – (I)
I
I
I
I
I
I
I
I
I
I
I
I
P
P
P
P
STATE
CODE
STATE
I
CODE
H
STATE
I
CODE
L
STATE
CODE
–
1,2
O
DON’T CARE
INACTIVE
“OR” ARRAY – (F)
P
P
S
S
CODE
A
CODE
P
STATUS
1
P STATUS
n
INACTIVE
n
•
ACTIVE
NOTES:
1. This is the initial unprogrammed state of all links. It is normally associated with all unused
(inactive) AND gates P .
n
2. Any gate P will be unconditionally inhibited if any one of its (I) link pairs is left intact.
n
VIRGIN STATE
The PLS100/101 virgin devices are factory
shipped in an unprogrammed state, with all
fuses intact, such that:
1. All P terms are disabled (inactive) in the
n
AND array.
2. All P terms are active in the OR array.
n
3. All outputs are Active-High.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
54
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16 × 48 × 8)
PLS100/PLS101
PROGRAM TABLE
POLARITY
OR
AND
INPUT (I )
T
E
R
M
m
OUTPUT (F )
P
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
PIN
NO.
20 21 22 23 24 25 26 27
2
3
4
5
6
7
8
9
10 11 12 13 15 16 17 18
55
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(16 × 48 × 8)
PLS100/PLS101
SNAP RESOURCE SUMMARY DESIGNATIONS
DIN100
NIN100
I0
I1
I15
AND
TOUT100
F0
OR
S
0
6
7
S
S
F6
F7
EXOR100
P
P
P
47
0
1
CE
NOE100
56
October 22, 1993
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