PMBF107 [NXP]
N-channel enhancement mode vertical D-MOS transistor; N沟道增强型垂直的D- MOS晶体管
| 型号： | PMBF107 |
| 厂家： | 
NXP |
| 描述： | N-channel enhancement mode vertical D-MOS transistor |
| 文件： | 总12页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
PMBF107
N-channel enhancement mode
vertical D-MOS transistor
April 1995
Product specification
File under Discrete Semiconductors, SC13b
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF107
FEATURES
QUICK REFERENCE DATA
• Direct interface to C-MOS, TTL,
etc.
SYMBOL
PARAMETER
CONDITIONS MAX. UNIT
VDS
ID
drain-source voltage
drain current
200
100
28
V
• High-speed switching
DC value
mA
Ω
• No secondary breakdown.
RDS(on)
drain-source on-resistance
ID = 20 mA
VGS = 2.6 V
DESCRIPTION
VGS(th)
gate-source threshold voltage
ID = 1 mA
2.4
V
VGS = VDS
N-channel enhancement mode
vertical D-MOS transistor in a SOT23
envelope and intended for use as a
line current interruptor in telephone
sets and for applications in relay,
high-speed and line transformer
drivers.
PIN CONFIGURATION
d
s
ndbook, halfpage
3
PINNING - SOT23
PIN
1
DESCRIPTION
g
gate
1
2
2
source
drain
MBB076 - 1
Top view
MSB003
3
Fig.1 Simplified outline and symbol.
April 1995
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF107
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134).
SYMBOL
PARAMETER
drain-source voltage
CONDITIONS
MIN. MAX. UNIT
VDS
±VGSO
ID
−
200
20
V
gate-source voltage
drain current
open drain
DC value
−
V
−
100
250
250
150
150
mA
mA
mW
°C
°C
IDM
Ptot
Tstg
Tj
drain current
peak value
−
total power dissipation
storage temperature range
junction temperature
Tamb = 25 °C (note 1)
−
−65
−
Note
1. Device mounted on an FR4 printboard.
THERMAL RESISTANCE
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-a
from junction to ambient (note 1)
500
K/W
Note
1. Device mounted on an FR4 printboard.
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF107
CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
ID = 10 µA
GS = 0
MIN. TYP. MAX. UNIT
V(BR)DSS
drain-source breakdown voltage
200
−
−
V
V
IDSS
drain-source leakage current
drain cut-off current
VDS = 130 V
VGS = 0
−
−
30
1
nA
µA
nA
V
IDSX
VDS = 70 V
VGS = 0.2 V
−
−
±IGSS
VGS(th)
RDS(on)
gate-source leakage current
gate-source threshold voltage
drain-source on-resistance
±VGS = 15 V
VDS = 0
−
−
10
2.4
28
−
ID = 1 mA
VGS = VDS
0.8
−
−
ID = 20 mA
20
14
180
50
Ω
V
GS = 2.6 V
ID = 150 mA
VGS = 10 V
−
Ω
Yfs
transfer admittance
input capacitance
ID = 250 mA
VDS = 15 V
90
−
−
mS
pF
Ciss
VDS = 10 V
VGS = 0
65
f = 1 MHz
Coss
output capacitance
VDS = 10 V
VGS = 0
f = 1 MHz
−
−
16
4
25
10
pF
pF
Crss
feedback capacitance
VDS = 10 V
VGS = 0
f = 1 MHz
Switching times (see Figs 2 and 3)
ton
turn-on time
ID = 250 mA
VDD = 50 V
VGS = 0 to 10 V
−
−
2
5
10
20
ns
ns
toff
turn-off time
ID = 200 mA
VDD = 50 V
VGS = 0 to 10 V
April 1995
4
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF107
V
= 50 V
handbook, halfpage
DD
handbook, halfpage
INPUT
90 %
10 %
90 %
10 V
0 V
I
D
OUTPUT
50 Ω
10 %
MSA631
t
t
off
on
MBB692
Fig.2 Switching time test circuit.
Fig.3 Input and output waveforms.
MDA783
MDA782
300
300
handbook, halfpage
handbook, halfpage
V
= 10 V
GS
I
P
D
tot
5 V
4 V
(mA)
(mW)
3 V
200
200
100
100
0
0
0
0
4
8
12
16
50
100
150
T
200
(°C)
V
(V)
DS
amb
Fig.4 Power derating curve.
Fig.5 Typical output characteristics; Tj = 25 °C.
April 1995
5
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF107
MDA702
MDA784
30
300
handbook, halfpage
handbook, halfpage
R
DSon
I
(Ω)
4 V
V
= 3 V
D
GS
26
(mA)
5 V
200
22
10 V
18
14
100
10
1
0
3
2
0
1
2
3
4
10
10
10
I
(mA)
V
(V)
D
GS
Fig.6 Typical transfer characteristic;
Fig.7 Typical on-resistance as a function of drain
VDS = 10 V; Tj = 25 °C.
current; Tj = 25 °C.
MDA703
60
handbook, halfpage
C
(pF)
40
20
C
iss
C
oss
C
rss
0
0
10
20
30
V
(V)
DS
Fig.8 Typical capacitances as a function of
drain-source voltage; VGS = 0; f = 1 MHz;
Tj = 25 °C.
April 1995
6
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF107
PACKAGE OUTLINES
Plastic surface mounted package; 3 leads
SOT23
D
B
E
A
X
H
v
M
A
E
3
Q
A
A
1
c
1
2
e
1
b
p
w M
B
L
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
b
c
D
E
e
e
H
L
Q
v
w
A
p
p
1
E
max.
1.1
0.9
0.48
0.38
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.45
0.15
0.55
0.45
mm
0.1
1.9
0.95
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-02-28
SOT23
April 1995
7
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF107
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
April 1995
8
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF107
NOTES
April 1995
9
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF107
NOTES
April 1995
10
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PMBF107
NOTES
April 1995
11
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SCA54
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Date of release: April 1995
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