PN7362AUHN_技术文档

PN736X

NFC Cortex-M0 microcontroller

Rev. 3.2 — 13 December 2016

406332

Product data sheet

COMPANY PUBLIC

1. General description

The PN736X family is a family of 32-bit ARM Cortex-M0-based NFC microcontrollers

offering high performance and low power consumption. It has a simple instruction set and

memory addressing along with a reduced code size compared to existing architectures.

PN736Xoffers an all in one solution, with features such as NFC, microcontroller, and

software in a single chip. It operates at CPU frequencies of up to 20 MHz. It is part of the

PN7462AU product family which offers a common set of features, library and tools.

The peripheral complement of the PN736X microcontroller includes 160/80 kB of flash

memory, 12 kB of SRAM data memory and 4 kB EEPROM. It also includes one host

interface with either high-speed mode I²C-bus, SPI, USB or high-speed UART, and two

master interfaces, SPI and Fast-mode Plus I²C-bus. Four general-purpose counter/timers,

a random number generator, one CRC coprocessor and up to 21 general-purpose I/O

pins are also available.

The PN736X NFC microcontroller offer a one chip solution to build contactless

applications. It is equipped with a highly integrated high-power output NFC-IC for

contactless communication at 13.56 MHz enabling EMV-compliance on RF level, without

additional external active components.

PN736X supports the following operating modes:

• ISO/IEC 14443-A and B, MIFARE

• JIS X 6319-4 (comparable with FeliCa scheme)

• ISO/IEC 15693, ICODE, ISO/IEC 18000-3 mode 3

• NFC protocols - tag reader/writer, P2P

• ISO/IEC 14443- type A card emulation

• EMVCo compliance

2. Features and benefits

2.1 Integrated contactless interface frontend

 High RF output power frontend IC for transfer speed up to 848 kbit/s

 NFC IP1 and NFC IP2 support

 Full NFC tag support (type 1, type 2, type 3, type 4A and type 4B)

 P2P active and passive, target and initiator

 Card emulation ISO14443 type A

 ISO/IEC 14443 type A and type B

PN736X

NXP Semiconductors

NFC Cortex-M0 microcontroller

 MIFARE classic card

 ISO/IEC 15693, and ISO/IEC 18000-3 mode 3

 Low-power card detection

 Dynamic Power Control (DPC) support

 Compliance with EMV contactless protocol specification

 Compliance with NFC standards

2.2 Cortex-M0 microcontroller

 Processor core

 ARM Cortex: 32-bit M0 processor

 Built-in Nested Vectored Interrupt Controller (NVIC)

 Non-maskable interrupt

 24-bit system tick timer

 Running frequency of up to 20 MHz

 Clock management to enable low power consumption

 Memory

 Flash: 160 (PN7362) / 80 kB (PN7360)

 SRAM: 12 kB

 EEPROM: 4 kB

 40 kB boot ROM included, including USB mass storage primary boot loader for

code download

 Debug option

 Serial Wire Debug (SWD) interface

 Peripherals

 Host interface:

 USB 2.0 full speed with USB 3.0 hub connection capability

 HSUART for serial communication, supporting standards speeds from 9600 bauds

to 115200 bauds, and faster speed up to 1.288 Mbit/s

 SPI with half-duplex and full duplex capability with speeds up to 7 Mbit/s

 I²C supporting standard mode, fast mode and high-speed mode with multiple

address support

 Master interface:

 SPI with half-duplex capability from 1 Mbit/s to 6.78 Mbit/s

 I²C supporting standard mode, fast mode, fast mode plus and clock stretching

 Up to 21 General-Purpose I/O (GPIO) with configurable pull-up/pull-down resistors

 GPIO1 to GPIO12 can be used as edge and level sensitive interrupt sources

 Power

 Two reduced power modes: standby mode and hard power-down mode

 Supports suspend mode for USB host interface

 Processor wake-up from hard power-down mode, standby mode, suspend mode

via host interface, GPIOs, RF field detection

 Integrated PMU to adjust internal regulators automatically, to minimize the power

consumption during all possible power modes

 Power-on reset

PN736X

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Product data sheet

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PN736X

NXP Semiconductors

NFC Cortex-M0 microcontroller

 RF supply: external, or using an integrated LDO (TX LDO, configurable with 3 V,

3.3 V, 3.6 V, 4.5 V, and 4.75 V)

 Pad voltage supply: external 3.3 V or 1.8 V, or using an integrated LDO (3.3 V

supply)

 Timers

 Four general-purpose timers

 Programmable Watchdog Timer (WDT)

 CRC coprocessor

 Random number generator

 Clocks

 Crystal oscillator at 27.12 MHz

 Dedicated PLL at 48 MHz for the USB

 Integrated HFO 20 MHz and LFO 365 kHz

 General

 HVQFN64 package

 Temperature range: 40 C to +85 C

3. Applications

 Physical access control

 Gaming

 USB NFC reader, including dual interface smart card readers

 Home banking, payment readers EMVCo compliant

 High integration devices

 NFC applications

4. Quick reference data

Table 1.

Quick reference data

Operating range: 40 C to +85 C unless specified; contactless interface: internal LDO not used

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDP(VBUS)

power supply voltage card emulation, passive target

2.3

-

5.5

V

on pin VBUS

(PLM)

all RF modes

2.7

3

-

5.5

V

-

5.5

V_DD(PVDD)

PVDD supply voltage 1.8 V

3.3 V

1.65

3

1.8

3.3

1.95

3.6

PN736X

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Product data sheet

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PN736X

NXP Semiconductors

NFC Cortex-M0 microcontroller

Table 1.

Quick reference data …continued

Operating range: 40 C to +85 C unless specified; contactless interface: internal LDO not used

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_DDP(VBUS)

power supply current in hard power-down mode;

-

12

18

A

on pin VBUS

T = 25 C; V_DDP(VBUS)= 5.5 V;

RST_N = 0

stand by mode; T = 25 C;

V_DDP(VBUS)= 3.3 V; external

PVDD LDO used

-

18

55

120

-

A

mA

stand by mode; T = 25 C;

-

V_DDP(VBUS)= 5.5 V; internal

PVDD LDO used

suspend mode, USB interface;

250

V_DDP(VBUS)= 5.5 V; external

PVDD supply; T = 25 C

I_DD(TVDD)

TVDD supply current on pin TVDD_IN; maximum

supported current by the

contactless interface

P_max

T_amb

maximum power

dissipation

-

1050

+85

mW

ambient temperature JEDEC PCB

40

C

5. Ordering information

The PN736X family includes the following products:

PN7362AU: Full memory available, no contact interface

PN7360AU: Memory limited to 80 kB, and no contact interface.

The table below lists the ordering information for these two products.

Table 2.

Ordering information

Type number

Package

Name

Description

Version

PN7360AUHN

PN7362AUHN

HVQFN64

plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; SOT804-4

body 9 9 0.85 mm

HVQFN64

plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; SOT804-4

body 9 9 0.85 mm

PN736X

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Product data sheet

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Rev. 3.2 — 13 December 2016

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PN736X

NXP Semiconductors

NFC Cortex-M0 microcontroller

6. Block diagram

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Fig 1. Block diagram

PN736X

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Product data sheet

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NFC Cortex-M0 microcontroller

7. Pinning information

7.1 Pinning

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Fig 2. Pin configuration

Important note: the inner leads below the package are internally connected to the PIN.

Special care needs to be taken during the design so that no conductive part is present

under these PINs, which could cause short cuts.

7.2 Pin description

Table 3.

Pin description

Symbol

Description

I2CM_SDA

CLK_AUX

IO_AUX

1

2

3

4

5

6

7

8

I²C-bus serial data I/O master/GPIO13

auxiliary card contact clock/GPIO14

auxiliary card contact I/O/GPIO15

INT_AUX

auxiliary card contact interrupt/GPIO16

not connected

ATX_A

ATX_B

ATX_C

SPI slave select input (NSS_S)/I²C-bus serial clock input (SCL_S)/HSUART RX

SPI slave data input (MOSI_S)/I²C-bus serial data I/O (SDA_S)/HSUART TX

USB D+/SPI slave data output (MISO_S)/I²C-bus address bit0 input/HSUART RTS

PN736X

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Product data sheet

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NFC Cortex-M0 microcontroller

Table 3.

Symbol

ATX_D

PVDD_IN

DVDD

DWL_REQ

IRQ

Pin description …continued

9

Description

USB D-/SPI clock input (SCK_S)/I²C-bus address bit1 input/HSUART CTS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

pad supply voltage input

digital core logic supply voltage input

entering in download mode

interrupt request output

SWDCLK

SWDIO

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

RXN

SW serial debug line clock

SW serial debug line input/output

general-purpose I/O/SPI master select2 output

general-purpose I/O

receiver input

RXP

receiver input

VMID

receiver reference voltage input

antenna driver output

TX2

TVSS

ground for antenna power supply

antenna driver output

TX1

TVDD_IN

ANT1

antenna driver supply voltage input

antenna connection for load modulation in card emulation and P2P passive target modes

antenna driver supply, output of TX_LDO

supply of the contactless TX_LDO

1.8 V regulator output for digital blocks

27.12 MHz clock input for crystal

reset pin

ANT2

TVDD_OUT

VUP_TX

VDD

XTAL1

XTAL2

RST_N

VBUS

main supply voltage input of microcontroller

output of PVDD_LDO for pad voltage supply

Ground

PVDD_OUT

GNDP

-

not connected

-

not connected

VBUSP

-

Connected to VBUS

not connected

PN736X

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Product data sheet

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NXP Semiconductors

NFC Cortex-M0 microcontroller

Table 3.

Pin description …continued

Symbol

50

Description

-

not connected

-

51

not connected

-

52

not connected

-

53

not connected

GNDC

54

connected to the ground

not connected

-

55

-

56

not connected

-

57

not connected

USB_VBUS

PVDD_M_IN

SPIM_SSN

SPI_SCLK

SPIM_MOSI

SPIM_MISO

I2CM_SCL

GND

58

used for USB VBUS detection

pad supply voltage input for master interfaces

SPI master select 1 output/GPIO17

SPI master clock output/GPIO18

SPI master data output/GPIO19

SPI master data input/GPIO20

I²C-bus serial clock output master/GPIO21

Ground

59

60

61

62

63

64

Die pad

8. Functional description

8.1 ARM Cortex-M0 microcontroller

The PN736X is an ARM Cortex-M0-based 32-bit microcontroller, optimized for low-cost

designs, high energy efficiency, and simple instruction set.

The CPU operates on an internal clock, which can be configured to provide frequencies

such as 20 MHz, 10 MHz, and 5 MHz.

The peripheral complement of the PN736X includes a 160 kB flash memory, a 12 kB

SRAM, and a 4 kB EEPROM. It also includes one configurable host interface (Fast-mode

Plus and high-speed I²C, SPI, HSUART, and USB), two master interfaces (Fast-mode

Plus I²C, SPI), 4 timers, 12 general-purpose I/O pins, and one 13.56 MHz contactless

interface.

8.2 Memories

8.2.1 On-chip flash programming memory

The PN736X contains160 / 80 kB on-chip flash program memory depending on the

version. The flash can be programmed using In-System Programming (ISP) or

In-Application Programming (IAP) via the on-chip boot loader software.

The flash memory is divided into two instances of 80 kB each, with each sector consisting

of individual pages of 64 bytes.

8.2.1.1 Memory mapping

The flash memory mapping is described in Figure 3.

PN736X

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Product data sheet

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PN736X

NXP Semiconductors

NFC Cortex-M0 microcontroller

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8.2.2 EEPROM

The PN736X embeds 4 kB of on-chip byte-erasable and byte-programmable EEPROM

data memory.

The EEPROM can be programmed using In-System Programming (ISP).

8.2.2.1 Memory mapping

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PN736X

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Product data sheet

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PN736X

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8.2.3 SRAM

NFC Cortex-M0 microcontroller

The PN736X contains a total of 12 kB on-chip static RAM memory.

8.2.3.1 Memory mapping

The SRAM memory mapping is shown in Figure 5.

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8.2.4 ROM

The PN736X contains 40 kB of on-chip ROM memory. The on-chip ROM contains boot

loader, USB mass storage primary download and the following Application Programming

Interfaces (APIs):

• In-Application Programming (IAP) support for flash

• Lifecycle management of debug interface, code write protection of flash memory and

USB mass storage primary download

• USB descriptor configuration

• Configuration of timeout and source of pad supply

8.2.5 Memory map

The PN736X incorporates several distinct memory regions. Figure 6 shows the PN736X

memory map, from the user program perspective, following reset.

The APB peripheral area is 512 kB in size, and is divided to allow up to 32 peripherals.

Only peripherals from 0 to 15 are accessible. Each peripheral is allocated 16 kB, which

simplifies the address decoding for the peripherals. APB memory map is described in

Figure 7.

PN736X

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Product data sheet

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PN736X

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NFC Cortex-M0 microcontroller

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Fig 6. PN736X memory map

PN736X

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Product data sheet

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PN736X

NXP Semiconductors

NFC Cortex-M0 microcontroller

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8.3 Nested Vectored Interrupt Controller (NVIC)

Cortex-M0 includes a Nested Vectored Interrupt Controller (NVIC). The tight coupling to

the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

8.3.1 NVIC features

• System exceptions and peripheral interrupts control

• Support 32 vectored interrupts

• Four interrupt priority levels with hardware priority level masking

• One Non-Maskable Interrupt (NMI) connected to the watchdog interrupt

• Software interrupt generation

8.3.2 Interrupt sources

The following table lists the interrupt sources available in the PN736X microcontroller.

Table 4.

Interrupt sources

EIRQ# Source

Description

0

general-purpose timer 0/1/2/3 interrupt

timer 0/1/2/3

1

2

3

4

5

6

7

-

reserved

CLIF

contactless interface module interrupt

EECTRL

EEPROM controller

-

reserved

-

reserved

host IF

-

TX or RX buffer from I²C, SPI, HSU, or USB module

reserved

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Table 4.

Interrupt sources …continued

EIRQ# Source

Description

8

9

-

reserved

PMU

power management unit (temperature sensor, over current, overload,

and VBUS level)

10

11

12

SPI master

I²C master

PCR

TX or RX buffer from SPI master module

TX or RX buffer from I²C master module

high temperature from temperature sensor 0 and 1; interrupt to CPU from

PCR to indicate wake-up from suspend mode; out of standby; out of

suspend; event on GPIOs configured as inputs

13

14

PCR

interrupt common GPIO1 to GPIO12

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO1

15

16

17

18

19

20

21

22

23

24

25

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO2

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO3

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO4

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO5

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO6

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO7

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO8

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO9

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO10

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO11

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

programmed) GPIO12

26

-

reserved

27

-

reserved

28

-

reserved

29

-

reserved

30

-

reserved

31

-

reserved

NMI^[1]

WDT

watchdog interrupt is connected to the non-maskable interrupt pin

[1] The NMI is not available on an external pin.

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8.4 GPIOs

NFC Cortex-M0 microcontroller

The PN736X has 12 general-purpose I/O (GPIO) with configurable pull-up and pull-down

resistors, plus nine additional GPIOs multiplexed with SPI master, I²C-bus master and

AUX pins.

Pins can be dynamically configured as inputs or outputs. GPIO read/write are made by the

FW using dedicated registers that allow reading, setting or clearing inputs. The value of

the output register can be read back, as well as the current state of the input pins.

8.4.1 GPIO features

• Dynamic configuration as input or output

• 3.3 V and 1.8 V signaling

• Programmable weak pull-up and weak pull-down

• Independent interrupts for GPIO1 to GPIO12

• Interrupts: edge or level sensitive

• GPIO1 to GPIO12 can be programmed as wake-up sources

• Programmable spike filter (3 ns)

• Programmable slew rate (3 ns and 10 ns)

• Hysteresis receiver with disable option

8.4.2 GPIO configuration

The GPIO configuration is done through the PCR module (power, clock, and reset).

8.4.3 GPIO interrupts

GPIO1 to GPIO12 can be programmed to generate an interrupt on a level, a rising or

falling edge or both.

8.5 CRC engine 16/32 bits

The PN7362 has a configurable 16/32-bit parallel CRC coprocessor.

The 16-bit CRC is compliant to X.25 (CRC-CCITT, ISO/IEC 13239) standard with a

generator polynome of:

gx = x¹⁶+ x¹²+ x⁵+ 1

The 32-bit CRC is compliant to the ethernet/AAL5 (IEEE 802.3) standard with a generator

polynome of:

gx = x³²+ x²⁶+ x²³+ x²²+ x¹⁶+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁷+ x⁵+ x⁴+ x²+ x + 1

CRC calculation is performed in parallel, meaning that one CRC calculation is performed

in one clock cycle. The standard CRC 32 polynome is compliant with FIPS140-2.

Note: No final XOR calculation is performed.

Following are the CRC engine features:

• Configurable CRC preset value

• Selectable LSB or MSB first

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• CRC 32 calculation based on 32-bit, 16-bit, and 8-bit words

• CRC16 calculation based on 32-bit, 16-bit, and 8-bit words

• Supports bit order reverse

8.6 Random Number Generator (RNG)

The PN736X integrates a random number generator. It consists of an analog True

Random Number Generator (TRNG), and a digital Pseudo Random Number Generator

(PRNG). The TRNG is used for loading a new seed in the PRNG.

The random number generator features:

• 8-bit random number

• Compliant with FIPS 140-2

• Compliant with BSI AIS20 and SP800-22

8.7 Master interfaces

2

8.7.1 I C master interface

The PN736X contains one I²C master and one I²C slave controller. This chapter

describes the master interface. For more information on the I²C slave controller, refer to

Section 8.8.2.

The I²C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial Data Line (SDA). Each device has a unique address. The device can

operate either as a receive-only device (such as LCD driver) or a transmitter with the

capability to both receive and send information (such as memory).

8.7.1.1 I²C features

The I²C master interface supports the following features:

• Standard I²C compliant bus interface with open-drain pins

• Standard-mode, fast mode and fast mode plus (up to 1 Mbit/s).

• Support I²C master mode only.

• Programmable clocks allowing versatile rate control.

• Clock stretching

• 7-bit and 10-bit I²C slave addressing

• LDM/STM instruction support

• Maximum data frame size up to 1024 bytes

8.7.2 SPI interface

The PN736X contains one SPI master controller and one SPI slave controller.

The SPI master controller transmits the data from the system RAM to the SPI external

slaves. Similarly, it receives data from the SPI external slaves and stores them into the

system RAM. It can compute a CRC for received frames and automatically compute and

append CRC for outgoing frames (optional feature).

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8.7.2.1 SPI features

The SPI master interface provides the following features:

• SPI master interface: synchronous, half-duplex

• Supports Motorola SPI frame formats only (SPI block guide V04.0114 (Freescale)

specification)

• Maximum SPI data rate of 6.78 Mbit/s

• Multiple data rates such as 1, 1.51, 2.09, 2.47, 3.01, 4.52, 5.42 and 6.78 Mbit/s

• Up to two slaves select with selectable polarity

• Programmable clock polarity and phase

• Supports 8-bit transfers only

• Maximum frame size: 511 data bytes payload + 1 CRC byte

• Optional 1 byte CRC calculation on all data of TX and RX buffer

• AHB master interface for data transfer

8.8 Host interfaces

The PN736X embeds four different interfaces for host connection: USB, HSUART, I²C,

and SPI.

The four interfaces share the buffer manager and the pins; see Table 5.

Table 5.

Name

Pin description for host interface

SPI

I²C

USB

HSU

ATX_A

SCL_S

-

HSU_RX

NSS_S

MOSI_S

MISO_S

SCK_S

ATX_B

ATX_C

ATX_D

SDA_S

-

HSU_TX

I²C_ADR0

I²C_ADR1

DP

DM

HSU_RTS_N

HSU_CTS_N

The interface selection is done by configuring the Power Clock Reset (PCR) registers.

Note: The host interface pins should not be kept floating.

8.8.1 High-speed UART

The PN736X has a high-speed UART which can operate in slave mode only.

Following are the HSUART features:

• Standard bit-rates are 9600, 19200, 38400, 57600, 115200, and up to 1.288 Mbit/s

• Supports full duplex communication

• Supports only one operational mode: start bit, 8 data bits (LSB), and stop bits

• The number of “stop bits” programmable for RX and TX is 1 stop bit or 2 stop bits

• Configurable length of EOF (1-bit to 122-bits)

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Table 6.

HSUART baudrates

Bit rate (kBd)

9.6

19.2

38.4

57.6

115.2

230.4

460.8

921.6

1288 K

8.8.2 I²C host interface controller

The PN736X contains one I²C master and one I²C slave controller. This section describes

the slave interface used for host communication. For more information on the I²C master

controller, refer to Section 8.7.1.

The I²C-bus is bidirectional and uses only two wires: a Serial Clock Line (SCL) and a

Serial Data Line (SDA). I²C standard mode (100 kbit/s), fast mode (400 kbit/s and up to 1

Mbit/s), and high-speed mode (3.4 Mbit/s) are supported.

8.8.2.1 I²C host interface features

The PN736X I²C slave interface supports the following features:

• Support slave I²C bus

• Standard mode, fast mode (extended to 1 Mbit/s support), and high-speed modes

• Supports 7-bit addressing mode only

• Selection of the I²C address done by two pins

– It supports multiple addresses

– The upper bits of the I²C slave address are hard-coded. The value corresponds to

the NXP identifier for I²C blocks. The value is 01010XXb.

• General call (software reset only)

• Software reset (in standard mode and fast mode only)

Table 7.

I²C_ADR1 I²C_ADR0 I²C address (R/W = 0, write)

I²C interface addressing

I²C address (R/W = 0, read)

0

1

0

1

0

1

0 28

0  29

0  2A

0  2B

0  28

029

0  2A

0  2B

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8.8.3 SPI host/Slave interface

The PN736X host interface can be used as SPI slave interface.

The SPI slave controller operates on a four wire SSI: Master In Slave Out (MISO), Master

Out Slave In (MOSI), Serial Clock (SCK), and Not Slave Select (NSS). The SPI slave

select polarity is fixed to positive polarity.

8.8.3.1 SPI host interface features

The SPI host/slave interface has the following features:

• SPI speeds up to 7 Mbit/s

• Slave operation only

• 8-bit data format only

• Programmable clock polarity and phase

• SPI slave select polarity selection fixed to positive polarity

• Half-duplex in HDLL mode

• Full-duplex in native mode

If no data is available, the MISO line is kept idle by making all the bits high (0xFF).

Toggling the NSS line indicates a new frame.

Note: Programmable echo-back operation is not supported.

Table 8.

SPI configuration

connection

CPHA switch: Clock phase: Defines the sampling edge of MOSI data

• CPHA = 1: Data are sampled on MOSI on the even clock edges of SCK, after NSS goes low

• CPHA = 0: Data are sampled on MOSI on the odd clock edges of SCK, after NSS goes low

CPOL switch: Clock polarity

• IFSEL1 = 0: The clock is idle low, and the first valid edge of SCK is a rising one

• IFSEL1 = 0: The clock is idle high, and the first valid edge of SCK is a falling one

8.8.4 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and up to 127 peripherals. The host controller allocates the USB bandwidth to

attached devices through a token-based protocol. The bus supports hot-plugging and

dynamic configuration of devices. The host controller initiates all transactions. The

PN736X USB interface consists of a full-speed device controller with on-chip PHY

(physical layer) for device functions.

8.8.4.1 Full speed USB device controller

The PN736X embeds a USB device peripheral, compliant with USB 2.0 specification, full

speed. It is interoperable with USB 3.0 host devices.

The device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, and endpoint buffer memory. The

serial interface engine decodes the USB data stream and writes data to the appropriate

endpoint buffer.

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The status of a completed USB transfer or error condition is indicated via status registers.

If enabled, an interrupt is generated.

Following are the USB interface features:

• Fully compliant with USB 2.0 specification (full speed)

• Dedicated USB PLL available

• Supports 14 physical (7 logical) endpoints including one control endpoint

• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types

• Single or double buffering allowed

• Support wake-up from suspend mode on USB activity and remote wake-up

• Soft-connect supported

8.9 I/O auxiliary - ISO/IEC 7816 UART - connecting an external TDA

To address applications where ISO/IEC 7816 interface is needed, the PN736X integrates

the possibility to connect contact slot extender like TDA8026, TDA8020 or TDA8035, and

to drive it thanks to its integrated ISO/IEC7816 UART.

The following pins are available:

• INT_AUX

• CLK_AUX

• IO_AUX

For more details about the connection, refer to the slot extender documentation.

The integrated ISO/IEC 7816 UART has APB access for automatic convention

processing, variable baud rate through frequency or division ratio programming, error

management at character level for T = 0 and extra guard time register.

• FIFO 1 character to 32 characters in both reception and transmission mode

• Parity error counter in reception mode and transmission mode with automatic

retransmission

• Card clock stop (at HIGH or LOW level)

• Automatic activation and deactivation sequence through a sequencer

• Supports the asynchronous protocols T=0 and T=1 in accordance with ISO/IEC 7816

and EMV

• Versatile 24-bit timeout counter for Answer To Reset (ATR) and waiting times

processing

• Specific Elementary Time Unit (ETU) counter for Block Guard Time (BGT); 22 ETU in

T=1 and 16 ETU in T=0

• Supports synchronous cards

8.10 Contactless interface - 13.56 MHz

The PN736X embeds a high power 13.56 MHz RF frontend. The RF interface implements

the RF functionality like antenna driving, the receiver circuitry, and all the low-level

functionalities. It helps to realize an NFC forum or an EMVCo compliant reader.

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The PN736X allows different voltages for the RF drivers. For information related to the RF

interface supply, refer Section 8.15.

The PN736X uses an external oscillator, at 27.12 MHz. It is a clock source for generating

RF field and its internal operation.

Key features of the RF interface are:

• ISO/IEC 14443 type A & B compliant

• MIFARE functionality, including MIFARE classic encryption in read/write mode

• ISO/IEC 15693 compliant

• NFC Forum - NFCIP-1 & NFCIP-2 compliant

– P2P, active and passive mode

– reading of NFC forum tag types 1, 2, 3, 4, and 5

• FeliCa

• ISO/IEC 18000-3 mode 3

• EMVCo contactless 2.3.1 and 2.5

– RF level can be achieved without the need of booster circuitry (for some antenna

topologies the EMV RF-level compliance might physically not be achievable)

• Card mode - enabling the emulation of an ISO/IEC 14443 type A card

– Supports Passive Load Modulation (PLM) and Active Load Modulation (ALM)

• Low Power Card Detection (LPCD)

• Adjustable RX-voltage level

A minimum voltage of 2.3 V helps to use card emulation, and P2P passive target

functionality in passive load modulation.

A voltage above 2.7 V enables all contactless functionalities.

8.10.1 RF functionality

8.10.1.1 ISO/IEC14443 A/MIFARE functionality

The physical level of the communication is shown in Figure 8.

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(2) Card to Reader: Subcarrier load modulation Manchester coded or BPSK, transfer speed 106 kbit/s

to 848 kbit/s

Fig 8. ISO/IEC 14443 A/MIFARE read/write mode communication diagram

The physical parameters are described in Table 9.

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Table 9.

Communication overview for ISO/IEC 14443 A/MIFARE reader/writer

Communication

direction

Signal type

Transfer speed

106 kbit/s

212 kbit/s

424 kbit/s

848 kbit/s

reader to card (send

reader side

100 % ASK

data from the PN736X modulation

to a card)

f_c= 13.56 MHz

bit encoding

modified miller

encoding

modified miller

encoding

modified miller

encoding

modified miller

encoding

bit rate (kbit/s)

f_c/ 128

f_c/ 64

f_c/ 32

f_c/ 16

card to reader (PN736X card side

sub carrier load

modulation

sub carrier load

modulation

sub carrier load

modulation

sub carrier load

modulation

receives data from a

card)

modulation

subcarrier

frequency

f_c/ 16

bit encoding

Manchester

encoding

BPSK

Figure 9 shows the data coding and framing according to ISO/IEC 14443 A/MIFARE.

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Fig 9. Data coding and framing according to ISO/IEC 14443 A card response

The internal CRC coprocessor calculates the CRC value based on the selected protocol.

In card mode for higher baudrates, the parity is automatically inverted as end of

communication indicator.

8.10.1.2 ISO/IEC14443 B functionality

The physical level of the communication is shown in Figure 10.

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(1) Reader to Card: NRZ; transfer speed 106 kbit/s to 848 kbit/s

(2) Card to reader: Subcarrier load modulation Manchester coded or BPSK, transfer speed 106 kbit/s to 848 kbit/s

Fig 10. ISO/IEC 14443 B read/write mode communication diagram

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The physical parameters are described in Table 10.

Table 10. Communication overview for ISO/IEC 14443 B reader/writer

Communication

direction

Signal type

Transfer speed

106 kbit/s

212 kbit/s

424 kbit/s

848 kbit/s

reader to card (send

reader side

10 % ASK

data from the PN736X modulation

to a card)

f_c= 13.56 MHz

bit encoding

NRZ

64/f_c

NRZ

32/f_c

NRZ

16/f_c

bit rate [kbit/s]

128/f_c

card to reader (PN736X card side

sub carrier load

modulation

sub carrier load

modulation

sub carrier load

modulation

sub carrier load

modulation

receives data from a

card)

modulation

sub carrier

frequency

f_c/ 16

bit encoding

BPSK

8.10.1.3 FeliCa functionality

The FeliCa mode is a general reader/writer to card communication scheme, according to

the FeliCa specification. The communication on a physical level is shown in Figure 11.

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Fig 11. FeliCa read/write communication diagram

The physical parameters are described in Table 11.

Table 11. Communication overview for FeliCa reader/writer

Communication direction

Signal type

Transfer speed FeliCa

FeliCa higher transfer

speeds

212 kbit/s

424 kbit/s

reader to card (send data

from the PN736X to a card)

f_c= 13.56 MHz

reader side modulation

bit encoding

8 % to 30 % ASK

Manchester encoding

f_c/ 64

8 % to 30 % ASK

Manchester encoding

f_c/ 32

bit rate

card to reader (PN736X

receives data from a card)

card side modulation

bit encoding

load modulation

Manchester encoding

load modulation

Manchester encoding

Note: The PN736X does not manage FeliCa security aspects.

PN736X supports FeliCa multiple reception cycles.

PN736X

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Fig 12. Multiple reception cycles - data format

8.10.1.4 ISO/IEC 15693 functionality

The physical level of the communication is shown in Figure 13.

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(1) Reader to Card: 1/256 and 1/4 encoding

(2) Card to Reader: Manchester coding

Fig 13. ISO/IEC 15693 read/write mode communication diagram

The physical parameters are described in Table 12.

Table 12. Communication overview for ISO/IEC 15693 reader to label

Communication direction

Signal type

Transfer speed

f_c/ 8192 kbit/s

f_c/ 512 kbit/s

reader to label (send data

from the PN736X to a card)

reader side modulation

10 % to 30 % ASK or

100 % ASK

10 % to 30 % ASK or 90 % to

100 % ASK

bit encoding

bit length

1/256

1/4

4.833 s

302.08 s

Table 13. Communication overview for ISO/IEC 15693 label to reader

Communication

direction

Signal type

Transfer speed

6.62 kbit/s

13.24 kbit/s^[1]

26.48 kbit/s

52.96 kbit/s

label to reader

card side

modulation

not supported

single (dual) sub

carrier load

modulation ASK

single sub carrier

load modulation ASK

(PN736X receives

data from a card) f_c

= 13.56 MHz

bit length (s)

-

37.76

18.88

bit encoding

Manchester coding

f_c/ 32

Manchester coding

f_c/ 32

subcarrier

frequency (MHz)

[1] Fast inventory (page) read command only (ICODE proprietary command).

PN736X

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Fig 14. Data coding according to ISO/IEC 15693 standard mode reader to label

8.10.1.5 ISO/IEC18000-3 mode 3 functionality

The ISO/IEC 18000-3 mode 3 is not described in this document. For a detailed

explanation of the protocol, refer to the ISO/IEC 18000-3 standard.

PN736X supports the following features:

• TARI = 9.44 s or 18.88 s

• Downlink: Four subcarrier pulse Manchester and two subcarrier pulse Manchester

• Subcarrier: 423 kHz (f_c/ 32) with DR = 0 kHz and 847 kHz (f_c/ 16) with DR = 1

8.10.1.6 NFCIP-1 modes

The NFCIP-1 communication differentiates between an active and a passive

communication mode.

• In active communication mode, both initiator and target use their own RF field to

transmit data

• In passive communication mode, the target answers to an initiator command in a load

modulation scheme. The initiator is active in terms of generating the RF field

• The initiator generates RF field at 13.56 MHz and starts the NFCIP-1 communication

• In passive communication mode, the target responds to initiator command in load

modulation scheme. In active communication mode, it uses a self-generated and

self-modulated RF field.

PN736X supports NFCIP-1 standard. PN736X supports active and passive

communication mode at transfer speeds of 106 kbit/s, 212 kbit/s, and 424 kbit/s, as

defined in the NFCIP-1 standard.

PN736X

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Fig 15. Active communication mode

Table 14. Communication overview for active communication mode

Communication

direction

Transfer speed

106 kbit/s

212 kbit/s

424 kbit/s

initiator to target

target to initiator

according to ISO/IEC 14443 A

100 % ASK, modified

miller coded

according to

FeliCa, 8-30 %

ASK Manchester

coded

according to

FeliCa, 8-30 %

ASK Manchester

coded

Note: Transfer speeds above 424 kbit/s are not defined in the NFCIP-1 standard.

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Fig 16. Passive communication mode

PN736X

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Table 15. Communication overview for passive communication mode

Communication

direction

Transfer speed

106 kbit/s

212 kbit/s

424 kbit/s

initiator to target

according to

according to FeliCa,

8-30 % ASK

Manchester coded

according to FeliCa,

8-30 % ASK

Manchester coded

ISO/IEC 14443 A

100 % ASK, modified

miller coded

target to initiator

according to

according to FeliCa, > according to FeliCa, >

12 % ASK Manchester 12 % ASK Manchester

ISO/IEC 14443 A

@106 kB modified

miller coded

coded

The NFCIP-1 protocol is managed in the PN736X customer application firmware.

Note: Transfer speeds above 424 kbit/s are not defined in the NFCIP-1 standard.

ISO/IEC14443 A card operation mode: PN736X can be addressed as a ISO/IEC 14443

A card. It means that PN736X can generate an answer in a load modulation scheme

according to the ISO/IEC 14443 A interface description.

Note: PN736X components do not support a complete card protocol. The PN736X

customer application firmware handles it.

The following table describes the physical layer of a ISO/IEC14443 A card mode:

Table 16. ISO/IEC14443 A card operation mode

Communication direction

ISO/IEC 14443 A (transfer speed: 106 kbit per second)

reader/writer to PN736X

modulation on reader side

bit coding

100 % ASK

modified miller

128/f_c

bit length

PN736X to reader/writer

modulation on PN736X side sub carrier load modulation

subcarrier frequency

bit coding

f_c/ 16

Manchester coding

NFCIP-1 framing and coding: The NFCIP-1 framing and coding in active and passive

communication mode is defined in the NFCIP-1 standard.

PN736X supports the following data rates:

Table 17. Framing and coding overview

Transfer speed

106 kbit/s

Framing and coding

according to the ISO/IEC 14443 A/MIFARE scheme

according to the FeliCa scheme

212 kbit/s

424 kbit/s

NFCIP-1 protocol support: The NFCIP-1 protocol is not elaborated in this document.

The PN736X component does not implement any of the high-level protocol functions.

These high-level protocol functions are implemented in the microcontroller. For detailed

explanation of the protocol, refer to the NFCIP-1 standard. However, the datalink layer is

according to the following policy:

• Speed shall not be changed while there is continuous data exchange in a transaction.

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• Transaction includes initialization, anticollision methods, and data exchange (in a

continuous way means no interruption by another transaction).

In order not to disturb current infrastructure based on 13.56 MHz, the following general

rules to start NFCIP-1 communication are defined:

1. By default, NFCIP-1 device is in target mode. It means that its RF field is switched off.

2. The RF level detector is active.

3. Only if the application requires, the NFCIP-1 device switches to initiator mode.

4. An initiator shall only switch on its RF field if the RF level detector does not detect

external RF field during a time of T_IDT

.

5. The initiator performs initialization according to the selected mode.

8.10.2 Contactless interface

8.10.2.1 Transmitter (TX)

The transmitter is able to drive an antenna circuit connected to outputs TX1 and TX2 with

a 13.56 MHz carrier signal. The signal delivered on pins TX1 and pin TX2 is a 13.56 MHz

carrier, modulated by an envelope signal for energy and data transmission. It can be used

to drive an antenna directly, using a few passive components for matching and filtering.

For a differential antenna configuration, either TX1 or TX2 can be configured to put out an

inverted clock.

100 % modulation and several levels of amplitude modulation on the carrier can be

performed to support 13.56 MHz carrier-based RF-reader/writer protocols. The standards

ISO/IEC14443 A and B, FeliCa and ISO/IEC18092 define the protocols.

The PN736X embeds an overshoot and undershoot protection. It is used to configure

additional signals on the transmitter output, for controlling the signal shape at the antenna

output.

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Fig 17. PN736X output driver

8.10.2.2 Receiver (RX)

In reader mode, the response of the PICC device is coupled from the PCB antenna to the

differential input RXP/RXN. The reader mode receiver extracts this signal by first

removing the carrier in passive mixers (direct conversion for I and Q). It then filters and

amplifies the baseband signal before converting to digital values. The conversion to digital

values is done with two separate ADCs, for I and Q channels. Both I and Q channels have

a differential structure, which improves the signal quality.

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The I/Q mixer mixes the differential input RF-signal down to the baseband. The mixer has

a bandwidth of 2 MHz.

The down-mixed differential RX input signals are passed to the BBA and a band-pass

filter. For considering all the protocols (type A/B, FeliCa), the high-pass cut-off frequency

of BBA is configured between 45 kHz and 250 kHz. The configuration is done in four

different steps. The low-pass cut-off frequency is greater than 2 MHz.

The output of band-pass filter is further amplified with a gain factor which is configurable

between 30 dB and 60 dB. The baseband amplifier (BBA)/ADC I-channel and Q-channel

can be enabled separately. It is required for ADC-based card mode functionality as only

the I-channel is used in this case.

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Fig 18. Receiver block diagram

VMID: A resistive divider between AVDD and GND generates VMID. The resistive divider

is connected to the VMID pin. An external blocking capacitor of typical value 100 nF is

connected.

Automatic Gain Control (AGC): The contactless interface AGC is used to control the

amplitude of 13.56 MHz sine-wave input signal received. The signal is received at the

antenna connected between the pins RXP and RXN. A comparator is used to compare

the peak value of the input signal with a reference voltage.

A voltage divider circuit is used to generate the reference voltage. An external resistor

(typically 3.3 k) is connected to the RX input, which forms a voltage divider with an

on-chip variable resistor. The voltage divider circuit so formed has a 10-bit resolution.

Note: The comparator monitors the RXP signal only.

By varying the on-chip resistor, the amplitude of the input signal can be modified. The

value of on-chip resistor is increased or decreased, depending on the output of the

sampled comparator. The on-chip resistor value is adjusted until the peak of the input

signal matches the reference voltage. Thus, the AGC circuit automatically controls the

amplitude of the RX input.

The internal amplitude controlling resistor in the AGC has a default value of 10 K. It

means that, when the resistor control bits in AGC_VALUE_REG <9:0> are all 0, the

resistance is 10 K. As the control bits are increased, resistors are switched in parallel to

the 10 K resistor. It lowers the resultant resistance value to 5 k (AGC_VALUE_REG

<9:0>, all bits set to 1).

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Mode detector: The mode detector is a functional block of the PN736X which senses for

an RF field generated by another device. The mode detector facilitates to distinguish

between type A and FeliCa target mode. The host responds depending on the recognized

protocol generated by an initiator peer device.

Note: The PN736X emulates type A cards and peer-to-peer active target modes

according to ISO / IEC18092.

8.10.3 Low-Power Card Detection (LPCD)

The low-power card detection is an energy saving feature of the PN736X. It detects the

presence of a card without starting a communication. Communication requires more

energy to power the card and takes time, increasing the energy consumption.

It is based on antenna detuning detection. When a card comes close to the reader, it

affects the antenna tuning, which is detected by PN736X.

The sensitivity can be varied for adjusting to various environment and applications

constraints.

Remark: Reader antenna detuning may have multiple sources such as cards and metal

near the antenna. Hence it is important to adjust the sensitivity with care to optimize the

detection and power consumption. As the generated field is limited, distance for card

detection might be reduced compared to normal reader operation. Performances depend

on the antenna and the sensitivity used.

8.10.4 Active Load Modulation (ALM)

When PN736X is used in card emulation mode or P2P passive target mode, it modulates

the field emitted by the external reader or NFC passive initiator.

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(2) PN736X modulates the field of reader for sending its answer

Fig 19. Communication in card emulation of NFC passive target

To modulate the field, PN736X offers two possibilities:

• Passive Load Modulation (PLM): The PN736X modifies the antenna characteristics,

which are detected by the reader through antenna coupling.

• Active Load Modulation (ALM): The PN736X generates a small field, in phase

opposition with the field emitted by the reader. This modulation is detected by the

reader reception stage.

The modulation type to use depends on the external reader and the antenna of PN736X

and the application.

PN736X

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8.10.5 Dynamic Power Control (DPC)

The PN736X supports the Dynamic Power Control (DPC) feature.

A lookup table is used to configure the output voltage and to control the transmitter

current. In addition to the control of the transmitter current, wave shaping settings can be

controlled as well, depending on the selected protocol and the measured antenna load.

8.10.5.1 RF output control

The DPC controls the RF output current and output voltage depending on the loading

condition of the antenna.

8.10.5.2 Adaptive Waveform Control (AWC)

The DPC includes the Adaptive Waveform Control (AWC) feature.

Depending on the level of detected detuning on the antenna, RF wave shaping related

register settings can be automatically updated, according to the selected protocol. A

lookup table is used to configure the modulation index, the rise time and the fall time.

8.11 Timers

The PN736X includes two 12-bit general-purpose timers (on LFO clock domain) with

match capabilities. It also includes two 32-bit general-purpose timers (on HFO clock

domain) and a Watchdog Timer (WDT).

The timers and WDT can be configured through software via a 32-bit APB slave interface.

Table 18. Timer characteristics

Name

Clock

source

Frequency Counter

length

Resolution Maximum

delay

Chaining

Timer 0

Timer 1

Timer 2

Timer 3

Watchdog

LFO/2

HFO

182.5 kHz

20 MHz

12 bit

32 bit

10 bit

300 s

50 ns

1.2 s

214 s

22 s

No

Yes

No

HFO

20 MHz

50 ns

LFO/128

2.85 kHz

21.5 ms

8.11.1 Features of timer 0 and timer 1

• 12-bit counters

• One match register per timer, no capture registers and capture trigger pins are

needed

• One common output line gathering the four timers (Timer 0, Timer 1, Timer 2, and

Timer 3)

• Interrupts

• Timer 0 and timer 1 can be concatenated (multiplied)

• Timer 0 and timer 1 have two count modes: single-shot or free-running

• Timer 0 and timer 1 timeout interrupts can be individually masked

• Timer 0 and timer 1 clock source is LFO clock (LFO/2 = 182.5 kHz)

Remark: The timers are dedicated for RF communication.

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8.11.2 Features of timer 2 and timer 3

• 32-bit counters

• 1 match register per timer, no capture registers and capture trigger pins are needed

• 1 common output line gathering four timers (Timer 0, Timer 1, Timer 2, and Timer 3)

• Interrupts

• Timer 2 and timer 3 have two count modes: single-shot and free-running

• Timer 2 and timer 3 timeout interrupts can be individually masked

• Timer 2 and timer 3 clock source is the system clock

8.12 System tick timer

The PN736X microcontroller includes a system tick timer (SYSTICK) that generates a

dedicated SYSTICK exception at a fixed time interval (10 ms).

8.13 Watchdog timer

If the microcontroller enters an erroneous state, the watchdog timer resets the

microcontroller. When the watchdog timer is enabled, if the user program fails to “feed”

(reload) the watchdog timer within a predetermined time, it generates a system reset.

The watchdog timer can be enabled through software. If there is a watchdog timeout

leading to a system reset, the timer is disabled automatically.

• 10-bit counter

• Based on a 2.85 kHz clock

• Triggers an interrupt when a predefined counter value is reached

• Connected to the ARM subsystem NMI (non-maskable interrupt)

• If the watchdog timer is not periodically loaded, it resets PN736X

8.14 Clocks

The PN736X clocks are based on the following clock sources:

• 27.12 MHz external quartz

• 27.12 MHz crystal oscillator

• Internal oscillator: 20 MHz High Frequency Oscillator (HFO)

• Internal oscillator: 365 kHz Low Frequency Oscillator (LFO)

• Internal PLL at 48 MHz for the USB interface

Figure 20 indicates the clocks used by each IP.

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Fig 20. Clocks and IP overview

8.14.1 Quartz oscillator (27.12 MHz)

The 27.12 MHz quartz oscillator is used as a reference for all operations where the

stability of the clock frequency is important for reliability. It includes contactless interface,

SPI and I²C master interfaces, USB PLL for the USB interface, and HSUART.

Regular and low-power crystals can be used. Figure 21 shows the circuit for generating

stable clock frequency. The quartz and trimming capacitors are off-chip.

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Fig 21. Crystal oscillator connection

Table 19 describes the levels of accuracy and stability required on the crystal.

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Table 19. Crystal requirements

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_xtal

crystal frequency

ISO/IEC and FCC

compliancy

27.12

MHz

[1]

f_xtal

ESR

C_L

crystal frequency accuracy

equivalent series resistance

load capacitance

50

+50

100

ppm



50

10

pF

P_drive

drive power

100

W

[1] This requirement is according to FCC regulations requirements. The frequency should be +/ 14 kHz to

meet ISO/IEC 14443 and ISO/IEC 18092.

8.14.2 USB PLL

The PN736X integrates a dedicated PLL to generate a low-noise 48 MHz clock, by using

the 27.12 MHz from the external crystal. The 48 MHz clock generated is used as the USB

main clock.

Following are the USB PLL features:

• Low-skew, peak-to-peak cycle-to-cycle jitter, 48 MHz output clock

• Low power in active mode, low power-down current

• On-chip loop filter, external RC components not needed

8.14.3 High Frequency Oscillator (HFO)

The PN736X has an internal low-power High Frequency Oscillator (HFO) that generates a

20 MHz clock. The HFO is used to generate the system clock. The system clock default

value is 20 MHz, and it can be configured to 10 MHz and 5 MHz for reducing power

consumption.

8.14.4 Low Frequency Oscillator (LFO)

The PN736X has an internal low-power Low Frequency Oscillator (LFO) that generates a

365 kHz clock. The LFO is used by EEPROM, POR sequencer, contactless interface,

timers, and watchdog.

8.14.5 Clock configuration and clock gating

In order to reduce the overall power consumption, the PN736X facilitates adjustment of

system clock. It integrates clock gating mechanisms.

The system clock can be configured to the following values: 20 MHz, 10 MHz, and 5 MHz.

The clock of the following blocks can be activated or deactivated, depending on the

peripherals used:

• Contactless interface

• Host interfaces

• I²C master interface

• SPI master interface

• CRC engine

• Timers

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• Random generator

• System clock

• EEPROM

• Flash memory

8.15 Power management

8.15.1 Power supply sources

The PN736X is powered using the following supply inputs:

• VBUS: main supply voltage for internal analog modules, digital logic and memories

• TVDD_IN: supply for the contactless interface

• PVDD_IN: pad voltage reference and supply of the host interface (HSU, USB, I²C,

and SPI) and the GPIOs

• PVDD_M_IN: pad voltage reference and supply for the master interface (SPI and I²C)

• DVDD: supply for the internal digital blocks

8.15.2 PN736X Power Management Unit (PMU)

The integrated Power Management Unit (PMU) provides supply for internal analog

modules, internal digital logic and memories, pads. It also provides supply voltages for the

contactless interface.

It automatically adjusts internal regulators to minimize power consumption during all

possible power states.

The power management unit embeds a mechanism to prevent the IC from overheat,

overconsumption, or overloading the DC-to-DC converter:

• TXLDO 5 V monitoring

• Temperature sensor

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Fig 22. PN736X LDOs and power pins overview

PN736X embeds five Low Drop-Out regulators (LDO) for ensuring the stability of power

supply, while the application is running.

• MLDO (main LDO): It provides1.8 V supply for internal analog, digital and memory

modules

• TXLDO: This LDO can be used to supply the RF transmitter

• PVDD_LDO: PVDD_LDO provides 3.3 V that can be used for all pads supply

Some are used while some are optional, like the TX_LDO which is proposed for the RF

interface. It is up to the application designer to decide whether LDOs should be used.

8.15.2.1 Main LDO

The Main LDO (MLDO) provides a 1.8 V supply for all internal, digital and memory

modules. It takes input from VBUS. MLDO includes a current limiter that avoids damage

to the output transistors.

Output supply is available on VDD pin which must be connected externally to the DVDD

pin.

Following are the main LDO features:

• Main Low-Drop-Out (MLDO) voltage regulator powered by VBUS (external supply)

• Current limiter to avoid damaging the output transistors

8.15.2.2 PVDD_LDO

The PVDD_LDO provides 3.3 V supply, that can be used for all digital pads. It may also be

used to provide 3.3 V power to external components, avoiding an external LDO. It is

supplied by VBUS, and requires a minimum voltage of 4 V to be functional. It delivers a

maximum of 30 mA.

The output pin for PVDD_LDO is PVDD_OUT.

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PVDD_LDO is used to provide the necessary supply to PVDD_IN and PVDD_M_IN (pad

supply for master interfaces).

When an external supply is used, PVDD_OUT must be connected to the ground. When

the LDO output is connected to the ground, the PN736X chip switches off the

PVDD_LDO.

The PVDD_LDO has a low-power mode, which is used automatically by the PN736X

when the chip is in standby mode or suspend mode. It facilitates supply to HOST pads

and GPIOS, and to detect wake-up signals coming from these interfaces.

Following are the PVDD_LDO features:

• Low-Drop-Out voltage regulator powered by V_DDP(VBUS)(external supply)

• Supports soft-start mode to limit inrush current during the initial charge of the external

capacitance when the LDO is powered up

• Current limiter to avoid damaging the output transistors

Note: When PVDD_LDO is used, there must not be any load current drawn from

PVDD_LDO during the soft start of the PVDD_LDO.

8.15.2.3 TXLDO

The PN736X consists of an internal transmitter supply LDO. The TXLDO can be used to

maintain a constant output voltage for the RF interface.

The TXLDO is designed to protect the chip from voltage ripple introduced by the power

supply on the pin VUP_TX. It is powered through the pin VUP_TX.

The programmable output voltages are: 3.0 V, 3.3 V, 3.6 V, 4.5 V, and 4.75 V.

For a given output voltage, VUP_TX shall always be higher than 0.3 V. In other words, to

supply a 3 V output, the minimum voltage to be applied on VUP_TX is 3.3 V. If the voltage

is not sufficient, then the voltage at the pin TVDD_OUT follows the voltage at the pin

VUP_TX, lowered of 0.3 V.

When it is not used, TVDD_OUT shall be connected to TVDD_IN, and TX_LDO shall be

turned off.

Following are the TXLDO features:

• Low-Drop-Out (TXLDO) voltage regulator

• Current load up to 180 mA

• Supports soft-start mode to limit inrush current during the initial charge of the external

capacitance

• Current limiter to avoid damaging the output transistors

8.15.3 Power modes

The PN736X offers four different power modes, that enable the user to optimize its energy

consumption. They are:

• Hard power-down mode

• Standby mode

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• USB suspend mode

• Active mode

8.15.3.1 Active mode

In active mode, all functionalities are available and all IPs can be accessed. It is possible

to configure the various clocks (IP clock, system clock) using register settings so that chip

consumption is reduced. If IPs are not used, they can be disabled.

8.15.3.2 Standby mode

In standby mode, only a reduced part of the digital and the analog is active. It reduces the

chip power consumption. The possible wake-up sources are still powered.

The LFO clock is used to lower the energy needs.

Active part in standby mode: Main LDO is active, in a low-power mode, plus all

configured wake-up sources.

Depending on the application requirements, it is possible to configure PVDD_LDO in

active mode, low-power mode or shut down mode when PN736X is going to standby

mode. PVDD_LDO is active in a low-power mode by default.

Entering in standby mode: The application code triggers standby mode.

The PN736X has two internal temperature sensors. If these sensors detect an overheat,

the PN736X is put into standby mode by the application firmware. The chip leaves the

standby mode when both temperature sensors indicate that the temperature has come

below the configured limit.

Limitations: Standby mode is not possible in the following cases:

• A host communication is in progress

• A wake-up condition is fulfilled. For example, external RF field presence is a wake-up

source, and PN736X detects a field

• The RF field detector is a possible wake-up source, and the RF field detector is

disabled

• PVDD is not present

8.15.3.3 Suspend mode

In suspend mode, clock sources are stopped except LFO. It reduces the chip power

consumption.

Entering in suspend mode: An interrupt indicates to the application firmware when no

activity has been detected on the USB port for more that 3 ms. The application code

triggers the suspend mode.

Limitations: Suspend mode is prevented in the following cases:

• A host communication is in progress

• A wake-up condition is fulfilled. For example, external RF field presence is a wake-up

source, and PN736X detects a field

• The RF field detector is a possible wake-up source, and the RF field detector is

disabled

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• No voltage at pin PVDD

8.15.3.4 Wake-up from standby mode and suspend mode

PN736X can be woken-up from standby mode, and suspend mode, using the following

means:

• Host Interface: SPI, HSUART, I²C, and USB if already selected before standby mode

(SPI, HSUART, and I²C) or suspend mode (USB).

• RF field detection (presence of a reader or an NFC device in reader mode or P2P

initiator)

• GPIO

• Interrupt generated on the auxiliary UART interface, through the interrupt pin

• Wake-up counter, for example to timely check for the presence of any contactless

card

• Current overconsumption on the PVDD_OUT, voltage above 5 V on TVDD_IN

• Temperature sensor: When the PN736X goes in to standby mode because of

over-heating, and when the temperature goes below the sensor configured value,

PN736X wakes-up automatically. Each temperature sensor can be configured

separately.

It is possible to configure the sources as enabled or disabled.

8.15.3.5 Hard Power-Down (HPD) mode

The PN736X Hard Power-Down (HPD), reduces the chip power consumption, by

powering down most of the chip blocks. All clocks and LDOs are turned off, except the

main LDO which is set in low-power mode.

Entering in HPD mode: If the RST_N pin is set to low, the PN736X enters in to Hard

Power Down (HPD) mode. It also enters in to HPD mode if the V_DDP(VBUS)goes below the

critical voltage necessary for the chip to work (2.3 V) and the auto HPD feature is enabled.

Exiting the HPD mode: The PN736X leaves the HPD mode, when both RST_N pin is set

to high level and the V_DDP(VBUS)voltage is above 2.3 V.

8.15.4 Voltage monitoring

The voltage monitoring mode detects whether the voltage is within the operational

conditions to enable a proper operation of the RF interface. The following power supplies

are monitored: VBUS (two voltage monitors), VBUS_P (one voltage monitor).

Section 9.1.2 discusses about the minimum voltages necessary for contactless interface

operation.

Table 20. Threshold configuration for voltage monitor

Voltage monitor

VBUSMON1

VBUSMON2

VBUSP

Threshold 1

2.3 V

Threshold 2

2.7 V

Threshold 3

n.a.^[1]

2.7 V

4.0 V

2.7 V

3.0 V

3.9 V

[1] n.a. means not applicable.

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8.15.4.1 VBUS monitor

The PN736X includes up to two levels (2.3 V or 2.7 V) for monitoring the voltage on the

VBUS pin. If this voltage falls below one of the selected levels, the BOD asserts an

interrupt signal to the PCR. This signal may be enabled for interrupt in the interrupt enable

register in the PCR, to cause a CPU interrupt. Alternatively, software can monitor the

signal by reading a dedicated status register. Two threshold levels (2.3 V or 2.7 V) can be

selected to cause a forced Hard Power-Down (HPD) of chip.

8.15.4.2 VBUSP monitor

The PN736X includes three levels (2.7 V, 3.0 V, and 3.9 V) for monitoring the voltage on

the VBUSP pin.

8.15.4.3 PVDD LDO supply monitor

The PN736X includes up to two levels (VBUSMON2: 2.7 V or 4.0 V) for monitoring the

voltage on the PVDD LDO input supply. If supply voltage is 4.0 V or above, PVDD LDO

can be enabled. The software has to check whether the voltage is sufficient before

enabling the LDO.

8.15.5 Temperature sensor

The PN736X power management unit provides temperature sensors, associated to the

TX_LDO. It detects problems that would result in high power consumption and heating,

which could damage the chip and the user device.

Triggering levels are configurable. Following temperatures can be chosen: 135 C,

130 C, 125 C, and 120 C. By default, the temperature sensor is set to 120 C.

When one of the temperature sensors detects an increase in temperature above the

configured level, an interrupt is generated. The application can then decide to go into

standby or suspend mode. The PN registers indicate which temperature sensor

generated the interrupt.

When the temperature goes below the configured threshold temperature, PN736X wakes

up automatically.

8.16 System control

8.16.1 Reset

PN736X has six possible sources for reset. The list of sources is described in Table 21.

Table 21. Reset sources

Source

Description

software - PCR

software - ARM

I²C interface

watchdog

soft reset from the PCR peripheral

software reset form the ARM processor

I²C Standard 3.0 defines a method to reset the chip via an I²C command^[1]

reset the chip if the watchdog threshold is not periodically reloaded

power-on reset sequence; if the voltage is above 2.3 V, reset the chip

VBUS voltage

[1] This feature can be disabled.

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The watchdog reset, I²C reset and soft resets from PCR and ARM processor resets the

chip except the PCR and the ARM debug interface. The Power-On Reset (POR) resets

the complete chip including the PCR and ARM debug interface.

Upon reset, the processor executes the first instruction at address 0, which is initially the

reset vector mapped from the boot block. At that point, all the processor and peripheral

registers are initialized to predetermined values.

8.16.2 Brown-Out Detection (BOD)

The PN736X includes up to two levels for monitoring the voltage on the VBUS pin. If this

voltage falls below one of the selected voltages (2.3 V or 2.7 V), the BOD asserts an

interrupt signal to the PCR. This signal can be enabled for interrupt in the interrupt enable

register in the PCR, to cause a CPU interrupt. Alternatively, software can monitor the

signal by reading a dedicated status register. Two threshold levels (2.3 V and 2.7 V) can

be selected to cause a forced Hard Power-Down (HPD) of the chip.

8.16.3 APB interface and AHB-Lite

All APB peripherals are connected to one APB bus.

The AHB-Lite connects the AHB masters. The AHB masters include the CPU bus of the

ARM Cortex-M0, host interface, contactless interface, SPI interface to the flash memory. It

also includes EEPROM memory, SRAM, ROM, and AHB to APB bridge.

8.16.4 External interrupts

PN736X enables the use of 12 GPIOs as edge or level sensitive inputs (GPIO1 to

GPIO12).

8.17 SWD debug interface

The Cortex-M0 processor-based devices use serial wire ARM CoreSight^TMDebug

technology. The PN736X is configured to support four break points and two watch points.

The SWD interface can be disabled for having code (or data) read/write access

protection. A dedicated SWD disable bit is available in the protected area of the EEPROM

memory. Once the SWD interface is disabled, it is not possible to enable it anymore.

8.17.1 SWD interface features

• Run control of the processor allowing to start and stop programs

• Single step one source or assembler line

• Set breakpoints while the processor is running

• Read/write memory contents and peripheral registers on-the-fly

• “Printf” like debug messages through the SWD interface

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9. Application design-in information

9.1 Power supply connection

The following table indicates the power sources for all the PN736X power inputs.

Table 22. Power supply connection

Power inputs Power sources

Comment

VBUS

external source

chosen according to the expected performances

(RF power when TX_LDO is used, global power

consumption)

VBUSP

external source; connected to

VBUS

VBUSP is connected to VBUS, with the addition

of a decoupling capacitor

TVDD_IN

PVDD_IN

external supply or using the

TX_LDO

external supply can be used (up to 5.5 V) to

increase RF power

external supply or using

PVDD_LDO

PVDD_LDO can be used, when V_DDP(VBUS)>

4 V. It makes a regulated 3.3 V supply available

to GPIO and host interface pads, without the

addition of an external LDO

for 1.8 V, external supply is used

PVDD_M_IN external supply or using

PVDD_LDO

PVDD_LDO can be used, when V_DDP(VBUS)>

4 V. It makes a regulated 3.3 V supply available

to GPIO and host interface pads, without the

addition of an external LDO

external supply is used for 1.8 V

DVDD

connected to the VDD output

VDD provides 1.8 V stabilized supply, out of the

MAIN_LDO

[1] When external supply and PVDD_OUT are not used, PVDD_OUT must be connected to the ground, with a

ground resistance of less than 10 .

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9.1.1 Powering up the microcontroller

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(1) Powering up the microcontroller and the digital blocks (DVDD).

(2) Two possibilities for powering the pad interfaces (PVDD_IN and PVDD_M_IN).

Remark: The capacitance must be chosen so that the capacitance value is correct at 5 V

Fig 23. Powering up the PN736X microcontroller

The schematics in Figure 23 describe the power supply of the chip (V_DDP(VBUS)), including

the digital blocks supply (DVDD). It indicates two possibilities to supply the pads, using the

internal LDO, or using an external supply. The internal LDO requires that V_DDP(VBUS)> 4

V. It avoids the requirement of a separate LDO when V_DDP(VBUS)has a sufficient voltage.

Power supply is available to pads through PVDD_IN (host interface). Similarly, power

supply is available to master interface pads through PVDD_M_IN. When PVVD _LDO is

used, maximum total current available from PVDD_OUT for the pads supply is 30 mA.

When an external source is used for PVDD_IN and PVDD_M_IN, PVDD_OUT must be

connected to the ground, with a ground resistance of less than 10 .

9.1.2 Powering up the contactless interface

Powering of contactless interface is done though TVDD_IN. Internal LDO (TXLDO) or

external supply can be used.

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(2) Without using TXLDO

Fig 24. Powering up the contactless interface using a single power supply

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The capacitance value must be chosen so that the capacitance value is correct at 5 V.

(1) Using TXLDO.

(2) Without using TXLDO.

Fig 25. Powering up the contactless interface using an external RF transmitter supply

Note: The TVDD_OUT pin must not be left floating. It should be at the same voltage as

the TVDD_IN pin.

The power design must be designed properly to be able to deliver a clean power supply

voltage.

In any case (external TVDD or internal TX_LDO internal supply), TVDD_IN supply must

be stable before turning on the RF field. The capacitor shall be 6.8 F or higher

(up to 10 F)

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Every noise level on top of the supply voltage can disturb the RF communication

performance of the PN736X. Therefore, special attention must be paid to the filtering

circuit.

When powering up the device through the USB interface, TVDD capacitor value shall be

chosen so that the maximum capacitance on VBUS remains as per the USB specification.

9.2 Connecting the USB interface

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Fig 26. USB interface on a bus-powered device

When the USB interface is not used, the USB_VBUS pin shall be connected to the

ground.

9.3 Connecting the RF interface

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Fig 27. RF interface - example of connection to an antenna

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9.4 Unconnected I/Os

When not used, the following pins need to be “not connected”:

• I2C Master interface: I2CM_SDA, I2CM_SCL

• SPI Master interface: SPIM_SSN, SPIM_SCLK, SPIM_MOSI, SPIM_MISO

• AUX interface: INT_AUX, IO_AUX, CLK_AUX

Pads have to be configured in GPIO mode, pad input and out put driver need to be

disabled.

10. Limiting values

Table 23. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

V_ESD

electrostatic discharge voltage

Human Body Model (HBM)

[1]

on all pins

2

+2

kV

Charged Device Model (CDM)

on all pins

1

+1

kV

T_stg

storage temperature

non-operating

55

+150

+125

1050

C

T_j(max)

P_tot

maximum junction temperature

total power dissipation

-

C

reader mode; V_DDP(VBUS)= 5.5 V

mW

[1] EIA/JESD22-A114-D.

Table 24. Limiting values for GPIO1 to GPIO12

Symbol

Parameter

Conditions

Min

Max

Unit

V_i

input voltage

0.3

4.2

V

Table 25. Limiting values for I²C master pins (i2cm_sda, i2cm_scl)

Symbol

Parameter

Conditions

Min

Max

Unit

V_i

input voltage

0.3

4.2

V

Table 26. Limiting values for SPI master pins ( spim_nss, spim_miso, spim_mosi and spi_clk)

Symbol

Parameter

Conditions

Min

Max

Unit

V_i

input voltage

0.3

4.2

V

Table 27. Limiting values for host interfaces atx_a, atx_b, atx_c, atx_d in all configurations (USB, HSUART, SPI and

I²C)

Symbol

Parameter

Conditions

Min

Max

Unit

V_i

input voltage

0.3

4.2

V

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Table 28. Limiting values for crystal oscillator

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

V_IH

high-level input voltage

XTAL1, XTAL2

0

2.2

V

Table 29. Limiting values for power supply

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions

Min

0.3

Max

6

Unit

V

[1]

V_DDP(VBUS)power supply voltage on pin VBUS

V_DDP(VBUSP)power supply voltage on pin VBUSP

6

V

pin supply voltage for host interface and GPIOs (on pin PVDD_IN)

[1]

V_DD(PVDD)

PVDD supply voltage

on pin PVDD_IN; power supply

for host interfaces and GPIOs

0.3

4.2

V

pin supply voltage for master interfaces (on pin PVDD_M_IN)

V_DD(PVDD)

PVDD supply voltage

on pin PVDD_M_IN; power

supply for master interfaces

RF interface LDO (pin VUP_TX)

V_I(LDO)LDO input voltage

RF transmitter (pin TVDD_IN)

V_DD(TVDD)TVDD supply voltage

[1]

for RF interface LDO

0.3

6

V

for RF interface transmitter

[1] Maximum/minimum voltage above the maximum operating range and below ground that can be applied for a short time (< 10 ms) to a

device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter life time of the device.

Table 30. Limiting values for RF interface

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

V_i

input voltage

on pins RXN and RXP

0

2.2

V

[1] Maximum/minimum voltage above the maximum operating range and below ground that can be applied for a short time (< 10 ms) to a

device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter life time of the device.

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11. Recommended operating conditions

Table 31. Operating conditions

Symbol

T_amb

Parameter

Conditions

Min

40

2.3

Typ

25

-

Max Unit

ambient temperature

JDEC PCB0.5

85

C

V_DDP(VBUS)

power supply voltage on pin VBUS external PVDD supply, card

5.5

V

emulation and passive target

(PLM)

external PVDD supply, reader

mode, NFC initiator and

passive/active target mode (ALM

and PLM)

2.7

4

-

5.5

V

internal PVDD_LDO supply,

reader mode, NFC initiator and

passive/active target mode (ALM

and PLM)

host interface and GPIOs pin power supply (pin PVDD_IN)

V_DD(PVDD)

PVDD supply voltage

for digital pins

1.8 V pin supply

1.65 1.8

3.3

1.95

3.6

V

3.3 V pin supply

3

SPI master and I²C master interfaces pin power supply (on pin PVDD_M_IN)

V_DD(PVDD)

PVDD supply voltage

for master pins

1.8 V pin supply

3.3 V pin supply

1.65 1.8

1.95

3.6

V

3

3.3

RF interface LDO (pin VUP_TX)

V_I(LDO)LDO input voltage

TX_LDO supply for powering up

RF interface

3

5

5.5

V

RF interface transmitter

I_DD(TVDD)

TVDD supply current

on pin TVDD_IN

-

250

mA

12. Thermal characteristics

Table 32. Thermal characteristics

Symbol

Parameter

Conditions

Typ

40

Unit

K/W

R_th(j-a)

thermal resistance from junction to in free air with exposed pad soldered on a

ambient

four-layer JEDEC PCB

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13. Characteristics

13.1 Static characteristics

Table 33. Static characteristics for RST_N input pin

Data are given for T_amb= 40 C to +85 C; unless otherwise specified

Symbol

V_IH

Parameter

Conditions

Min

1.1

0

Typ

Max

Unit

V

high-level input voltage

low-level input voltage

-

V_DDP(VBUS)

V_IL

-

0.4

V

I_IH

high-level input current V_i= V_DDP(VBUS)

low-level input current V_i= 0 V

input capacitance

-

1

-

A

pF

I_IL

1

-

C_in

5

-

Table 34. Static characteristics for IRQ input pin

Data are given for T_amb= 40 C to +85 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_OH

high-level output

voltage

I_OH< 3 mA

V_{PVDD_IN}

0.4



-

V_{PVDD_IN}

V

V_OL

low-level output

voltage

I_OL< 3 mA

0

-

0.4

V

C_L

load capacitance

extra pull down

-

20

pF

R_pull-down

extra pull-down is

activated in HDP

0.45

0.8

M

Table 35. Static characteristics for DWL_REQ

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IH

high-level input voltage VV_{PVDD_IN}= 1.8 V

0.65 

-

V

V_{PVDD_IN}

V_IL

high-level input voltage VV_{PVDD_IN}= 1.8 V

-

0.35 

V

V_{PVDD_IN}

V_IH

V_IL

I_IH

high-level input voltage VV_{PVDD_IN}= 3.3 V

high-level input current V_I= PVDD_IN

low-level input current V_I= 0 V

load capacitance

2

-

V

-

0.8

V

-

1

-

A

pF

I_IL

1

-

C_L

5

-

13.1.1 GPIO static characteristics

Table 36. Static characteristics for GPIO1 to GPIO21

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_OH

high-level output

voltage

I_OH< 3 mA

V_{PVDD_IN}

0.4

-

V_{PVDD_IN}

V

V_OL

V_IH

low-level output

voltage

I_OH< 3 mA

0

2

-

0.4

V

high-level input voltage V_{PVDD_IN}= 3.3 V

V_{PVDD_IN}= 1.8 V

-

V

0.65 

V_{PVDD_IN}

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Table 36. Static characteristics for GPIO1 to GPIO21 …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

V_IL

low-level input voltage V_{PVDD_IN}= 3.3 V

V_{PVDD_IN}= 1.8 V

-

0.8

0.35 

V

V_{PVDD_IN}

V_hys

I_OZ

hysteresis voltage

V_{PVDD_IN}= 1.8 V and

V_{PVDD_IN}= 3.3 V

0.1 

V_{PVDD_IN}

-

V

OFF-state output

current

V_O= 0 V;

-

1000

nA

V_O= V_{PVDD_IN};on-chip

pull-up/pull-down

resistors disabled

R_pd

R_pu

I_OSH

pull-down resistance

pull-up resistance

V_{PVDD_IN}= 3.3 V

V_{PVDD_IN}= 1.8 V

V_{PVDD_IN}= 3.3 V

V_{PVDD_IN}= 1.8 V

65

-

90

-

120

58

k

mA

short circuit current

output high

Drive high; cell

connected to ground;

V_{PVDD_IN}= 3.3 V

Drive low; cell

connected to

PVDD_IN;

-

30

mA

V_{PVDD_IN}= 1.8 V

I_OSL

short circuit current

output low

V_OH= V_{PVDD_IN}= 3.3

V

-

54

37

mA

V_OH= V_{PVDD_IN}= 1.8

V

I_IL

low-level input current V_I= 0 V

1

-

µA

mA

I_IH

I_OH

high-level input current V_I= V_{PVDD_IN}

1

3

high-level output

current

V_OH= V_{PVDD_IN}

-

I_OL

low-level output

current

V_OL= 0 V

-

3

mA

13.1.2 Static characteristics for I²C master

Table 37. Static characteristics for I²CM_SDA, I²CM_SCL - S

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_OH

high-level output

voltage

I_OH< 3 mA

0.7 

V_{PVDD_M_IN}

-

V_{PVDD_M_IN}

V

V_OL

low-level output

voltage

I_OL< 3 mA

0

-

0.4

V

C_L

load capacitance

-

10

-

pF

V

V_IH

High-level input

voltage

0.7 

V_{PVDD_M_IN}

V_IL

low-level input voltage

-

0.3 

V

V_{PVDD_M_IN}

I_IH

I_IL

high-level input current V_I= V_{PVDD_M_IN}

low-level input current V_I= 0 V

input capacitance

-

1

-

A

pF

1

-

C_in

5

-

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13.1.3 Static characteristics for SPI master

Table 38. Static characteristics for SPIM_MOSI

Symbol

V_OH

Parameter

Conditions

Min

Typ

Max

Unit

V

high-level output voltage I_OH< 3 mA

V_{PVDD_M_IN}0.4

-

V_{PVDD_M_IN}

V_OL

low-level output voltage

load Capacitance

I_OL< 3 mA

0

-

0.4

20

V

C_L

pF

Table 39. Static characteristics for SPIM_NSS

Symbol

V_OH

Parameter

Conditions

Min

Typ

Max

Unit

V

high-level output voltage I_OH< 3 mA

V_{PVDD_M_IN}0.4

-

V_{PVDD_M_IN}

V_OL

low-level output voltage

load Capacitance

I_OL< 3 mA

0

-

0.4

20

V

C_L

pF

Table 40. Static characteristics for SPIM_MISO

Symbol

V_IH

V_IL

Parameter

Conditions

Min

Typ

Max

Unit

V

high-level input voltage

low-level input voltage

high-level input voltage

low-level input voltage

high-level input current

low-level input current

input capacitance

V_{PVDD_M_IN}= 1.8 V

V_{PVDD_M_IN}= 3.3 V

V_i= V_{PVDD_M_IN}

V_i= 0 V

0.65  V_{PVDD_M_IN}

-

5

-

0.35 V_{PVDD_M_IN}

V

V_IH

V_IL

2

-

V

0.8

V

I_IH

-

1

-

µA

pF

I_IL

1

-

C_in

-

Table 41. Static characteristics for SPI_SCLK

Symbol

V_OH

Parameter

Conditions

Min

Typ

Max

Unit

V

high-level output voltage I_OH< 3 mA

V_{PVDD_M_IN}0.4

-

V_{PVDD_M_IN}

V_OL

low-level output voltage

load capacitance

I_OL< 3 mA

0

-

0.4

20

V

C_L

pF

13.1.4 Static characteristics for host interface

Table 42. Static characteristics for ATX_ used as SPI_NSS, ATX_ used as I²CADR0, ATX_ used as SPI_SCK, ATX_

used as SPI_MOSI

Symbol

V_IH

V_IL

Parameter

Conditions

Min

Typ

Max

Unit

V

high-level input voltage

low-level input voltage

high-level input voltage

low-level input voltage

high-level input current

low-level input current

input capacitance

V_{PVDD_IN}= 1.8 V

V_{PVDD_IN}= 3.3 V

V_i= V_{PVDD_IN}

V_i= 0 V

0.65  V_{PVDD_M_IN}

-

5

-

0.35  V_{PVDD_M_IN}

V

V_IH

V_IL

2

-

V

0.8

V

I_IH

-

1

-

µA

pF

I_IL

1

-

C_in

-

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Table 43. Static characteristics of ATX_ used as I²CSDA, ATX_ used as I²CSCL

Symbol

V_OH

V_OL

C_L

Parameter

Conditions

Min

Typ

Max

Unit

V

high-level output voltage I_OH< 3 mA

0.7  V_{PVDD_IN}

-

5

V_{PVDD_IN}

low-level output voltage

load capacitance

I_OL< 3 mA

0

0.4

V

-

10

pF

V

V_IH

high-level input voltage

low-level input voltage

high-level input current

low-level input current

Input capacitance

0.7  V_{PVDD_IN}

-

V_IL

-

0.3  V_{PVDD_IN}

V

I_IH

V_i= V_{PVDD_IN}

V_i= 0 V

-

1

-

A

pF

I_IL

1

-

C_in

-

Table 44. Static characteristics of ATX_ used as SPIMISO

Symbol

V_OH

Parameter

Conditions

Min

Typ

Max

V_{PVDD_IN}

0.4

Unit

V

high-level output voltage I_OH< 3 mA

low-level output voltage I_OL< 3 mA

load capacitance

V_{PVDD_IN} 0.4

-

V_OL

0

-

V

C_L

20

pF

Table 45. USB characteristics

Data are given for T_amb= 40 C to +85 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

10

4

Typ

Max

10

Unit

A

V

I_OZ

OFF-state output current 0 V < V_i< 3.3 V

-

V_DDP(VBUS)power supply voltage on

pin VBUS

5.5

V_DI

differential input

sensitivity voltage

(D+) (D)

0.2

0.8

-

V

V_CM

differential common

mode voltage range

includes V_DIrange

2.5

2

V_th(rs)se

single-ended receiver

switching threshold

voltage

V_OL

low-level output voltage for low-speed or

full-speed; R_Lof 1.5

-

0.3

V

k to 3.6 V

V_OH

high-level output voltage driven; for low- speed

or full-speed;

2.8

V_{PVDD_IN}

R_Lof 15 k to GND

transceiver capacitance pin to GND

C_trans

Z_DRV

-

15

-

pF

driver output impedance with 33  series

28

44

2



for driver which is not

resistor; steady state

high-speed capable

drive

V_CRS

output signal crossover

voltage

1.3

-

V

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Table 46. Static characteristics of HSU_TX and HSU RTS pin

Data are given for T_amb= 40 C to +85 C; unless otherwise specified

Symbol

V_OH

Parameter

Conditions

Min

Typ

Max

V_{PVDD_IN}

0.4

Unit

V

high-level output voltage I_OH< 3 mA

low-level output voltage I_OL< 3 mA

load capacitance

V_{PVDD_IN} 0.4

-

V_OL

0

-

V

C_L

20

pF

Table 47. Static characteristics of HSU_RX, HSU_CTS

Data are given for T_amb= 40 C to +85 C; unless otherwise specified

Symbol

V_IH

V_IL

Parameter

high-level input voltage V_{PVDD_M_IN}= 1.8 V

low-level input voltage V_{PVDD_M_IN}= 1.8 V

high-level input voltage V_{PVDD_M_IN}= 3.3 V

Conditions

Min

Typ

Max

Unit

V

0.65  V_{PVDD_IN}

-

5

-

0.35  V_{PVDD_IN}

V

V_IH

V_IL

2

-

V

low-level input voltage

high-level input current

low-level input current

load capacitance

V_{PVDD_M_IN}= 3.3 V

0.8

V

I_IH

-

1

-

A

pF

I_IL

1

-

C_L

-

13.1.5 Clock static characteristics

Table 48. Static characteristics of XTAL pin (XTAL1, XTAL2)

T_amb= 40 C to +85C

Symbol

Parameter^[1]

Conditions

Min

Typ^[2]Max

Unit

Input clock characteristics on XTAL1 when using PLL

V_i(p-p)

peak-to-peak input

voltage

0.2

-

1.65

V

XTAL pin characteristics XTAL PLL input

I_IH

high-level input current

low-level input current

input voltage

V_i= V_DD

V_i= 0 V

-

1

A

V

I_IL

1

-

V_i

-

V_DD

V_AL

C_in

input voltage amplitude

input capacitance

200

-

mV

pF

all power modes

2

Pin characteristics for 27.12 MHz crystal oscillator

C_in

input capacitance

pin XTAL1

pin XTAL2

-

2

-

pF

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C) with nominal supply voltages.

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13.1.6 Static characteristics - power supply

Table 49. Static characteristics for power supply

Data are given for T_amb= 40 C to +85 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

pin supply: PVDD_LDO

V_O(LDO)

LDO output voltage

V_DDP(VBUS)>= 4.0 V, I_PVDDOUT

<= 30 mA

3

-

3.3

-

3.6

30

V

I_{DD(PVDD_OUT)}maximum supply

current

for pin PVDD_OUT

mA

pin supply for host interface and GPIOs (on pin PVDD_IN)

I_DD(PVDD)PVDD supply current

pin supply for master interfaces (on pin PVDD_M_IN)

I_DD(PVDD)PVDD supply current

contactless interface: TX_LDO (pins VUP_TX, TVDD_OUT)

-

25

mA

V_I(LDO)

LDO input voltage

3

-

5.5

V

I_L(LDO)(max)

maximum LDO load

current

180

mA

V_O(LDO)

LDO output voltage

DC output voltage (target: 3.0 V)

5.5 V > V_I(LDO)> 3.3 V

2.8

-

3

3.25

-

V

DC output voltage (target: 3.0 V)

3.3 V > V_I(LDO)> 2.7 V

V_I(LDO)

0.3



V

DC output voltage (target: 3.3 V)

5.5 V > V_I(LDO)> 3.6 V

3.1

-

3.3

3.55

-

V

DC output voltage (target: 3.3 V)

3.6 V > V_I(LDO)> 2.7 V

V_I(LDO)

0.3

V

DC output voltage (target: 3.6 V)

5.5 V > V_I(LDO)> 3.9 V

3.4

-

3.6

3.95

-

V

DC output voltage (target: 3.6 V)

3.9 V > V_I(LDO)> 2.7 V

V_I(LDO)

0.3

V

DC output voltage (target: 4.5 V)

5.5 V > V_I(LDO)> 5.0 V

4.3

4.55

-

4.5

4.75

-

4.9

5.2

180

V

DC output voltage (target: 4.7 V)

5.5 V > V_I(LDO)> 5.0 V

V

I_O(LDO)

LDO output current

V_I(LDO)= 5.5 V

mA

Contactless interface: RF transmitter (on pin TVDD_IN)

I_DD(TVDD)

TVDD supply current

maximum current supported by

the RF transmitter

-

250

mA

Table 50. Static characteristics for voltage monitors

T_amb= 40 C to +85 C

Symbol

Parameter

Conditions

VBUS monitor;

set to 2.3 V

set to 2.7 V

set to 4.0 V

Min

Typ

Max

Unit

V_(th)HL

negative-going

threshold voltage

2.15

2.6

2.3

2.45

2.95

3.9

V

2.75

3.8

3.6

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Table 50. Static characteristics for voltage monitors

T_amb= 40 C to +85 C

Symbol

Parameter

Conditions

VBUS monitor

set to 2.3 V

set to 2.7 V

set to 4.0 V

VBUSP monitor

set to 2.7 V

set to 3.0 V

set to 3.9 V

VBUSP monitor

set to 2.7 V

set to 3.0 V

set to 3.9 V

Min

Typ

Max

Unit

V_hys

hysteresis voltage

100

40

150

80

200

100

mV

V_(th)HL

negative-going

threshold voltage

2.45

2.68

3.7

2.56

2.825

3.9

2.65

2.95

4.1

V

V_hys

hysteresis voltage

12

14

20

25

30

35

40

55

mV

13.1.7 Static characteristics for power modes

Table 51. Static characteristics for power modes

T_amb= 40 C to +85 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_DDP(VBUS)power supply current on

pin VBUS

active mode; V_DDP(VBUS)= 5.5 V,

external PVDD, external TVDD, all

IP clocks disabled

-

6.5

-

mA

code

while(1){}

executed from flash;

active mode; V_DDP(VBUS)= 5.5 V,

external PVDD, external TVDD, all

IP clocks enabled

-

8.5

-

mA

code

while(1){}

executed from flash;

suspend mode; V_DDP(VBUS)= 5.5 V,

external PVDD, T = 25 C

-

120

360

250

440

A

V_BUS= 5.5 V, T = 25 °C, internal

PVDD LDO, including D+ and D

pull-up

µA

standby mode; V_DDP(VBUS)= 3.3 V;

external PVDD supply; T_amb= 25 C

-

18

55

12

-

A

standby mode; V_DDP(VBUS)= 5.5 V;

V_internalPVDD supply; T_amb= 25 C

-

hard power down; V_DDP(VBUS)

=

18

5.5 V; RST_N = 0 V; T_amb= 25C

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13.1.8 Static characteristics RF interface

Table 52. Static characteristics for RF interface

Data are given for T_amb= 40 C to +85 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

pins ANT1 and ANT2

Z

impedance

between ANT1 and ANT2;

low impedance

-

10

17



pins RXN and RXP

V_i(dyn)

C_in

dynamic input voltage

on pins RXN and RXP

-

V_DD 0.05 V

input pin capacitance

impedance

-

12

-

pF

Z

between pins RX to VMID;

reader, card emulation and

P2P modes

0

15

k

V_det

detection voltage

card emulation and target

modes; configuration for

19 mV threshold

-

30

-

mV_(p-p)

pins TX1 and TX2

V_OH

high-level output voltage pins TX1 and TX2;

V_{TVDD_IN}

mV

T_{VDD_IN}= 3.1 V and

I_OH= 30 mA

 150

V_OL

R_OL

low-level output voltage pins TX1 and TX2;

-

200

80

mV



T_{VDD_IN}= 3.1; I_TX= 30 mA

low-level output

resistance

V_TX= V_TVDD 100 mV;

CWGsN = 01h

V_TX= V_TVDD100 mV;

10



CWGsN = 0Fh

R_OH

high-level output

resistance

V_TX= V_TVDD 100 mV

10



13.2 Dynamic characteristics

Table 53. Dynamic characteristics for IRQ input pin

Data are given for T_amb= 40 C to +85 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_f

fall time

high speed; C_L= 12 pF;

V_{PVDD_IN}= 3.3 V

1

-

3.5

ns

high speed; C_L= 12 pF;

V_{PVDD_IN}= 1.8 V

1

3

2

-

3.5

10

ns

t_f

fall time

slow speed; C_L= 12 pF;

V_{PVDD_IN}= 3.3 V

slow speed; C_L= 12 pF;

V_{PVDD_IN}= 1.8 V

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Table 53. Dynamic characteristics for IRQ input pin …continued

Data are given for T_amb= 40 C to +85 C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_r

rise time

high speed: C_L= 12 pF;

V_{PVDD_IN}= 3.3 V

1

-

3.5

ns

high speed: C_L= 12 pF;

1

3

2

-

3.5

10

ns

V_{PVDD_IN}= 1.8 V

t_r

rise time

slow speed: C_L= 12 pF;

V_{PVDD_IN}= 3.3 V

slow speed: C_L= 12 pF;

V_{PVDD_IN}= 1.8 V

13.2.1 Flash memory dynamic characteristics

Table 54. Dynamic characteristics for flash memory

Symbol

t_prog

Parameter

Conditions

Min

Typ

-

Max

Unit

programming time

endurance

1 page (64 bytes); slow clock

-

2.5

ms

N_Endu

t_ret

200

-

500

20

-

cycles

years

retention time

13.2.2 EEPROM dynamic characteristics

Table 55. Dynamic characteristics for EEPROM

Symbol

t_prog

Parameter

Conditions

Min

Typ

2.8

500

20

Max

Unit

programming time

endurance

1 page (64 bytes)

-

ms

N_Endu

t_ret

300

-

Kcycles

years

retention time

13.2.3 GPIO dynamic characteristics

ꢈꢂꢁꢑ

ꢍꢂꢁꢑ

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Fig 28. Output timing measurement condition for GPIO

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Table 56. Dynamic characteristics for GPIO1 to GPIO21

T_amb= 40 C to +85 C

Symbol

Parameter

Conditions

Min

2.0

1.0

3.0

1.0

2.0

1.0

3.0

1.0

Max

10.0

3.5

Unit

ns

t_r

rise time

C_L= 12 pF; PVDD = 1.8 V; slow speed

C_L= 12 pF; PVDD = 1.8 V; fast speed

C_L= 12 pF; PVDD = 3.3 V; slow speed

C_L= 12 pF; PVDD = 3.3 V; fast speed

C_L= 12 pF; PVDD = 1.8 V; slow speed

C_L= 12 pF; PVDD = 1.8 V; fast speed

C_L= 12 pF; PVDD = 3.3 V; slow speed

C_L= 12 pF; PVDD = 3.3 V; fast speed

10.0

3.5

t_f

fall time

10.0

3.5

10.0

3.5

13.2.4 Dynamic characteristics for I²C master

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Fig 29. I C-bus pins clock timing

Table 57. Timing specification for fast mode plus I²C

T_amb= 40 C to +85 C

Symbol

f_SCL

Parameter

Conditions

Min

0

Max

Unit

MHz

ns

SCL clock frequency

fast mode plus; C_b< 100 pF

1

-

t_SU;STA

set-up time for a

(repeated) START

condition

260

t_HD;STA

t_LOW

hold time (repeated)

START condition

fast mode plus; C_b< 100 pF

260

500

260

-

ns

low period of the SCL

clock

t_HIGH

high period of the SCL

clock

t_SU;DAT

t_HD;DAT

t_r(SDA)

t_f(SDA)

V_hys

data set-up time

data hold time

SDA rise time

SDA fall time

fast mode plus; C_b< 100 pF

50

-

ns

V

0

-

120

-

hysteresis of Schmitt

trigger inputs

0.1 

V_{PVDD_M_IN}

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Table 58. Timing specification for fast mode I²C

T_amb= 40 C to +85 C

Symbol

f_SCL

Parameter

Conditions

Min

0

Max

400

-

Unit

kHz

ns

SCL clock frequency

fast mode; C_b< 400 pF

t_SU;STA

set-up time for a (repeated) START fast mode; C_b< 400 pF

condition

600

t_HD;STA

hold time (repeated) START

condition

fast mode; C_b< 400 pF

600

-

ns

t_LOW

low period of the SCL clock

high period of the SCL clock

data set-up time

fast mode; C_b< 400 pF

fast mode plus; C_b< 100 pF

1.3

600

100

0

-

s

ns

V

t_HIGH

-

t_SU;DAT

t_HD;DAT

t_r(SDA)

t_f(SDA)

V_hys

-

data hold time

900

250

-

SDA rise time

30

SDA fall time

30

hysteresis of Schmitt trigger inputs fast mode; C_b< 400 pF

0.1 

V_{PVDD_IN}

13.2.5 Dynamic characteristics for SPI

7

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Yꢏ4ꢐ

'$7$ꢁ9$/,'

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026,

0,62

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Fig 30. SPI master timing

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Table 59. Dynamic characteristics and Timing specification for SPI master interface

Symbol

Parameter

Conditions

Min

Max

Unit

f_SCK

SCK frequency

0

6.78

MHz

controlled by the host

t_DS

data set-up time

data hold time

25

-

ns

t_DH

t_v(Q)

-

data output valid time

25

t_h(Q)

data output hold time

-

25

ns

Dynamic characteristics for SPI_SCLK, SPIM_NSS, SPIM_MOSI

t_f

t_r

t_f

t_r

fall time

rise time

fall time

rise time

C_L= 12 pF; high speed; V_{PVDD_IN}= 3.3 V

C_L= 12 pF; slow speed; V_{PVDD_IN}= 3.3 V

C_L= 12 pF; high speed; V_{PVDD_IN}= 3.3 V

C_L= 12 pF; slow speed; V_{PVDD_IN}= 3.3 V

C_L= 12 pF; high speed; V_{PVDD_IN}= 1.8 V

C_L= 12 pF; slow speed; V_{PVDD_IN}= 1.8 V

C_L= 12 pF; high speed; V_{PVDD_IN}= 1.8 V

C_L= 12 pF; slow speed; V_{PVDD_IN}= 1.8 V

1

3

1

3

1

2

1

2

3.5

10

ns

3.5

10

3.5

10

3.5

10

13.2.6 Dynamic characteristics of host interface

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Fig 31. I²C-bus pins clock timing

Table 60. Timing specification for I2C high speed

T_amb= 40 C to +85 C

Symbol

f_scl

Parameter

Conditions

high speed; C_b< 100 pF

Min

0

Max

3.4

-

Unit

MHz

ns

clock frequency

t_SU;STA

set-up time for a (repeated) high speed; C_b< 100 pF

START condition

160

t_HD;STA

hold time (repeated) START high speed; C_b< 100 pF

condition

160

-

ns

t_LOW

low period of the SCL clock high speed; C_b< 100 pF

high period of the SCL clock high speed; C_b< 100 pF

160

60

10

0

-

ns

s

t_HIGH

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

high speed; C_b< 100 pF

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Table 60. Timing specification for I2C high speed

T_amb= 40 C to +85 C

Symbol

t_r(SDA)

t_f(SDA)

V_hys

Parameter

Conditions

Min

10

Max

80

-

Unit

ns

SDA rise time

SDA fall time

high speed; C_b< 100 pF

10

ns

hysteresis of Schmitt trigger high speed; C_b< 100 pF

inputs

0.1 

V_{PVDD_IN}

V

Table 61. Dynamic characteristics for the I²C slave interface: ATX_B used as I²C_SDA, ATX_A used as I²C_SCL

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_f

fall time

C_L= 100 pF, R_pull-up= 2 K,

standard and fast mode

30

-

250

ns

C_L= 100 pF, R_pull-up= 1 K, high

speed

10

30

10

-

80

ns

t_r

rise time

C_L= 100 pF, R_pull-up= 2 K,

standard and fast mode

250

100

C_L= 100 pF, R_pull-up= 1 K, high

speed

7

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Fig 32. SPI slave timings

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Table 62. Dynamic characteristics for SPI slave interface

Symbol

Parameter

Conditions

Min

Max

Unit

f_SCK

SCK frequency

0

7

MHz

controlled by the host

t_DS

data set-up time

data hold time

25

-

ns

t_DH

t_v(Q)

-

data output valid time

25

t_h(Q)

data output hold time

-

25

ns

Table 63. Dynamic characteristics for SPI slave interface: ATX_C as SPI_MISO

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_f

fall time

C_L= 12 pF; high speed;

V_{PVDD_IN}= 3.3 V

1

-

3.5

ns

C_L= 12 pF; slow speed;

V_{PVDD_IN}= 3.3 V

3

1

3

1

2

1

2

10

t_r

t_f

t_r

rise time

fall time

rise time

C_L= 12 pF; high speed;

V_{PVDD_IN}= 3.3 V

3.5

10

C_L= 12 pF; slow speed;

V_{PVDD_IN}= 3.3 V

C_L= 12 pF; high speed;

V_{PVDD_IN}= 1.8 V

3.5

10

C_L= 12 pF; slow speed;

V_{PVDD_IN}= 1.8 V

C_L= 12 pF; high speed;

V_{PVDD_IN}= 1.8 V

3.5

10

C_L= 12 pF; slow speed;

V_{PVDD_IN}= 1.8 V

Table 64. Dynamic characteristics for HSUART ATX_ as HSU_TX, ATX_ as HSU_RTS

Symbol

Parameter

Conditions^[1]

Min

1

Typ

Max

3.5

10

Unit

ns

t_f

fall time

high speed; V_{PVDD_IN}= 3.3 V

slow speed; V_{PVDD_IN}= 3.3 V

high speed; V_{PVDD_IN}= 3.3 V

slow speed; V_{PVDD_IN}= 3.3 V

high speed; V_{PVDD_IN}= 1.8 V

slow speed; V_{PVDD_IN}= 1.8 V

high speed; V_{PVDD_IN}= 1.8 V

slow speed; V_{PVDD_IN}= 1.8 V

-

3

t_r

t_f

t_r

rise time

fall time

rise time

1

3.5

10

3

1

3.5

10

2

1

3.5

10

2

[1] C_L=12 pF maximum.

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Table 65. Dynamic characteristics for USB interface

C_L= 50 pF; R_pu= 1.5 k on D+ to VBUS

Symbol

Parameter

rise time

fall time

Conditions

10 % to 90 %

t_r/ t_f

Min

Typ

Max

20

Unit

ns

t_r

4

-

t_f

20

ns

t_FRFM

differential rise and fall time

matching

109

%

V_CRS

output signal crossover voltage

source SE0 interval of EOP

1.3

160

2

-

2

V

t_FEOPT

t_FDEOP

T = 25 °C; see Figure 33

175

+5

ns

source jitter for differential transition T = 25 °C; see Figure 33

to SE0 transition

t_JR1

receiver jitter to next transition

receiver jitter for paired transitions

receiver SE0 interval of EOP

T = 25 °C

18.5

9

-

+18.5 ns

t_JR2

10 % to 90 %; T = 25 °C

+9

-

ns

t_FEOPR

must accept as EOP;

see Figure 33

82

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Fig 33. USB interface differential data-to-EOP transition skew and EOP width

13.2.7 Clock dynamic characteristics

Table 66. Dynamic characteristics for internal oscillators

T_amb= 40 C to +85 C

Symbol

low frequency oscillator

Parameter^[1]

Conditions

Min

300

18

Typ^[2]Max

Unit

kHz

f_osc(int)

internal oscillator frequency

V_DDP(VBUS)= 3.3 V

365

20

400

22

high frequency oscillator

f_osc(int)

internal oscillator frequency

MHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C) with nominal supply voltages.

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Table 67. Dynamic characteristics for PLL

T_amb= 40 C to +85C

Symbol

Parameter^[1]

Conditions

Min

Typ^[2]Max

Unit

f

frequency deviation

deviation added to

CLK_XTAL1 frequency on RF

frequency generated using

PLL

50

-

50

ppm

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C) with nominal supply voltages.

13.2.8 Dynamic characteristics for power supply

Table 68. Dynamic characteristics for power supply

Symbol

DC-to-DC internal oscillator

f_osc(int)internal oscillator frequency

Parameter

Conditions

Min

Typ

Max

Unit

DC-to-DC converter

-

3.39

-

MHz

13.2.9 Dynamic characteristics for boot and reset

Table 69. Dynamic characteristics for boot and reset

Symbol

t_{wL(RST_N)}RST_N Low pulse width time

t_bootboot time

Parameter

Conditions

Min

10

-

Typ

Max

-

Unit

s

-

external PVDD supply; supply

is stable at reset

320

µs

internal PVDD_LDO supply;

supply is stable at reset

-

2.2

ms

13.2.10 Dynamics characteristics for power mode

Table 70. Power modes - wake-up timings

Symbol

Parameter

Conditions

Min

Typ

Max

500

150

Unit

s

[1]

t_wake

wake-up time

standby mode

suspend mode

-

s

[1] Wake-up timings are measured from the wake-up event to the point in which the user application code reads the first instruction.

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14. Marking

Table 71. Marking codes

Type number

PN736X

Line A

Marking code

PN7362AU-00

Line B

Diffusion Batch ID, Assembly Sequence ID

Line C

Characters: Diffusion and assembly location, date code, product version

(indicated by mask version), product life cycle status. This line includes the

following elements at 8 positions:

1. Diffusion center code: Z

2. Assembly center code: S

3. RHF-2006 indicator: D “Dark Green”

4. Year code (Y) 1

5. Year code (Y) 2

6. Week code (W) 1

7. Week code (W) 2

8. HW version

Line D

Line E

Empty

14.1 Package marking drawing

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Fig 34. Marking PN736X in HVQFN64

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15. Package outline

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Fig 36. Footprint information for reflow soldering of HVQFN64

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16. Packing information

Moisture Sensitivity Level (MSL) evaluation has been performed according to JEDEC

J-STD-020C. MSL for this package is level 3 which means 260 C Pb-free convection

reflow maximum temperature peak.

Dry packing is required with following floor conditions: 168 hours out of bag floor life at

maximum ambient temperature 30 C/60 % RH.

For information on packing, refer to the PIP relating to this product at http://www.nxp.com.

17. Abbreviations

Table 72. Abbreviations

Acronym

ADC

ALM

ASK

Description

Analog to Digital Convertor

Active Load Modulation

Amplitude Shift Keying

BPSK

CLIF

CRC

DPC

EEPROM

GPIO

I²C

Binary Phase Shift Keying

Contactless Interface

Cyclic Redundancy Check

Dynamic Power Control

Electrically Erasable Programmable Read-Only Memory

General-Purpose Input Output

Inter-Interchanged Circuit

Integrated Circuit

IC

IAP

In-Application Programming

In-System Programming

Low DropOut

ISP

LDO

LPCD

NFC

NRZ

NVIC

P2P

Low-Power Card Detection

Near Field Communication

Non-Return to Zero

Nested Vectored Interrupt Controller

Peer-to-Peer

PLL

Phase-Locked Loop

PLM

SPI

Passive Load Modulation

Serial Peripheral Interface

Serial Wire Debug

SWD

UART

USB

Universal Asynchronous Receiver Transmitter

Universal Serial Bus

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18. Revision history

Table 73. Revision history

Document ID

PN736X v. 3.2

Modifications:

Release date

20161213

Data sheet status

Change notice

Supersedes

Product data sheet

-

PN746X_736X v.3.1

• Product name title and Descriptive title updated

• Editorial changes

PN746X_736X v.3.1

Modifications:

20160405

Product data sheet

-

PN746X_736X v.3.0

• Descriptive title updated

• Section 1 “General description”: updated

PN746X_736X v.3.0

20160330

Product data sheet

-

PN736X

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

19.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

19.4 Licenses

Purchase of NXP ICs with NFC technology

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Purchase of an NXP Semiconductors IC that complies with one of the Near

Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481

does not convey an implied license under any patent right infringed by

implementation of any of those standards. Purchase of NXP

Semiconductors IC does not include a license to any NXP patent (or other

IP right) covering combinations of those products with other products,

whether hardware or software.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

Purchase of NXP ICs with ISO/IEC 14443 type B functionality

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

This NXP Semiconductors IC is ISO/IEC 14443 Type B

software enabled and is licensed under Innovatron’s

Contactless Card patents license for ISO/IEC 14443 B.

The license includes the right to use the IC in systems

and/or end-user equipment.

RATP/Innovatron

Technology

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

19.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

MIFARE — is a trademark of NXP B.V.

ICODE and I-CODE — are trademarks of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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21. Contents

1

2

3

4

5

6

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.10.1.2 ISO/IEC14443 B functionality . . . . . . . . . . . . 21

8.10.1.3 FeliCa functionality. . . . . . . . . . . . . . . . . . . . . 22

8.10.1.4 ISO/IEC 15693 functionality. . . . . . . . . . . . . . 23

8.10.1.5 ISO/IEC18000-3 mode 3 functionality . . . . . . 24

8.10.1.6 NFCIP-1 modes . . . . . . . . . . . . . . . . . . . . . . . 24

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Quick reference data . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

8.10.2

Contactless interface . . . . . . . . . . . . . . . . . . . 27

8.10.2.1 Transmitter (TX). . . . . . . . . . . . . . . . . . . . . . . 27

8.10.2.2 Receiver (RX) . . . . . . . . . . . . . . . . . . . . . . . . 27

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

8.10.3

8.10.4

8.10.5

Low-Power Card Detection (LPCD). . . . . . . . 29

Active Load Modulation (ALM). . . . . . . . . . . . 29

Dynamic Power Control (DPC) . . . . . . . . . . . 30

8

8.1

8.2

Functional description . . . . . . . . . . . . . . . . . . . 8

ARM Cortex-M0 microcontroller . . . . . . . . . . . . 8

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

On-chip flash programming memory . . . . . . . . 8

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . 8

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Memory mapping . . . . . . . . . . . . . . . . . . . . . . 10

ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 10

Nested Vectored Interrupt Controller (NVIC) . 12

NVIC features. . . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12

GPIOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

GPIO features. . . . . . . . . . . . . . . . . . . . . . . . . 14

GPIO configuration. . . . . . . . . . . . . . . . . . . . . 14

GPIO interrupts. . . . . . . . . . . . . . . . . . . . . . . . 14

CRC engine 16/32 bits . . . . . . . . . . . . . . . . . . 14

Random Number Generator (RNG) . . . . . . . . 15

Master interfaces . . . . . . . . . . . . . . . . . . . . . . 15

I²C master interface . . . . . . . . . . . . . . . . . . . . 15

I²C features. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 15

SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Host interfaces . . . . . . . . . . . . . . . . . . . . . . . . 16

High-speed UART. . . . . . . . . . . . . . . . . . . . . . 16

I²C host interface controller . . . . . . . . . . . . . . 17

I²C host interface features . . . . . . . . . . . . . . . 17

SPI host/Slave interface . . . . . . . . . . . . . . . . . 18

SPI host interface features . . . . . . . . . . . . . . . 18

USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 18

Full speed USB device controller . . . . . . . . . . 18

I/O auxiliary - ISO/IEC 7816 UART - connecting

an external TDA . . . . . . . . . . . . . . . . . . . . . . . 19

Contactless interface - 13.56 MHz . . . . . . . . . 19

RF functionality. . . . . . . . . . . . . . . . . . . . . . . . 20

8.10.5.1 RF output control . . . . . . . . . . . . . . . . . . . . . . 30

8.10.5.2 Adaptive Waveform Control (AWC) . . . . . . . . 30

8.11

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Features of timer 0 and timer 1 . . . . . . . . . . . 30

Features of timer 2 and timer 3 . . . . . . . . . . . 31

System tick timer . . . . . . . . . . . . . . . . . . . . . . 31

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 31

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Quartz oscillator (27.12 MHz) . . . . . . . . . . . . 32

USB PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

High Frequency Oscillator (HFO). . . . . . . . . . 33

Low Frequency Oscillator (LFO) . . . . . . . . . . 33

Clock configuration and clock gating . . . . . . . 33

Power management. . . . . . . . . . . . . . . . . . . . 34

Power supply sources . . . . . . . . . . . . . . . . . . 34

PN736X Power Management Unit (PMU) . . . 34

8.2.1

8.2.1.1

8.2.2

8.2.2.1

8.2.3

8.2.3.1

8.2.4

8.2.5

8.3

8.3.1

8.3.2

8.4

8.4.1

8.4.2

8.4.3

8.5

8.11.1

8.11.2

8.12

8.13

8.14

8.14.1

8.14.2

8.14.3

8.14.4

8.14.5

8.15

8.15.1

8.15.2

8.15.2.1 Main LDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.15.2.2 PVDD_LDO . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.15.2.3 TXLDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.6

8.7

8.15.3

Power modes. . . . . . . . . . . . . . . . . . . . . . . . . 36

8.15.3.1 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.15.3.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 37

8.15.3.3 Suspend mode. . . . . . . . . . . . . . . . . . . . . . . . 37

8.15.3.4 Wake-up from standby mode and suspend

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.7.1

8.7.1.1

8.7.2

8.7.2.1

8.8

8.8.1

8.8.2

8.8.2.1

8.8.3

8.8.3.1

8.8.4

8.8.4.1

8.9

8.15.3.5 Hard Power-Down (HPD) mode. . . . . . . . . . . 38

8.15.4

Voltage monitoring . . . . . . . . . . . . . . . . . . . . . 38

8.15.4.1 VBUS monitor . . . . . . . . . . . . . . . . . . . . . . . . 39

8.15.4.2 VBUSP monitor . . . . . . . . . . . . . . . . . . . . . . . 39

8.15.4.3 PVDD LDO supply monitor . . . . . . . . . . . . . . 39

8.15.5

8.16

Temperature sensor. . . . . . . . . . . . . . . . . . . . 39

System control . . . . . . . . . . . . . . . . . . . . . . . . 39

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Brown-Out Detection (BOD) . . . . . . . . . . . . . 40

APB interface and AHB-Lite. . . . . . . . . . . . . . 40

External interrupts . . . . . . . . . . . . . . . . . . . . . 40

SWD debug interface. . . . . . . . . . . . . . . . . . . 40

8.16.1

8.16.2

8.16.3

8.16.4

8.17

8.10

8.10.1

8.10.1.1 ISO/IEC14443 A/MIFARE functionality. . . . . . 20

continued >>

PN736X

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 3.2 — 13 December 2016

71 of 72

PN736X

NXP Semiconductors

NFC Cortex-M0 microcontroller

8.17.1

SWD interface features . . . . . . . . . . . . . . . . . 40

9

Application design-in information . . . . . . . . . 41

Power supply connection . . . . . . . . . . . . . . . . 41

Powering up the microcontroller. . . . . . . . . . . 42

Powering up the contactless interface . . . . . . 42

Connecting the USB interface . . . . . . . . . . . . 44

Connecting the RF interface. . . . . . . . . . . . . . 44

Unconnected I/Os. . . . . . . . . . . . . . . . . . . . . . 45

9.1

9.1.1

9.1.2

9.2

9.3

9.4

10

11

12

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 45

Recommended operating conditions. . . . . . . 47

Thermal characteristics . . . . . . . . . . . . . . . . . 47

13

13.1

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 48

Static characteristics. . . . . . . . . . . . . . . . . . . . 48

GPIO static characteristics . . . . . . . . . . . . . . . 48

Static characteristics for I²C master . . . . . . . . 49

Static characteristics for SPI master. . . . . . . . 50

Static characteristics for host interface . . . . . . 50

Clock static characteristics . . . . . . . . . . . . . . . 52

Static characteristics - power supply. . . . . . . . 53

Static characteristics for power modes . . . . . . 54

Static characteristics RF interface . . . . . . . . . 55

Dynamic characteristics . . . . . . . . . . . . . . . . . 55

Flash memory dynamic characteristics. . . . . . 56

EEPROM dynamic characteristics . . . . . . . . . 56

GPIO dynamic characteristics . . . . . . . . . . . . 56

Dynamic characteristics for I²C master . . . . . 57

Dynamic characteristics for SPI . . . . . . . . . . . 58

Dynamic characteristics of host interface. . . . 59

Clock dynamic characteristics . . . . . . . . . . . . 62

Dynamic characteristics for power supply . . . 63

Dynamic characteristics for boot and reset. . . 63

13.1.1

13.1.2

13.1.3

13.1.4

13.1.5

13.1.6

13.1.7

13.1.8

13.2

13.2.1

13.2.2

13.2.3

13.2.4

13.2.5

13.2.6

13.2.7

13.2.8

13.2.9

13.2.10 Dynamics characteristics for power mode . . . 63

14

14.1

15

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Package marking drawing . . . . . . . . . . . . . . . 64

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 65

Packing information . . . . . . . . . . . . . . . . . . . . 67

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 67

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 68

16

17

18

19

Legal information. . . . . . . . . . . . . . . . . . . . . . . 69

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 69

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 70

19.1

19.2

19.3

19.4

19.5

20

21

Contact information. . . . . . . . . . . . . . . . . . . . . 70

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 December 2016

406332


型号：	PN7362AUHN
厂家：	NXP
描述：	RISC MICROCONTROLLER
文件：	总72页 (文件大小：577K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PN7362AUHN [NXP]

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