PNX8526EH/M0_技术文档

PNX8526

Programmable source decoder with integrated peripherials

Rev. 02 — 11 July 2005

Product data sheet

1. General description

The PNX8526 is a highly integrated media processor for use in Advanced Set Top Boxes

(ASTB) and Digital Television (DTV) systems. The PNX8526 is targeted at the mid to

high-end ASTB/DTV systems, decoding ‘all format’ HD and SD MPEG-2 source material

with Standard Deﬁnition (SD), or double line-rate SD display capabilities. Although the

PNX8526 can process high level input formats, its display capabilities are primarily

targeted at NTSC, PAL and SECAM televisions. It is also intended for lower cost DTVs,

those not considered high deﬁnition. Progressive output is also available for double

line-rate television displays, or for high resolution graphic content to be displayed on a

computer monitor. The PNX8526 is designed in a high performance 0.12 micron process.

The PNX8526 performs source decode functions, including conditional access, MPEG-2

transport stream demultiplexing, MPEG-2 video decode, audio decode and processing,

graphics generation, video processing, and image composition and display. A 32-bit,

200 MHz VLIW processor, referred to as the TriMedia 3200 CPU core (TM32 CPU),

carries out the majority of media processing operations performed by the PNX8526. Fixed

function hardware will perform some operations that are not handled by the TM32 CPU.

Additionally, the PNX8526 supports a number of peripheral interfaces such as I²C-bus,

USB, IDE and UART. Other interfaces such as IEEE-1284 and Ethernet may be supported

via SuperI/O devices that reside on a PCI expansion bus. The expansion bus also

provides for glueless interface to 8-bit wide slave devices, such as ﬂash/ROM, DOCSIS

modem, UARTs, etc.

An embedded MIPS processor (PR3940) running at 150 MHz is intended to run the OS.

(There is no direct support for an external processor; however, a CPU of any type may be

connected to the PNX8526 via the PCI interface.) This implies a complete CPU

subsystem consisting of the CPU itself, local memory, and an interface to PCI. The MIPS

processor is primarily responsible for control functions and graphics-intensive operating

systems, while the TM32 CPU is responsible for running all real-time media processing

functions. All resources supported within the PNX8526 are accessible by both the MIPS

processor and the TM32 CPU. The software documentation of the PNX8526 provides

more details on the interaction between the MIPS and the TM32 CPU.

The PNX8526 is intended to be used with a small companion IC, the PNX8510. This

analog companion chip provides the majority of analog video and audio support for the

output of the PNX8526. The PNX8510 companion is capable of simultaneously driving

two video channels (six DACs) and two stereo audio channels (four DACs).

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

2. Features

■ 200 MHz, 5-instruction/clock cycle, 32-bit VLIW processing core (TM32 CPU)

■ 150 MHz, MIPS PR3940 processing core

■ External CPU support via PCI

■ Support for multiple digital video (D1) input streams

■ Support for multiple MPEG-2 or DIRECTV transport streams (parallel format)

■ On-chip conditional access for DVB, DES, MULTI2, CAM and DIRECTV

■ On-chip copy protection support for OpenCable and ATSC (NRSS-B)

■ Simultaneous decode of two SD streams (MPEG-2) or one HD MPEG stream

(AFD style HD-SD decode)

■ Simultaneous decode of two AC-3 or equivalent audio streams

■ High performance 2D rendering and DMA capability

■ Dual image composition/screen refresh engines: four layer primary output, two layer

secondary output

■ Multiple channel output to support watch/record and multi-room modes

■ Embedded 1394 link layer with 5C copy protection

■ Soft modem support via SSI interface

■ 16 MB, 32 MB and 64 MB uniﬁed memory architecture implemented with high-speed

SDRAM (166 MHz)

■ System expansion capability via industry standard PCI bus

■ Core peripherals (I²C-bus, UART, USB, etc.) on the chip, other peripherals supported

via third-party ‘SuperI/O’ chip.

3. Applications

■ Advanced Set Top Box (ASTB)

■ Digital Television (DTV)

4. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

PNX8526EH/M0

HBGA456

plastic thermal enhanced ball grid array package; SOT610-1

456 balls; body 35 × 35 × 1.8 mm; heatsink

PNX8526EH/M0/G HBGA456^[1]plastic thermal enhanced ball grid array package; SOT610-1

456 balls; body 35 × 35 × 1.8 mm; heatsink

[1] Lead-free (Pb-free) package.

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

2 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

5. Block diagram

166 MHz, 64-bit wide SDRAM

IEEE1394

PHY

1394

PNX8526

MMI

(1)

TS_OUT

656

DV_OUT1

656/HD/VGA

(1)

DV1 656

VIP1

VIP2

AICP1

AICP2

OUTPUT

MODE

656

TS

TS and 656

ROUTER

DV_OUT2

656

DV2 656/TS

DV3 656/TS

2

(1)

(2)

I S-bus audio

MSP1-2

MSP3

AO1-3

TS

SPDIF audio

SPDO

2

(1)

(2)

I S-bus audio

AI1-3

TSDMA

MBS

SPDIF audio

SPDI

(1)

UART1 and 2

(1)

UART3/sync serial i/f

VMPG

12

general purpose I/O

USB host i/f (2 port)

smart card1 and 2

OTHER

I/O

DE (2D)

2

I S-bus (2x)

27 MHz

crystal

BOOT, RESET, CLOCK

TM-DBG

DMA

JTAG

TM32 MEDIA PROCESSOR

5 issue, 200 MHz

PR3940 MIPS CPU

150 MHz

16 kB I-cache

8 kB D-cache

R4K series MMU

EJTAG

debug

32 kB I-cache

16 kB 2-port D-cache

128 32-bit registers

PCI

33 MHz, 32-bit PCI 2.2

(includes NAND/nor flash, IDE drive and 68 kB peripheral capability)

mce540

(1) I/O can also function as general purpose a serial input/output.

(2) Due to pin sharing, either AI1-3 or AO1-3 can be active, not both (audio input/output data bits S_IO_SD[3:0]).

Fig 1. Block diagram

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

3 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

6. Pinning information

6.1 Pinning

ball A1

index area

2

4 6 8 10 12 14 16 18 20 22 24 26

1

3

5

7

9

11 13 15 17 19 21 23 25

A

B

C

D

E

F

G

H

PNX8526EH

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

001aac986

Transparent top view

Fig 2. Pin conﬁguration

6.2 Pin description

All pad inputs and input/output have built-in pull-up resistors (approximately 80 kΩ) and

Schmitt trigger input thresholds. (See Table 18 for maximum ratings).

The following pins do not have pull-ups resistors:

XTALI, PCIx, analog pins, I²C-bus, main memory interface, USB_DPx and USB_DMx.

The following pins do not have Schmitt trigger inputs:

XTALI, analog pins, USB_DPx and USB_DMx.

Table 2:

Peripheral Controller Interface (PCI)

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

PCI_AD[31]

PCI_AD[30]

PCI_AD[29]

PCI_AD[28]

PCI_AD[27]

PCI_AD[26]

PCI_AD[25]

PCI_AD[24]

PCI_AD[23]

PCI_AD[22]

AB1

AB2

AB3

AB4

I/O

multiplexed address or data bit 31

multiplexed address or data bit 30

multiplexed address or data bit 29

multiplexed address or data bit 28

multiplexed address or data bit 27

multiplexed address or data bit 26

multiplexed address or data bit 25

multiplexed address or data bit 24

multiplexed address or data bit 23

multiplexed address or data bit 22

AC1 I/O

AC2 I/O

AC3 I/O

AD2 I/O

AE3

AF4

I/O

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

4 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 2:

Peripheral Controller Interface (PCI) …continued

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

PCI_AD[21]

PCI_AD[20]

PCI_AD[19]

PCI_AD[18]

PCI_AD[17]

PCI_AD[16]

PCI_AD[15]

PCI_AD[14]

PCI_AD[13]

PCI_AD[12]

PCI_AD[11]

PCI_AD[10]

PCI_AD[9]

PCI_AD[8]

PCI_AD[7]

PCI_AD[6]

PCI_AD[5]

PCI_AD[4]

PCI_AD[3]

PCI_AD[2]

PCI_AD[1]

PCI_AD[0]

PCI_CBE[3]

PCI_CBE[2]

PCI_CBE[1]

PCI_CBE[0]

CLK

AE4

I/O

multiplexed address or data bit 21

multiplexed address or data bit 20

multiplexed address or data bit 19

multiplexed address or data bit 18

multiplexed address or data bit 17

multiplexed address or data bit 16

multiplexed address or data bit 15

multiplexed address or data bit 14

multiplexed address or data bit 13

multiplexed address or data bit 12

multiplexed address or data bit 11

multiplexed address or data bit 10

multiplexed address or data bit 9

multiplexed address or data bit 8

multiplexed address or data bit 7

multiplexed address or data bit 6

multiplexed address or data bit 5

multiplexed address or data bit 4

multiplexed address or data bit 3

multiplexed address or data bit 2

multiplexed address or data bit 1

multiplexed address or data bit 0

multiplexed command or byte enable 3

multiplexed command or byte enable 2

multiplexed command or byte enable 1

multiplexed command or byte enable 0

PCI bus clock

AD4 I/O

AE5 I/O

AD5 I/O

AC5 I/O

AC6 I/O

AD8 I/O

AC8 I/O

AF9

AE9

I/O

AD9 I/O

AC9 I/O

AF10 I/O

AE10 I/O

AC10 I/O

AF11 I/O

AE11 I/O

AD11 I/O

AC11 I/O

AE12 I/O

AD12 I/O

AC12 I/O

AD1 I/O

AF5

AE8

I/O

AD10 I/O

AA1

AF7

I

PCI_DEVSEL

I/O

device select is asserted when a target address is

decoded and remains asserted to indicate that a

target device is selected

PCI_FRAME

PCI_GNT

AF6

Y3

I/O

frame is asserted to indicate start of bus

transaction and remains asserted until ﬁnal data

phase begins

arbitration grant is asserted to indicate access to

the bus has been granted; this pin is an input

when an external arbiter is used and an output

when using the internal arbiter

PCI_GNT_A

Y4

I/O

auxiliary arbitration PCI_GNT_A is asserted to

indicate bus access has been granted to an

external PCI master; used where internal arbiter is

conﬁgured

#

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

5 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 2:

Peripheral Controller Interface (PCI) …continued

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

PCI_GNT_B

AA4

I/O

auxiliary arbitration grant PCI_GNT_B is asserted

to indicate bus access has been granted to an

external PCI master; used where internal arbiter is

conﬁgured

#

IDSEL

AF3

V4

I/O

initialization device select provides chip select

during conﬁguration read and write transactions

PCI_INTA

interrupt a is asserted to request an interrupt; this

pin may be conﬁgured as an input if the internal

pic is used, or as an output if the external interrupt

controller is used; polarity in active low

PCI_IRDY

PCI_PAR

AE6

AF8

I/O

initiator ready is asserted during writes to indicate

valid data on AD[31:0]. also asserted during reads

to indicate the target is prepared to accept data.

wait states are inserted until PCI_IRDY and

PCI_TRDY are both asserted

parity supports even parity across the PCI

address/data bus PCI_AD[31:0]) and command/

byte enable bus (PCI_CBE[3:0]); the bus master

drives PCI_PAR for address and write data

phases. the target drives PCI_PAR for the read

data phases

PCI_PERR

PCI_REQ

AD7 I/O

parity error indicates data parity errors during all

PCI transactions except special cycle

Y2

I/O

arbitration request on PCI bus; request is an

output when using an external arbiter and an input

when using an internal arbiter

PCI_REQ_A

PCI_REQ_B

AA2

AA3

W3

I/O

I

auxiliary arbitration PCI_REQ_A on PCI bus; used

in modes where internal arbiter is conﬁgured

#

auxiliary arbitration PCI_REQ_B on PCI bus; used

in modes where internal arbiter is conﬁgured

RESET_IN

PCI_SERR

PCI_STOP

PCI bus global reset

system error

AC7 I/O

AE7 I/O

stop is asserted to indicate a request from the

target for the master to stop the current

transmission

PCI_TRDY

AD6 I/O

target ready is asserted during reads to indicate

valid data on AD[31:0]; it is asserted during writes

to indicate the target is prepared to accept data;

wait states are inserted until PCI_IRDY and

PCI_TRDY are both asserted

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

6 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 3:

Miscellaneous system interface (MISC)

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

XIO_A25

AE13

AF13

AF12

AC13

AD13

Y1

I/O

O

XIO address bit 25

#

XIO_ACK

XIO Acknowledge (EEPROM)

external input/output select2

external input/output select1

external input/output select0

system reset output

XIO_SEL[2]

XIO_SEL[1]

XIO_SEL[0]

SYS_RSTN_OUT

Table 4:

Main Memory Interface (MMI)

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

MA[11]

MA[10]

MA[9]

C22

B21

A21

C21

A20

C20

D18

D19

C19

D20

B20

D21

M25

M24

M23

L26

L25

L24

L23

K26

K24

K23

J26

O

memory address bit 11

memory address bit 10

memory address bit 9

memory address bit 8

memory address bit 7

memory address bit 6

memory address bit 5

memory address bit 4

memory address bit 3

memory address bit 2

memory address bit 1

memory address bit 0

memory data bit 63

memory data bit 62

memory data bit 61

memory data bit 60

memory data bit 59

memory data bit 58

memory data bit 57

memory data bit 56

memory data bit 55

memory data bit 54

memory data bit 53

memory data bit 52

memory data bit 51

memory data bit 50

memory data bit 49

memory data bit 48

memory data bit 47

O

MA[8]

O

MA[7]

O

MA[6]

O

MA[5]

O

MA[4]

O

MA[3]

O

MA[2]

O

MA[1]

O

MA[0]

O

MD[63]

MD[62]

MD[61]

MD[60]

MD[59]

MD[58]

MD[57]

MD[56]

MD[55]

MD[54]

MD[53]

MD[52]

MD[51]

MD[50]

MD[49]

MD[48]

MD[47]

I/O

J25

J24

J23

H26

H25

H23

9397 750 15101

Product data sheet

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7 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 4:

Main Memory Interface (MMI) …continued

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

MD[46]

MD[45]

MD[44]

MD[43]

MD[42]

MD[41]

MD[40]

MD[39]

MD[38]

MD[37]

MD[36]

MD[35]

MD[34]

MD[33]

MD[32]

MD[31]

MD[30]

MD[29]

MD[28]

MD[27]

MD[26]

MD[25]

MD[24]

MD[23]

MD[22]

MD[21]

MD[20]

MD[19]

MD[18]

MD[17]

MD[16]

MD[15]

MD[14]

MD[13]

MD[12]

MD[11]

MD[10]

MD[9]

G26

G25

G24

G23

F26

F25

F24

F23

E25

E24

D25

D26

E23

D24

C25

A18

B18

C18

A19

B17

C17

D17

A16

B16

C16

D16

A15

B15

C15

D15

C14

A14

D14

A13

B13

C13

D13

A12

B12

I/O

memory data bit 46

memory data bit 45

memory data bit 44

memory data bit 43

memory data bit 42

memory data bit 41

memory data bit 40

memory data bit 39

memory data bit 38

memory data bit 37

memory data bit 36

memory data bit 35

memory data bit 34

memory data bit 33

memory data bit 32

memory data bit 31

memory data bit 30

memory data bit 29

memory data bit 28

memory data bit 27

memory data bit 26

memory data bit 25

memory data bit 24

memory data bit 23

memory data bit 22

memory data bit 21

memory data bit 20

memory data bit 19

memory data bit 18

memory data bit 17

memory data bit 16

memory data bit 15

memory data bit 14

memory data bit 13

memory data bit 12

memory data bit 11

memory data bit 10

memory data bit 9

memory data bit 8

MD[8]

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 4:

Main Memory Interface (MMI) …continued

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

MD[7]

C12

A11

B11

D11

A10

C11

B10

C10

K25

H24

E26

A24

A17

B14

D12

A9

I/O

O

memory data bit 7

MD[6]

memory data bit 6

MD[5]

memory data bit 5

MD[4]

memory data bit 4

MD[3]

memory data bit 3

MD[2]

memory data bit 2

MD[1]

memory data bit 1

MD[0]

memory data bit 0

MDQM[7]

MDQM[6]

MDQM[5]

MDQM[4]

MDQM[3]

MDQM[2]

MDQM[1]

MDQM[0]

MBA[1]

MBA[0]

MCKE

SDRAM control bit 7

SDRAM control bit 6

SDRAM control bit 5

SDRAM control bit 4

SDRAM control bit 3

SDRAM control bit 2

SDRAM control bit 1

SDRAM control bit 0

SDRAM bank select

memory clock enable

memory clock bit 1

memory clock bit 0

memory chip select

EDODRAM row address strobe

memory column address select

memory write enable

O

D22

B22

C23

C26

B19

A22

B23

A23

B24

O

MCLK[1]

MCLK[0]

MCS

O

MRAS

O

MCAS

O

MWE

O

Table 5:

General Purpose Input/Output (GPIO)

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

GPIO[11]

GPIO[10]

GPIO[9]

GPIO[8]

GPIO[7]

GPIO[6]

GPIO[5]

GPIO[4]

GPIO[3]

N26

I/O

general purpose input/output bit 11

general purpose input/output bit 10

general purpose input/output bit 9

general purpose input/output bit 8

general purpose input/output bit 7

general purpose input/output bit 6

general purpose input/output bit 5

general purpose input/output bit 4

general purpose input/output bit 3

#

N24

N23

M26

AE14

AF14

AD14

AC14

C5

9397 750 15101

Product data sheet

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 5:

General Purpose Input/Output (GPIO) …continued

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

GPIO[2]

GPIO[1]

GPIO[0]

B4

D5

C4

I/O

general purpose input/output bit 2

general purpose input/output bit 1

general purpose input/output bit 0

#

Table 6:

Serial communication (COM)

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

UA1_TX

U24

U25

T23

U26

T24

T25

T26

R23

R24

R25

R26

P23

P24

P26

P25

N25

I/O

O

UART1 transmit

#

UA1_RX

UART1 receive

UA2_TX

UART2 transmit

UA2_RX

UART2 receive

UA2_RTSN

UA2_CTSN

SC1_DA

UART2 request to send

UART2 clear to send

smart card1 data

SC1_CMD

SC1_RST

SC1_OFFN

SC1_SCCK

SC2_DA

smart card1 command

smart card1 reset

O

I

smart card1 off

O

smart card1 bit clock

smart card2 data

I/O

O

SC2_CMD

SC2_RST

SC2_OFFN

SC2_SCCK

smart card2 command

smart card2 reset

O

I

smart card2 off

O

smart card2 bit clock

synchronous serial interface clock input

synchronous serial interface frame sync

synchronous serial interface receive

synchronous serial interface transmit

SSI_SCLK_CTSN V1

I/O

#

SSI_FS_RTSN

SSI_RXD

V2

U4

V3

SSI_TXD

Table 7:

Universal Serial Bus (USB)

Symbol

A5

B6

C6

D7

W1

Type

I/O

O

Description

USB_DP[1]

USB_DP[0]

USB_DM[0]

USB_DM[1]

USB_PWR

data plus bit 1

data plus bit 0

data minus bit 0

data minus bit 1

USB port power on/off

0 = power on

1 = power off

9397 750 15101

Product data sheet

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10 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 7:

Symbol

Universal Serial Bus (USB) …continued

Type

Description

USB_OVRCUR W2

I

indicates over current being drawn by a USB device

0 = over current detected

1 = no over current

Table 8:

IEEE 1394 port

Symbol

B9

Type

Description

PHY_D[7]

PHY_D[6]

PHY_D[5]

PHY_D[4]

PHY_D[3]

PHY_D[2]

PHY_D[1]

PHY_D[0]

I/O

O

PHY data bit 7; data is expected on ports 7:0 for 400 MB packets

PHY data bit 6; data is expected on ports 7:0 for 400 MB packets

PHY data bit 5; data is expected on ports 7:0 for 400 MB packets

PHY data bit 4; data is expected on ports 7:0 for 400 MB packets

PHY data bit 3; data is expected on ports 3:0 for 200 MB packets

PHY data bit 2; data is expected on ports 3:0 for 200 MB packets

PHY data bit 1; data is expected on ports 1:0 for 100 MB packets

PHY data bit 0; data is expected on ports 1:0 for 100 MB packets

PHY control bit 1; indicates the mode for data on the Din port

PHY control bit 0; indicates the mode for data on the Din port

D10

C9

A8

B8

D9

C8

A7

PHY_CTL[1] B7

PHY_CTL[0] C7

PHY_LREQ B5

used by the link to make bus requests and to access PHY

registers; this is a serial bus; a train of pulses is sent on this

signal

PHY_ISO_N A6

I

signals which type of isolation mode is used at the PHY-Link

interface

0 = this is 1394-1995 annex J type isolation; enables

differentiator circuitry

1 = direct connection or single capacitor isolation mode; this

will disable the differentiator circuitry

CLK_L1394 D8

I

system clock. 49.152 MHz input

Table 9:

Serial communication port (I²C-bus)

Pin Type Description

Symbol

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

D6

A4

H1

K4

I/O

serial communications port (I²C-bus) clock

serial communications port (I²C-bus) data

serial communications port (I²C-bus) clock

serial communications port (I²C-bus) data

Table 10: Audio and video interface

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

M2

M1

N4

Type Description

Alternate

function

DV_OUT1[9]

DV_OUT1[8]

DV_OUT1[7]

O

digital video output1; bit 9 for primary display

channel from AICP

digital video output1; bit 8 for primary display

channel from AICP

digital video output1; bit 7 for primary display

channel from AICP

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

11 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 10: Audio and video interface …continued

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

N3

N1

N2

P2

P1

P4

P3

R2

R4

R3

T1

T2

T3

U1

T4

U2

U3

M3

R1

Type Description

Alternate

function

DV_OUT1[6]

DV_OUT1[5]

DV_OUT1[4]

DV_OUT1[3]

DV_OUT1[2]

DV_OUT1[1]

DV_OUT1[0]

DV_OUT2[9]

DV_OUT2[8]

DV_OUT2[7]

DV_OUT2[6]

DV_OUT2[5]

DV_OUT2[4]

DV_OUT2[3]

DV_OUT2[2]

DV_OUT2[1]

DV_OUT2[0]

DV_CLK1

O

digital video output1; bit 6 for primary display

channel from AICP

digital video output1; bit 5 for primary display

channel from AICP

digital video output1; bit 4 for primary display

channel from AICP

digital video output1; bit 3 for primary display

channel from AICP

digital video output1; bit 2 for primary display

channel from AICP

digital video output1; bit 1 for primary display

channel from AICP

digital video output1; bit 0 for primary display

channel from AICP

digital video output2; bit 9 for secondary display

channel from AICP

digital video output2; bit 8 for secondary display

channel from AICP

digital video output2; bit 7 for secondary display

channel from AICP

digital video output2; bit 6 for secondary display

channel from AICP

digital video output2; bit 5 for secondary display

channel from AICP

digital video output2; bit 4 for secondary display

channel from AICP

digital video output2; bit 3 for secondary display

channel from AICP

digital video output2; bit 2 for secondary display

channel from AICP

digital video output2; bit 1 for secondary display

channel from AICP

digital video output2; bit 0 for secondary display

channel from AICP

digital video clock1 for primary display channel

from AICP

DV_CLK2

digital video clock2 for secondary display

channel from AICP

HSYNC

L1

L2

M4

O

horizontal sync for primary display

vertical sync for primary display

blanking for primary display

audio IN1oversample clock

audio IN1 serial clock

VSYNC

I/O

O

BLANK

I2S_IN1_OSCLK

I2S_IN1_SCK

I2S_IN1_WS

AD20 O

AC19 I/O

AF21 I/O

audio IN1 word select

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

12 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 10: Audio and video interface …continued

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type Description

Alternate

function

I2S_IN1_SD

AE21

I

audio IN1 data

I2S_IN2_OSCLK

I2S_IN2_SCK

I2S_IN2_WS

I2S_IN2_SD

AD21 O

AC20 I/O

AF22 I/O

audio IN2 oversample clock

audio IN2 serial clock

audio IN2 word select

AE22

I

audio IN2 data

I2S_IO_OSCLK

I2S_IO_SCK

I2S_IO_WS

AF15 I/O

AE15 I/O

AC15 I/O

AD15 I/O

AF16 I/O

AE16 I/O

AD16 I/O

audio input/output oversample clock

audio input/output serial clock

audio input/output word select

audio input/output data bit 3

audio input/output data bit 2

audio input/output data bit 1

audio input/output data bit 0

audio out1 oversample clock

audio out1 serial clock

audio out1 word select

audio out1 data

#

I2S_IO_SD[3]

I2S_IO_SD[2]

I2S_IO_SD[1]

I2S_IO_SD[0[

I2S_OUT1_OSCLK K3

O

I2S_OUT1_SCK

I2S_OUT1_WS

I2S_OUT1_SD

J1

J3

J2

I/O

O

I2S_OUT2_OSCLK K2

O

audio out2 oversample clock

audio out2 serial clock

audio out2 word select

audio out2 data

#

I2S_OUT2_SCK

I2S_OUT2_WS

I2S_OUT2_SD

SPDIF_IN

L3

I/O

O

K1

L4

AF17

I

multi-channel/SPDIF input

multi-channel/SPDIF output

SPDIF_OUT

AC16 O

Table 11: Digital video bus

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

DV1_DATA[9]

DV1_DATA[8]

DV1_DATA[7]

DV1_DATA[6]

DV1_DATA[5]

DV1_DATA[4]

DV1_DATA[3]

DV1_DATA[2]

DV1_DATA[1]

DV1_DATA[0]

DV1_VALID

DV1_CLK

AE17

AD17

AF18

AC17

AE18

AD18

AF19

AE19

AC18

AD19

AF20

AE20

AF23

I/O

I

ITU-656 VIP data bit 9 (most signiﬁcant bit)

ITU-656 VIP data bit 8

#

ITU-656 VIP data bit 7

ITU-656 VIP data bit 6

ITU-656 VIP data bit 5

ITU-656 VIP data bit 4

ITU-656 VIP data bit 3

ITU-656 VIP data bit 2

ITU-656 VIP data bit 1

ITU-656 VIP data bit 0 (least signiﬁcant bit)

ITU-656 VIP data valid

ITU-656 VIP data clock

DV2_DATA[7]

digital video transport stream2 data bit 7

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

13 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 11: Digital video bus …continued

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Type

Description

Alternate

function

DV2_DATA[6]

DV2_DATA[5]

DV2_DATA[4]

DV2_DATA[3]

DV2_DATA[2]

DV2_DATA[1]

DV2_DATA[0]

DV2_SOP

AC21

AD22

AE23

AC22

AD23

AE24

AF24

AD24

AD26

AD25

AC24

W23

Y24

I

digital video transport stream2 data bit 6

digital video transport stream2 data bit 5

digital video transport stream2 data bit 4

digital video transport stream2 data bit 3

digital video transport stream2 data bit 2

digital video transport stream2 data bit 1

digital video transport stream2 data bit 0

digital video transport stream2 start of packet

digital video transport stream2 error

digital video transport stream2 data valid

digital video transport stream2 clock

digital video transport stream3 data bit 7

digital video transport stream3 data bit 6

digital video transport stream3 data bit 5

digital video transport stream3 data bit 4

digital video transport stream3 data bit 3

digital video transport stream3 data bit 2

digital video transport stream3 data bit 1

digital video transport stream3 data bit 0

digital video transport stream3 start of packet

digital video transport stream3 error

digital video transport stream3 data valid

digital video transport stream3 clock

transport stream data bit 7

#

I

DV2_ERR

I

DV2_VALID

DV2_CLK

I

DV3_DATA[7]

DV3_DATA[6]

DV3_DATA[5]

DV3_DATA[4]

DV3_DATA[3]

DV3_DATA[2]

DV3_DATA[1]

DV3_DATA[0]

DV3_SOP

I

Y25

I

Y26

I

W24

V23

I

W25

W26

V24

I

DV3_ERR

U23

I

DV3_VALID

DV3_CLK

V25

I

V26

I

TS_DATA[7]

TS_DATA[6]

TS_DATA[5]

TS_DATA[4]

TS_DATA[3]

TS_DATA[2]

TS_DATA[1]

TS_DATA[0]

TS_SOP

AB23

AC25

AB24

AA23

AC26

AB25

AB26

Y23

I/O

transport stream data bit 6

transport stream data bit 5

transport stream data bit 4

transport stream data bit 3

transport stream data bit 2

transport stream data bit 1

transport stream data bit 0

AA24

AA25

AA26

transport stream start of packet (parallel/serial)

transport stream data valid (parallel/serial)

transport stream clock (parallel/serial)

TS_VALID

TS_CLK

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

14 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 12: Phase Lock Loop (PLL)

Symbol

XTALI

C2

D3

W4

Type

Description

I

PLL reference crystal input

PLL reference crystal feedback driver

general purpose PLL clock output

XTALO

PLL_OUT

O

Table 13: Analog and digital power (PWR)

Symbol

AB18

AB17

AB14

AB13

AB12

AB9

AB8

N5

Description

V_DDC1

system 1.26 V

P5

U5

V5

K5

J5

E14

E13

E10

E9

E15

E18

E19

U22

V22

P22

N22

K22

J22

D1

E2

E1

G4

F3

F2

F1

H4

G3

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

15 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 13: Analog and digital power (PWR) …continued

Symbol

Description

V_DDC2

E4

system 1.26 V (analog power 1.728 GHz PLL)

system ground (analog ground 1.728 GHz PLL)

system 3.3 V

E3

V_SS

D2

F4

V_DD1

AB6

AB7

AB10

AB11

AB16

AB19

AB20

E12

E11

E8

system 3.3 V

E7

system 3.3 V

E16

E17

E20

E21

M22

L22

H22

G22

R22

T22

W22

Y22

T5

system 3.3 V

R5

system 3.3 V

M5

system 3.3 V

L5

system 3.3 V

W5

system 3.3 V

Y5

system 3.3 V

V_DD2

G5

system 3.3 V (CAB)

system 3.3 V (TM-PLL)

system ground

H5

V_DD3

V_SS

AB15

AF25

AF26

AE26

AE25

AC23

system ground

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

16 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 13: Analog and digital power (PWR) …continued

Symbol

Description

V_SS

AB22

AB21

AA22

F22

E22

D23

C24

B25

A25

A26

B26

L15

L14

L13

L12

L11

M11

N11

P11

R11

T11

T12

T13

R13

R14

T14

T15

T16

R16

AA5

AB5

AC4

AD3

AE2

AE1

AF1

AF2

F5

system ground

E5

E6

D4

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

17 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 13: Analog and digital power (PWR) …continued

Symbol

Description

V_SS

B2

system ground

A2

A1

B1

R15

R12

P12

P13

N13

N14

P14

P15

P16

N16

N15

N12

M12

M13

M14

L16

M16

M15

Table 14: Test

Symbol

Type

Description

DBG_TDI

DBG_TDO

DBG_TCK

DBG_TMS

JTAG_TRST

JTAG_TDI

JTAG_TDO

JTAG_TCK

JTAG_TMS

A3

B3

C3

C1

G2

J4

I

PR3940 debug port data in

PR3940 debug port data out

PR3940 debug port clock

PR3940 debug port mode select

JTAG port reset

O

I

JTAG data in

H2

G1

H3

O

I

JTAG data out

JTAG data clock

I

JTAG data mode select

Table 15: All pins (in alpha-numeric sequence)

Symbol

A1

A2

A3

A4

Group Type

Description

V_SS

PWR

TEST

-

I

system ground

DBG_TDI

I2C1_SDA

PR3940 debug port data in

serial communications port (I²C-bus) data

I²C-bus I/O

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

18 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

A5

A6

Group Type

Description

USB_DP[1]

PHY_ISO_N

USB

1394

I/O

I

data plus bit 1

signals type of isolation mode used at the

PHY-Link interface

0 = 1394-1995 annex J type isolation; enables

differentiator circuitry

1 = direct connection or single capacitor

isolation mode; this will disable the

differentiator circuitry

PHY_D[0]

PHY_D[4]

A7

A8

1394

I/O

PHY data bit 0; data is expected on ports 1:0 for

100 MB packets

PHY data bit 4; data is expected on ports 7:0 for

400 MB packets

MDQM[0]

MD[3]

A9

MMI

PWR

TEST

GPIO

1394

O

SDRAM control bit 0

memory data bit 3

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B1

I/O

O

MD[6]

memory data bit 6

MD[9]

memory data bit 9

MD[13]

MD[15]

MD[20]

MD[24]

MDQM[3]

MD[31]

MD[28]

MA[7]

memory data bit 13

memory data bit 15

memory data bit 20

memory data bit 24

SDRAM control bit 3

memory data bit 31

memory data bit 28

memory address bit 7

memory address bit 9

memory chip select

memory column address select

SDRAM control bit 4

system ground

I/O

O

MA[9]

O

MCS

O

MCAS

MDQM[4]

V_SS

O

-

system ground

-

system ground

B2

-

system ground

DBG_TDO

GPIO[2]

B3

O

PR3940 debug port data out

general purpose input/output bit 2

B4

I/O

O

PHY_LREQ

B5

used by the link to make bus requests and to

access PHY registers; this is a serial bus; a train

of pulses is sent on this signal

USB_DP[0]

PHY_CTL[1]

B6

B7

USB

1394

I/O

data plus bit 0

PHY control bit 1; indicates the mode for data on

the Din port

PHY_D[3]

PHY_D[7]

B8

B9

1394

I/O

PHY data bit 3; data is expected on ports 3:0 for

200 MB packets

PHY data bit 7; data is expected on ports 7:0 for

400 MB packets

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

19 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

MD[1]

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

Group Type

Description

MMI

PWR

TEST

PLL

I/O

O

memory data bit 1

MD[5]

memory data bit 5

MD[8]

memory data bit 8

MD[12]

MDQM[2]

MD[19]

MD[23]

MD[27]

MD[30]

MCLK[0]

MA[1]

memory data bit 12

SDRAM control bit 2

memory data bit 19

I/O

O

memory data bit 23

memory data bit 27

memory data bit 30

memory clock bit 0

O

memory address bit 1

memory address bit 10

SDRAM bank select

EDODRAM row address strobe

memory write enable

system ground

MA[10]

MBA[0]

MRAS

MWE

O

V_SS

-

system ground

DBG_TMS

XTALI

I

PR3940 debug port mode select

PLL reference crystal input

PR3940 debug port clock

general purpose input/output bit 0

general purpose input/output bit 3

data minus bit 0

C2

I

DBG_TCK

GPIO[0]

C3

TEST

GPIO

USB

1394

I

C4

I/O

GPIO[3]

C5

USB_DM[0]

PHY_CTL[0]

C6

C7

PHY control bit 0; indicates the mode for data on

the Din port

PHY_D[1]

PHY_D[5]

C8

C9

1394

I/O

PHY data bit 1; data is expected on ports 1:0 for

100 MB packets

PHY data bit 5; data is expected on ports 7:0 for

400 MB packets

MD[0]

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

MMI

I/O

O

memory data bit 0

memory data bit 2

memory data bit 7

memory data bit 11

memory data bit 16

memory data bit 18

memory data bit 22

memory data bit 26

memory data bit 29

memory address bit 3

memory address bit 6

memory address bit 8

memory address bit 11

MD[2]

MD[7]

MD[11]

MD[16]

MD[18]

MD[22]

MD[26]

MD[29]

MA[3]

MA[6]

O

MA[8]

O

MA[11]

O

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

20 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

MCKE

C23

C24

C25

C26

D1

Group Type

Description

MMI

O

-

memory clock enable

V_SS

PWR

MMI

system ground

MD[32]

MCLK[1]

V_DDC

I/O

O

-

memory data bit 32

MMI

memory clock bit 1

PWR

PLL

system 1.26 V

V_SS

D2

-

system ground (analog ground 1.728 GHz PLL)

PLL reference crystal feedback driver

system ground

XTALO

V_SS

D3

O

-

D4

PWR

GPIO[1]

I2C1_SCL

USB_DM[1]

CLK_L1394

PHY_D[2]

D5

GPIO

I²C-bus I/O

I/O

general purpose input/output bit 1

serial communications port (I²C-bus) clock

data minus bit 1

D6

D7

USB

1394

I/O

I

D8

system clock; 49.152 MHz input

D9

I/O

PHY data bit 2; data is expected on ports 3:0 for

200 MB packets

PHY_D[6]

D10

1394

I/O

PHY data bit 6; data is expected on ports 7:0 for

400 MB packets

MD[4]

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

E1

MMI

PWR

MMI

PWR

I/O

O

I/O

O

-

memory data bit 4

MDQM[1]

MD[10]

MD[14]

MD[17]

MD[21]

MD[25]

MA[5]

SDRAM control bit 1

memory data bit 10

memory data bit 14

memory data bit 17

memory data bit 21

memory data bit 25

memory address bit 5

memory address bit 4

memory address bit 2

memory address bit 0

SDRAM bank select

system ground

MA[4]

MA[2]

MA[0]

MBA[1]

V_SS

MD[33]

MD[36]

MD[35]

V_DDC1

I/O

-

memory data bit 33

memory data bit 36

memory data bit 35

system 1.26 V

E2

-

system 1.26 V

V_DDC2

E3

-

system 1.26 V (analog power 1.728 GHz PLL)

system ground

E4

-

V_SS

E5

-

E6

-

system ground

V_DD1

E7

-

system 3.3 V

E8

-

system 3.3 V

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

21 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

E9

Group Type

Description

V_DDC1

PWR

MMI

-

system 1.26 V

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

-

system 1.26 V

V_DD1

-

system 3.3 V

-

system 3.3 V

V_DDC1

-

system 1.26 V

-

system 1.26 V

-

system 1.26 V

V_DD1

V_DDC1

V_DD1

-

system 3.3 V

-

system 3.3 V

-

system 1.26 V

-

system 1.26 V

-

system 3.3 V

-

system 3.3 V

V_SS

-

system ground

MD[34]

MD[37]

MD[38]

MDQM[5]

V_DDC1

I/O

O

-

memory data bit 34

memory data bit 37

memory data bit 38

SDRAM control bit 5

system 1.26 V

MMI

PWR

MMI

F2

-

system 1.26 V

F3

-

system 1.26 V

V_SS

F4

-

system ground (analog ground 1.728 GHz PLL)

system ground

F5

-

F22

F23

F24

F25

F26

G1

-

system ground

MD[39]

I/O

I

memory data bit 39

memory data bit 40

memory data bit 41

memory data bit 42

JTAG data clock

JTAG port reset

MD[40]

MMI

MD[41]

MMI

MD[42]

MMI

JTAG_TCK

JTAG_TRST

V_DDC1

TEST

PWR

MMI

G2

I

G3

-

system 1.26 V

G4

-

system 1.26 V

V_DD2

G5

-

system 3.3 V (CAB)

system 3.3 V

V_DD1

G22

G23

G24

G25

G26

H1

-

MD[43]

I/O

memory data bit 43

memory data bit 44

memory data bit 45

memory data bit 46

serial communications port (I²C-bus) clock

JTAG data OUT

MD[44]

MMI

MD[45]

MMI

MD[46]

MMI

I²C-bus I/O

I2C2_SCL

JTAG_TDO

JTAG_TMS

H2

TEST

O

I

H3

JTAG data mode select

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

22 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

H4

Group Type

Description

V_DDC1

PWR

MMI

AVIF

TEST

PWR

MMI

AVIF

-

system 1.26 V

V_DD2

H5

-

system 3.3 V (CAB)

system 3.3 V

V_DD1

H22

H23

H24

H25

H26

J1

-

MD[47]

I/O

O

memory data bit 47

SDRAM control bit 6

memory data bit 48

memory data bit 49

audio OUT1 serial clock

audio OUT1 data

MDQM[6]

MD[48]

I/O

O

MD[49]

I2S_OUT1_SCK

I2S_OUT1_SD

I2S_OUT1_WS

JTAG_TDI

V_DDC1

J2

J3

I/O

I

audio OUT1 word select

JTAG data IN

J4

J5

-

system 1.26 V

J22

J23

J24

J25

J26

K1

-

system 1.26 V

MD[50]

I/O

O

memory data bit 50

memory data bit 51

memory data bit 52

memory data bit 53

audio OUT2 word select

audio OUT2 oversample clock

audio OUT1 oversample clock

serial communications port (I²C-bus) data

system 1.26 V

MD[51]

MD[52]

MD[53]

I2S_OUT2_WS

I2S_OUT2_OSCLK K2

I2S_OUT1_OSCLK K3

O

I2C2_SDA

V_DDC1

K4

I²C-bus I/O

K5

PWR

MMI

-

K22

K23

K24

K25

K26

L1

-

system 1.26 V

MD[54]

I/O

O

I/O

O

I/O

O

-

memory data bit 54

memory data bit 55

SDRAM control bit 7

memory data bit 56

horizontal sync for primary display

vertical sync for primary display

audio OUT2 serial clock

audio OUT2 Data

MD[55]

MMI

MDQM[7]

MD[56]

MMI

HSYNC

AVIF

PWR

MMI

VSYNC

L2

I2S_OUT2_SCK

I2S_OUT2_SD

V_DD1

L3

L4

L5

system 3.3 V

V_SS

L11

L12

L13

L14

L15

L16

L22

L23

L24

-

system ground

-

system ground

-

system ground

-

system ground

-

system ground

-

system ground

V_DD1

-

system 3.3 V

MD[57]

MD[58]

I/O

memory data bit 57

memory data bit 58

MMI

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

23 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

MD[59]

L25

L26

M1

Group Type

Description

MMI

AVIF

I/O

O

memory data bit 59

memory data bit 60

MD[60]

DV_OUT1[8]

digital video output1; bit 8 for primary display

channel from AICP

DV_OUT1[9]

DV_CLK1

M2

M3

AVIF

O

digital video output1; bit 9 for primary display

channel from AICP

digital video clock1 for primary display channel

from AICP

BLANK

V_DD1

V_SS

M4

AVIF

PWR

MMI

O

-

blanking for primary display

system 3.3 V

M5

M11

M12

M13

M14

M15

M16

M22

M23

M24

M25

M26

N1

-

system ground

-

system ground

-

system ground

-

system ground

-

system ground

-

system ground

V_DD1

-

system 3.3 V

MD[61]

MD[62]

MD[63]

GPIO[8]

DV_OUT1[5]

I/O

O

memory data bit 61

memory data bit 62

memory data bit 63

general purpose input/output Bit 8

MMI

GPIO

AVIF

digital video output1; bit 5 for primary display

channel from AICP

DV_OUT1[4]

DV_OUT1[6]

DV_OUT1[7]

N2

N3

N4

AVIF

O

digital video output1; bit 4 for primary display

channel from AICP

digital video output1; bit 6 for primary display

channel from AICP

digital video output1; bit 7 for primary display

channel from AICP

V_DDC1

V_SS

N5

PWR

GPIO

COM

GPIO

AVIF

-

system 1.26 V

N11

N12

N13

N14

N15

N16

N22

N23

N24

N25

N26

P1

-

system ground

-

system ground

-

system ground

-

system ground

-

system ground

-

system ground

V_DDC1

-

system 1.26 V

GPIO[9]

I/O

O

I/O

O

general purpose input/output bit 9

general purpose input/output bit 10

smart card2 bit clock

general purpose input/output bit 11

GPIO[10]

SC2_SCCK

GPIO[11]

DV_OUT1[2]

digital video output1; bit 2 for primary display

channel from AICP

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

24 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

Group Type

Description

DV_OUT1[3]

P2

AVIF

O

digital video output1; bit 3 for primary display

channel from AICP

DV_OUT1[0]

DV_OUT1[1]

P3

P4

digital video output1; bit 0 for primary display

channel from AICP

digital video output1; bit 1 for primary display

channel from AICP

V_DDC1

V_SS

P5

PWR

COM

AVIF

-

system 1.26 V

P11

P12

P13

P14

P15

P16

P22

P23

P24

P25

P26

R1

-

system ground

system 1.26 V

-

V_DDC1

-

SC2_DA

I/O

O

I

smart card2 data

smart card2 command

smart card2 off

smart card2 reset

SC2_CMD

SC2_OFFN

SC2_RST

DV_CLK2

O

digital video clock2 for secondary display

channel from AICP

DV_OUT2[9]

DV_OUT2[7]

DV_OUT2[8]

R2

R3

R4

AVIF

O

digital video output2; bit 9 for secondary display

channel from AICP

digital video output2; bit 7 for secondary display

channel from AICP

digital video output2; bit 8 for secondary display

channel from AICP

V_DD1

V_SS

R5

PWR

COM

AVIF

-

system 3.3 V

R11

R12

R13

R14

R15

R16

R22

R23

R24

R25

R26

T1

-

system ground

system 3.3 V

-

V_DD1

-

SC1_CMD

SC1_RST

SC1_OFFN

SC1_SCCK

DV_OUT2[6]

O

I

smart card1 command

smart card1 reset

smart card1 off

smart card1 bit clock

O

digital video output2; bit 6 for secondary display

channel from AICP

DV_OUT2[5]

T2

AVIF

O

digital video output2; bit 5 for secondary display

channel from AICP

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

25 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

Group Type

Description

DV_OUT2[4]

T3

AVIF

O

digital video output2; bit 4 for secondary display

channel from AICP

DV_OUT2[2]

T4

AVIF

O

digital video output2; bit 2 for secondary display

channel from AICP

V_DD1

V_SS

T5

PWR

COM

AVIF

-

system 3.3 V

T11

T12

T13

T14

T15

T16

T22

T23

T24

T25

T26

U1

-

system ground

system 3.3 V

-

V_DD1

-

UA2_TX

I/O

O

UART2 transmit

UART2 request to send

UART2 clear to send

smart card1 data

UA2_RTSN

UA2_CTSN

SC1_DA

DV_OUT2[3]

digital video output2; bit 3 for secondary display

channel from AICP

DV_OUT2[1]

DV_OUT2[0]

U2

U3

AVIF

O

digital video output2; bit 1 for secondary display

channel from AICP

digital video output2; bit 0 for secondary display

channel from AICP

SSI_RXD

V_DDC1

U4

COM

PWR

DVB

I/O

-

synchronous serial interface receive

system 1.26 V

U5

U22

U23

U24

U25

U26

-

system 1.26 V

DV3_ERR

UA1_TX

UA1_RX

UA2_RX

I

digital video transport stream3 error

UART1 transmit

COM

PCI

I/O

UART1 receive

UART2 receive

SSI_SCLK_CTSN V1

synchronous serial interface clock

synchronous serial interface frame sync

synchronous serial interface transmit

SSI_FS_RTSN

SSI_TXD

V2

V3

V4

PCI_INTA

interrupt acknowledge is asserted to request an

interrupt

V_DDC1

V5

PWR

DVB

-

I

system 1.26 V

V22

V23

V24

V25

V26

system 1.26 V

DV3_DATA[2]

DV3_SOP

digital video transport stream3 data bit 2

digital video transport stream3 start of packet

digital video transport stream3 data valid

digital video transport stream3 clock

DV3_VALID

DV3_CLK

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

26 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

Group Type

Description

USB_PWR

W1

USB

O

USB port power on/off

0 = power on

1 = power off

USB_OVRCUR

W2

USB

I

indicates over current being drawn by a USB

device

0 = over current detected

1 = no over current

RESET_IN

PLL_OUT

V_DD1

W3

PCI

I

PCI bus global reset

W4

PLL

O

general purpose PLL clock output

system 3.3 V

W5

PWR

DVB

MISC

PCI

-

W22

W23

W24

W25

W26

-

system 3.3 V

DV3_DATA[7]

DV3_DATA[3]

DV3_DATA[1]

DV3_DATA[0]

I

digital video transport stream3 data bit 7

digital video transport stream3 data bit 3

digital video transport stream3 data bit 1

digital video transport stream3 data bit 0

system reset output

I

SYS_RSTN_OUT Y1

O

I/O

PCI_REQ

Y2

arbitration request on PCI bus; request is an

output when using an external arbiter and an

input when using an internal arbiter

PCI_GNT

Y3

PCI

I/O

arbitration grant is asserted to indicate access to

the bus has been granted; this pin is an input

when an external arbiter is used and an output

when using the internal arbiter

PCI_GNT_A

Y4

auxiliary arbitration grant GNT_A is asserted to

indicate bus access has been granted to an

external PCI master; used where internal arbiter

is conﬁgured

V_DD1

Y5

PWR

DVB

PCI

-

system 3.3 V

Y22

Y23

Y24

Y25

Y26

AA1

AA2

-

system 3.3 V

TS_DATA[0]

DV3_DATA[6]

DV3_DATA[5]

DV3_DATA[4]

CLK

I/O

transport stream data bit 0

digital video transport stream3 data bit 6

digital video transport stream3 data bit 5

digital video transport stream3 data bit 4

PCI bus clock

I

PCI_REQ_A

PCI

I/O

auxiliary arbitration PCI_REQ_A on PCI Bus;

used in modes where internal arbiter is

conﬁgured

PCI_REQ_B

PCI_GNT_B

AA3

AA4

PCI

I/O

auxiliary arbitration PCI_REQ_B on PCI Bus;

used in modes where internal arbiter is

conﬁgured

auxiliary arbitration grant GNT_B is asserted to

indicate bus access has been granted to an

external PCI master; used where internal arbiter

is conﬁgured

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

27 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

Group Type

Description

V_SS

AA5

PWR

DVB

PCI

-

system ground

AA22

AA23

AA24

AA25

AA26

AB1

-

system ground

TS_DATA[4]

TS_SOP

TS_VALID

TS_CLK

I/O

-

transport stream data bit 4

transport stream start of packet (parallel/serial)

transport stream data valid (parallel/serial)

transport stream clock (parallel/serial)

multiplexed address or data bit 31

multiplexed address or data bit 30

multiplexed address or data bit 29

multiplexed address or data bit 28

system ground

PCI_AD[31]

PCI_AD[30]

PCI_AD[29]

PCI_AD[28]

V_SS

AB2

PCI

AB3

PCI

AB4

PCI

AB5

PWR

DVB

PCI

V_DD1

AB6

-

system 3.3 V

AB7

-

system 3.3 V

V_DDC1

AB8

-

system 1.26 V

AB9

-

system 1.26 V

V_DD1

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AC1

-

system 3.3 V

-

system 3.3 V

V_DDC1

-

system 1.26 V

-

system 1.26 V

-

system 1.26 V

V_DD1

V_DD3

V_DDC1

-

system 3.3 V (TM-PLL)

system 3.3 V

-

system 1.26 V

-

system 1.26 V

V_DD1

-

system 3.3 V

-

system 3.3 V

V_SS

-

system ground

-

system ground

TS_DATA[7]

TS_DATA[5]

TS_DATA[2]

TS_DATA[1]

PCI_AD[27]

PCI_AD[26]

PCI_AD[25]

V_SS

I/O

-

transport stream data bit 7

transport stream data bit 5

transport stream data bit 2

transport stream data bit 1

multiplexed address or data bit 27

multiplexed address or data bit 26

multiplexed address or data bit 25

system ground

AC2

PCI

AC3

PCI

AC4

PWR

PCI

PCI_AD[17]

PCI_AD[16]

PCI_SERR

PCI_AD[14]

PCI_AD[10]

AC5

I/O

multiplexed address or data bit 17

multiplexed address or data bit 16

system error

AC6

PCI

AC7

PCI

AC8

PCI

multiplexed address or data bit 14

multiplexed address or data bit 10

AC9

PCI

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

28 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

Group Type

Description

PCI_AD[7]

PCI_AD[3]

PCI_AD[0]

XIO_SEL[1]

GPIO[4]

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

PCI

I/O

O

multiplexed address or data bit 7

multiplexed address or data bit 3

multiplexed address or data bit 0

external input/output select1

general purpose input/output bit 4

audio input/output word select

multi-channel/SPDIF Output

ITU-656 VIP data bit 6

PCI

MISC

GPIO

AVIF

DVB

AVIF

DVB

PWR

DVB

PCI

I2S_IO_WS

SPDIF_OUT

DV1_DATA[6]

DV1_DATA[1]

I2S_IN1_SCK

I2S_IN2_SCK

DV2_DATA[6]

DV2_DATA[3]

V_SS

I/O

I

ITU-656 VIP data bit 1

audio IN1 serial clock

audio IN2 serial clock

digital video transport stream2 data bit 6

digital video transport stream2 data bit 3

system ground

I

-

DV2_CLK

I

digital video transport stream2 clock

transport stream data bit 6

transport stream data bit 3

multiplexed command or byte enable 3

multiplexed address or data bit 24

system ground

TS_DATA[6]

TS_DATA[3]

PCI_CBE[3]

PCI_AD[24]

V_SS

I/O

-

AD2

PCI

AD3

PWR

PCI

PCI_AD[20]

PCI_AD[18]

PCI_TRDY

AD4

I/O

multiplexed address or data bit 20

multiplexed address or data bit 18

AD5

PCI

AD6

PCI

parity error indicates data parity errors during all

PCI transactions except special cycle

PCI_PERR

AD7

PCI

I/O

parity error indicates data parity errors during all

PCI transactions except special cycle

PCI_AD[15]

PCI_AD[11]

PCI_CBE[0]

PCI_AD[4]

AD8

PCI

I/O

O

multiplexed address or data bit 15

multiplexed address or data bit 11

multiplexed command or byte enable 0

multiplexed address or data bit 4

multiplexed address or data bit 1

external input/output select0

AD9

PCI

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

PCI

PCI_AD[1]

PCI

XIO_SEL[0]

GPIO[5]

MISC

GPIO

AVIF

DVB

AVIF

DVB

general purpose input/output bit 5

audio input/output data bit 3

I2S_IO_SD[3]

I2S_IO_SD[0]

DV1_DATA[8]

DV1_DATA[4]

DV1_DATA[0]

I2S_IN1_OSCLK

I2S_IN2_OSCLK

DV2_DATA[5]

audio input/output data bit 0

ITU-656 VIP data bit 8

ITU-656 VIP data bit 4

ITU-656 VIP data bit 0 (least signiﬁcant bit)

audio IN1 oversample clock

O

audio IN2 oversample clock

I

digital video transport stream2 data bit 5

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

29 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

Group Type

Description

DV2_DATA[2]

DV2_SOP

DV2_VALID

DV2_ERR

V_SS

AD23

AD24

AD25

AD26

AE1

DVB

PWR

PCI

I

digital video transport stream2 data bit 2

digital video transport stream2 start of packet

digital video transport stream2 data valid

digital video transport stream2 error

system ground

I

-

AE2

-

system ground

PCI_AD[23]

PCI_AD[21]

PCI_AD[19]

PCI_IRDY

AE3

I/O

multiplexed address or data bit 23

multiplexed address or data bit 21

multiplexed address or data bit 19

AE4

PCI

AE5

PCI

AE6

PCI

initiator ready is asserted during writes to

indicate valid data on PCI_AD[31:0]; also

asserted during reads to indicate the target is

prepared to accept data; wait states are inserted

until PCI_IRDY and PCI_TRDY are both

asserted

PCI_STOP

AE7

PCI

I/O

stop is asserted to indicate a request from the

target for the master to stop the current

transmission

PCI_CBE[1]

PCI_AD[12]

PCI_AD[8]

PCI_AD[5]

PCI_AD[2]

XIO_A25

AE8

PCI

I/O

I

multiplexed command or byte enable 1

multiplexed address or data bit 12

multiplexed address or data bit 8

multiplexed address or data bit 5

multiplexed address or data bit 2

XIO address bit 25

AE9

PCI

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF1

PCI

MISC

GPIO

AVIF

DVB

AVIF

DVB

PWR

PCI

GPIO[7]

general purpose input/output bit 7

audio input/output serial clock

audio input/output data bit 1

ITU-656 VIP data bit 9 (most signiﬁcant bit)

ITU-656 VIP data bit 5

I2S_IO_SCK

I2S_IO_SD[1]

DV1_DATA[9]

DV1_DATA[5]

DV1_DATA[2]

DV1_CLK

ITU-656 VIP data bit 2

ITU-656 VIP data clock

I2S_IN1_SD

I2S_IN2_SD

DV2_DATA[4]

DV2_DATA[1]

V_SS

audio IN1 data

I

audio IN2 data

I

digital video transport stream2 data bit 4

digital video transport stream2 data bit 1

system ground

I

-

system ground

-

system ground

AF2

-

system ground

IDSEL

AF3

I/O

initialization device select provides chip select

during conﬁguration read and write transactions

PCI_AD[22]

PCI_CBE[2]

AF4

AF5

PCI

I/O

multiplexed address or data bit 22

multiplexed command or byte enable 2

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

30 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 15: All pins (in alpha-numeric sequence) …continued

Symbol

Group Type

Description

PCI_FRAME

AF6

PCI

I/O

frame is asserted to indicate start of bus

transaction and remains asserted until ﬁnal data

phase begins

PCI_DEVSEL

PCI_PAR

AF7

AF8

device select is asserted when a target address

is decoded and remains asserted to indicate that

a target device is selected

parity supports even parity across the PCI

address/data bus AD[31:0]) and command/ byte

enable bus (PCI_CBE[3:0]); bus master drives

PCI_PAR for address and write data phases;

target drives PCI_PAR for the read data phases

PCI_AD[13]

PCI_AD[9]

PCI_AD[6]

XIO_SEL[2]

XIO_ACK

AF9

PCI

I/O

I

multiplexed address or data bit 13

multiplexed address or data bit 9

multiplexed address or data bit 6

external input/output select2

XIO acknowledge (EEPROM)

general purpose input/output bit 6

audio input/output oversample clock

audio input/output data bit 2

multi-channel/SPDIF input

ITU-656 VIP data bit 7

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

PCI

MISC

GPIO

AVIF

DVB

AVIF

DVB

PWR

GPIO[6]

I2S_IO_OSCLK

I2S_IO_SD[2]

SPDIF_IN

DV1_DATA[7]

DV1_DATA[3]

DV1_VALID

I2S_IN1_WS

I2S_IN2_WS

DV2_DATA[7]

DV2_DATA[0]

V_SS

I/O

I

ITU-656 VIP data bit 3

ITU-656 VIP data valid

audio in1 word select

audio in2 word select

digital video transport stream2 data bit 7

digital video transport stream2 data bit 0

system ground

I

-

system ground

6.2.1 Multi-function pins

Table 16 identiﬁes and describes alternate signals that are available in the PNX8526. In

Section 6.2 alternate signals are also identiﬁed by a hash (#) within each functional group

of signals.

Remark: The PNX8526 has a number of General Purpose Input Output (GPIO) pins.

Some of these are dedicated pins, while others are conﬁgured as alternate signals on

multifunction pins. The standard function of these pins may not be required in some

system conﬁgurations.

For more details on GPIO functionality, see “PNX8526 User Manual, Chapter 10”.

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

31 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 16: Multiplexed (MUX) pins

Pin MUX contacts

Type^[1]Description

primary signal and

alternate function

AF15 I2S_IO_OSCLK

GPIO[45]

I/O

O

audio input/output oversample clock

general purpose input/output 45

audio input/output serial clock

general purpose input/output 46

audio input/output word select

general purpose input/output 47

audio input/output data bit 3

general purpose input/output 51

audio input/output data bit 2

general purpose input/output 50

audio input/output data bit 1

general purpose input/output 49

audio input/output data bit 0

general purpose input/output 48

AE15 I2S_IO_SCK

GPIO[46]

AC15 I2S_IO_WS

GPIO[47]

AD15 I2S_IO_SD[3]

GPIO[51]

AF16 I2S_IO_SD[2]

GPIO[50]

AE16 I2S_IO_SD[1]

GPIO[49]

AD16 I2S_IO_SD[0]

GPIO[48]

R2

DV_OUT2[9]

digital video output2, Bit 9 for secondary display channel

from AICP

SPY_OUT[9]

DV_OUT2[8]

O

SPY micro-architecture output signal, Bit 9

R4

digital video output2, bit 8 for secondary display channel

from AICP

SPY_OUT[8]

DSU_TPC1

DV_OUT2[7]

O

SPY micro-architecture output signal, bit 8

debug support unit1, tpc1

R3

T1

T2

T3

U1

digital video output2, bit 7 for secondary display channel

from AICP

SPY_OUT[7]

DSU_TPC0

DV_OUT2[6]

O

SPY micro-architecture output signal, bit 7

debug support unit0, TPC0

digital video output2, bit 6 for secondary display channel

from AICP

SPY_OUT[6]

DSU_PCST1[2]

DV_OUT2[5]

O

SPY micro-architecture output signal, bit 6

program counter status1, bit 2

digital video output2, bit 5 for secondary display channel

from AICP

SPY_OUT[5]

DSU_PCST1[1]

DV_OUT2[4]

O

SPY micro-architecture output signal, bit 5

program counter status1, bit 1

digital video output2, bit 4 for secondary display channel

from AICP

SPY_OUT[4]

DSU_PCST1[0]

DV_OUT2[3]

O

SPY micro-architecture output signal, bit 4

program counter status1, bit 0

digital video output2, bit 3 for secondary display channel

from AICP

SPY_OUT[3]

O

SPY micro-architecture output signal, bit 3

program counter status0, bit 2

DSU_PCST0[2]

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

32 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 16: Multiplexed (MUX) pins …continued

MUX contacts

Type^[1]Description

primary signal and

alternate function

T4

DV_OUT2[2]

O

digital video output2, bit 2 for secondary display channel

from AICP

SPY_OUT[2]

DSU_PCST0[1]

DV_OUT2[1]

O

SPY micro-architecture output signal, bit 2

program counter status0, bit 1

U2

U3

digital video output2, bit 1 for secondary display channel

from AICP

SPY_OUT[1]

DSU_PCST0[0]

DV_OUT2[0]

O

SPY micro-architecture output signal, bit 1

program counter status0, bit 0

digital video output2, bit 0 for secondary display channel

from AICP

SPY_OUT[0]

DSU_CLK

O

I/O

O

I/O

O

I

SPY micro-architecture output signal, bit 0

debug support unit clock

K2

L3

K1

L4

I2S_OUT2_OSCLK

DV_OUT[20]

audio out2 oversample clock

AICP RGB data bit 20

SPY_OUT[11]

I2S_OUT2_SCK

DV_OUT[21]

SPY micro-architecture output signal, bit 11

audio OUT2 serial clock

AICP RGB data bit 21

SPY_OUT[10]

I2S_OUT2_WS

DV_OUT[22]

SPY micro-architecture output signal, bit 10

audio OUT2 Word Select

AICP RGB data bit 22

DBG_EXT_STOP

I2S_OUT2_SD

DV_OUT[23]

external stop request signal

audio OUT2 data

O

I

AICP RGB data bit 23 (most signiﬁcant bit)

SPY micro-architecture clock output signal

ITU-656 VIP data bit 9 (most signiﬁcant bit)

general purpose input/output 42

ITU-656 VIP data bit 8

CLK_SPY

AE17 DV1_DATA[9]

GPIO[42]

I/O

I

AD17 DV1_DATA[8]

GPIO[41]

I/O

I

general purpose input/output 41

ITU-656 VIP data bit 7

AF18 DV1_DATA[7]

GPIO[40]

I/O

I

general purpose input/output 40

ITU-656 VIP data bit 6

AC17 DV1_DATA[6]

GPIO[39]

I/O

I

general purpose input/output 39

ITU-656 VIP data bit 5

AE18 DV1_DATA[5]

GPIO[38]

I/O

I

general purpose input/output 38

ITU-656 VIP data bit 4

AD18 DV1_DATA[4]

GPIO[37]

I/O

I

general purpose input/output 37

ITU-656 VIP data bit 3

AF19 DV1_DATA[3]

GPIO[36]

I/O

I

general purpose input/output 36

ITU-656 VIP data bit 2

AE19 DV1_DATA[2]

GPIO[35]

I/O

general purpose input/output 35

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Product data sheet

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 16: Multiplexed (MUX) pins …continued

Pin MUX contacts

Type^[1]Description

primary signal and

alternate function

AC18 DV1_DATA[1]

GPIO[34]

I

ITU-656 VIP data bit 1

I/O

general purpose input/output 34

AD19 DV1_DATA[0]

GPIO[33]

I

ITU-656 VIP data bit 0 (least signiﬁcant bit)

general purpose input/output 33

I/O

AF20 DV1_VALID

GPIO[44]

I

ITU-656 VIP data valid

I/O

general purpose input/output 44

AE20 DV1_CLK

GPIO[43]

I

ITU-656 VIP data clock

I/O

I

general purpose input/output 43

AF23 DV2_DATA[7]

VIP[9]

digital video transport stream2 data bit 7

ITU-656 VIP data bit 9 (most signiﬁcant bit)

digital video transport stream2 data bit 6

ITU-656 VIP data bit 8

I

AC21 DV2_DATA[6]

VIP[8]

I

TSS_DATA2

AD22 DV2_DATA[5]

VIP[7]

I

digital video transport stream2 serial data2

digital video transport stream2 data bit 5

ITU-656 VIP data bit 7

I

TSS_SOP2

I

digital video transport stream2 serial start of packet2

digital video transport stream2 data bit 4

ITU-656 VIP data bit 6

AE23 DV2_DATA[4]

VIP[6]

I

TSS_ERR2

I

digital video transport stream2 serial error2

digital video transport stream2 data bit 3

ITU-656 VIP data bit 5

AC22 DV2_DATA[3]

VIP[5]

I

TSS_VALID2

AD23 DV2_DATA[2]

VIP[4]

I

digital video transport stream2 serial valid2

digital video transport stream2 data bit 2

ITU-656 VIP data bit 4

I

TSS_CLK2

I

digital video transport stream2 serial clock2

digital video transport stream2 data bit 1

ITU-656 VIP data bit 3

AE24 DV2_DATA[1]

VIP[3]

I

AF24 DV2_DATA[0]

VIP[2]

I

digital video transport stream2 data bit 0

ITU-656 VIP data bit 2

I

TSS_DATA1

AD24 DV2_SOP

VIP[1]

I

digital video transport stream2 serial data1

digital video transport stream2 start of packet

ITU-656 VIP data bit 1

I

TSS_SOP1

I

digital video transport stream2 serial start of packet1

digital video transport stream2 error

ITU-656 VIP data bit 0 (least signiﬁcant bit)

digital video transport stream2 serial error1

digital video transport stream2 data valid

ITU-656 VIP data valid

AD26 DV2_ERR

VIP[0]

I

TSS_ERR1

I

AD25 DV2_VALID

VIP_VALID

I

TSS_VALID1

I

digital video transport stream2 serial valid1

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 16: Multiplexed (MUX) pins …continued

Pin MUX contacts

Type^[1]Description

primary signal and

alternate function

AC24 DV2_CLK

VIP_CLK

I

digital video transport stream2 clock

I

ITU-656 VIP data clock

TSS_CLK1

I

digital video transport stream2 serial clock1

digital video transport stream3 data bit 7

ITU-656 VIP data bit 9 (most signiﬁcant bit)

digital video transport stream3 data bit 6

ITU-656 VIP data bit 8

W23 DV3_DATA[7]

VIP[9]

I

Y24 DV3_DATA[6]

VIP[8]

I

TSS_DATA2

Y25 DV3_DATA[5]

VIP[7]

I

digital video transport stream3 serial data2

digital video transport stream3 data bit 5

ITU-656 VIP data bit 7

I

TSS_SOP2

I

digital video transport stream3 serial start of packet2

digital video transport stream3 data bit 4

ITU-656 VIP data bit 6

Y26 DV3_DATA[4]

VIP[6]

I

TSS_ERR2

I

digital video transport stream3 serial error2

digital video transport stream3 data bit 3

ITU-656 VIP data bit 5

W24 DV3_DATA[3]

VIP[5]

I

TSS_VALID2

V23 DV3_DATA[2]

VIP[4]

I

digital video transport stream3 serial valid2

digital video transport stream3 data bit 2

ITU-656 VIP data bit 4

I

TSS_CLK2

I

digital video transport stream3 serial clock2

digital video transport stream3 data bit 1

ITU-656 VIP data bit 3

W25 DV3_DATA[1]

VIP[3]

I

W26 DV3_DATA[0]

VIP[2]

I

digital video transport stream3 data bit 0

ITU-656 VIP data bit 2

I

TSS_DATA1

V24 DV3_SOP

VIP[1]

I

digital video transport stream3 serial data1

digital video transport stream3 start of packet

ITU-656 VIP data bit 1

I

TSS_SOP1

I

digital video transport stream3 serial start of packet1

digital video transport stream3 error

ITU-656 VIP data bit 0 (least signiﬁcant bit)

digital video transport stream3 serial error1

digital video transport stream3 data valid

ITU-656 VIP data valid

U23 DV3_ERR

VIP[0]

I

TSS_ERR1

I

V25 DV3_VALID

VIP_VALID

I

TSS_VALID1

V26 DV3_CLK

VIP_CLK

I

digital video transport stream3 serial valid1

digital video transport stream3 clock

ITU-656 VIP data clock

I

TSS_CLK1

I

digital video transport stream3 serial clock1

transport stream data bit 7

AB23 TS_DATA[7]

GPIO[29]

O

I/O

general purpose input/output 29

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 16: Multiplexed (MUX) pins …continued

Pin MUX contacts

Type^[1]Description

primary signal and

alternate function

AC25 TS_DATA[6]

GPIO[28]

O

transport stream data bit 6

I/O

O

general purpose input/output 28

transport stream data bit 5

AB24 TS_DATA[5]

GPIO[27]

I/O

O

general purpose input/output 27

transport stream data bit 4

AA23 TS_DATA[4]

GPIO[26]

I/O

O

general purpose input/output 26

transport stream data bit 3

AC26 TS_DATA[3]

GPIO[25]

I/O

O

general purpose input/output 25

transport stream data bit 2

AB25 TS_DATA[2]

GPIO[24]

I/O

O

general purpose input/output 24

transport stream data bit 1

AB26 TS_DATA[1]

GPIO[23]

I/O

O

general purpose input/output 23

transport stream data bit 0

Y23 TS_DATA[0]

GPIO[22]

I/O

O

general purpose input/output 22

transport stream serial data output

transport stream start of packet (parallel/serial)

general purpose input/output 31

transport stream data valid (parallel/serial)

general purpose input/output 32

transport stream clock (parallel/serial)

general purpose input/output 30

TS_SD

AA24 TS_SOP

GPIO[31]

O

I/O

O

AA25 TS_VALID

GPIO[32]

I/O

O

AA26 TS_CLK

GPIO[30]

AA2 PCI_REQ_A^[2]

I/O

auxiliary arbitration PCI_REQ_A on PCI bus; used in

modes where internal arbiter is conﬁgured

GPIO[57]

AA3 PCI_REQ_B^[2]

I/O

general purpose input/output 57

auxiliary arbitration PCI_REQ_B on PCI bus; used in

modes where internal arbiter is conﬁgured

GPIO[58]

PCI_GNT_A^[2]

I/O

general purpose input/output 58

Y4

auxiliary arbitration grant GNT_A is asserted to indicate bus

access has been granted to an external PCI master; used

where internal arbiter is conﬁgured

GPIO[59]

AA4 PCI_GNT_B^[2]

I/O

general purpose input/output 59

auxiliary arbitration grant GNT_B is asserted to indicate bus

access has been granted to an external PCI master; used

where internal arbiter is conﬁgured

GPIO[60]

AF12 XIO_SEL[2]^[2]

GPIO[54]

I/O

O

general purpose input/output 60

external MMIO select 2

I/O

O

general purpose input/output 54

external MMIO select 1

AC13 XIO_SEL[1]^[2]

GPIO[53]

I/O

O

general purpose input/output 53

external MMIO select 0

AD13 XIO_SEL[0]^[2]

GPIO[52]

I/O

general purpose input/output 52

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 16: Multiplexed (MUX) pins …continued

Pin MUX contacts

Type^[1]Description

primary signal and

alternate function

AF13 XIO_ACK^[2]

I

XIO acknowledge (EEPROM)

GPIO[55]

I/O

O

general purpose input/output 55

XIO address bit 25

AE13 XIO_A25^[2]

GPIO[56]

I/O

O

general purpose input/output 56

UART1 transmit

U24 UA1_TX

GPIO[12]

I/O

I

general purpose input/output 12

UART1 receive

U25 UA1_RX

GPIO[13]

I/O

O

general purpose input/output 13

UART2 transmit

T23 UA2_TX

GPIO[14]

I/O

I

general purpose input/output 14

U26 UA2_RX

UART2 receive

ICAM1_SETVPP

O

ICAM1 VPP^[3]

GPIO[15]

T24 UA2_RTSN

ICAM1_C8

I/O

O

general purpose input/output 15

UART2 request to send

ICAM1 C8^[3]

I

GPIO[16]

I/O

I

general purpose input/output 16

UART2 clear to send

T25 UA2_CTSN

ICAM1_C4

I/O

I

ICAM1 C4

GPIO[17]

general purpose input/output 17

synchronous serial interface clock input

UART2 clear to send

V1

V2

SSI_SCLK_CTSN

UART CTS

GPIO[21]

I

I/O

I

general purpose input/output 21

synchronous serial interface frame sync

UART2 request to send

SSI_FS_RTSN

UART RTS

GPIO[20]

O

I/O

I

general purpose input/output 20

synchronous serial interface receive

general purpose input/output 19

synchronous serial interface transmit

general purpose input/output 18

ICAM2 C4

U4

V3

SSI_RXD

GPIO[19]

I/O

O

SSI_TXD

GPIO[18]

I/O

O

N26 ICAM2_C4

GPIO[11]

general purpose input/output 11

ICAM2 C8

N24 ICAM2_C8

GPIO[10]

general purpose input/output 10

ICAM2 VPP

N23 ICAM2_SETVPP

GPIO[9]

I/O

I

general purpose input/output 9

select conﬁguration bit 2 during system reset

general purpose input/output 2

select conﬁguration bit 1 during system reset

general purpose input/output 1

B4

BOOTMODE[2]

GPIO[2]

I/O

I

D5

BOOTMODE[1]

GPIO[1]

I/O

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 16: Multiplexed (MUX) pins …continued

MUX contacts

Type^[1]Description

primary signal and

alternate function

C4

BOOTMODE[0]

GPIO[0]

I

select conﬁguration bit 0 during system reset

I/O

I

general purpose input/output 0

smart card Off

ICAM2 detect

P25 SC2_OFFN

ICAM2_DETECT

P24 SC2_CMD

ICAM2_SETVCC

P26 SC2_RST

ICAM2_RESET

I

O

I/O

I

smart card command

ICAM2 V_CC

smart card reset

ICAM2reset

N25 SC2_SCCK

ICAM2_CLK

smart card clock

ICAM2 clock

P23 SC2_DA

ICAM2_C7

smart card2 data

ICAM2 C7

R25 SC1_OFFN

smart card off

ICAM1_DETECT

R23 SC1_CMD

ICAM1_SETVCC

R24 SC1_RST

ICAM1_RESET

I

ICAM1 detect

O

I/O

smart card command

ICAM1 VCC

smart card reset

ICAM1 reset

R26 SC1_SCCK

ICAM1_CLK

smart card clock

ICAM1 clock

T26 SC1_DA

ICAM1_C7

smart card1 data

ICAM1 C7

[1] In this table ‘type’ reﬂects MUX pin function only. A pin may have other ‘type’ capabilities as noted in its

functional group.

[2] These pins are included in the XIO set. Refer to “PNX8526 User Manual, Chapter 8" for additional

functions.

[3] The ICAM1_SETVPP and ICAM1_C8 signals are automatically selected when the ICAM function is

selected. Refer to Table 17 (Offset 0x04 D600 IO_MUX_CTR). Selecting GPIO mode will disable this ICAM

functionality.

7. Functional description

Figure 3 shows a block diagram of a typical PNX8526-based system. The system shown

is a ‘stand-alone system’ which uses the internal MIPS host.

The PNX8526 runs on a single 27 MHz crystal from which all internal and external clocks

are derived by on-chip synthesizers. The PNX8526 boots directly from attached ﬂash

memory or ROM. If desired, custom boot methods can be programmed using the optional

I²C-bus boot EEPROM.

The PNX8526 has three digital video inputs that accept digitized analog video (ITU-656),

although only two ITU-656 streams can be processed simultaneously. Two of these inputs,

DV2 and DV3, can also accept scrambled transport streams.

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

The DV inputs support parallel transport stream formats. In addition, a single incoming

1394 transport stream is supported. Two selected transport streams can undergo internal

de-scrambling and decoding.

Based on the system implementation, one or both transport streams may pass through

Point Of Deployment (POD) or Common Interface (CI) conditional access modules before

transfer into the PNX8526. Either a single companion IC, such as the SCM microsystems

CIMaX, or two CIMaX chips can be used. In the latter case, it is possible to handle dual

decoding no matter which conditional access system is used.

The PNX8526 contains on-chip DVB, MULTI2 and DES hardware de-scramblers, as well

as an ICAM veriﬁer. The entitlement system for these de-scramblers is provided via two

smart card interfaces.

The TM32 CPU does further processing on the result of the transport stream

demultiplexing.

For MPEG-2 video, a slice level HL MPEG-2 video decoder performs the majority of the

MPEG-2 algorithm. This MPEG decoder is capable of full-resolution decoding. The

TM32 CPU does all MPEG-2 processing above the slice level. Two simultaneous SD

streams or one HD stream may be processed.

All audio processing is done by the TM32 CPU. Compressed audio will be present in

memory from either the transport stream de-multiplex or from the SPDIF input port. The

SPDIF input port is intended primarily for DTV applications where a SPDIF source is

available from an external source device, such as a DVD player. PCM (stereo sample)

audio is present in memory from the I²S-bus input ports or SPDIF input. Two AC-3 (or

equivalent) compressed audio streams may be decoded simultaneously. The TM32 CPU

may also process effects, enhancements and mix the audio data. Multi-channel

compressed audio or down-mixed stereo PCM audio is transmitted over the SPDIF output

interface. Multi-channel audio samples are Dolby Pro Logic down-mixed into the two

stereo I²S-bus interfaces to the PNX8510 companion IC. In addition to the two I²S-bus

inputs and two I²S-bus outputs, a bidirectional I²S-bus interface is provided. This allows

connection of other audio inputs or outputs - headphones, for example. Note that there is

not enough compute power to support encoding of multi-channel compressed audio

simultaneous with video processing. So the multi-channel compressed audio transmitted

over SPDIF must be from one of the original compressed sources.

Graphics rendering may be accomplished with the MIPS or the TM32 CPU by utilizing the

2D drawing and DMA engine. This engine can perform fast area ﬁlls, 3-operand bitblt,

monochrome data expansion, and lines. It can also be used as a generic DMA engine to

transfer data between memory locations on a byte-aligned basis. An alpha bitblt capability

is also provided to allow for anti-aliased text and lines as well as source/destination

blending operations.

Once all video and graphics data for speciﬁc ﬁelds or frames has been generated in

memory, the video display pipeline starts processing those images for display. The video

processing functions include 6-tap horizontal/vertical scaling, anti-ﬂicker ﬁltering, and

de-interlacing (when progressive output is required). The processed images are then

combined for each output. Up to four surfaces of any supported format may be combined

to produce the primary display output. Up to two surfaces are combined to produce the

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

secondary output. Compositing of more surfaces for future video algorithms is possible by

using the TM32 CPU and/or the memory based scaler prior to invoking the

compositing/display engine. This is subject to CPU and memory bandwidth availability.

The PNX8526 contains a 1394 interface with 5C copy protection. The PNX8526 1394 can

simultaneously transmit two transport streams while receiving one transport stream. The

transmitted streams can be partial transport streams (created by PID ﬁltering of an input)

or one of the two streams can be software generated. In the case of receiving a scrambled

1394 transport stream input, the stream can either use the on-chip de-scramblers, or may

be routed to the external companion CA IC for de-scrambling by the POD/CI CA

module(s).

The PNX8526 contains a variety of peripheral interfaces to support both ASTB and DTV

requirements. There are two smart card interfaces, two USB ports, two I²C-bus ports, one

IrDA data UART and two general purpose UARTs, one of which (UART3) is multiplexed

with an SSI interface for soft modem support. The PNX8526 also contains an integrated

IDE controller, which only requires an external isolation buffer to implement a full disk

interface with sustained speeds up to 10 MB/s. A third-party PCI SuperI/O chip may be

utilized to provide peripheral functionality not contained on the PNX8526. Functions such

as IEEE-1284, 10/100 Ethernet, ﬂoppy drive support, UDMA66 IDE controllers and others

are currently available in low-cost, commercially-available parts.

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

to digital VCR

to HDTV set

from external tuner

16/32/64 MB

SDRAM

IEEE 1394

PHY

64-bit

10

3

1

1394

TS (output)

transport stream

DV_OUT1

DV_OUT2

I2S_OUT1

I2S_OUT2

I2C-2

RGB or Y/C

CVBS

1

OOB in

Y

POD-1/

PNX8510

C (CVBS)

NRSS-B/CI

CA

INTERFACE

IC

2

OOB out

DV3 (656/TS in)

A1 R/L

A2 R/L

POD-2/

NRSS-B/CI

2

I C-bus

5

GPIO

PNX8526

27 MHz

transport stream

ANALOG

FRONT-END

OR MODEM

SSI/UART3

PSTN

analog

711X

DV2 (656/TS in)

video

1

transport stream

SPDIF out

SPDIFOUT

I2S I/O

2

I S-bus

analog

711X

auxiliary audio

DV1 (656 in)

video

> = 12

s/w I/O pins

GPIO

stereo audio (2×)

SPDIF in

I2S_IN1/2

SPDIFIN

GPIO

2

I C-bus

I2C-1

IR remote

USB (2×)

UART2

IrDA data (UART1)

OPTIONAL

BOOT

EEPROM

SC1 & SC2

smart card (2×)

TDA8004

XIO_SEL0

PCI-XIO8 expansion bus

DOCSIS

MODEM

PCI SUPER I/O

BUFFER

FLASH

mce541

IDE

LAN

1284

IDE

UDMA66

10 MB/s

Fig 3. PNX8526-based system block diagram

8. I/O multiplexer control register

The I/O multiplexer control register is used to conﬁgure the multifunction pins to alternate

functions as described in Table 16. Control is achieved via the global 2 register

IO_MUX_CTRL Table 17.

Table 17: Global 2 registers

Bit Symbol

Access Value

Description

0x04 D600 IO_MUX_CTRL

31, 15 not used

ignore during writes and read as zeros

I2S_IO audio mode

14

AIO_MUX_SEL

R/W

select I2S_IO as audio output

select I2S_IO as audio input

0

1

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 17: Global 2 registers …continued

Bit

Symbol

Access Value

Description

13

SSI_SEL

R/W

0

SSI or UART3 mode:

select UART3

select SSI

1

12

RGB24_SEL

R/W

audio Out2 or RGB mode:

select audio Out2

0

1

1select RGB (DV_OUT [23:20])

ICAM or smart card2 mode:

smart card1 module ports go to smart card2 pins

smart card2 module ports go to smart card2 pins

ICAM1 module ports go to smart card2 pins

ICAM2 module ports go to smart card2 pins

ICAM or smart card2 mode:

smart card1 module ports go to smart card1 pins

smart card2 module ports go to smart card1 pins

ICAM1 module ports go to smart card1 pins

ICAM2 module ports go to smart card1 pins

ignore during writes and read as zeroes

VIP2 module selection:

11:10 SMCRD2_MUX_CTRL[1:0] R/W

00

01

10

11

9:8

SMCRD1_MUX_CTRL[1:0] R/W

00

01

10

11

-

7

not used

6:4

VIP2_MUX_CTRL[2:0]

R/W

000

001

010

011

100

-

VIP data from DV1 port

VIP data from DV2 port

VIP data from DV3 port

VIP data from DV_OUT1 (AICP1) port

1394 data from link core

3

not used

ignore during writes and read as zeroes

VIP1 module selection:

2:0

VIP1_MUX_CTRL[2:0]

R/W

VIP data from DV1 port

000

001

010

011

100

VIP data from DV2 port

VIP data from DV3 port

VIP data from DV_OUT2 (AICP2) port

1394 data from link core

9. Power supply sequencing

Power application and power removal should obey the following rules:

9.1 Power-on sequence

• Apply power to V_DDC(1.26 V)

• Allow V_DDC(1.26 V) to stabilize (approximately 100 ms recommended)

• Apply power to V_DD(3.3 V).

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

9.2 Power-off sequence

• Power may be removed from V_DD(3.3 V) and V_DDC(1.26 V) at the same time

• Otherwise remove power from V_DD(3.3 V) followed by V_DDC(1.26 V).

10. Limiting values

Table 18: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

3.0

Max

3.6

Unit

V

V_DD

V_DDC

V_I/O

I/O pad DC supply voltage

logic core supply voltage

voltage on

1.20

1.32

V

with respect to V_SS

3 V I/O pins

−0.5

1.46

V_DD+ 0.5 V

5 V tolerant I/O pins

+5.5

1.76

V

V_I(th)

voltage on I/O pins with non

Schmitt trigger input voltage

threshold

V_IL(ST)

LOW-level input voltage

threshold on I/O pins with

Schmitt trigger input

0.93

1.66

-

1.06

1.79

10

V

V_IH(ST)

HIGH-level input voltage

threshold on I/O pins with

Schmitt trigger input

V_trt

transient voltages on I/O

pins

P_tot

total power dissipation

dynamic

-

2

W

static

AICP off

-

1

W

T_amb

T_stg

T_j

ambient temperature

storage temperature

junction temperature

0

70

°C

kV

−40

+125

100

± 1.5

-

V_esd

electrostatic discharge

voltage

human body model

11. Thermal characteristics

PNX8526 can be used in different environments creating different junction temperatures.

The thermal resistance from junction to ambient (R_th(j-a)) of the PNX8526 in its HBGA456

package is approximately 11.7 K/W. This value is achieved using natural convection, no

external heatsink and using a JEDEC-deﬁned printed-circuit board with high thermal

conduction (see “JEDEC standards 51-2 and 51-7” for details).

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

43 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Given the power dissipation of the PNX8526 and the ambient temperature inside the

enclosure, the expected junction temperature can be calculated using the following

equation:

T_j= T_amb+ P × R_th(j-a)

(1)

In some applications the junction temperature may be judged too high, reducing the

acceptable lifetime (see Section 13.2). However cooling can be improved by ﬁtting an

additional external heatsink, or increasing the airﬂow around the device. Table 19 shows

the improvements that can be expected if these measures are taken.

Table 19: PNX8526 thermal data

Heatsink size = 37 mm × 37 mm × 10 mm.

PNX8526

Thermal resistance R_th(j-a)(K/W)

Airﬂow

0 m/s

1 m/s

10.0

7.6

2 m/s

8.5

Standard

11.7

With external heatsink 9.5

6.3

12. Characteristics

The characteristics listed in the following tables apply to standard operating conditions,

unless otherwise noted. All voltages are referenced to V_SS(0 V, ground). Positive current

ﬂows into the referenced pin. The standard operating voltage range is V_DD= 3.3 V ± 0.3 V

and V_DDC= 1.26 V ± 0.06 V. All digital input/output pins are 3.3 V tolerant.

In all cases described below, digital V_DD= 3.3 V ± 5 % and ambient temperature is 0 °C to

70 °C.

All AC timings are based on a 30 pF test load and are measured at a 1.6 V threshold (see

Figure 4). Actual input/output voltage threshold is dependent on pad type, for example,

Schmitt trigger input (see Section 6.1).

2.4 V

1.6 V

0.8 V

mce542

Fig 4. General AC characteristics

The AC voltage characteristics for active signal pins of the controller are listed in Table 20.

Signal names for the PCI bus conﬁguration are listed, as well as the minimum and

maximum voltage, current, and capacitance for each pin.

Table 20: Digital AC/DC characteristics

V_DD= 3.3 V ± 5 %; T_amb= 0 °C to 70 °C; unless otherwise speciﬁed.

[1]

Symbol Parameter

Conditions

Min

−0.5

2.4

0

Typ

Max

Unit

V_IL

LOW-level input voltage

-

+0.8

V

V_IH

V_OL

HIGH-level input voltage

LOW-level output voltage

V_DD+ 0.5 V

0.4

V

9397 750 15101

Product data sheet

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 20: Digital AC/DC characteristics …continued

V_DD= 3.3 V ± 5 %; T_amb= 0 °C to 70 °C; unless otherwise speciﬁed.

[1]

Symbol Parameter

Conditions

Min

Typ

Max

-

Unit

V

V_OH

I_OL1

I_OH1

HIGH-level output voltage

2.4

-

[2]

LOW-level output current 1

-

5

mA

HIGH-level output

current 1

−5

[3]

I_OL2

I_OH2

LOW-level output current 2

-

8

mA

HIGH-level output

current 2

−8

[4]

I_OL3

I_OH3

LOW-level output current 3

-

12

mA

HIGH-level output

current 3

−12

[5]

I_OL4

I_OH4

LOW-level output current 4

-

14

mA

HIGH-level output

current 4

−14

I_OZ

3-state output leakage

current

-

41

µA

C_in

input capacitance

-

3.5

1.5

0.2

pF

A

I_DD(core)supply current; core

0.9

0.13

I_DD(periph)supply current; peripherals

A

[1] The pin names used in the following notes are the primary names for PCI conﬁgurations. Output signals

multiplexed on some pins have the same drive level.

[2] l_OL1(5 mA); l_OH1(−5 mA):

I2S_IN1_SCK, I2S_IN1_WS, I2S_IN2_SCK, I2S_IN2_WS, I2S_OUT1_SCK, I2S_OUT1_WS,

I2S_OUT1_SD, I2S_OUT2_SD, DV1_DATA[9:0], DV1_VALID, DV1_CLK, DBG_TDO, JTAG_TDO, XTALO,

UA1_TX, UA1_RX, UA2_TX, UA2_RX, UA2_RTS, UA2_CTS, SC1_DA, SC1_CMD, SC1_RST,

SC1_SCCK, SC2_DA, SC2_CMD, SC2_RST, SC2_SCCK, SSI_SCLK_CTSN, SSI_FS_RTSN, SSI_RXD,

SSI_TX, USB_DM[1:0], USB_DP[1:0], USB_PWR.

[3] I_OL2(8 mA); I_OH2(−8 mA):

DV_OUT1[9:0], DV_OUT2[9:0], DV_CLK1, DV_CLK2, HSYNC, VSYNC, I2S_IN1_OSCLK,

I2S_IN2_OSCLK, I2S_IO_OSCLK, I2S_IO_SCK, I2S_IO_WS, I2S_IO_SD[3:0], I2S_OUT1_OSCLK,

I2S_OUT2_OSCLK, I2S_OUT2_SCK, I2S_OUT2_WS, TS_DATA[7:0], TS_SOP, TS_VALID, TS_CLK,

PHY_D[7:0], PHY_CTL[1:0], PHY_LREQ, MD[63:0], MDQM[7:0], MCKE, I2C1_SCL, I2C1_SDA,

I2C2_SCL, I2C2_SDA, GPIO[11:0], SYS_RSTN_OUT, XIO_SEL[2:0], XIO_ACK, XIO_AD25.

[4] I_OL3(12 mA); I_OH3(−12 mA):

PCI_AD[31:0], PCI_CBE[3:0], PCI_DEVSEL, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_STOP, PCI_PERR,

PCI_PAR, PCI_INTA, PCI_REQ, PCI_GNT, PCI_REQ_A, PCI_REQ_B, PCI_GNT_A, PCI_GNT_B,

PCI_SERR,MWE, PLL_OUT.

[5] I_OL4(14 mA); I_OH4(−14 mA):

SPDIF_OUT, MCLK[1:0], MA[11:0], MBA[1:0], MCS, MRAS, MCAS.

9397 750 15101

Product data sheet

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

12.1 Reset timing

t

LOW

RESET_IN

mce543

Fig 5. Reset timing

Table 21: Reset timing

Symbol Parameter

Conditions

Min

Typ

Max Unit

- µs

t_LOW

RESET_IN active pulse width after stable power

400

-

12.2 Peripheral Controller Interface (PCI) timing

For additional timing diagram information on XIO and IDE interfaces see “PNX8526 User

Manual, Chapter 8".

PCI CLOCK

t

su

h

PCI-XIO

INPUTS

t

OD(max)

t

OD(min)

PCI-XIO

OUTPUTS

mce544

Fig 6. PCI timing

Table 22: PCI input timing (with reference to PCI clock)

Symbol Parameter Conditions

t_susetup time on pins

Min

Typ

Max

Unit

PCI_AD[31:0], PCI_CBE[3:0],

PCI_FRAME, PCI_IRDY

7

-

ns

PCI_GNT

10

t_h

hold time on pins

PCI_AD[31:0]

0

-

ns

PCI_CBE[3:0], PCI_FRAME,

PCI_IRDY, PCI_IDSEL

PCI_GNT

0

-

ns

9397 750 15101

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 23: PCI output valid timing (with reference to PCI clock)

Symbol Parameter

t_OD(min)minimum output delay on pins

PCI_AD[31:0], PCI_CBE[3:0]

PCI_DEVSEL, PCI_PAR

PCI_STOP

Conditions

Min

Typ

Max

Unit

[1]

2

-

ns

PCI_TRDY

[2]

t_OD(max)maximum output delay on pins

PCI_AD[31:0], PCI_CBE[3:0]

PCI_DEVSEL, PCI_PAR

PCI_STOP

-

11

12

ns

PCI_TRDY

PCI_REQ

[1] Minimum delay is the minimum time after the clock edge that a valid signal state from the previous cycle will

begin transition to the next state (become invalid).

[2] Maximum delay is the maximum time after the clock edge that a signal state is valid for the next cycle.

12.3 Main Memory Interface (MMI) timing

f

MCLK

t

clk(H)

clk(L)

MMI CLK

t

ch

cs

MMI control

and address

valid

MMI DATA

t

dhi, dho

dsi, dso

mce545

Fig 7. MMI timing

Table 24: MMI timing (with reference to MCLK)

Symbol Parameter

Conditions

Min

1.5

0.8

1.5

0.8

0

Typ

Max Unit

t_cs

CS setup time

-

ns

t_ch

CS hold time

t_dso

t_dho

t_dsi

t_dhi

data output setup time

data output hold time

data input setup time

data input hold time

write cycle

read cycle

2.0

9397 750 15101

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 24: MMI timing (with reference to MCLK) …continued

Symbol Parameter Conditions

Min

2.9

Typ

Max Unit

t_clk(L)

t_clk(H)

f_MCLK

clock LOW time

-

ns

clock HIGH time

-

ns

memory clock frequency (MCLK[1:0])

166

MHz

12.4 GPIO timing

GPIO

1.5 V

t

MIN

001aad371

Fig 8. GPIO timing

Table 25: GPIO timing

Symbol Parameter

Conditions

Min

Typ

Max

Unit

[1]

t_MIN

pulse width

GPIO as input

GPIO as output

10

75

-

ns

[1] If GPIO is to be time-stamped, the minimum pulse width is 75 ns.

12.5 UART timing

UART TX/RX

RTSN/CTSN

1.5 V

t

MIN

001aad372

Fig 9. UART timing

Table 26: UART output timing (with reference to UART clock)

Symbol Parameter

t_MINpulse width

Conditions

UART TX

Min

4.3

Typ

Max

Unit

µs

[1]

-

UART RX

µs

UART RTSN

UART CTSN

µs

[1] Maximum baud rate: 230 kBd.

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PNX8526

Philips Semiconductors

12.6 SSI timing

Programmable source decoder with integrated peripherials

t

clk(H)

clk(L)

SSI_SCLK

t

cs

ch

CONTROL

DATA

valid

t

dhi, dho

dsi, dso

mce548

Fig 10. SSI timing

Table 27: SSI timing (with reference to MCLK)

Symbol Parameter

Conditions

Min

Typ

Max Unit

t_cs

CS setup time

3

-

ns

t_ch

CS hold time

2

t_dso

t_dho

t_dsi

data output setup time

data output hold time

data input setup time

data input hold time

clock LOW time

3

2

1.0

25

t_dhi

t_clk(L)

t_clk(H)

clock HIGH time

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

12.7 I²C-bus timing

t

LOW

HIGH

SCL

t

h(STA)

su(STA)

SDA

SCL

t

dv(STO)

h(SDA)

t

su(SDA)

dv(SDA)

SDA

valid

mce549

Fig 11. I²C-bus timing

Table 28: I²C-bus timing

Symbol

f_SCL

Parameter

Conditions

Min

Typ

Max

Unit

kHz

µs

SCL clock frequency

-

400

t_su(STA)

t_h(STA)

t_LOW

start condition setup time

start condition hold time

SCL LOW time

1

-

1

-

µs

1

-

µs

t_HIGH

SCL HIGH time

1

-

µs

t_su(SDA)

t_h(SDA)

t_dv(SDA)

t_dv(STO)

data setup time

100

0

100

0

-

ns

data hold time

-

ns

SCL LOW to data out valid

SCL HIGH to data out

-

0.5

-

µs

1

µs

12.8 IEEE 1394 Phy-Link interface

f

1394

CLK_1394

t

h

su

1394 link

input port

t

p

1394 link

output port

mce550

Fig 12. IEEE 1394 Phy-Link interface timing

Rev. 02 — 11 July 2005

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Product data sheet

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 29: IEEE 1394 Phy-Link interface signals

Symbol Parameter

f₁₃₉₄CLK_1394 frequency

t_su

Conditions

Min

Typ Max

Unit

49.147 -

49.157 MHz

setup time for 1394 link

input port

PHY_D[7:0];

PHY_CTL[1:0]

6

-

ns

t_h

t_p

input hold time

0

-

ns

output propagation delay PHY_D[9:0]; PHY_LREQ;

for 1394 link output port PHY_CTL[1:0]

9

12.9 I²S-bus audio input and output timing

f

Al_SCK

t

su(CLK)

h(CLK)

Al_SD

Al_WS

valid

t

ws(SCK)

valid

Al_WS

mce551

Fig 13. I²S-bus audio input timing

Table 30: I²S-bus audio input

Timing is with respect to the SCK clock edge. The PNX8526 is the source of AI_WS.

Symbol Parameter

Conditions

Min

Typ

Max Unit

f_{AI_SCK}

audio-in clock AI_SCK frequency

-

20

-

MHz

ns

t_su(CLK)audio-in to AI_SCK setup time

audio interface

as slave

3

t_h(CLK)

audio-in from AI_SCK hold time

audio interface

as slave

2

-

ns

t_ws(SCK)audio-in clock AI_SCK to audio-in

word-select AI_WS valid

10

9397 750 15101

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

AO_SCK

t

dv(SCK)

AO_SD

AO_WS

valid

t

ws(SCK)

mce552

Fig 14. I²S-bus audio output timing

Table 31: I²S-bus audio output

Symbol Parameter

Conditions

Min

Typ

Max Unit

f_{AO_SCK}audio-out clock AO_SCK frequency

-

20

-

MHz

ns

t_dv(SCK)audio-out clock AO_SCK to

audio-out data AO_SD valid

2

t_ws(SCK)audio-out clock AO_SCK to

audio-out word-select AO_WS valid

-

10

ns

12.10 SPDIF timing

t

HIGH

t

LOW

mce553

Fig 15. SPDIF clock

Table 32: SPDIF timing

Symbol Parameter

Conditions

Min

Typ

5.2

Max

Unit

t_HIGH

t_LOW

clock HIGH time (PCI)

clock LOW time (PCI)

-

µs

9397 750 15101

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

12.11 Digital video output (DV_OUT) timing

DV_CLK

t

h(CLK)

su(CLK)

HSYNC

VSYNC

BLANK

valid

t

dv(CLK)

DV_OUT

(Data)

valid

mce554

Fig 16. DV_OUT timing

Table 33: DV_OUT timing

Symbol Parameter

Conditions

Min

Typ

Max

Unit

[1]

f_{DV_CLK}

t_dv(CLK)

t_su(CLK)

t_h(CLK)

video out clock DV_CLK

frequency

27

-

MHz

video out clock DV_CLK to

video out DV_OUT valid

−3.7

3

0

-

ns

VSYNC to DV_CLK setup DV_CLK as input

time

CRT control from DV_CLK

HSYNC, VSYNC, BLANK

hold time

0

-

[1] DV_CLK period is programmable via the internal PLL.

12.12 Digital video input (DV Input) timing

f

DVB

CLOCK

1.5 V

t

h

su

INPUTS

(DATA, SOP,

1.5 V

ERROR, VALID)

001aad295

Fig 17. DV input timing

Table 34: DV input timing (referenced to input video clock)

Symbol Parameter Conditions

f_DVBDVB clock frequency

t_su

Min

Typ

Max

Units

MHz

ns

-

27

-

input data setup time

input data hold time

3

t_h

-

ns

9397 750 15101

Product data sheet

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PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

12.13 Transport Stream Output (TSO) timing

CLOCK

t

h

su

OUTPUT

(DATA, SOP,

VALID)

mce556

Fig 18. TSO timing

Table 35: TSO timing

Symbol Parameter

Conditions

Min

Typ

Max

Unit

ns

t_su

t_h

data setup time

data hold time

3

0

-

ns

9397 750 15101

Product data sheet

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54 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

13. Application information

13.1 Differences between PNX8525 and PNX8526

There are a number of differences between the PNX8525 and the PNX8526 with respect

to the physical interfacing of the device. These differences are described in Table 36.

Table 36: Differences between PNX8525 and PNX8526

PNX8525

PNX8526

Core supply voltage

1.8 V ± 5 %

1.26 V ± 0.06 V

I²C-bus pads

GPIO pads with Schmitt trigger and pull-ups

Special I²C-bus pads designed to meet the

I²C-bus speciﬁcation

IEEE-1394 pads

GPIO pads with Schmitt trigger and pull-ups

Special IEEE-1394 pads designed to meet the

IEEE-1394 link to Phy speciﬁcation

PCI interface

Supports 5 V tolerant interface with 3.3 V

signalling

No 5 V tolerant interface, all signals limited to

3.3 V

System reset output (SYS_RSTN_OUT)

Drive capability 12 mA

Drive capability 8 mA

Drive capability 14 mA

Clock output (PLL_OUT)

Drive capability 12 mA

SPDIF output

Drive capability 16 mA

DV1 port, SSI, UART2, smart card1 and smart card2

Drive capability 4 mA

Drive capability 5 mA, INputs support hysteresis

I²S-bus CLK and WS

Drive capability 4 mA

Drive capability 5 mA

TS interface and I²S-bus data lines

Hysteresis on inputs not supported

SDRAM interface

Hysteresis on inputs supported

Supports 5 V tolerant signalling, with 3.3 V

drive. (AD[11:0], CLK[1:0], RAS,CAS, CS and

BA[1:0] drive capability 16 mA)

No 5 V tolerant signalling. Drive capability 14

mA

XIO SEL[2:0], ACK, A25

Drive capability 12 mA

Peripheral power supply

Drive capability 8 mA

Single connection on PCB for all V_DDbond pads Requires separation of V_DDCinto

three segments, each segment ﬁltered and star

connected back to source^[1]

Core power supply

Single connection on PCB for all V_DDCbond

pads

Requires separation of V_DDCinto two segments,

each segment ﬁltered and star connected back

to source^[2]

9397 750 15101

Product data sheet

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55 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

[1] The new connections are:

a) V_DD1- the input/output supply connection

b) V_DD2- analog clock generation unit; Custom Analog Block (CAB)

c) V_DD3- Trimedia clock generation PLL.

[2] The new connections are:

a) V_DDC1- main core supply connection

b) V_DDC2- 1.728GHz PLL supply connection.

13.2 Lifetime versus temperature

The relationship between operating (junction) temperature and the expected lifetime of a

device is shown in Figure 19.

mgx461

25

useful

life

(years)

20

15

10

5

0

100

105

110

115

120

125

T (°C)

j

Useful life (years) as a function of junction temperature (°C); 1 % cumulative failures;

8 hours/day.

Fig 19. Lifetime dependency on temperature

As shown in Figure 19, at a junction temperature of 110 °C a 10 year lifetime can be

expected (at 8 hours per day). If the junction temperature is increased to 125 °C, the

lifetime can be reduced to 4 years. The junction temperature can be inﬂuenced by

following the guidelines given in Section 11.

9397 750 15101

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56 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

14. Package outline

HBGA456: plastic thermal enhanced ball grid array package; 456 balls;

body 35 x 35 x 1.8 mm; heatsink

SOT610-1

B

D

A

D

1

ball A1

index area

A

2

A

j

E

1

A

1

detail X

C

e

1

y

e

1/2 e

v M

C

1

b

A

B

w M

C

AF

AE

AD

AB

Y

AC

AA

W

U

e

V

T

R

P

e

2

N

M

K

L

1/2 e

J

H

G

E

F

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21 23 25

10 12 14 16 18 20 22 24 26

shape

optional (4x)

2

4

6

8

X

0

10

20 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

E

e

2

j

y

D

E

v

w

1

2

1

max.

0.7

0.5

1.90

1.65

0.9

0.6

35.2 30.75 35.2 30.75

34.8 29.75 34.8 29.75

26

22

mm

2.6

0.2

0.35

1.27 31.75 31.75

0.3

0.15

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

00-12-13

02-01-30

SOT610-1

144E

MS-034

- - -

Fig 20. Package outline SOT610-1 (HBGA456)

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

57 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

15. Soldering

15.1 Introduction

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering is often

preferred when through-hole and surface mount components are mixed on one

printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it

is not suitable for ﬁne pitch SMDs. In these situations reﬂow soldering is recommended.

Driven by legislation and environmental forces the worldwide use of lead-free solder

pastes is increasing.

15.2 Through-hole mount packages

15.2.1 Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

15.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

15.3 Surface mount packages

15.3.1 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

58 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

15.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

15.3.3 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

59 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

15.4 Package related soldering information

Table 37: Suitability of IC packages for wave, reﬂow and dipping soldering methods

Mounting

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

Dipping

Through-hole mount

CPGA, HCPGA

suitable

−

DBS, DIP, HDIP, RDBS, SDIP, SIL suitable^[3]

−

suitable

Through-hole-surface

mount

PMFP^[4]

not suitable

−

Surface mount

BGA, HTSSON..T^[5], LBGA,

not suitable

suitable

−

LFBGA, SQFP, SSOP..T^[5]

TFBGA, VFBGA, XSON

,

DHVQFN, HBCC, HBGA, HLQFP, not suitable^[6]

HSO, HSOP, HSQFP, HSSON,

HTQFP, HTSSOP, HVQFN,

HVSON, SMS

PLCC^[7], SO, SOJ

suitable

−

LQFP, QFP, TQFP

not recommended^{[7] [8]}

not recommended^[9]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[10], WQCCN..L^[10]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips

Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with

respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of

the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

[4] Hot bar soldering or manual soldering is suitable for PMFP packages.

[5] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no account be processed

through more than one soldering cycle or subjected to infrared reﬂow soldering with peak temperature exceeding 217 °C ± 10 °C

measured in the atmosphere of the reﬂow oven. The package body peak temperature must be kept as low as possible.

[6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate

between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the

heatsink surface.

[7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint

must incorporate solder thieves downstream and at the side corners.

[8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is deﬁnitely not suitable for

packages with a pitch (e) equal to or smaller than 0.65 mm.

[9] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is deﬁnitely

not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on ﬂex foil.

However, the image sensor package can be mounted by the client on a ﬂex foil by using a hot bar soldering process. The appropriate

soldering proﬁle can be provided on request.

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

60 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

16. Abbreviations

Table 38: Abbreviations

Acronym

2D

Description

two-dimensional

5C

5C digital copy protection technology

Audio Coding version 3

AC-3

ATSB

ATSC

AVIF

bitblt

CI

Advanced Set Top Box

Advanced Television Systems Committee

Audio and Video Interface

bit-block transfer of color data

Common Interface

CPU

CRT

Central Processor Unit

Cathode Ray Tube

DAC

Digital Analog Conversion

Data Encryption Standard

Direct Memory Allocation

Digital Video Broadcast

DES

DMA

DVB

DTV

Digital Television

DVD

Digital Video Disc

EEPROM

GPIO

HBGA

HD

Electrically Erasable Programmable Read Only Memory

General Purpose Input/Output

Heat slug Ball Grid Array

High Deﬁnition

I²C-bus

I²S-bus

IC

Inter Integrated Circuit bus

Inter Integrated Circuit Sound bus

Integrated Circuit

ICAM

IDE

Integrated Conditional Access Module

Integrated Drive Electronics

Institute of Electrical and Electronic Engineers

Joint Electronic Device Engineering Council

Million Instructions Per Second

Motion Picture Experts Group

Security standard for Japanese market

National TV Systems Committee

Operating System

IEEE

JEDEC

MIPS

MPEG

MULTI2

NTSC

OS

PAL

Phase Alternate Line

PCI

Peripheral Component Interconnect

Pulse Code Modulation

PCM

PID

Program Identiﬁer

PLL

Phase-Locked Loop

RGB

ROM

Red Green Blue

Read Only Memory

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

61 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

Table 38: Abbreviations …continued

Acronym

SD

Description

Standard Deﬁnition

SDRAM

SECAM

SPDIF

SSI

Synchronous Dynamic Random Access Memory

Systeme Electronique Couleur Avec Memoire

Sony Philips Digital Interface

Synchronous Serial Interface

Transport Stream Output

TSO

UART

USB

Universal Asynchronous Receiver Transmitter

Universal Serial Bus

VLIW

XIO

Very Long Instruction Word

Extended Input Output

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

62 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

17. Revision history

Table 39: Revision history

Document ID

PNX8526_2

Modiﬁcations:

Release date Data sheet status

20050711 Product data sheet

Change notice Doc. number

Supersedes

-

9397 750 15101 PNX8526_1

• Status changed to Product data sheet

• Editorial improvements made.

PNX8526_1

20040211

Preliminary data sheet

-

9397 750 11715

-

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

63 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

18. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

19. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

21. Trademarks

Notice — All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — wordmark and logo are trademarks of Koninklijke Philips

Electronics N.V.

TriMedia — is a trademark of Koninklijke Philips Electronics N.V.

Nexperia — is a trademark of Koninklijke Philips Electronics N.V.

20. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

22. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 15101

Product data sheet

Rev. 02 — 11 July 2005

64 of 65

PNX8526

Philips Semiconductors

Programmable source decoder with integrated peripherials

23. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

17

18

19

20

21

22

Revision history . . . . . . . . . . . . . . . . . . . . . . . 63

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 64

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Contact information . . . . . . . . . . . . . . . . . . . . 64

6

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

Multi-function pins. . . . . . . . . . . . . . . . . . . . . . 31

6.1

6.2

6.2.1

7

8

Functional description . . . . . . . . . . . . . . . . . . 38

I/O multiplexer control register. . . . . . . . . . . . 41

9

9.1

9.2

Power supply sequencing. . . . . . . . . . . . . . . . 42

Power-on sequence . . . . . . . . . . . . . . . . . . . . 42

Power-off sequence . . . . . . . . . . . . . . . . . . . . 43

10

11

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 43

Thermal characteristics. . . . . . . . . . . . . . . . . . 43

12

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 44

Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Peripheral Controller Interface (PCI) timing . . 46

Main Memory Interface (MMI) timing . . . . . . . 47

GPIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . 48

UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SSI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

I²C-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . 50

IEEE 1394 Phy-Link interface. . . . . . . . . . . . . 50

I²S-bus audio input and output timing. . . . . . . 51

SPDIF timing. . . . . . . . . . . . . . . . . . . . . . . . . . 52

Digital video output (DV_OUT) timing. . . . . . . 53

Digital video input (DV Input) timing . . . . . . . . 53

Transport Stream Output (TSO) timing. . . . . . 54

12.1

12.2

12.3

12.4

12.5

12.6

12.7

12.8

12.9

12.10

12.11

12.12

12.13

13

13.1

13.2

Application information. . . . . . . . . . . . . . . . . . 55

Differences between PNX8525 and PNX8526 55

Lifetime versus temperature . . . . . . . . . . . . . . 56

14

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 57

15

15.1

15.2

15.2.1

15.2.2

15.3

15.3.1

15.3.2

15.3.3

15.4

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Through-hole mount packages. . . . . . . . . . . . 58

Soldering by dipping or by solder wave . . . . . 58

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 58

Surface mount packages . . . . . . . . . . . . . . . . 58

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 58

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 59

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 59

Package related soldering information . . . . . . 60

16

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 61

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 11 July 2005

Document number: 9397 750 15101

Published in The Netherlands


型号：	PNX8526EH/M0
厂家：	NXP
描述：	IC SPECIALTY CONSUMER CIRCUIT, PBGA456, 35 X 35 MM, 1.8 MM HEIGHT, PLASTIC, MS-034, SOT610-1, HBGA-456, Consumer IC:Other 商用集成电路
文件：	总65页 (文件大小：269K)
中文：	中文翻译
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