PPC5676RDK2MVY1 [NXP]
MPC5676R Microcontroller Data Sheet;型号: | PPC5676RDK2MVY1 |
厂家: | NXP |
描述: | MPC5676R Microcontroller Data Sheet PC 微控制器 |
文件: | 总111页 (文件大小:2164K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5676R
Rev. 4, 16 Feb 2016
MPC5676R
MPC5676R Microcontroller
Data Sheet
TEPBGA–416
27 mm x 27 mm
TEPBGA–516
27mm x 27mm
On-chip modules available within the family include the
following features:
– Up to 96 eTPU2 channels (32 channels per eTPU2)
– total of 36 KB code RAM
– total of 9 KB parameter RAM
• Two identical dual issue, 32-bit CPU core complexes
(e200z7), each with
• Enhanced modular input output system supporting 32
unified channels (eMIOS) with each channel capable of
single action, double action, pulse width modulation
(PWM) and modulus counter operation
• Two enhanced queued analog-to-digital converter
(eQADC) modules with
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length
encoding (VLE), optional encoding of mixed 16-bit and
32-bit instructions, for code size footprint reduction
– Signal processing extension (SPE) instruction support
for digital signal processing (DSP)
– two separate analog converters per eQADC module
– support for a total of 64 analog input pins, expandable to
176 inputs with off-chip multiplexers
– Single-precision floating point operations (FPU)
– 16 KB I-Cache and 16 KB D-Cache
– Hardware cache coherency between cores
• 16 Hardware semaphores
• 3 channel CRC module
• 6MB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 384KB on-chip general-purpose SRAM including 48KB of
standby RAM
• Two multi-channel direct memory access controllers
(eDMA)
– one absolute reference ADC channel
– interface to twelve hardware decimation filters
– enhanced ‘Tap’ command to route any conversion to two
separate decimation filters
– Temperature sensor
• Five deserial serial peripheral interface (DSPI) modules
• Three enhanced serial communication interface (eSCI)
modules
• Four controller area network (FlexCAN) modules
• Dual-channel FlexRay controller
• Nexus development interface (NDI) per IEEE-ISTO
5001-2003 standard, with some support for 2010 standard.
• Device and board test support per Joint Test Action Group
(JTAG) (IEEE 1149.1)
• On-chip voltage regulator controller regulates supply
voltage down to 1.2 V for core logic
– 64 channels per eDMA
• Dual core Interrupt controller (INTC)
• Phase-locked loop with FM modulation (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters
• External Bus Interface (EBI) for calibration and
application development
• Self Test capability
• System integration unit (SIU) with error correction status
module (ECSM)
• Four protected port output pins (PPO)
• Boot assist module (BAM) supports serial bootload via
CAN or SCI
• Three second-generation enhanced time processor units
(eTPU2)
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2016. All rights reserved.
Table of Contents
1
2
3
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
4.7.2 I/O Pad VDD33 Current Specifications . . . . . . . 24
4.7.3 LVDS Pad Specifications . . . . . . . . . . . . . . . . . 25
4.8 Oscillator and FMPLL Electrical Characteristics . . . . . 27
4.9 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . 29
4.10 C90 Flash Memory Electrical Characteristics . . . . . . . 31
4.11 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.11.1 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . 32
4.11.2 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 33
4.12 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.12.1 Generic Timing Diagrams. . . . . . . . . . . . . . . . . 34
4.12.2 Reset and Configuration Pin Timing. . . . . . . . . 35
4.12.3 IEEE 1149.1 Interface Timing. . . . . . . . . . . . . . 36
4.12.4 Nexus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.12.5 External Bus Interface (EBI) Timing. . . . . . . . . 41
4.12.6 External Interrupt Timing (IRQ Pin) . . . . . . . . . 46
4.12.7 eTPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.12.8 eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.12.9 DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.1 416-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2 516-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
MPC5676R Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1 416-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .6
3.2 516-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .7
3.3 Pin Muxing and Reset States . . . . . . . . . . . . . . . . . . . . .8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2.1 General Notes for Specifications at
4
Maximum Junction Temperature . . . . . . . . . . . .11
4.3 EMI (Electromagnetic Interference) Characteristics . . .12
4.4 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.5 PMC/POR/LVI Electrical Specifications . . . . . . . . . . . .13
4.5.1 Regulator Example . . . . . . . . . . . . . . . . . . . . . .16
4.6 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . .18
4.6.1 Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.6.2 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.6.3 Power Sequencing and POR Dependent
5
6
on VDDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .20
4.7.1 I/O Pad Current Specifications . . . . . . . . . . . . .23
Appendix ASignal Properties and Muxing . . . . . . . . . . . . . . . . . . 59
Appendix BRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MPC5676R Microcontroller Data Sheet, Rev. 4
2
Freescale Semiconductor
Ordering Information
1
Ordering Information
1.1
Orderable Parts
Figure 1 and Table 1describe and list the orderable part numbers for the MPC5676R.
PC 5676R K2 M VU 1
R
M
D
Qualification status
Core code
Device number
(Optional) Dual-core identifier
Fab/Revision
Temperature range
Package identifier
Operating frequency
Tape and reel status
Temperature Range
M = –40 °C to 125 °C
Package Identifier
VU = 416 TEPBGA
Pb-Free
Operating Frequency Tape and Reel Status
1 = 2 x 180 MHz
R = Tape and reel
(blank) = Trays
VY = 516 TEPBGA
Pb-Free
Qualification Status
P = Pre qualification
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Note: Not all options are available on all devices. Refer to Table 1.
Figure 1. MPC5676R Orderable Part Number Description
Table 1. Orderable Part Numbers
Speed (MHz)2
Operating Temperature3
NXP Part Number1
SPC5676RDK2MVU1R
SPC5676RDK2MVY1R
Package Description
Nominal
Max4 (fMAX
)
Min (TL)
Max (TH)
MPC5676R 416 package
Lead-free (Pb-free)
180
184
–40 °C
125 °C
MPC5676R 516 package
Lead-free (Pb-free)
180
184
–40 °C
125 °C
1
All packaged devices are PPC5676R, rather than MPC5676R or SPC5676R, until product qualifications are complete. The
unpackaged device prefix is PCC, rather than SCC, until product qualification is complete.
Not all configurations are available in the PPC parts.
2
3
4
For the operating mode frequency of various blocks on the device, see Table 28.
The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH.
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
180 MHz parts allow for 180 MHz system clock + 2% FM.
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
3
MPC5676R Blocks
2
MPC5676R Blocks
2.1
Block Diagram
The following figure shows a top-level block diagram of the MPC5676R. The purpose of the block diagram is to show the
general interconnection of functional modules through the crossbar switch and from the Dual Interrupt Controller, and provide
an indication of the modules that connect to external pins. For clarity, the following modules are omitted from the diagram:
PMU, SWT, STM, PIT, ECSM, DTS, and CRC.
Power Architecture
e200z7 Core
Power Architecture
e200z7 Core
JTAG
MPC5676R
SPE
VLE
SPE
VLE
Nexus
IEEE-ISTO
5001-2003
Dual Interrupt
Controller
MMU
MMU
16K
16K
16K
16K
eDMA2
64 Channels
eDMA2
64 Channels
EBI
(Calibration)
FlexRay
I-Cache D-Cache
I-Cache D-Cache
Crossbar Switch
MPU
384KB
I/O
BridgeA
I/O
BridgeB
Boot Assist
Module
6MB
FLASH
FMPLL
STCU
SIUA
SRAM
Semaphores
(48KB S/B)
eQADC eQADC
6KB
Data
RAM
3KB
Data
RAM
SIUB
12 x DECFILT
eMIOS
32
eTPU2
32
eTPU2
32
Channel
eTPU2
32
Channel
Channel Channel
24KB
Code
RAM
12KB
Code
RAM
PPO
AMux
LEGEND
I-Cache – Instruction Cache
ADC
– Analog to Digital Convertor
AMux – Analog Pin Multiplexer
D-Cache– Data Cache
DECFILT– Decimation Filter
DSPI
EBI
eDMA2 – Enhanced Direct Memory Access controller version 2
eMIOS – Enhanced Modular I/O System
eQADC – Enhanced Queued Analog to Digital Converter
IRC
– Internal RC Oscillator
JTAG
MMU
MPU
PPO
S/B
– Joint Test Action Group controller
– Memory Management Unit
– Memory Protection Unit
– Protected Port Output
– Stand-by
– Deserial/Serial Peripheral Interface
– External Bus Interface
SIUA
SIUB
SPE
– System Integration Unit A
– System Integration Unit B
– Signal Processing Engine
eSCI
– Enhanced Serial Communications Interface
eTPU2 – Enhanced Time Processing Unit version 2
FlexCAN– Flexible Controller Area Network controller
FMPLL – Frequency Modulated Phase Lock Loop clock generator
SRAM – Static RAM
STCU – Self Test Control Unit
VLE
– Variable Length instruction Encoding
Figure 2. MPC5676R Block Diagram
MPC5676R Microcontroller Data Sheet, Rev. 4
4
Freescale Semiconductor
Pin Assignments
3
Pin Assignments
3.1
416-ball TEPBGA Pin Assignments
Figure 3 shows the 416-ball TEPBGA pin assignments.
CAUTION
This ball map is preliminary and subject to change. Do not use it for board design.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
REF–
REF–
ANA4
ANA8
ANA11
ANA15 VDDA_A0
VRL_A VRH_A
AN28
AN32
AN36 VDDA_B0
AN33 VDDA_B1
VRL_B VRH_B
ANB7
ANB11
ANB14 ANB17 ANB21 ANB23
VSS
A
B
VSS
VDD
RSTOUT ANA0
A
BYPCA1
BYPCB1
REF–
AN24
REF–
ANB6
ANA14 VDDA_A1 VSSA_A1
AN27
AN26
AN25
AN29
AN30
AN31
ANB8
ANB5
ANB9
ANB10 ANB15 ANB18 ANB22
VSS
TCRCLKC
VDDEH1
VSS
VDD
TEST
VDD
ANA1
ANA2
VDD
ANA5
ANA6
ANA3
ANA10
ANA9
ANA7
VSSA_B0
AN38
B
BYPCA
BYPCB
ANA13 ANA17 ANA19 ANA21 ANA23
ANA12 ANA16 ANA18 ANA20 ANA22
AN34
AN35
AN37
AN39
ANB0
ANB2
ANB4
ANB3
ANB12 ANB16 ANB19
VSS
ETPUC0 ETPUC1
ETPUC2 ETPUC3
C
D
E
ETPUA30 ETPUA31 VSS
C
ANB1
ANB13 ANB20
VSS
VDDEH7
ETPUA27 ETPUA28 ETPUA29 VSS
ETPUA23 ETPUA24 ETPUA25 ETPUA26
ETPUA19 ETPUA20 ETPUA21 ETPUA22
ETPUA15 ETPUA16 ETPUA17 ETPUA18
ETPUA11 ETPUA12 ETPUA14 ETPUA13
ETPUA7 ETPUA8 ETPUA9 ETPUA10
ETPUA3 ETPUA4 ETPUA5 ETPUA6
TCRCLKA ETPUA0 ETPUA1 ETPUA2
D
VDDEH7 ETPUC4 ETPUC5 ETPUC6
ETPUC7 ETPUC8 ETPUC9 ETPUC10
ETPUC11 ETPUC12 ETPUC13 ETPUC14
ETPUC15 ETPUC16 ETPUC17 ETPUC18
ETPUC19 ETPUC20 ETPUC21ETPUC22
ETPUC23 ETPUC24ETPUC25ETPUC26
ETPUC27ETPUC28ETPUC29ETPUC30
ETPUC31ETPUB15 ETPUB14 VDDEH7
VDDEH6 ETPUB11 ETPUB12 ETPUB13
ETPUB7 ETPUB8 ETPUB9 ETPUB10
ETPUB3 ETPUB4 ETPUB5 ETPUB6
TCRCLKB ETPUB0 ETPUB1 ETPUB2
ETPUB19 ETPUB18 ETPUB17 ETPUB16
ETPUB26 ETPUB22 ETPUB21 ETPUB20
REGSEL ETPUB25 ETPUB24 ETPUB23
ETPUB29 ETPUB28 ETPUB27 REGCTL
VDD33_3 ETPUB30 VDDREG VSSSYN
E
F
F
MPC5676R 416-ball TEPBGA
(as viewed from top through the package)
G
H
J
G
H
J
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
K
L
L
VDD33_1 TXDA
RXDA
VSTBY
VSS
M
N
P
M
N
BOOT–
RXDB
VDDE2
WKPCFG VDD
CFG1
VDDE2 VDDE2
VDDE2 VDDE2
TXDB
PLLCFG2 VDDEH1
P
PLLCFG1
JCOMP RESET PLLCFG0 RDY
R
T
R
VDDE2 MCKO MSEO1
EVTO MSEO0 MDO0
EVTI
MDO1
MDO5
VDDE2 VDDE2 VDDE2
VDDE2 VDDE2 VDDE2
T
U
V
U
MDO2
MDO6
MDO3
MDO7
MDO4
V
MDO8 VDDE2
W
Y
W
Y
MDO9 MDO10 MDO11 MDO15
MDO12 MDO13 MDO14 VDD33_2
AA
AB
AA
AB
AC
AD
AE
AF
VSSFL
TDO
TCK
TDI
TMS
VDD
VSS
VDD
VSS
VDD ETPUB31
EXTAL
PCSA1 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4
VDD
EMIOS8 EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1
VSS
VDD
VSS
VDDEH6 XTAL
VDD VDDSYN
AC VDDE2
VDDE2
FR_A_ FR_B_
TX TX
EMIOS5 EMIOS9 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30
RXDC
SINC
PCSC3
AD ENGCLK VDD
PCSA5 SOUTA
SCKA
SCKB
PCSB0 PCSB3 EMIOS2
CNTXB CNTXD
SCKC
FR_A_ FR_B_
RX RX
PCSA4 PCSA0 PCSA3
SINB
EMIOS0 EMIOS3 EMIOS6 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0
PCSC2 PCSC5
VSS
VDD
AE
AF
VDD
VSS
FR_A_ FR_B_
TX_EN TX_EN
EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28
VDDEH4 TXDC
PCSC4 VDDEH5
VSS
26
VSS
1
VDDE2
2
VDDEH3 PCSB5
SINA
7
PCSB2 SOUTB EMIOS1 EMIOS4
10 11
CNTXA CNTXC SOUTC
19 20 21
3
4
5
6
8
9
12
13
14
15
16
17
18
22
23
24
25
Figure 3. MPC5676R 416-ball TEPBGA (full diagram)
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
5
Pin Assignments
3.2
516-ball TEPBGA Pin Assignments
Figure 4 shows the 516-ball TEPBGA pin assignments.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
REF–
REF–
A
B
C
D
E
F
VDD
RSTOUT ANA0
ANA4
ANA9
ANA11
ANA15 VDDA_A0
VRL_A VRH_A
AN28
AN29
AN36 VDDA_B0
VRL_B VRH_B
ANB5
ANB9
ANB12 ANB18 ANB21
VSS
A
B
C
D
E
F
BYPCA1
BYPCB1
REF–
AN24
REF–
ANB4
VDDEH1
VSS
VDD
TEST
VDD
ANA1
ANA2
VDD
ANA5
ANA6
ANA3
VDD
ANA10 ANA14 VDDA_A1 VSSA_A1
AN27
AN25
AN26
VSS
AN30
AN31
AN33
VSS
AN32 VDDA_B1 VSSA_B0
ANB8
ANB6
ANB10 ANB13 ANB19 ANB22
VSS
VSS
BYPCA
BYPCB
ETPUA30 ETPUA31 VSS
ANA7
ANA8
VSS
ANA13 ANA17 ANA19 ANA21 ANA22
ANA12 ANA16 ANA18 ANA20 ANA23
AN34
AN35
VSS
AN39
AN38
VSS
AN37
ANB1
VSS
ANB0
ANB2
VSS
ANB7
ANB3
ANB11
ANB15 ANB20
VSS
ETPUC0 ETPUC1
ETPUA27 ETPUA28 ETPUA29 VSS
ANB14 ANB16 ANB17
VSS
VDDEH7 ETPUC2 ETPUC3
ETPUA23 ETPUA24 ETPUA25 ETPUA26 VSS
ETPUA19 ETPUA20 ETPUA21 ETPUA22 VSS
ETPUA11 ETPUA13 ETPUA15 ETPUA17 ETPUA18
VSS
VSS
VSS
VSS
VSS
VSS
ANB23
VSS
VSS
VDDEH7 ETPUC4 ETPUC5 ETPUC6
VDDE8
VDDE8
VDDE8 VDDE8
VSS
VSS
VDDE10 VDDE10
VDDE10
VDDE10 TCRCLKC ETPUC7 ETPUC8 ETPUC9 ETPUC10
ETPUC11 ETPUC12 ETPUC13 ETPUC14 ETPUC15
G
H
J
G
H
J
MPC5676R 516-ball TEPBGA
ETPUA5 ETPUA7 ETPUA8 ETPUA3 ETPUA14 ETPUA16
ETPUA1 ETPUA2 ETPUA9 ETPUA4 ETPUA12
ETPUC19 ETPUC16 ETPUC17 ETPUC18 ETPUC20 ETPUC21
ETPUC22 ETPUC23 ETPUC24 ETPUC26 ETPUC27
(as viewed from top through the package)
K
L
TXDB
TXDA
RXDA TCRCLKA ETPUA6 ETPUA10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ETPUC25 ETPUC28 ETPUC29 ETPUC30 ETPUC31 D_DAT15
VDD33_6 D_DAT14 D_DAT13 D_DAT12 D_DAT11 D_DAT10
D_DAT9 D_DAT8 D_DAT7 D_DAT5 VDDEH7
K
L
BOOT– BOOT–
RXDB ETPUA0
PLLCFG1 PLLCFG2
CFG1
CFG0
VSS
M
N
P
R
T
VDD33_1 D_BDIP PLLCFG0 VSTBY WKPCFG
M
N
P
R
T
D_WE0 D_WE2 D_WE3
VDD
RESET VDDE8
VDDE2
VDDE10 D_DAT6 VDDEH6 D_DAT2 D_DAT3 D_DAT4
D_ADD9 D_ADD10 D_ADD11 VDDEH1 D_WE1 VDD33_1
D_ADD12 D_ADD13 D_ADD14 D_ADD15 D_ADD16
VDDE2 VDDE2
VDDE2 VDDE2
VDDE10 ETPUB13 D_OE
D_ALE D_DAT0 D_DAT1
D_RD_
ETPUB9 ETPUB12 ETPUB14 ETPUB15
WR
VDDE2
D_ADD18 D_ADD19 D_ADD20 D_ADD17 D_CS3
VDDE2 VDDE2 VDDE2
VDDE2 VDDE2 VDDE2
ETPUB17 ETPUB3 ETPUB7 ETPUB8 ETPUB10 ETPUB11
ETPUB23 ETPUB1 ETPUB2 ETPUB4 ETPUB5 ETPUB6
ETPUB21 ETPUB22 ETPUB16 TCRCLKB ETPUB0
U
V
W
Y
D_CS2 JCOMP
RDY
MDO0
MDO6
MCKO MSEO1 MSEO0
U
V
W
Y
EVTI
MDO4
MDO7
EVTO
MDO5
MDO2
MDO3
MDO8
VDDE2
MDO1
VSS
ETPUB25 ETPUB29 REGSEL ETPUB20 ETPUB19 ETPUB18
ETPUB31 ETPUB26 ETPUB27 ETPUB24 REGCTL
MDO9 MDO10 MDO11 MDO12
AA MDO13 MDO14 MDO15 VDD33_1 VDDE8
PCSA5
SCKA
SCKB
SOUTB VDD33_4
VDDE9 VDD33_4
EMIOS23 EMIOS31
CNRXB
VSS
VDDE10 VDD33_3 ETPUB28 VDDREG VSSSYN AA
AB
TDO
TCK
TDI
TMS
VDD
VSS
VDD
VSS
VSS
VDDE9 VDDE9
SINB
D_CS1 D_ADD21 D_ADD29 EMIOS1 EMIOS11 EMIOS17 EMIOS19 EMIOS29 VDDE9 VDDE9 VDDE9 VDDE9
VSS
VDD ETPUB30 VSSFL
EXTAL AB
EMIOS0 EMIOS8 EMIOS13 EMIOS22 EMIOS24 EMIOS28 CNTXB CNRXD VDDEH5 PCSC1
VSS
VDD
VSS
VDDEH6 XTAL
AC VDDE2
AD ENGCLK
VDDE2 PCSA1 SOUTA
FR_B_
PCSB3 VDDEH3 VDDEH4
VDD
AC
FR_A_
TX
VDD
VSS
PCSA0 PCSA3 PCSB2 D_CS0 D_ADD22 D_ADD25 D_ADD28 EMIOS2 EMIOS7 EMIOS12 EMIOS16 EMIOS18 EMIOS27 CNRXA CNTXD
SCKC
RXDC
SINC
PCSC3
VDD VDDSYN AD
TX
FR_A_
RX
FR_B_
RX
AE
AF
VDD
PCSA4 PCSB5
SINA
PCSB1
D_TS D_ADD23 D_ADD26 D_ADD30 EMIOS3 EMIOS6 EMIOS10 EMIOS15 EMIOS21 EMIOS26 CNTXA CNRXC PCSC0
PCSC2 PCSC5
VSS
VDD
AE
AF
D_
CLKOUT
FR_A_
FR_B_
VDDE2
2
VDDEH3 PCSA2 PCSB4 PCSB0
D_TA D_ADD24 D_ADD27
EMIOS4 EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30 CNTXC SOUTC VDDEH4 TXDC
PCSC4 VDDEH5
TX_EN TX_EN
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Figure 4. MPC5676R 516-ball TEPBGA (full diagram)
MPC5676R Microcontroller Data Sheet, Rev. 4
6
Freescale Semiconductor
Electrical Characteristics
3.3
Pin Muxing and Reset States
See Appendix A, Signal Properties and Muxing, for a listing and description of the pin functions and properties.
4
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC5676R.
The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon
these specifications will be met. Finalized specifications will be published after complete characterization and device
qualifications have been completed.
4.1
Maximum Ratings
1
Table 2. Absolute Maximum Ratings
Spec
Characteristic
1.2 V Core Supply Voltage3
Symbol
Min
Max2
Unit
1
2
VDD
VSTBY
VDDSYN
VDD33
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.1
–0.3
–0.3
–0.1
–0.1
–3 13
1.65 4
V
V
5,6
SRAM Standby Voltage
5.5
3
Clock Synthesizer Voltage
4.5 6,7
4.5 6,7
5.5 5,6
4.5 6
5.5 5,6
5.55,6
5.5 5,6
0.1
V
4
I/O Supply Voltage (I/O buffers and predrivers)
V
8
9
5
Analog Supply Voltage (reference to VSSA
)
VDDA
V
6
I/O Supply Voltage (fast I/O pads)
VDDE
VDDEH
VDDREG
V
7
I/O Supply Voltage (medium I/O pads)
Voltage Regulator Input Supply Voltage
V
8
V
10
11
9
Analog Reference High Voltage (reference to VRL
)
VRH
V
10
11
12
13
14
15
V
V
SS to VSSA8 Differential Voltage
VSS – VSSA
VRH – VRL
V
REF Differential Voltage
5.5 5,6
0.3
V
VRL to VSSA Differential Voltage
VRL – VSSA
VDD33 – VDDSYN
VSSSYN – VSS
IMAXD
V
V
DD33 to VDDSYN Differential Voltage
SSSYN to VSS Differential Voltage
0.1
V
V
0.1
V
Maximum Digital Input Current 12 (per pin, applies to all
digital pins)
3 13
mA
16
Maximum Analog Input Current 14 (per pin, applies to all
analog pins)
IMAXA
–3 9,13
3 9,13
mA
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
7
Electrical Characteristics
Spec
1
Table 2. Absolute Maximum Ratings (continued)
Characteristic
Symbol
Min
Max2
Unit
17
Maximum Operating Temperature Range 15 – Die Junction
Temperature
TJ
–40.0
150.0
oC
18
19
Storage Temperature Range
Tstg
Tsdr
–55.0
150.0
oC
oC
Maximum Solder Temperature 16
Pb-free package
—
—
260.0
245.0
SnPb package
20
Moisture Sensitivity Level 17
MSL
—
3
—
1
2
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or
cause permanent damage to the device.
Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have
not yet been determined.
3
4
5
6
7
8
9
1.2 V ±10% for proper operation. This parameter is specified at a maximum junction temperature of 150 °C.
2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.
6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
4.5 V for 10 hours cumulative time, 3.3 V +10% for time remaining.
MPC5676R has two analog power supply pins on the pinout: VDDA_A and VDDA_B.
MPC5676R has two analog ground supply pins on the pinout: VSSA_A and VSSA_B.
10 MPC5676R has two analog low reference voltage pins on the pinout: VRL_A and VRL_B.
11 MPC5676R has two analog high reference voltage pins on the pinout: VRH_A and VRH_B.
12 Total injection current for all pins must not exceed 25 mA at maximum operating voltage.
13 Injection current of ±5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated
time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or VDDEH supply when under
this stress condition.
14 Total injection current for all analog input pins must not exceed 15 mA.
15 Lifetime operation at these specification limits is not guaranteed.
16 Solder profile per CDF-AEC-Q100.
17 Moisture sensitivity per JEDEC test method A112.
4.2
Thermal Characteristics
1
Table 3. Thermal Characteristics, 416-pin TEPBGA Package
Characteristic
Symbol
Value
Unit
Junction to Ambient 2,3 Natural Convection (Single layer board)
Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p)
Junction to Ambient (@200 ft./min., Single layer board)
RJA
RJA
24
16
18
°C/W
°C/W
°C/W
RJMA
MPC5676R Microcontroller Data Sheet, Rev. 4
8
Freescale Semiconductor
Electrical Characteristics
Table 3. Thermal Characteristics, 416-pin TEPBGA Package (continued)
1
Characteristic
Symbol
Value
Unit
Junction to Ambient (@200 ft./min., Four layer board 2s2p)
Junction to Board 5
RJMA
RJB
RJC
JT
13
8
°C/W
°C/W
°C/W
°C/W
Junction to Case 6
4
Junction to Package Top 7 Natural Convection
3
1
2
Thermal characteristics are targets based on simulation that are subject to change per device
characterization.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.
3
4
5
Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
6
7
Indicates the average thermal resistance between the die and the case top surface as measured by the
cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature.
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
1
Table 4. Thermal Characteristics, 516-pin TEPBGA Package
Characteristic
Symbol
Value
Unit
Junction to Ambient 2,3 Natural Convection (Single layer board)
Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p)
Junction to Ambient (@200 ft./min., Single layer board)
Junction to Ambient (@200 ft./min., Four layer board 2s2p)
Junction to Board 5
RJA
RJA
RJMA
RJMA
RJB
RJC
JT
24
17
19
14
9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction to Case 6
5
Junction to Package Top 7 Natural Convection
2
1
2
Thermal characteristics are targets based on simulation that are subject to change per device
characterization.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.
3
4
5
Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
6
Indicates the average thermal resistance between the die and the case top surface as measured by the
cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature.
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
9
Electrical Characteristics
7
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
4.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
* P )
Eqn. 1
J
A
JA
D
where:
T = ambient temperature for the package ( C)
o
A
o
R
= junction to ambient thermal resistance ( C/W)
JA
P = power dissipation in the package (W)
D
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the TEPBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to
ambient thermal resistance:
R
= R
+ R
CA
Eqn. 2
JA
JC
where:
o
R
R
R
= junction to ambient thermal resistance ( C/W)
JA
JC
CA
o
= junction to case thermal resistance ( C/W)
o
= case to ambient thermal resistance ( C/W)
R
is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
JC
ambient thermal resistance, R
. For instance, the user can change the size of the heat sink, the air flow around the device, the
CA
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at
JT
the top center of the package case using the following equation:
T = T + ( x P )
Eqn. 3
J
T
JT
D
where:
o
T = thermocouple temperature on top of the package ( C)
T
o
= thermal characterization parameter ( C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
MPC5676R Microcontroller Data Sheet, Rev. 4
10
Freescale Semiconductor
Electrical Characteristics
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
•
•
•
C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53-58, March 1998.
B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
4.3
EMI (Electromagnetic Interference) Characteristics
To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go
to www.nxp.com and perform a keyword search for “radiated emissions.” The following tables list the values of the device's
radiated emissions operating behaviors.
Table 5. EMC Radiated Emissions Operating Behaviors: 416 BGA
fOSC
fSYS
Frequency
band (MHz)
Level
(max.)
Symbol
Description
Conditions
Unit Notes
1
VRE_TEM
Radiated emissions,
electric field and
magnetic field
VDD = 1.2 V
VDDE = 3.3 V
VDDEH = 5 V
TA = 25 °C
416 BGA
EBI off
40 MHz crystal
180 MHz
(fEBI_CAL = 46
MHz)
0.15–50
50–150
26
30
34
30
I2
dBV
150–500
500–1000
1, 3
CLK off
FM off
IEC and SAE level
—
1
VRE_TEM
Radiated emissions,
electric field and
magnetic field
VDD = 1.2 V
VDDE = 3.3 V
40 MHz crystal
180 MHz
(fEBI_CAL = 46
MHz)
0.15–50
50–150
24
25
25
21
K5
dBV
VDDEH = 5 V
TA = 25 °C
416 BGA
EBI off
150–500
500–1000
1,3
CLK off
IEC and SAE level
—
FM on4
1
Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell
Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM
(GTEM) Cell Method.
2
3
I = 36 dBV
Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
4
5
“FM on” = FM depth of ±2%
K = 30 dBV
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
11
Electrical Characteristics
4.4
ESD Characteristics
1,2
Table 6. ESD Ratings
Spec
Characteristic
Symbol
Value
Unit
1
2
ESD for Human Body Model (HBM)
ESD for Charged Device Model (CDM)
VHBM
VCDM
2000
V
V
750 (corners)
500 (other)
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the
device specification.
4.5
PMC/POR/LVI Electrical Specifications
Table 7. PMC Operating conditions
Spec
Name
Parameter
Condition
Min
Typ
Max
Unit
1
VDDREG
Supply voltage VDDREG LDO5V / SMPS5V mode
5 V nominal1
4.5
5
5.5
V
2
3
4
VDDREG
VDD33
VDD
Supply voltage VDDREG LDO3V mode
3 V nominal1
3.0
3.0
3.3
3.3
1.2
3.6
3.6
V
V
V
Supply voltage VDDSYN / LDO3V mode
VDD33 3.3 V nominal2
Supply voltage VDD
1.2 V nominal3
—
1.14
1.32
1
2
Voltage should be higher than maximum VLVDREG to avoid LVD event
Applies to both VDD33 (flash supply) and VDDSYN (PLL supply) pads. Voltage should be higher than maximum VLVD33
to avoid LVD event
3
Voltage should be higher than maximum VLVD12 to avoid LVD event
NOTE
In the following table, “untrimmed” means “at reset” and “trimmed” means “after reset”.
Table 8. PMC Electrical Specifications
Spec
Name
Symbol
Condition
Min
Typ
Max
Unit
1
Nominal bandgap reference
voltage
VBG
—
0.59
0.620
0.65
V
1a Bandgap reference voltage
during power on reset
—
—
—
—
VBG – 5%
VBG – 2%
VBG
VBG + 5%
VBG + 2%
V
V
1b Bandgap reference voltage at
nominal voltage / nominal
temperature after power on
reset
VBG
MPC5676R Microcontroller Data Sheet, Rev. 4
12
Freescale Semiconductor
Electrical Characteristics
Table 8. PMC Electrical Specifications
Spec
Name
Symbol
Condition
Min
Typ
Max
Unit
1c Bandgap reference voltage /
temperature dependence after
power on reset
—
—
—
300
—
ppm/C
1d Bandgap reference voltage /
—
—
—
—
1500
1.2
—
—
voltage dependence (VDDREG
after power on reset
)
2
Nominal VRC regulated 1.2V
output VDD1
VDD12OUT
—
V
2a VRC 1.2V output variation at
reset (unloaded)2
—
—
At POR
VDD12OUT – 8% VDD12OUT VDD12OUT + 10%
2b VRC 1.2V output variation after
reset(REGCTL load max.
After POR VDD12OUT – 5% VDD12OUT VDD12OUT + 10%
20mA, VDD load max. 1A)
2c Trimming step Vdd1p2
VSTEPV12
VPORC
—
—
—
—
10
0.7
—
mV
V
3
POR rising VDD 1.2V
-
VPORC – 30%
—
—
VPORC + 30%
—
3a POR VDD 1.2V variation
3b POR 1.2V hysteresis
—
VPORC
75
—
—
mV
V
4
Nominal rising LVD 1.2V3
VLVD12
—
—
—
1.100
VLVD12
—
4a LVD 1.2V variation before band
gap trim4
At POR
VLVD12 – 6%
VLVD12 + 6%
4b LVD 1.2V variation after band
gap trim4
—
After POR
VLVD12 – 3%
VLVD12
VLVD12 + 3%
4c LVD 1.2V Hysteresis
—
—
—
—
15
—
—
20
10
—
25
—
20
mV
mV
mA
4d Trimming step LVD 1.2V
VLVDSTEP12
IREGCTL
5
6
7
VRC 1.2V max DC output
current
Voltage regulator 1.2V current
consumption VDDREG
—
—
—
3
—
mA
V
Nominal Vreg 3.3V output5
VDD33OUT
—
—
—
3.3
—
7a Vreg 3.3V output variation at
reset (unloaded)6
At POR
VDD33OUT – 6% VDD33OUT VDD33OUT + 10%
7b Vreg 3.3V output variation after
reset (max. load 60mA)
—
After POR VDD33OUT – 5% VDD33OUT VDD33OUT + 10%
7c Trimming step VDDSYN
VSTEPV33
VLVD33
—
—
—
—
—
30
—
—
mV
V
8
Nominal rising LVD 3.3V7
2.950
VLVD33
8a LVD 3.3V variation before band
gap trim6
At POR
VLVD33 – 5%
VLVD33 + 5%
8b LVD 3.3V variation after bad gap
trim6
—
After POR
VLVD33 – 3%
VLVD33
VLVD33 + 3%
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
13
Electrical Characteristics
Table 8. PMC Electrical Specifications
Spec
Name
Symbol
Condition
Min
Typ
Max
Unit
8c LVD 3.3V Hysteresis
—
—
—
—
—
—
60
30
30
—
—
—
—
mV
mV
mA
8d Trimming step LVD 3.3V
VLVDSTEP33
IDD33
9
Vreg 3.3V minimum peak DC
output current supplied by
regulator without causing
8
VLVD33
10 Voltage regulator 3.3V current
consumption VDDREG9
—
—
—
—
2
—
—
mA
V
11 POR rising on VDDREG
11a POR VDDREG variation
11b POR VDDREG hysteresis
12 Nominal rising LVD VDDREG
VPORREG
—
—
—
—
2.00
VPORREG – 30% VPORREG VPORREG + 30%
—
—
—
250
—
—
mV
V
VLVDREG
LDO3V /
LDO5V
mode
2.950
12a LVD VDDREG variation at
reset10
—
—
—
At POR
VLVDREG – 5% VLVDREG VLVDREG + 5%
12b LVD VDDREG variation after
reset10
After POR
VLVDREG – 3% VLVDREG VLVDREG + 3%
12c LVD VDDREG Hysteresis
12d Trimming step LVD VDDREG
13 Nominal rising LVD VDDREG
LDO3V /
LDO5V
mode
—
—
—
30
30
—
—
—
mV
mV
V
VLVDSTEPREG
LDO3V /
LDO5V
mode
VLVDREG
SMPS5V
mode
4.360
13a LVD VDDREG variation at
reset10
—
—
—
At POR
After POR
—
VLVDREG – 5% VLVDREG VLVDREG + 5%
13b LVD VDDREG variation after
reset10
VLVDREG – 3% VLVDREG VLVDREG + 3%
14 SMPS regulator output
resistance11
—
15
25
Ohm
15 SMPS regulator clock frequency
—
—
After POR
1.0
—
1.5
—
MHz
V
16 SMPS regulator overshoot at
start-up12
GBD/GBC13
1.32
1.4
17 SMPS maximum output current,
as required by SoC14
—
—
—
—
—
1.0
—
—
A
V
18 Voltage variation on current step
(20% to 80% of maximum
current with 4 usec constant
time)14
GBD/GBC13
0.1
MPC5676R Microcontroller Data Sheet, Rev. 4
14
Freescale Semiconductor
Electrical Characteristics
1
2
3
4
5
6
7
8
9
Nominal internal regulator output voltage is 1.27V
Voltage should be higher than maximum VLVD12 to avoid LVD event
~VDD12OUT *0.87
Rising VDD
Nominal internal regulator output voltage is 3.4V
Rising VDDSYN
~VDD33OUT *0.872
VDDSYN
Except IDD33
10 Rising VDDREG
11 Pull up to VDDREG when high, pull down to VSSREG when low.
12 Depends on external device, can be as high as 1.6V for short time (<100 usec each start-up)
13 GBD — Guaranteed By Design; GBC — Guaranteed by Characterization
14 Proper external devices required
4.5.1
Regulator Example
VDDREG
The resistor may or may
not be required.
This depends on the
allowable power dissipation of
the npn bypass transistor
device.
IPP_INA_SMPS_SEL5
The bypass transistor
MUST be operated out
of saturation region.
VRCCTL
VDD1p2
MCU
Mandatory decoupling capacitor
network
VSS
VRCCTL capacitor: may or
may not be required
Figure 5. VRC 1.2 V LDO configuration with external bipolar
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
15
Electrical Characteristics
VDDREG
IPP_INA_SMPS_SEL5
VRCCTL
MCU
VDD1p2
VSS
Mandatory decoupling capacitor
network
No VRCCTL capacitor is allowed
Figure 6. VRC 1.2V buck SMPS LDO configuration with external MOS - Schottky diode
Table 9. VRC LDO recommended external devices
Part Name
Part Type
Nominal
Description
ON Semiconductor TM
NJD2873
Beta (Bf)
Vbe
NPN
From 60 to 550
From 0.4 V to 1.0 V
Vce
From 0.2 V to 0.6 V depends on package / power
Capacitor 6 x 4.7 uF - 20 V Ceramic low ESR—One for each VDD pin
Capacitor 6 x 0.1 uF - 20 V Ceramic —One capacitor for each VDD pin
Capacitor 20 uF
Capacitor 2.2 uF
Supply decoupling cap (close to bipolar collector)
Snubber cap, required with NJD2873 (on bipolar base)
Optional ESR for snubber cap
Resistor
12
MPC5676R Microcontroller Data Sheet, Rev. 4
16
Freescale Semiconductor
Electrical Characteristics
Table 10. VRC SMPS recommended external devices
Part Name
Part Type
Nominal
Description
IR7353
HS nMOS +
Schottky
Low threshold n-MOS/Low Vf Schottky diode
SS8P3L
Schottky
Low Vf Schottky diode
From 0.4V to 0.6 V
Vf
SI3460 or equivalent
Vth
nMOS
Low threshold n-MOS
Less than 2 V
Ids
More than 1.5 A
Vds
More than 12 V
Rdson
Less than 100 Ohms
Cg
Less than 5 nF
Turn on / off delay
Rise time
Less than 50 ns
Less than 90 ns
LQH66SN2R2M03
C3225X7R1E106M
C3225X7R1E225K
inductor
2.2 uH—3.2 A
22 uF — 25 V
muRata TM shielded coil, preferred fmax > 40 MHz
TDK high capacitance ceramic SMD (on VDD close to coil)
TDK ceramic SMD (on VDD close to MCU)
capacitor
capacitor 2 to 6 x 2.2 uF
— 25 V
capacitor
6 x 0.1 uF
— 20 V
Ceramic -One capacitor for each VDD pin
C3225X7R1E106M
capacitor
resistor
22 uF — 25 V
20 K
Supply decoupling cap—close to n-MOS drain
Pull down for power n—MOS gate
4.6
Power Up/Down Sequencing
There is no power sequencing required among power sources during power up and power down in order to operate within
specification as long as the following two rules are met:
•
•
When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG.
When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the
internal 3.3V regulator.
The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up
each V /V first and then power up V . For power down, drop V to 0 V first, and then drop all V /V
DDE DDEH
DD
DD
DDE DDEH
supplies. There is no limit on the fall time for the power supplies.
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,
the state of the I/O pins during power up/down varies according to Table 11 and Table 12.
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
17
Electrical Characteristics
Table 11. Power Sequence Pin States for MH and AE pads
VDD
VDD33
VDDE
MH Pad
MH+LVDS Pads1
AE/up-down Pads
High
—
High
Low
High
High
Normal operation
Normal operation
Normal operation
Pin is tri-stated (output buffer,
input buffer, and weak pulls
disabled)
Outputs driven high
Pull-ups enabled,
pull-downs disabled
Low
Low
High
High
Low
Output low,
pin unpowered
Outputs disabled
Outputs disabled
Output low,
pin unpowered
High
Pin is tri-stated (output buffer,
input buffer, and weak pulls
disabled)
Pull-ups enabled,
pull-downs disabled
1
MH+LVDS pads are output-only.
Table 12. Power Sequence Pin States for F and FS pads
VDD
VDD33
VDDE
F and FS pads
low
low
low
high
low
high
—
Outputs drive high
Outputs Disabled
Outputs Disabled
Outputs drive high
high
high
high
low
high
low
low
high
Normal operation - except no drive current
and input buffer output is unknown.1
high
high
high
Normal Operation
1
The pad pre-drive circuitry will function normally but since VDDE is unpowered
the outputs will not drive high even though the output pmos can be enabled.
4.6.1
Power-Up
If V
/V
is powered up first, then a threshold detector tristates all drivers connected to V
/V
. There is no limit
DDE DDEH
DDE DDEH
to how long after V
/V
powers up before V must power up. If there are multiple V
/V
supplies, they can
DDE DDEH
DD
DDE DDEH
be powered up in any order. For each V
/V
supply not powered up, the drivers in that V
/V
segment exhibit
DDE DDEH
DDE DDEH
the characteristics described in the next paragraph.
If V is powered up first, then all pads are loaded through the drain diodes to V
/V . This presents a heavy load that
DDE DDEH
DD
pulls the pad down to a diode above V . Current injected by external devices connected to the pads must meet the current
SS
injection specification. There is no limit to how long after V powers up before V
/V
must power up.
DD
DDE DDEH
The rise times on the power supplies are to be no faster than 25 V/millisecond.
4.6.2
Power-Down
If V is powered down first, then all drivers are tristated. There is no limit to how long after V powers down before
DD
DD
V
/V
must power down.
DDE DDEH
If V
/V
is powered down first, then all pads are loaded through the drain diodes to V
/V
. This presents a heavy
DDE DDEH
DDE DDEH
load that pulls the pad down to a diode above V . Current injected by external devices connected to the pads must meet the
SS
current injection specification. There is no limit to how long after V
/V
powers down before V must power down.
DDE DDEH DD
MPC5676R Microcontroller Data Sheet, Rev. 4
18
Freescale Semiconductor
Electrical Characteristics
There are no limits on the fall times for the power supplies.
4.6.3
Power Sequencing and POR Dependent on VDDA
During power up or down, V
can lag other supplies (of magnitude greater than V
/2) within 1 V to prevent any
DDA
DDEH
forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between V
is more than 1 V, the following will result:
and V
DDEH
DDA
•
Triggers POR (ADC monitors on V
segment which powers the RESET pin) if the leakage current path created,
DDEH1
when V
level.
is sufficiently low, causes sufficient voltage drop on V
node monitored crosses low-voltage detect
DDA
DDEH1
•
•
•
If V
out of reset.
is between 0–2 V, powering all the other segments (especially V
) will not be sufficient to get the part
DDEH1
DDA
Each V
up to (V
will have a leakage current to V
of a magnitude of ((V
– V
– 1 V(diode drop)/200 KOhms)
DDA
DDEH
DDA
DDEH
/2 = V
+ 1 V). .
DDEH
DDA
Each V has the same behavior; however, the leakage will be small even though there is no current limiting resistor
DD
since V = 1.32 V max.
DD
4.7
DC Electrical Specifications
1
Table 13. DC Electrical Specifications
Spec
Characteristic
Symbol
Min
Max
Unit
1
1a
2
Core Supply Voltage (External Regulation)
Core Supply Voltage (Internal Regulation)4
I/O Supply Voltage (fast I/O pads)
I/O Supply Voltage (medium I/O pads)
3.3 V I/O Buffer Voltage
VDD
VDD
1.14
1.08
3.0
1.322, 3
1.32
V
V
V
V
V
V
V
V
V
V
V
VDDE
3.62
3
VDDEH
VDD33
3.0
5.252
3.62
4
3.0
5
Analog Supply Voltage
VDDA
4.75
0.955
2
5.252
1.2
6a
6b
7
SRAM Standby Voltage low range
SRAM Standby Voltage high range
Voltage Regulator Control Input Voltage6
Clock Synthesizer Operating Voltage8
VSTBY_LOW
VSTBY_HIGH
VDDREG
VDDSYN
VIH_F
6
2.77
3.0
5.52
8
3.62
9
Fast I/O Input High Voltage
Hysteresis enabled
V
DDE + 0.3
0.65 × VDDE
0.55 × VDDE
Hysteresis disabled
10
11
Fast I/O Input Low Voltage
Hysteresis enabled
VIL_F
VSS – 0.3
V
V
0.35 × VDDE
0.40 × VDDE
Hysteresis disabled
Medium I/O Input High Voltage
Hysteresis enabled
VIH_S
VDDEH + 0.3
0.65 × VDDEH
Hysteresis disabled
0.55 × V
DDEH
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
19
Electrical Characteristics
Spec
1
Table 13. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
12
Medium I/O Input Low Voltage
VIL_S
VSS – 0.3
V
Hysteresis enabled
Hysteresis disabled
0.35 × VDDEH
0.40 × VDDEH
13
14
15
16
17
18
19
Fast I/O Input Hysteresis
VHYS_F
VHYS_S
VINDC
VOH_F
VOH_S
VOL_F
VOL_S
0.1 × VDDE
0.1 × VDDEH
VSSA – 0.1
0.8 × VDDE
0.8 × VDDEH
—
—
V
V
V
V
V
V
V
Medium I/O Input Hysteresis
Analog Input Voltage
—
VDDA + 0.1
—
Fast I/O Output High Voltage9
Medium I/O Output High Voltage10
Fast I/O Output Low Voltage9
Medium I/O Output Low Voltage
—
0.2 × VDDE
1
—
0.2 × VDDEH
0
0.15 × VDDEH
11
20
Load Capacitance (Fast I/O)12
DSC(PCR[8:9]) = 0b00
DSC(PCR[8:9]) = 0b01
DSC(PCR[8:9]) = 0b10
DSC(PCR[8:9]) = 0b11
CL
—
—
—
—
10
20
30
50
pF
pF
pF
pF
21
22
23
24
Input Capacitance (Digital Pins)
CIN
—
—
—
7
pF
pF
pF
Input Capacitance (Analog Pins)
CIN_A
CIN_M
10
12
Input Capacitance (Digital and Analog Pins13
)
Operating Current 1.2 V Supplies @ fsys = 180 MHz
VDD (including VDDF current)@1.32 V
VSTBY14 @1.2 V and 85oC
VSTBY @6.0 V and 85oC
VDDF15 (P/E)
IDD
IDDSTBY
—
—
—
—
—
—
—
—
1.016
0.10
A
mA
mA
mA
mA
mA
mA
mA
IDDSTBY6
IDDFPE
IDDFREAD
IDDFRWW
IDDplTANDBY
IDDFDISABLED
0.15
3617
VDDF15 (Read)
5017
VDDF15 (RWW)
9017
VDDF15 (Standby)
0.2017
0.1017
VDDF15 (Disabled)
25
Operating Current 3.3 V Supplies @ fsys = 180 MHz
note18
720
mA
mA
mA
mA
mA
mA
mA
18
VDD33
VDDSYN
IDD33
IDDSYN
IDDFLASHPE
—
—
—
—
—
—
—
VFLASH19 (P/E)
VFLASH19 (Read)
VFLASH19 (RWW)
VFLASH19 (Standby)
VFLASH19 (Disabled)
3221
IDDFLASHREADS
IDDFLASHRWW
IDDFLASHSTANDBY
IDDFLASHDISABLED
6.421
4021
3.421
0.1021
26
Operating Current 5.0 V Supplies @ fsys = 180 MHz
VDDA
IDDA
IREF
IREG
—
—
—
5022
1.0
22
mA
mA
mA
Analog Reference Supply Current (Transient)
VDDREG
MPC5676R Microcontroller Data Sheet, Rev. 4
20
Freescale Semiconductor
Electrical Characteristics
1
Table 13. DC Electrical Specifications (continued)
Spec
Characteristic
Symbol
Min
Max
Unit
27
Operating Current VDDE/VDDEH23 Supplies
VDDE2
IDD2
IDD1
IDD3
IDD4
IDD5
IDD6
IDD7
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
VDDEH1
VDDEH3
VDDEH4
VDDEH5
VDDEH6
VDDEH7
note23
28
29
Fast I/O Weak Pull Up/Down Current24
3.0 V–3.6 V
IACT_F
IACT_S
42
158
A
Medium I/O Weak Pull Up/Down Current25
3.0 V–3.6 V
4.5 V–5.5 V
15
35
95
200
A
A
30
31
32
I/O Input Leakage Current26
DC Injection Current (per pin)
IINACT_D
IIC
–2.5
–1.0
–250
2.5
1.0
A
mA
nA
Analog Input Current, Channel Off27, AN[0:7], AN38,
AN39
IINACT_A
250
Analog Input Current, Channel Off, all other analog
inputs AN[x] = -/+ 150nA
–150
150
nA
33
34
35
36
37
38
39
40
41
42
43
V
SS Differential Voltage
Analog Reference Low Voltage
RL Differential Voltage
Analog Reference High Voltage
VSS – VSSA
VRL
VRL – VSSA
VRH
–100
VSSA
–100
VDDA – 100
4.75
100
VSSA + 100
100
mV
mV
mV
mV
V
V
VDDA
5.25
V
V
REF Differential Voltage
VRH – VRL
VSSSYN – VSS
TA (TL to TH)
—
SSSYN to VSS Differential Voltage
–100
–40.0
—
100
mV
C
Operating Temperature Range—Ambient (Packaged)
Slew rate on power supply pins
125.0
25
V/ms
k
Weak Pull-Up/Down Resistance28,29 200 k Option
Weak Pull-Up/Down Resistance28,29 100 k Option
RPUPD200K
RPUPD100K
RPUPD5K
130
280
65
140
k
Weak Pull-Up/Down Resistance28 (5 k Option)
5 V ± 10% supply
k
1.4
1.7
5.2
7.7
3.3 V ± 10% supply
44
Pull-Up/Down Resistance Matching Ratios
(100K/200K)
RPUPDMATCH
–2.5
2.5
%
(Pull-up and pull-down resistances both enabled and
settings are equal)
1
2
3
These specifications are design targets and subject to change per device characterization.
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
21
Electrical Characteristics
4
Assumed with DC load.
5
VSTBY below 0.95 V the RAM will not retain states, but will be operational. VSTBY can be 0 V when bypass standby mode.
6
Regulator is functional with derated performance, with supply voltage down to 4.0 V for system with VDDREG = 4.5 V (min).
7
2.7 V minimum operating voltage allowed during vehicle crank for system with VDDREG = 3.0 V (min). Normal operating voltage
should be either VDDREG = 3.0 V (min) or 4.5 V (min) depending on the user regulation voltage system selected.
8
Required to be supplied when 3.3 V regulator is disabled. See Section 4.5, “PMC/POR/LVI Electrical Specifications.”
9
IOH_F = {12,20,30,40} mA and IOL_F = {24,40,50,65} mA for {00,01,10,11} drive mode with VDDE= 3.0 V.
10
I
= {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with VDDEH = 4.5 V;
OH_S
IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDEH = 3.0 V
11
I = 2 mA
OL_S
12 Applies to D_CLKOUT, external bus pins, and Nexus pins.
13 Applies to the FCK, SDI, SDO, and SDS_B pins.
14
V
current specified at 1.0 V at a junction temperature of 85 oC. VSTBY current is 700 µA maximum at a junction
STBY
temperature of 150 oC.
15 VDDF pin is shorted to VDD on the package substrate.
16 Preliminary. Specification pending typical and/or high-use Runidd pattern simulation as well as final silicon characterization.
1.0 A based on transistor count estimate at Worst Case (wcs) process and temperature condition.
17 Typical values from the simulation.
18 Power requirements for the VDD33 supply depend on the frequency of operation and load of all I/O pins, and the voltages on
the I/O segments. See Section 4.7.2, “I/O Pad VDD33 Current Specifications,” for information on both fast (F, FS) and medium
(MH) pads. Also refer to Table 15 for values to calculate power dissipation for specific operation.
19 VFLSH pin is shorted to VDD33 on the package substrate.
20 This value is a target that is subject to change.
21 Typical values from the simulation.
22 These value allows a 5 V 20 mA reference to supply ADC + REF.
23 Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. See Section 4.7.1, “I/O Pad Current Specifications,” for information on I/O pad
power. Also refer to Table 14 for values to calculate power dissipation for specific operation. The total power consumption of
an I/O segment is the sum of the individual power consumptions for each pin on the segment.
24 Absolute value of current, measured at VIL and VIH.
25 Absolute value of current, measured at VIL and VIH.
26 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types F and MH.
27 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each
8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types AE and AE/up-down.
28 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics.
29 When the pull-up and pull-down of the same nominal 200 k or 100 k value are both enabled, assuming no interference from
external devices, the resulting pad voltage will be 0.5*VDDEH ± 2.5%.
4.7.1
I/O Pad Current Specifications
The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power
consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from
Table 14 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency,
and load parameters that fall outside the values given in Table 14.
The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”
MPC5676R Microcontroller Data Sheet, Rev. 4
22
Freescale Semiconductor
Electrical Characteristics
1
Table 14. V
/V
I/O Pad Average DC Current
DDE DDEH
Frequency
(MHz)
Load2
(pF)
Voltage
(V)
Drive/Slew
Rate Select
Spec
Pad Type
Symbol
Current (mA)
1
2
Medium
IDRV_MH
50
20
50
50
50
200
10
20
30
50
10
20
30
50
50
50
50
50
200
5.25
5.25
5.25
5.25
3.6
11
01
00
00
00
01
10
11
00
01
10
11
11
10
01
00
00
16.0
6.3
3
3.0
2.0
66
1.1
4
2.4
5
Fast
IDRV_FC
6.5
6
66
3.6
9.4
7
66
3.6
10.8
33.3
2.0
8
66
3.6
9
66
1.98
1.98
1.98
1.98
3.6
10
11
12
13
14
15
16
17
66
3.0
66
4.4
66
15.1
12.0
6.2
Fast w/ Slew
Control
IDRV_FSR
66
50
3.6
33.33
20
3.6
4.0
3.6
2.4
20
3.6
8.9
1
2
These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only.
All loads are lumped.
4.7.2
I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption
is the sum of all input and output pin VDD33 currents for all I/O segments. The VDD33 current draw on fast speed pads can be
calculated from Table 15 dependent on the voltage, frequency, and load on all F type pins. The VDD33 current draw on medium
pads can be calculated from Table 15 dependent on voltage and independent on the frequency and load on all MH type pins.
Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table 15.
The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
23
Electrical Characteristics
1
Table 15. V
Pad Average DC Current
DD33
Frequency
(MHz)
Load2
(pF)
VDD33
(V)
VDDE
(V)
Drive/Slew
Rate Select
Spec
Pad Type
Symbol
Current (mA)
1
2
Medium
Fast
I33_MH
I33_FC
—
66
—
10
20
30
50
10
20
30
50
50
50
50
50
200
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
5.5
3.6
—
00
01
10
11
00
01
10
11
11
10
01
00
00
0.0007
0.92
1.14
1.50
2.19
0.70
0.90
1.08
1.52
0.74
0.52
0.36
0.19
0.19
3
66
3.6
4
66
3.6
5
66
3.6
6
66
1.98
1.98
1.98
1.98
3.6
7
66
8
66
9
66
10
11
12
13
14
Fast w/
Slew
Control
I33_FSR
66
50
3.6
33.33
20
3.6
3.6
20
3.6
1
2
These are average IDD33 for worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input
pins only for the medium pads.
All loads are lumped.
4.7.3
LVDS Pad Specifications
LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI
module.
1, 2
Table 16. DSPI LVDS Pad Specification
(VDD33 = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH)
Spec
Characteristic
Symbol
Min
Typical
Max
Unit
Data Rate
1
Data Frequency
fLVDSCLK
—
—
40
MHz
mV
Driver Specs
2
Differential Output Voltage
SRC=0b00 or 0b11
VOD
215
170
260
—
400
320
480
SRC=0b01
SRC=0b10
3
4
5
Common Mode Voltage (LVDS), VOS
Rise/Fall Time
VOS
tR or tF
tDZ
1.075
—
1.2
—
1.325
2.5
V
ns
ns
Delay, Z to Normal (High/Low)
—
—
100
MPC5676R Microcontroller Data Sheet, Rev. 4
24
Freescale Semiconductor
Electrical Characteristics
1, 2
Table 16. DSPI LVDS Pad Specification
(continued)
(VDD33 = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH)
6
Differential Skew between Positive and Negative
LVDS Pair
tSkew
—
—
0.5
ns
I tphla – tplhb I or I tplhb – tphla
I
Termination
7
8
Termination Resistance3
Load
RLoad
—
95
—
100
—
105
32
ohm
pF
1
2
3
These are typical values that are estimated from simulation.
These specifications are subject to change per device characterization.
The termination resistance spec is not meant to specify the receiver termination requirements. They are there to establish the
measurement criteria for the specs in this table. As per the TIA/EIA-644A standard, the LVDS receiver termination resistance
can vary from 90 to 132 .
4.8
Oscillator and FMPLL Electrical Characteristics
1
Table 17. FMPLL Electrical Specifications
(VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)
Spec
Characteristic
Symbol
Min
Max
Unit
1
PLL Reference Frequency Range2 (Normal Mode)
Crystal Reference (PLLCFG2 = 0b0)
Crystal Reference (PLLCFG2 = 0b1)
External Reference (PLLCFG2 = 0b0)
External Reference(PLLCFG2 = 0b1)
MHz
fref_crystal
fref_crystal
fref_ext
8
40
8
20
403
20
fref_ext
40
40
2
PLL Frequency 4
Enhanced Mode
fPLL
fLOR
fSCM
tLPLL
tDC
fvco(min) 64
fmax
1000
16
MHz
kHz
3
4
5
6
7
8
9
Loss of Reference Frequency5
Self Clocked Mode Frequency6
PLL Lock Time7
100
4
MHz
s
—
<750
60
Duty Cycle of Reference 8, 9
Frequency un-LOCK Range
Frequency LOCK Range
40
%
fUL
–4.0
–2.0
–5
4.0
2.0
5
% fsys
% fsys
fLCK
CJitter
D_CLKOUT Period Jitter10, 11 Measured at fSYS Max
Cycle-to-cycle Jitter
%fclko
ut
12,13
10
Peak-to-Peak Frequency Modulation Range Limit
Cmod
0
4
%fsys
(fsys Max must not be exceeded)
11
12
13
14
FM Depth Tolerance14
Cmod_err
fVCO
–0.25
192
0.400
4
0.25
600
1
%fsys
MHz
MHz
MHz
VCO Frequency
Modulation Rate Limits15
Predivider Operating Frequency
fmod
fprediv
10
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
25
Electrical Characteristics
1
All values given are initial design targets and subject to change.
2
Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default
PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz.
3
4
5
6
Upper tolerance of less than 1% is allowed on 40MHz crystal.
All internal registers retain data at 0 Hz.
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR. This
frequency is measured at D_CLKOUT with the divider set to divide-by-2 of the system clock. NOTE: in SCM, the PLL is running
open loop at a centercode 0x4. The MFD has no effect and the RFD is bypassed.
7
This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal
startup time.
8
9
For FlexRay operation, duty cycle requirements are higher.
Duty cycle can be 20–80% when PLL is used with a pre-divider greater than 1.
10 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter
percentage for a given interval. D_CLKOUT divider set to divide-by-2.
11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter + Cmod
12 Modulation depth selected must not result in fpll value greater than the fpll maximum specified value.
.
13 Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in
control register are: 1%, 2%, 3%, and 4% peak-to-peak.
14 Depth tolerance is the programmed modulation depth ±0.25% of Fsys. Initial design target pending silicon evaluation.
15 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz
will result in reduced calibration accuracy.
1
Table 18. Oscillator Electrical Specifications
(VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)
Spec
Characteristic
Symbol
Min
Max
Unit
| Vextal – Vxtal
> 0.4 V
|
1
Crystal Mode Differential Amplitude2
(Min differential voltage between EXTAL and XTAL)
V
crystal_diff_amp
—
V
2
3
4
Crystal Mode: Internal Differential Amplifier Noise
Rejection
Vcrystal_diff_amp_nr
—
| Vextal – Vxtal
< 0.2 V
|
V
V
V
EXTAL Input High Voltage
VIHEXT
((V
/2) + 0.4 V)
—
DD33
Bypass mode, External Reference
—
EXTAL Input Low Voltage
VILEXT
(V
/2) – 0.4 V
DD33
Bypass mode, External Reference
5
6
XTAL Current3
IXTAL
1
3
mA
pF
—
Total On-chip stray capacitance on XTAL
CS_XTAL
1.5
MPC5676R Microcontroller Data Sheet, Rev. 4
26
Freescale Semiconductor
Electrical Characteristics
1
Table 18. Oscillator Electrical Specifications (continued)
(VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)
Spec
Characteristic
Symbol
Min
—
Max
Unit
7
8
Total On-chip stray capacitance on EXTAL
CS_EXTAL
CL
1.5
pF
pF
Crystal manufacturer’s recommended capacitive
load
See crystal spec
See crystal spec
—
—
9
Discrete load capacitance to be connected to EXTAL
CL_EXTAL
(2 × C – C
pF
pF
L
S_EXTA
4
– C
L
PCB_EXTAL )
10
Discrete load capacitance to be connected to XTAL
CL_XTAL
(2 × C – C
L S_XTAL
4
– C
PCB_XTAL )
1
2
All values given are initial design targets and subject to change.
This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In
that case, Vextal – Vxtal 400 mV criterion has to be met for oscillator’s comparator to produce output clock.
Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
3
4
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
4.9
eQADC Electrical Characteristics
Table 19. eQADC Conversion Specifications (Operating)
Spec
Characteristic
Symbol
Min
Max
Unit
1
2
ADC Clock (ADCLK) Frequency
Conversion Cycles
fADCLK
CC
2
2 + 13
10
16
128 + 14
—
MHz
ADCLK cycles
s
3
Stop Mode Recovery Time1
TSR
4
Resolution2
—
1.25
–44
–84
–34
–34
04
—
mV
5
INL: 8 MHz ADC Clock3
INL8
44
LSB5
LSB
6
INL: 16 MHz ADC Clock3
INL16
DNL8
DNL16
OFFNC
OFFWC
GAINNC
GAINWC
IINJ
84
7
DNL: 8 MHz ADC Clock3
34
LSB
8
DNL: 16 MHz ADC Clock3
34
LSB
9
Offset Error without Calibration
Offset Error with Calibration
Full Scale Gain Error without Calibration
Full Scale Gain Error with Calibration
Disruptive Input Injection Current 7, 8, 9, 10
Incremental Error due to injection current11, 12
TUE value at 8 MHz 13, 14 (with calibration)
1004
44
LSB
10
11
12
13
14
15
–44
–1204
–44,6
–1
LSB
04
LSB
44,6
1
LSB
m
EINJ
—
+44
+44,6
Counts
Counts
TUE8
—
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
27
Electrical Characteristics
Table 19. eQADC Conversion Specifications (Operating) (continued)
Spec
Characteristic
Symbol
Min
Max
Unit
16
17
TUE value at 16 MHz 13, 14 (with calibration)
TUE16
—
+8
Counts
Variable gain amplifier accuracy (gain=1)15
INL, 8 MHz ADC
GAINVGA1
Counts17
–4
–8
4
8
INL, 16 MHz ADC
DNL, 8 MHz ADC
DNL, 16 MHz ADC
–316
–316
316
316
18
19
Variable gain amplifier accuracy (gain=2)15
INL, 8 MHz ADC
GAINVGA2
GAINVGA4
Counts
Counts
–5
–8
–3
–3
5
8
3
3
INL, 16 MHz ADC
DNL, 8 MHz ADC
DNL, 16 MHz ADC
Variable gain amplifier accuracy (gain=4)15
INL, 8 MHz ADC
–7
–8
–4
–4
7
8
4
4
INL, 16 MHz ADC
DNL, 8 MHz ADC
DNL, 16 MHz ADC
1
Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time
that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.
2
3
4
At VRH – VRL = 5.12 V, one count = 1.25 mV without using pregain.
INL and DNL are tested from VRL + 50 LSB to VRH – 50 LSB.
New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully
included.
5
6
7
At VRH – VRL = 5.12 V, one LSB = 1.25 mV.
The value is valid at 8 MHz, it is ±8 counts at 16 Mhz.
Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater
than VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions.
8
9
Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit
do not affect device reliability or cause permanent damage.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = –0.3 V, then use the larger of the
calculated values.
10 Condition applies to two adjacent pins at injection limits.
11 Performance expected with production silicon.
12
All channels have same 10 k < Rs < 100 kChannel under test has Rs = 10 k, IINJ=IINJMAX INJMIN.
,I
13 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors.
14 TUE does not apply to differential conversions.
15 Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1, 2, or
4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated.
16 Guaranteed 10-bit mono tonicity.
17 At VRH – VRL = 5.12 V, one LSB = 1.25 mV.
MPC5676R Microcontroller Data Sheet, Rev. 4
28
Freescale Semiconductor
Electrical Characteristics
4.9.1
ADC Internal Resource Measurements
Table 20. Power Management Control (PMC) Specification
Spec
Characteristic
Symbol
Min
Typical
Max
Unit
PMC Normal Mode
1
2
3
4
5
6
7
Bandgap 0.62 V
ADC0 channel 145
VADC145
VADC146
VADC147
VADC180
VADC181
VADC182
VADC183
0.59
0.62
1.22
0.65
V
V
V
V
V
V
V
Bandgap 1.2 V
ADC0 channel 146
1.10
1.34
Vreg1p2 Feedback
ADC0 channel 147
VDD/2.147
VDD/1.863
VDD / 2.045
VDD / 1.774
VDD/1.943
VDD/1.685
LVD 1.2 V
ADC0 channel 180
Vreg3p3 Feedback
ADC0 channel 181
Vreg3p3 /
5.733—
Vreg3p3 / 5.460 Vreg3p3 / 5.187
LVD 3.3 V
ADC0 channel 182
Vreg3p3 / 4.996 Vreg3p3 / 4.758 Vreg3p3 / 4.520
LVD 5.0 V
VDDREG / 4.996
VDDREG / 7.384
VDDREG / 4.520
VDDREG / 6.680
ADC0 channel 183
— LDO mode
— SMPS mode
VDDREG / 4.758
VDDREG/7.032
Table 21. Standby RAM Regulator Electrical Specifications
Spec
Characteristic
Symbol
Min
Typ
Max
Unit
Normal Mode
—
1
Standby Regulator Output
ADC1 channel 194
VADC194
1.2
—
—
V
2
Standby Source Bias
ADC1 channel 195
VADC195
150
360
mV
Table 22. ADC Band Gap Reference / LVI Electrical Specifications
Spec
Characteristic
Symbol
Min
Typ
Max
Unit
1
4.75 LVD (from VDDA
)
VADC196
—
4.75
—
V
ADC1 channel 196
2
ADC Bandgap
VADC45
—
1.220
—
V
ADC0 channel 45
ADC1 channel 45
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
29
Electrical Characteristics
Table 23. Temperature Sensor Electrical Specifications
Spec
Characteristic
Symbol
Min
Typ
Max
Unit
1
1
Slope
V
—
5.8
—
mV/ C
SADC128
–40 C to 100 C ±1.0 C
100 C to 150 C ±1.6 C
ADC0 channel 128
ADC1 channel 128
2
Accuracy
—
-20
—
+20
C
–40 C to 150 C
ADC0 channel 128
ADC1 channel 128
1
Slope is the measured voltage change per °C.
4.10 C90 Flash Memory Electrical Characteristics
Table 24. Flash Program and Erase Specifications (Pending Si characterization)
Initial
Max2
Lifetime
Spec
Characteristic
Symbol
Typ1
Unit
Max3
1
2
3
4
5
6
7
Double Word (64 bits) Program Time4
Page (128 bits) Program Time4
tdwprogram
tpprogram
38
45
—
500
500
s
s
160
16 KB Block Pre-program and Erase Time
48 KB Block Pre-program and Erase Time
64 KB Block Pre-program and Erase Time
128 KB Block Pre-program and Erase Time
256 KB Block Pre-program and Erase Time
t16kpperase
t48kpperase
t64kpperase
t128kpperase
t256kpperase
270
625
800
1500
3000
1000
1500
1800
2600
5200
5000
5000
5000
7500
15000
ms
ms
ms
ms
ms
1
2
3
4
Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 oC. These values are characterized, but not tested.
Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase
cycles, nominal supply values and operation at 25 oC. These values are verified at production test.
Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These values
are characterized, but not tested.
Program times are actual hardware programming times and do not include software overhead.
NOTE
The low, mid, and high address blocks of the flash arrays are erased (all bits set to 1) before
leaving the factory.
MPC5676R Microcontroller Data Sheet, Rev. 4
30
Freescale Semiconductor
Electrical Characteristics
1
Table 25. Flash Memory AC Timing Specifications
Parameter
Value
Symbol
Unit
Min
Typ
Max
TRES
TDONE
TPSRT
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low
—
—
100
ns
ns
s
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared
—
—
5
Time between program suspend resume and the next program
suspend request.2
100
—
—
—
—
TESRT
Time between erase suspend resume and the next erase
suspend request.3
10
ms
1
2
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by
completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish (MCR[DONE] = 1 during Program
operation). The minimum time between suspends to ensure this does notoccur is TPSRT
.
3
If Erase suspend rate is less than TESRT, an increase of slope voltage ramp occurs during erase pulse. This improves erase
time but reduces cycling figure due to overstress.
Table 26. Flash EEPROM Module Life
Spec
Characteristic
Symbol
Min
Typical1
Unit
1
Number of Program/Erase cycles per block for 16 KB and 64
KB blocks over the operating temperature range (TJ)
P/E
100,000
—
cycles
2
3
Number of Program/Erase cycles per block for 128 KB and
256 KB blocks over the operating temperature range (TJ)
P/E
1,000
100,000
—
cycles
years
Minimum Data Retention at 85 °C ambient temperature2
Blocks with 0–1,000 P/E cycles
Retention
20
10
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
1 – 5
1
Typical endurance is evaluated at 25 °C. Product qualification is performed to the minimum specification. For additional
information on the NXP definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for
Nonvolatile Memory.
2
Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
31
Electrical Characteristics
Table 27. BIUCR1/BIUCR3 Settings
Maximum Frequency
(MHz)
APC =
RWSC
Spec
WWSC DPFEN1 IPFEN1
PFLIM2
BFEN3
Core
fsys
Platform
fplatf
1
180 MHz
90 MHz
0b010
0b01
0b11
0b0
0b1
0b0
0b1
0b00
0b01
0b1x
0b0
0b1
Default setting after reset:
0b111
0b00
0b00
0b00
0b0
1
2
3
For maximum flash performance, set to 0b1.
For maximum flash performance, set to 0b10.
For maximum flash performance, set to 0b1.
4.11 AC Specifications
4.11.1 Clocking Modes
There are two main modes of operating frequency settings:
•
Double 2:1 (Core:Platform) Mode—the core is running at the system frequency setting while the platform and eTPU
are running at half the core frequency (system frequency divided by 2).
•
eTPU Mode—the core and eTPU are running at the system frequency setting while the platform is running at half the
core frequency (system frequency divided by 2).
Table 28 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings.
1, 2
Table 28. MPC5676R Block Operating Frequency
Double Mode Freq eTPU Mode Freq
Spec
Blocks
Symbol
(MHz)
(MHz)
1
Cores
fsys
fsys = 180
fsys = 180
(tcycsys = 1/fsys
)
2
Platform
fplatf
f
sys / 2
fsys / 2
(tcyc = 1/fplatf
)
3
4
eTPU
EBI
feTPU
fsys / 2
fsys / 4
fsys
febi
fsys / 4
1
2
The values in the table are specified at VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.5 V to 5.5 V, VDD33 and
VDDSYN = 3.0 V to 3.6 V, TA = TL to TH.
Up to the maximum frequency rating of the device (refer to Table 1). The fsys speed is the nominal maximum frequency.
MPC5676R Microcontroller Data Sheet, Rev. 4
32
Freescale Semiconductor
Electrical Characteristics
4.11.2 Pad AC Specifications
1
Table 29. Pad AC Specifications (V
= 5.0 V, V
= 3.3 V)
DDE
DDEH
Out Delay2,4
H/H L (ns)
Rise/Fall3,4
Load Drive
(pF)
Spec
Pad
SRC/DSC
L
(ns)
1
2
Medium5
00
152/165
205/220
28/34
70/74
96/96
12/15
28/31
5.3/5.9
22/22
50
200
50
3
01
11
4
52/59
200
50
5
12/12
6
32/32
200
10
7
Fast6
00
01
10
11
00
8
20
2.5
1.2
9
30
10
11
12
13
14
15
16
17
18
19
20
50
Fast with Slew Rate
40/40
50/50
13/13
19/19
8/8
16/16
21/21
5/5
50
200
50
01
10
11
8/8
200
50
2.4/2.4
5/5
12/12
5/5
200
50
1.1/1/1
2.6
8/8
200
50
Pull Up/Down (3.6 V max)
Pull Up/Down (5.25 V max)
—
—
—
7500
6000
5000/5000
50
1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH.
2
3
4
5
6
This parameter is supplied for reference and is not guaranteed by design and not tested.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock.
Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock.
1
Table 30. Derated Pad AC Specifications (V
= 3.3 V)
DDEH
Out Delay2,3
H/H L (ns)
Rise/Fall4,3
Load Drive
(pF)
Spec
Pad
SRC/DSC
L
(ns)
1
2
3
4
5
6
Medium5
00
200/210
270/285
37/45
86/86
120/120
15.5/19
38/43
50
200
50
01
11
69/82
200
50
18/17
7.6/8.5
30/34
46/49
200
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
33
Electrical Characteristics
1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
V
DD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH.
2
3
4
5
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock.
VDDEn / 2
VDDEHn / 2
Pad
Data Input
Rising
Edge
Falling
Edge
Output
Delay
Output
Delay
VOH
Pad
Output
VOL
Figure 7. Pad Output Delay
4.12 AC Timing
4.12.1 Generic Timing Diagrams
The generic timing diagrams in Figure 8 and Figure 9 apply to all I/O pins with pad types F and MH. See Table 39 for the pad
type for each pin.
MPC5676R Microcontroller Data Sheet, Rev. 4
34
Freescale Semiconductor
Electrical Characteristics
D_CLKOUT
VDDE / 2
A
B
I/O Outputs
VDDEn / 2
VDDEHn / 2
A – Maximum Output Delay Time
Figure 8. Generic Output Delay/Hold Timing
B – Minimum Output Hold Time
D_CLKOUT
VDDE / 2
B
A
I/O Inputs
VDDEn / 2
VDDEHn / 2
A – Minimum Input Setup Time
B – Minimum Input Hold Time
Figure 9. Generic Input Setup/Hold Timing
4.12.2 Reset and Configuration Pin Timing
1
Table 31. Reset and Configuration Pin Timing
Spec
Characteristic Symbol
Min
Max
Unit
2
2
2
2
1
2
3
4
RESET Pulse Width
tRPW
tGPW
tRCSU
tRCH
10
2
—
—
—
—
tcyc
tcyc
tcyc
tcyc
RESET Glitch Detect Pulse Width
PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid
PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid
10
0
1
Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.08 V to 1.32 V, TA = TL to TH.
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
35
Electrical Characteristics
2
See Notes on tcyc on Table 28.
2
RESET
1
RSTOUT
3
PLLCFG
BOOTCFG
WKPCFG
4
Figure 10. Reset and Configuration Pin Timing
4.12.3 IEEE 1149.1 Interface Timing
1
Table 32. JTAG Pin AC Electrical Characteristics
Spec
Characteristic
Symbol
Min
Max
Unit
1
2
TCK Cycle Time
tJCYC
tJDC
100
40
—
5
—
60
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK Clock Pulse Width (Measured at VDDE / 2)
TCK Rise and Fall Times (40%–70%)
TMS, TDI Data Setup Time
3
tTCKRISE
4
tTMSS, TDIS
TMSH, tTDIH
tTDOV
tTDOI
t
—
—
10
—
20
—
—
50
5
TMS, TDI Data Hold Time
t
25
—
0
6
TCK Low to TDO Data Valid
7
TCK Low to TDO Data Invalid
TCK Low to TDO High Impedance
JCOMP Assertion Time
8
tTDOHZ
tJCMPPW
tJCMPS
tBSDV
—
100
40
—
9
10
11
JCOMP Setup Time to TCK Low
TCK Falling Edge to Output Valid
MPC5676R Microcontroller Data Sheet, Rev. 4
36
Freescale Semiconductor
Electrical Characteristics
Table 32. JTAG Pin AC Electrical Characteristics (continued)
1
Spec
Characteristic
Symbol
Min
Max
Unit
12
13
14
15
TCK Falling Edge to Output Valid out of High Impedance
TCK Falling Edge to Output High Impedance
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
—
—
50
50
50
50
—
—
ns
ns
ns
ns
Boundary Scan Input Valid to TCK Rising Edge
TCK Rising Edge to Boundary Scan Input Invalid
1
JTAG timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and
CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 33 for
functional specifications.
TCK
2
3
2
3
1
Figure 11. JTAG Test Clock Input Timing
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
37
Electrical Characteristics
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 12. JTAG Test Access Port Timing
TCK
10
JCOMP
9
Figure 13. JTAG JCOMP Timing
MPC5676R Microcontroller Data Sheet, Rev. 4
38
Freescale Semiconductor
Electrical Characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 14. JTAG Boundary Scan Timing
4.12.4 Nexus Timing
1
Table 33. Nexus Debug Port Timing
Spec
Characteristic
Symbol
Min
Max
Unit
1
2
3
4
5
6
7
8
9
MCKO Cycle Time
tMCYC
tMDC
22
40
8
tCYC
%
MCKO Duty Cycle
60
0.2
0.2
0.2
—
MCKO Low to MDO Data Valid3
MCKO Low to MSEO Data Valid3
MCKO Low to EVTO Data Valid3
EVTI Pulse Width
tMDOV
–0.1
–0.1
–0.1
4.0
1
tMCYC
tMCYC
tMCYC
tTCYC
tMCYC
tCYC
%
tMSEOV
tEVTOV
tEVTIPW
tEVTOPW
tTCYC
EVTO Pulse Width
—
TCK Cycle Time
44
—
TCK Duty Cycle
tTDC
40
60
—
10 TDI, TMS Data Setup Time
t
NTDIS, tNTMSS
8
ns
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
39
Electrical Characteristics
Spec
1
Table 33. Nexus Debug Port Timing (continued)
Characteristic
Symbol
TNTDIH, NTMSH
tNTDOV
—
Min
Max
Unit
11 TDI, TMS Data Hold Time
12 TCK Low to TDO Data Valid
13 RDY Valid to MCKO5
t
5
0
—
10
—
—
ns
ns
—
ns
—
1
14 TDO hold time after TCLK low
tNTDOH
1
2
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified
at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with
DSC = 0b10.
The Nexus AUX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending
on the system frequency, not to exceed maximum Nexus AUX port frequency.
3
4
5
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
Lower frequency is required to be fully compliant to standard.
The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.
1
2
MCKO
3
4
5
MDO
Output Data Valid
7
MSEO
EVTO
6
EVTI
Figure 15. Nexus Timings
MPC5676R Microcontroller Data Sheet, Rev. 4
40
Freescale Semiconductor
Electrical Characteristics
8
9
TCK
10
11
TMS, TDI
14
12
TDO
Figure 16. Nexus TCK, TDI, TMS, TDO Timing
4.12.5 External Bus Interface (EBI) Timing
1
Table 34. Bus Operation Timing
66 MHz (Ext. Bus Freq)2 3
Spec
Characteristic
D_CLKOUT Period
Symbol
Unit
Notes
Min
Max
1
tC
15.2
—
ns Signals are measured at 50% VDDE
.
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
41
Electrical Characteristics
1
Table 34. Bus Operation Timing (continued)
66 MHz (Ext. Bus Freq)2 3
Spec
Characteristic
Symbol
Unit
Notes
Min
Max
2
3
4
5
D_CLKOUT Duty Cycle
D_CLKOUT Rise Time
D_CLKOUT Fall Time
tCDC
tCRT
tCFT
tCOH
45%
—
55%
tC
ns
ns
4
—
4
—
—
D_CLKOUT Posedge to Output
Signal Invalid or High Z (Hold Time)
1.0/1.5
—
ns Hold time selectable via
SIU_ECCR[EBTS] bit:
EBTS = 0: 1.0 ns
D_ADD[9:30]
D_BDIP
EBTS = 1: 1.5 ns
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
6
D_CLKOUT Posedge to Output
Signal Valid (Output Delay)
tCOV
—
8.5/9.0
ns Output valid time selectable via
SIU_ECCR[EBTS] bit:
EBTS = 0: 8.5 ns
D_ADD[9:30]
D_BDIP
EBTS = 1: 9.0 ns
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
7
8
9
Input Signal Valid to D_CLKOUT
Posedge (Setup Time)
tCIS
5.0/4.5
—
ns Input setup time selectable via
SIU_ECCR[EBTS] bit:
EBTS = 0; 5.0ns
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
EBTS = 1; 4.5ns
D_TS
D_CLKOUT Posedge to Input
Signal Invalid (Hold Time)
tCIH
1.0
—
ns
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
D_ALE Pulse Width
tAPW
tAAI
6.5
—
—
ns The timing is for Asynchronous
external memory system.
10 D_ALE Negated to Address Invalid
2.0/1.0 5
ns The timing is for Asynchronous
external memory system.
ALE is measured at 50% of VDDE.
MPC5676R Microcontroller Data Sheet, Rev. 4
42
Freescale Semiconductor
Electrical Characteristics
1
EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and
CL = 30 pF with DSC = 0b10.
2
3
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency.
The maximum external bus frequency is 66 MHz.
4
5
Refer to Fast pad timing in Table 29 and Table 30.
ALE hold time spec is temperature dependant. 1.0ns spec applies for temperature range -40 to 0 C. 2.0ns spec applies to
temperatures > 0 C. This spec has no dependency on SIU_ECCR[EBTS] bit.
VOH_F
VDDE / 2
VOL_F
D_CLKOUT
2
3
2
4
1
Figure 17. D_CLKOUT Timing
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
43
Electrical Characteristics
VDDE / 2
D_CLKOUT
6
5
5
Output
Bus
VDDE / 2
6
5
5
Output
Signal
VDDE / 2
6
Output
Signal
VDDE / 2
Figure 18. Synchronous Output Timing
MPC5676R Microcontroller Data Sheet, Rev. 4
44
Freescale Semiconductor
Electrical Characteristics
D_CLKOUT
VDDE / 2
7
8
Input
Bus
VDDE / 2
7
8
Input
Signal
VDDE / 2
Figure 19. Synchronous Input Timing
ipg_clk
D_CLKOUT
D_ALE
D_TS
D_ADD/D_DAT
DATA
ADDR
9
10
Figure 20. ALE Signal Timing
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
45
Electrical Characteristics
4.12.6 External Interrupt Timing (IRQ Pin)
1
Table 35. External Interrupt Timing
Spec
Characteristic
IRQ Pulse Width Low
Symbol
Min
Max
Unit
2
1
2
3
tIPWL
tIPWH
tICYC
3
3
6
—
—
—
tcyc
2
IRQ Pulse Width High
IRQ Edge to Edge Time3
tcyc
2
tcyc
1
IRQ timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL
to TH.
2
3
See Notes on tcyc Table 28.
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
IRQ
2
1
3
Figure 21. External Interrupt Timing
4.12.7 eTPU Timing
1
Table 36. eTPU Timing
Spec
Characteristic
Symbol
Min
Max
Unit
2
1
2
eTPU Input Channel Pulse Width
eTPU Output Channel Pulse Width
tICPW
4
13
—
—
tcyc
2
tOCPW
tcyc
1
eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH,
and CL = 200 pF with SRC = 0b00.
2
3
See Notes on tcyc Table 28.
This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
MPC5676R Microcontroller Data Sheet, Rev. 4
46
Freescale Semiconductor
Electrical Characteristics
eTPU Input
and TCRCLK
1
2
eTPU
Output
Figure 22. eTPU Timing
4.12.8 eMIOS Timing
1
Table 37. eMIOS Timing
Spec
Characteristic
Symbol
Min
Max
Unit
2
1
2
eMIOS Input Pulse Width
eMIOS Output Pulse Width
tMIPW
4
13
—
—
tcyc
2
tMOPW
tcyc
1
eMIOS timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH,
and CL = 50 pF with SRC = 0b00.
2
3
See Notes on tcyc on Table 28.
This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
47
Electrical Characteristics
eMIOS Input
1
2
eMIOS
Output
Figure 23. eMIOS Timing
4.12.9 DSPI Timing
1,2
Table 38. DSPI Timing
Peripheral Bus Freq:
92 MHz
Spec
Characteristic
Symbol
Unit
Min
Max
1
DSPI Cycle Time3, 4
Master (MTFE = 0)
Slave (MTFE = 0)
Master (MTFE = 1)
Slave (MTFE = 1)
tSCK
23.8
1800
ns
2
3
4
5
PCS to SCK Delay5
After SCK Delay6
SCK Duty Cycle
tCSC
tASC
tSDC
tA
12
12
—
—
ns
ns
ns
ns
0.4 * tSCK
—
0.6 * tSCK
25
Slave Access Time
(SS active to SOUT valid)
6
Slave SOUT Disable Time
tDIS
—
25
ns
(SS inactive to SOUT High-Z or invalid)
7
8
PCSx to PCSS time
PCSS to PCSx time
tPCSC
tPASC
4
5
—
—
ns
ns
MPC5676R Microcontroller Data Sheet, Rev. 4
48
Freescale Semiconductor
Electrical Characteristics
1,2
Table 38. DSPI Timing (continued)
Peripheral Bus Freq:
92 MHz
Spec
Characteristic
Symbol
Unit
Min
Max
9
Data Setup Time for Inputs
Master (MTFE = 0)
tSUI
27
10
7
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
27
10
11
Data Hold Time for Inputs
Master (MTFE = 0)
tHI
–3
7
12
–3
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
Data Valid (after SCK edge)
Master (MTFE = 0)
tSUO
—
—
—
—
—
10
30
20
10
5
ns
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (LVDS)
12
Data Hold Time for Outputs
Master (MTFE = 0)
tHO
–6
2.5
3
–7
–5
—
—
—
—
—
ns
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (LVDS)
1
2
DSPI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, and TA = TL to TH
Speed is the nominal maximum frequency of platform clock (fplatf). Max speed is the maximum speed allowed including
frequency modulation (FM).
3
The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two devices communicating over a DSPI link.
4
5
6
7
The actual minimum SCK cycle time is limited by pad performance.
The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
This number is calculated assuming the SMPL_PT bit-field in DSPI_MCR is set to 0b10.
The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.
DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high
speed operation.
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
49
Electrical Characteristics
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Figure 24. DSPI Classic SPI Timing — Master, CPHA = 0
2
3
PCSx
4
1
SCK Output
(CPOL=0)
4
10
SCK Output
(CPOL=1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Figure 25. DSPI Classic SPI Timing — Master, CPHA = 1
MPC5676R Microcontroller Data Sheet, Rev. 4
50
Freescale Semiconductor
Electrical Characteristics
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Figure 26. DSPI Classic SPI Timing — Slave, CPHA = 0
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Figure 27. DSPI Classic SPI Timing — Slave, CPHA = 1
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
51
Electrical Characteristics
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
10
SIN
First Data
12
Last Data
Last Data
Data
11
SOUT
First Data
Data
Figure 28. DSPI Modified Transfer Format Timing — Master, CPHA = 0
3
PCSx
1
4
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Figure 29. DSPI Modified Transfer Format Timing — Master, CPHA = 1
MPC5676R Microcontroller Data Sheet, Rev. 4
52
Freescale Semiconductor
Electrical Characteristics
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Figure 30. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
First Data
10
Data
SOUT
SIN
9
First Data
Data
Last Data
Figure 31. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
53
Electrical Characteristics
8
7
PCSS
PCSx
Figure 32. DSPI PCS Strobe (PCSS) Timing
MPC5676R Microcontroller Data Sheet, Rev. 4
54
Freescale Semiconductor
Package Information
5
Package Information
5.1
416-Pin Package
The package drawings of the 416-pin TEPBGA package are shown in Figure 33 and Figure 34.
Figure 33. 416 TEPBGA Package (1 of 2)
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
55
Package Information
Figure 34. 416 TEPBGA Package (2 of 2)
MPC5676R Microcontroller Data Sheet, Rev. 4
56
Freescale Semiconductor
Package Information
5.2
516-Pin Package
The package drawings of the 516-pin TEPBGA package are shown in Figure 35 and Figure 36.
Figure 35. 516 TEPBGA Package (1 of 2)
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
57
Package Information
Figure 36. 516 TEPBGA Package (2 of 2)
MPC5676R Microcontroller Data Sheet, Rev. 4
58
Freescale Semiconductor
Product Documentation
6
Product Documentation
This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these
types are available at: http://www.nxp.com.
The following documents are required for a complete description of the device and are necessary to design properly with the
parts:
•
MPC5676R RM Microprocessor Reference Manual (document number MPC5676RRM)
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
59
Appendix A Signal Properties and Muxing
The following table shows the signals properties for each pin on the MPC5676R. For each port pin that has an associated SIU_PCRn register to control its pin
properties, the supported functions column lists the functions associated with the programming of the SIU_PCRn[PA] bit in the order: Primary function (P),
Function 2 (F2), Function 3 (F3), and GPIO (G). See Figure 37.
U
Table 2. Signal Properties and Muxing Summar
P/
GPIO/
PCR1
F/
G
Pad
I/O Type
Signal Name2
Function3
TCRCLKA
Function Summary
Primary Functions
are listed First
P
113 TCRCLKA_IRQ7_GPIO113
eTPU A TCR clock
I
I
5V M
A1
A2
G
IRQ7
—
External interrupt request
Secondary Functions
are alternate functions
—
—
I/O
GPIO Functions are
GPIO113
GPIO
listed Last
Function not implemented on this device
Figure 37. Supported Functions Example
Table 39. Signal Properties and Muxing Summary
Package
Location
State
Stateduring
RESET7
Signal Name2
Function4
Function Summary
eTPU_A
after
RESET8
P
113 TCRCLKA_IRQ7_
GPIO113
TCRCLKA
IRQ7
eTPU A TCR clock
I
MH
MH
VDDEH1
—/Up
—/Up
L1
L2
K4
L6
A1
A2
G
External interrupt request
I
—
—
—
I/O
I/O
O
GPIO113
ETPUA0
ETPUA12
—
GPIO
P
114 ETPUA0_ETPUA12_
GPIO114
eTPU A channel
VDDEH1
—/WKPCFG
—/WKPCFG
A1
A2
G
eTPU A channel (output only)
—
—
I/O
GPIO114
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
115 ETPUA1_ETPUA13_
GPIO115
ETPUA1
eTPU A channel
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
L3
L4
K1
K2
K3
K4
J1
J2
A1
A2
G
ETPUA13
—
eTPU A channel (output only)
—
—
GPIO115
ETPUA2
ETPUA14
—
GPIO
I/O
I/O
O
P
116 ETPUA2_ETPUA14_
GPIO116
eTPU A channel
A1
A2
G
eTPU A channel (output only)
—
—
GPIO116
ETPUA3
ETPUA15
—
GPIO
I/O
I/O
O
P
117 ETPUA3_ETPUA15_
GPIO117
eTPU A channel
H4
J4
A1
A2
G
eTPU A channel (output only)
—
—
GPIO117
ETPUA4
ETPUA16
—
GPIO
I/O
I/O
O
P
118 ETPUA4_ETPUA16_
GPIO118
eTPU A channel
A1
A2
G
eTPU A channel (output only)
—
—
GPIO118
ETPUA5
ETPUA17
—
GPIO
I/O
I/O
O
P
119 ETPUA5_ETPUA17_
GPIO119
eTPU A channel
H1
K5
A1
A2
G
eTPU A channel (output only)
—
—
GPIO119
ETPUA6
ETPUA18
—
GPIO
I/O
I/O
O
P
120 ETPUA6_ETPUA18_
GPIO120
eTPU A channel
A1
A2
G
eTPU A channel (output only)
—
—
GPIO120
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
121 ETPUA7_ETPUA19_
GPIO121
ETPUA7
eTPU A channel
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
J1
J2
J3
J4
H1
H2
H2
H3
J3
A1
A2
G
ETPUA19
—
eTPU A channel (output only)
—
—
GPIO121
ETPUA8
ETPUA20
—
GPIO
I/O
I/O
O
P
122 ETPUA8_ETPUA20_
GPIO122
eTPU A channel
A1
A2
G
eTPU A channel (output only)
—
—
GPIO122
ETPUA9
ETPUA21
—
GPIO
I/O
I/O
O
P
123 ETPUA9_ETPUA21_
GPIO123
eTPU A channel
A1
A2
G
eTPU A channel (output only)
—
—
GPIO123
ETPUA10
ETPUA22
—
GPIO
I/O
I/O
O
P
124 ETPUA10_ETPUA22_
GPIO124
eTPU A channel
K6
G1
J5
A1
A2
G
eTPU A channel (output only)
—
—
GPIO124
ETPUA11
ETPUA23
—
GPIO
I/O
I/O
O
P
125 ETPUA11_ETPUA23_
GPIO125
eTPU A channel
A1
A2
G
eTPU A channel (output only)
—
—
GPIO125
ETPUA12
PCSB1
—
GPIO
I/O
I/O
O
P
126 ETPUA12_PCSB1_
GPIO126
eTPU A channel
A1
A2
G
DSPI B peripheral chip select
—
—
GPIO126
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
127 ETPUA13_PCSB3_
GPIO127
ETPUA13
eTPU A channel
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
H4
H3
G1
G2
G3
G4
G2
H5
G3
H6
G4
G5
A1
A2
G
PCSB3
—
DSPI B peripheral chip select
—
—
GPIO127
ETPUA14
PCSB4
—
GPIO
I/O
I/O
O
P
128 ETPUA14_PCSB4_
GPIO128
eTPU A channel
A1
A2
G
DSPI B peripheral chip select
—
—
GPIO128
ETPUA15
PCSB5
—
GPIO
I/O
I/O
O
P
129 ETPUA15_PCSB5_
GPIO129
eTPU A channel
A1
A2
G
DSPI B peripheral chip select
—
—
GPIO129
ETPUA16
PCSD1
—
GPIO
I/O
I/O
O
P
130 ETPUA16_PCSD1_
GPIO130
eTPU A channel
A1
A2
G
DSPI D peripheral chip select
—
—
GPIO130
ETPUA17
PCSD2
—
GPIO
I/O
I/O
O
P
131 ETPUA17_PCSD2_
GPIO131
eTPU A channel
A1
A2
G
DSPI D peripheral chip select
—
—
GPIO131
ETPUA18
PCSD3
—
GPIO
I/O
I/O
O
P
132 ETPUA18_PCSD3_
GPIO132
eTPU A channel
A1
A2
G
DSPI D peripheral chip select
—
—
GPIO132
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
133 ETPUA19_PCSD4_
GPIO133
ETPUA19
eTPU A channel
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
F1
F2
F3
F4
E1
E2
F1
F2
F3
F4
E1
E2
A1
A2
G
PCSD4
—
DSPI D peripheral chip select
—
—
I/O
I/O
I
GPIO133
ETPUA20
IRQ8
GPIO
P
134 ETPUA20_IRQ8_
GPIO134
eTPU A channel
A1
A2
G
External interrupt request
—
—
—
I/O
I/O
I
GPIO134
ETPUA21
IRQ9
GPIO
P
135 ETPUA21_IRQ9_
GPIO135
eTPU A channel
A1
A2
G
External interrupt request
—
—
—
I/O
I/O
I
GPIO135
ETPUA22
IRQ10
—
GPIO
P
136 ETPUA22_IRQ10_
GPIO136
eTPU A channel
A1
A2
G
External interrupt request
—
—
I/O
I/O
I
GPIO136
ETPUA23
IRQ11
—
GPIO
P
137 ETPUA23_IRQ11_
GPIO137
eTPU A channel
A1
A2
G
External interrupt request
—
—
I/O
I/O
I
GPIO137
ETPUA24
IRQ12
—
GPIO
P
138 ETPUA24_IRQ12_
GPIO138
eTPU A channel
A1
A2
G
External interrupt request
—
—
I/O
GPIO138
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
139 ETPUA25_IRQ13_
GPIO139
ETPUA25
eTPU A channel
I/O
I
MH
MH
MH
MH
MH
MH
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
E3
E4
D1
D2
D3
C1
E3
E4
D1
D2
D3
C1
A1
A2
G
IRQ13
—
External interrupt request
—
—
I/O
I/O
I
GPIO139
ETPUA26
IRQ14
—
GPIO
P
140 ETPUA26_IRQ14_
GPIO140
eTPU A channel
A1
A2
G
External interrupt request
—
—
I/O
I/O
I
GPIO140
ETPUA27
IRQ15
—
GPIO
P
141 ETPUA27_IRQ15_
GPIO141
eTPU A channel
A1
A2
G
External interrupt request
—
—
I/O
I/O
O
GPIO141
ETPUA28
PCSC1
—
GPIO
P
142 ETPUA28_PCSC1_
GPIO142
eTPU A channel
A1
A2
G
DSPI C peripheral chip select
—
—
I/O
I/O
O
GPIO142
ETPUA29
PCSC2
—
GPIO
P
143 ETPUA29_PCSC2_
GPIO143
eTPU A channel
A1
A2
G
DSPI C peripheral chip select
—
—
I/O
I/O
O
GPIO143
ETPUA30
PCSC3
—
GPIO
P
144 ETPUA30_PCSC3_
GPIO144
eTPU A channel
A1
A2
G
DSPI C peripheral chip select
—
—
I/O
GPIO144
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
145 ETPUA31_PCSC4_
GPIO145
ETPUA31
eTPU A channel
I/O
O
MH
VDDEH1
—/WKPCFG
—/WKPCFG
C2
C2
A1
A2
G
PCSC4
—
DSPI C peripheral chip select
—
—
GPIO145
GPIO
I/O
eTPU_B
P
146 TCRCLKB_IRQ6_
GPIO146
TCRCLKB
IRQ6
eTPU B TCR clock
I
MH
MH
MH
MH
MH
VDDEH6
VDDEH6
VDDEH6
VDDEH6
VDDEH6
—/Up
—/Up
T23
T24
T25
T26
R23
V25
V26
U22
U23
T22
A1
A2
G
External interrupt request
I
—
—
—
I/O
I/O
O
GPIO146
ETPUB0
ETPUB16
—
GPIO
P
147 ETPUB0_ETPUB16_
GPIO147
eTPU B channel
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
A1
A2
G
eTPU B channel (output only)
—
—
I/O
I/O
O
GPIO147
ETPUB1
ETPUB17
—
GPIO
P
148 ETPUB1_ETPUB17_
GPIO148
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
I/O
I/O
O
GPIO148
ETPUB2
ETPUB18
—
GPIO
P
149 ETPUB2_ETPUB18_
GPIO149
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
I/O
I/O
O
GPIO149
ETPUB3
ETPUB19
—
GPIO
P
150 ETPUB3_ETPUB19_
GPIO150
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
I/O
GPIO150
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
151 ETPUB4_ETPUB20_
GPIO151
ETPUB4
eTPU B channel
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH6
VDDEH6
VDDEH6
VDDEH6
VDDEH6
VDDEH6
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
R24
R25
R26
P23
P24
P25
U24
U25
U26
T23
T24
R22
A1
A2
G
ETPUB20
—
eTPU B channel (output only)
—
—
GPIO151
ETPUB5
ETPUB21
—
GPIO
I/O
I/O
O
P
152 ETPUB5_ETPUB21_
GPIO152
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
GPIO152
ETPUB6
ETPUB22
—
GPIO
I/O
I/O
O
P
153 ETPUB6_ETPUB22_
GPIO153
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
GPIO153
ETPUB7
ETPUB23
—
GPIO
I/O
I/O
O
P
154 ETPUB7_ETPUB23_
GPIO154
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
GPIO154
ETPUB8
ETPUB24
—
GPIO
I/O
I/O
O
P
155 ETPUB8_ETPUB24_
GPIO155
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
GPIO155
ETPUB9
ETPUB25
—
GPIO
I/O
I/O
O
P
156 ETPUB9_ETPUB25_
GPIO156
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
GPIO156
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
157 ETPUB10_ETPUB26_
GPIO157
ETPUB10
eTPU B channel
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH6
VDDEH6
VDDEH6
VDDEH6
VDDEH6
VDDEH6
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
P26
N24
N25
N26
M25
M24
T25
T26
R23
P22
R24
R25
A1
A2
G
ETPUB26
—
eTPU B channel (output only)
—
—
GPIO157
ETPUB11
ETPUB27
—
GPIO
I/O
I/O
O
P
158 ETPUB11_ETPUB27_
GPIO158
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
GPIO158
ETPUB12
ETPUB28
—
GPIO
I/O
I/O
O
P
159 ETPUB12_ETPUB28_
GPIO159
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
GPIO159
ETPUB13
ETPUB29
—
GPIO
I/O
I/O
O
P
160 ETPUB13_ETPUB29_
GPIO160
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
GPIO160
ETPUB14
ETPUB30
—
GPIO
I/O
I/O
O
P
161 ETPUB14_ETPUB30_
GPIO161
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
GPIO161
ETPUB15
ETPUB31
—
GPIO
I/O
I/O
O
P
162 ETPUB15_ETPUB31_
GPIO162
eTPU B channel
A1
A2
G
eTPU B channel (output only)
—
—
GPIO162
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
163 ETPUB16_PCSA1_
GPIO163
ETPUB16
eTPU B channel
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH6
VDDEH6
VDDEH6
VDDEH6
VDDEH6
VDDEH6
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
U26
U25
U24
U23
V26
V25
V24
T21
A1
A2
G
PCSA1
—
DSPI A peripheral chip select
—
—
GPIO163
ETPUB17
PCSA2
—
GPIO
I/O
I/O
O
P
164 ETPUB17_PCSA2_
GPIO164
eTPU B channel
A1
A2
G
DSPI A peripheral chip select
—
—
GPIO164
ETPUB18
PCSA3
—
GPIO
I/O
I/O
O
P
165 ETPUB18_PCSA3_
GPIO165
eTPU B channel
W26
W25
W24
V22
A1
A2
G
DSPI A peripheral chip select
—
—
GPIO165
ETPUB19
PCSA4
—
GPIO
I/O
I/O
O
P
166 ETPUB19_PCSA4_
GPIO166
eTPU B channel
A1
A2
G
DSPI A peripheral chip select
—
—
GPIO166
ETPUB20
—
GPIO
I/O
I/O
—
P
167 ETPUB20_
GPIO167
eTPU B channel
A1
A2
G
—
—
—
—
GPIO167
ETPUB21
—
GPIO
I/O
I/O
—
P
168 ETPUB21_
GPIO168
eTPU B channel
A1
A2
G
—
—
—
—
GPIO168
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
169 ETPUB22_
ETPUB22
eTPU B channel
I/O
—
MH
MH
MH
MH
MH
MH
VDDEH6
VDDEH6
VDDEH6
VDDEH6
VDDEH6
VDDEH6
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
V24
W26
W25
V23
U21
Y25
GPIO169
A1
A2
G
—
—
—
—
—
GPIO169
ETPUB23
—
GPIO
I/O
I/O
—
P
170 ETPUB23_
GPIO170
eTPU B channel
A1
A2
G
—
—
—
—
GPIO170
ETPUB24
—
GPIO
I/O
I/O
—
P
171 ETPUB24_
GPIO171
eTPU B channel
A1
A2
G
—
—
—
—
GPIO171
ETPUB25
—
GPIO
I/O
I/O
—
P
172 ETPUB25_
GPIO172
eTPU B channel
W24 W21
A1
A2
G
—
—
—
—
GPIO172
ETPUB26
—
GPIO
I/O
I/O
—
P
173 ETPUB26_
GPIO173
eTPU B channel
V23
Y25
Y23
Y24
A1
A2
G
—
—
—
—
GPIO173
ETPUB27
—
GPIO
I/O
I/O
—
P
174 ETPUB27_
GPIO174
eTPU B channel
A1
A2
G
—
—
—
—
GPIO174
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
175 ETPUB28_
ETPUB28
eTPU B channel
I/O
—
MH
MH
MH
MH
VDDEH6
VDDEH6
VDDEH6
VDDEH6
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
Y24 AA24
GPIO175
A1
A2
G
—
—
—
—
—
GPIO175
ETPUB29
—
GPIO
I/O
I/O
—
P
176 ETPUB29_
GPIO176
eTPU B channel
—/WKPCFG
Y23
W22
A1
A2
G
—
—
—
—
GPIO176
ETPUB30
—
GPIO
I/O
I/O
—
P
177 ETPUB30_
GPIO177
eTPU B channel
—/WKPCFG AA24 AB24
A1
A2
G
—
—
—
—
GPIO177
ETPUB31
—
GPIO
I/O
I/O
—
P
178 ETPUB31_
GPIO178
eTPU B channel
—/WKPCFG AB24 Y22
A1
A2
G
—
—
—
—
GPIO178
GPIO
I/O
eTPU_C
P
440 TCRCLKC_
GPIO440
TCRCLKC
—
eTPU C TCR clock
I
MH
MH
VDDEH7
—/Up
—/Up
B26
C25
F22
C25
A1
A2
G
—
—
—
—
—
GPIO440
ETPUC0
—
GPIO
I/O
I/O
—
P
441 ETPUC0_
GPIO441
eTPU C channel
VDDEH7
—/WKPCFG
—/WKPCFG
A1
A2
G
—
—
—
—
GPIO441
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
442 ETPUC1_
ETPUC1
eTPU C channel
I/O
—
MH
MH
MH
MH
MH
MH
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
C26
D25
D26
E24
E25
E26
C26
D25
D26
E24
E25
E26
GPIO442
A1
A2
G
—
—
—
—
—
GPIO442
ETPUC2
—
GPIO
I/O
I/O
—
P
443 ETPUC2_
GPIO443
eTPU C channel
A1
A2
G
—
—
—
—
GPIO443
ETPUC3
—
GPIO
I/O
I/O
—
P
444 ETPUC3_
GPIO444
eTPU C channel
A1
A2
G
—
—
—
—
GPIO444
ETPUC4
GPIO
I/O
I/O
P
445 ETPUC4_
eTPU C channel
PCSE1_GPIO445
A1
A2
G
DSPI E peripheral chip select
—
—
—
I/O
I/O
GPIO445
ETPUC5
GPIO
P
446 ETPUC5_
PCSE2_GPIO446
eTPU C channel
A1
A2
G
DSPI E peripheral chip select
—
—
—
I/O
I/O
GPIO446
ETPUC6
GPIO
P
447 ETPUC6_
PCSE3_GPIO447
eTPU C channel
A1
A2
G
DSPI E peripheral chip select
—
—
—
GPIO447
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
448 ETPUC7_
PCSE4_GPIO448
ETPUC7
eTPU C channel
I/O
MH
MH
MH
MH
MH
MH
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
F23
F24
F25
F26
G23
G24
F23
F24
F25
F26
G22
G23
A1
A2
G
DSPI E peripheral chip select
—
—
—
I/O
I/O
GPIO448
ETPUC8
GPIO
P
449 ETPUC8_
PCSE5_GPIO449
eTPU C channel
A1
A2
G
DSPI E peripheral chip select
—
—
—
I/O
I/O
I
GPIO449
ETPUC9
IRQ0
GPIO
P
450 ETPUC9_IRQ0_
GPIO450
eTPU C channel
A1
A2
G
External interrupt request
—
—
—
I/O
I/O
I
GPIO450
ETPUC10
IRQ1
GPIO
P
451 ETPUC10__IRQ1_
GPIO451
eTPU C channel
A1
A2
G
External interrupt request
—
—
—
I/O
I/O
I
GPIO451
ETPUC11
IRQ2
GPIO
P
452 ETPUC11_IRQ2_
GPIO452
eTPU C channel
A1
A2
G
External interrupt request
—
—
—
I/O
I/O
I
GPIO452
ETPUC12
IRQ3
GPIO
P
453 ETPUC12_IRQ3_
GPIO453
eTPU C channel
A1
A2
G
External interrupt request
—
—
—
I/O
GPIO453
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
454 ETPUC13_3_IRQ4_
GPIO454
ETPUC13
eTPU C channel
I/O
I
MH
MH
MH
MH
MH
MH
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
G25
G26
H23
H24
H25
H26
G24
G25
G26
H22
H23
H24
A1
A2
G
IRQ4
External interrupt request
—
—
—
I/O
I/O
I
GPIO454
ETPUC14
IRQ5
GPIO
P
455 ETPUC14_4_IRQ5_
GPIO455
eTPU C channel
A1
A2
G
External interrupt request
—
—
—
I/O
I/O
—
—
I/O
I/O
O
GPIO455
ETPUC15
—
GPIO
P
456 ETPUC15__
GPIO456
eTPU C channel
A1
A2
G
—
—
—
GPIO456
ETPUC16
FR_A_TX
—
GPIO
P
457 ETPUC16_FR_A_TX_
GPIO457
eTPU C channel
A1
A2
G
FlexRay A transfer
—
—
I/O
I/O
I
GPIO457
ETPUC17
FR_A_RX
—
GPIO
P
458 ETPUC17_FR_A_RX_
GPIO458
eTPU C channel
A1
A2
G
FlexRay A receive
—
—
I/O
I/O
O
GPIO458
ETPUC18
FR_A_TX_EN
—
GPIO
P
459 ETPUC18_FR_A_TX_EN_
GPIO459
eTPU C channel
A1
A2
G
FlexRay A transfer enable
—
—
I/O
GPIO459
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
460 ETPUC19_TXDA_
GPIO460
ETPUC19
eTPU C channel
I/O
O
MH
MH
MH
MH
MH
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
J23
J24
J25
J26
K23
H21
H25
H26
J22
J23
A1
A2
G
TXDA
eSCI A transmit
—
—
—
I/O
I/O
I
GPIO460
ETPUC20
RXDA
GPIO
P
461 ETPUC20_RXDA _
GPIO461
eTPU C channel
eSCI A receive
—
A1
A2
G
—
—
I/O
I/O
O
GPIO461
ETPUC21
TXDB
GPIO
P
462 ETPUC21_TXDB_
GPIO462
eTPU C channel
eSCI B transmit
—
A1
A2
G
—
—
I/O
I/O
I
GPIO462
ETPUC22
RXDB
GPIO
P
463 ETPUC22_RXDB_
GPIO463
eTPU C channel
eSCI B receive
—
A1
A2
G
—
—
I/O
I/O
O
GPIO463
ETPUC23
PCSD5
MAA0
GPIO
P
464 ETPUC23_PCSD5_
GPIO464
eTPU C channel
DSPI D peripheral chip select
ADC A Mux Address 0
ADC B Mux Address 0
GPIO
A1
A2
A3
G
O
MAB0
O
GPIO464
ETPUC24
PCSD4
MAA1
I/O
I/O
O
P
465 ETPUC24_PCSD4_
GPIO465
eTPU C channel
DSPI D peripheral chip select
ADC A Mux Address 1
ADC B Mux Address 1
GPIO
MH
VDDEH7
—/WKPCFG
—/WKPCFG
K24
J24
A1
A2
A4
G
O
MAB1
O
GPIO465
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
466 ETPUC25_PCSD3_
GPIO466
ETPUC25
eTPU C channel
I/O
O
MH
VDDEH7
—/WKPCFG
—/WKPCFG
K25
K21
A1
A2
A3
G
PCSD3
MAA2
DSPI D peripheral chip select
ADC A Mux Address 2
O
MAB2
ADC B Mux Address 2
O
GPIO466
ETPUC26
PCSD2
—
GPIO
I/O
I/O
O
P
467 ETPUC26_PCSD2_
GPIO467
eTPU C channel
MH
MH
MH
MH
MH
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
K26
L23
L24
L25
L26
J25
J26
K22
K23
K24
A1
A2
G
DSPI D peripheral chip select
—
—
GPIO467
ETPUC27
PCSD1
—
GPIO
I/O
I/O
O
P
468 ETPUC27_PCSD1_
GPIO468
eTPU C channel
A1
A2
G
DSPI D peripheral chip select
—
—
GPIO468
ETPUC28
PCSD0
—
GPIO
I/O
I/O
O
P
469 ETPUC28_PCSD0_
GPIO469
eTPU C channel
A1
A2
G
DSPI D peripheral chip select
—
—
GPIO469
ETPUC29
SCKD
GPIO
I/O
I/O
I/O
—
P
470 ETPUC29_SCKD_
GPIO470
eTPU C channel
DSPI D clock
—
A1
A2
G
—
GPIO470
ETPUC30
SOUTD
—
GPIO
I/O
I/O
O
P
471 ETPUC30_SOUTD_
GPIO471
eTPU C channel
DSPI D data output
—
A1
A2
G
—
GPIO471
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
472 ETPUC31_SIND_
ETPUC31
eTPU C channel
I/O
I
MH
VDDEH7
—/WKPCFG
—/WKPCFG
M23
K25
GPIO472
A1
A2
G
SIND
—
DSPI D data input
—
—
I/O
GPIO472
GPIO
eMIOS
P
179 EMIOS0_ETPUA0_
GPIO179
EMIOS0
ETPUA0
—
eMIOS channel
eTPU A channel
—
I/O
O
MH
MH
MH
MH
MH
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG AE10 AC13
—/WKPCFG AF10 AB13
—/WKPCFG AD11 AD13
—/WKPCFG AE11 AE13
—/WKPCFG AF11 AF13
A1
A2
G
—
GPIO179
EMIOS1
ETPUA1
—
GPIO
I/O
I/O
O
P
180 EMIOS1_ETPUA1_
GPIO180
eMIOS channel
eTPU A channel
—
A1
A2
G
—
GPIO180
EMIOS2
ETPUA2
—
GPIO
I/O
I/O
O
P
181 EMIOS2_ETPUA2_
GPIO181
eMIOS channel
eTPU A channel
—
A1
A2
G
—
GPIO181
EMIOS3
ETPUA3
—
GPIO
I/O
I/O
O
P
182 EMIOS3_ETPUA3_
GPIO182
eMIOS channel
eTPU A channel
—
A1
A2
G
—
GPIO182
EMIOS4
ETPUA4
—
GPIO
I/O
I/O
O
P
183 EMIOS4_ETPUA4_
GPIO183
eMIOS channel
eTPU A channel
—
A1
A2
G
—
GPIO183
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
184 EMIOS5_ETPUA5_
GPIO184
EMIOS5
eMIOS channel
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG AD12 AF14
—/WKPCFG AE12 AE14
—/WKPCFG AF12 AD14
—/WKPCFG AC13 AC14
—/WKPCFG AD13 AF15
—/WKPCFG AE13 AE15
A1
A2
G
ETPUA5
—
eTPU A channel
—
—
GPIO184
EMIOS6
ETPUA6
—
GPIO
I/O
I/O
O
P
185 EMIOS6_ETPUA6_
GPIO185
eMIOS channel
eTPU A channel
—
A1
A2
G
—
GPIO185
EMIOS7
ETPUA7
—
GPIO
I/O
I/O
O
P
186 EMIOS7_ETPUA7_
GPIO186
eMIOS channel
eTPU A channel
—
A1
A2
G
—
GPIO186
EMIOS8
ETPUA8
—
GPIO
I/O
I/O
O
P
187 EMIOS8_ETPUA8_
GPIO187
eMIOS channel
eTPU A channel
—
A1
A2
G
—
GPIO187
EMIOS9
ETPUA9
—
GPIO
I/O
I/O
O
P
188 EMIOS9_ETPUA9_
GPIO188
eMIOS channel
eTPU A channel
—
A1
A2
G
—
GPIO188
EMIOS10
SCKD
GPIO
I/O
I/O
O
P
189 EMIOS10_SCKD_
GPIO189
eMIOS channel
DSPI D clock
—
A1
A2
G
—
—
GPIO189
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
190 EMIOS11_SIND_
EMIOS11
eMIOS channel
I/O
I
MH
MH
MH
MH
MH
MH
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG AF13 AB14
—/WKPCFG AF14 AD15
—/WKPCFG AE14 AC15
—/WKPCFG AC14 AF17
—/WKPCFG AD14 AE16
—/WKPCFG AF15 AD16
GPIO190
A1
A2
G
SIND
DSPI D data input
—
—
—
I/O
O
GPIO190
EMIOS12
SOUTC
—
GPIO
P
191 EMIOS12_SOUTC_
GPIO191
eMIOS channel
DSPI C data output
—
A1
A2
G
O
—
I/O
O
GPIO191
EMIOS13
SOUTD
—
GPIO
P
192 EMIOS13_SOUTD_
GPIO192
eMIOS channel
DSPI D data output
—
A1
A2
G
O
—
I/O
O
GPIO192
EMIOS14
IRQ0
GPIO
P
193 EMIOS14_IRQ0_
GPIO193
eMIOS channel
External interrupt request
FlexCAN D transmit
GPIO
A1
A2
G
I
CNTXD
GPIO193
EMIOS15
IRQ1
O
I/O
O
P
194 EMIOS15_IRQ1_
GPIO194
eMIOS channel
External interrupt request
FlexCAN D receive
GPIO
A1
A2
G
I
CNRXD
GPIO194
EMIOS16
ETPUB0
FR_DBG[3]
GPIO195
I
I/O
I/O
O
P
195 EMIOS16_ETPUB0_
GPIO195
eMIOS channel
eTPU B channel
FlexRay debug
GPIO
A1
A2
G
O
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
196 EMIOS17_ETPUB1_
GPIO196
EMIOS17
eMIOS channel
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG AE15 AB15
—/WKPCFG AC15 AD17
—/WKPCFG AD15 AB16
—/WKPCFG AF16 AF16
—/WKPCFG AE16 AE17
—/WKPCFG AC16 AC16
A1
A2
G
ETPUB1
FR_DBG[2]
GPIO196
EMIOS18
ETPUB2
FR_DBG[1]
GPIO197
EMIOS19
ETPUB3
FR_DBG[0]
GPIO198
EMIOS20
ETPUB4
—
eTPU B channel
FlexRay debug
GPIO
O
I/O
I/O
O
P
197 EMIOS18_ETPUB2_
GPIO197
eMIOS channel
eTPU B channel
FlexRay debug
GPIO
A1
A2
G
O
I/O
I/O
O
P
198 EMIOS19_ETPUB3_
GPIO198
eMIOS channel
eTPU B channel
FlexRay debug
GPIO
A1
A2
G
O
I/O
I/O
O
P
199 EMIOS20_ETPUB4_
GPIO199
eMIOS channel
eTPU B channel
—
A1
A2
G
—
I/O
I/O
O
GPIO199
EMIOS21
ETPUB5
—
GPIO
P
200 EMIOS21_ETPUB5_
GPIO200
eMIOS channel
eTPU B channel
—
A1
A2
G
—
I/O
I/O
O
GPIO200
EMIOS22
ETPUB6
—
GPIO
P
201 EMIOS22_ETPUB6_
GPIO201
eMIOS channel
eTPU B channel
—
A1
A2
G
—
I/O
GPIO201
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
202 EMIOS23_ETPUB7_
GPIO202
EMIOS23
eMIOS channel
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG AD16 AA16
—/WKPCFG AF17 AC17
—/WKPCFG AE17 AF18
—/WKPCFG AD17 AE18
—/WKPCFG AC17 AD18
—/WKPCFG AF18 AC18
A1
A2
G
ETPUB7
—
eTPU B channel
—
—
GPIO202
EMIOS24
PCSB0
—
GPIO
I/O
I/O
I/O
—
P
203 EMIOS24_PCSB0_
GPIO203
eMIOS channel
A1
A2
G
DSPI B peripheral chip select
—
GPIO203
EMIOS25
PCSB1
—
GPIO
I/O
I/O
O
P
204 EMIOS25_PCSB1_
GPIO204
eMIOS channel
A1
A2
G
DSPI B peripheral chip select
—
—
GPIO204
EMIOS26
PCSB2
—
GPIO
I/O
I/O
O
P
432 EMIOS26_PCSB2_
GPIO432
eMIOS channel
A1
A2
G
DSPI B peripheral chip select
—
—
GPIO432
EMIOS27
PCSB3
—
GPIO
I/O
I/O
O
P
433 EMIOS27_PCSB3_
GPIO433
eMIOS channel
A1
A2
G
DSPI B peripheral chip select
—
—
GPIO433
EMIOS28
PCSC0
—
GPIO
I/O
I/O
I/O
—
P
434 EMIOS28_PCSC0_
GPIO434
eMIOS channel
A1
A2
G
DSPI C peripheral chip select
—
GPIO434
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
435 EMIOS29_PCSC1_
GPIO435
EMIOS29
eMIOS channel
I/O
O
MH
MH
MH
VDDEH4
VDDEH4
VDDEH4
—/WKPCFG
—/WKPCFG
—/WKPCFG
—/WKPCFG AE18 AB17
—/WKPCFG AD18 AF19
—/WKPCFG AC18 AA17
A1
A2
G
PCSC1
—
DSPI C peripheral chip select
—
—
GPIO435
EMIOS30
PCSC2
—
GPIO
I/O
I/O
O
P
436 EMIOS30_PCSC2_
GPIO436
eMIOS channel
A1
A2
G
DSPI C peripheral chip select
—
—
GPIO436
EMIOS31
PCSC5
—
GPIO
I/O
I/O
O
P
437 EMIOS31_PCSC5_
GPIO437
eMIOS channel
A1
A2
G
DSPI C peripheral chip select
—
—
GPIO437
GPIO
I/O
eQADC
ANA09
ANA19
ANA29
ANA39
ANA49
ANA59
ANA69
ANA79
eQADC A shared analog input
I
I
I
I
I
I
I
I
AE/up- VDDA_A1
down
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
A4
B5
C5
D6
A5
B6
C6
D7
A4
B5
C5
D6
A5
B6
C6
C7
P
P
P
P
P
P
P
P
—
—
—
—
—
—
—
—
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
eQADC A shared analog input
eQADC A shared analog input
eQADC A shared analog input
eQADC A shared analog input
eQADC A shared analog input
eQADC A shared analog input
eQADC A shared analog input
AE/up- VDDA_A1
down
AE/up- VDDA_A1
down
AE/up- VDDA_A1
down
AE/up- VDDA_A1
down
AE/up- VDDA_A1
down
AE/up- VDDA_A1
down
AE/up- VDDA_A1
down
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANA8
ANA9
ANA8
eQADC A analog input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A1
VDDA_A0
VDDA_A0
VDDA_A0
VDDA_A0
VDDA_A0
VDDA_A0
VDDA_B1
VDDA_B1
VDDA_B1
VDDA_B0
VDDA_B0
ANA8
ANA9
ANA10
ANA11
ANA12
ANA13
ANA14
ANA15
ANA16
ANA17
ANA18
ANA19
ANA20
ANA21
ANA22
ANA23
AN24
ANA8
ANA9
ANA10
ANA11
ANA12
ANA13
ANA14
ANA15
ANA16
ANA17
ANA18
ANA19
ANA20
ANA21
ANA22
ANA23
AN24
A6
C7
D7
A6
ANA9
ANA10
ANA11
ANA12
ANA13
ANA14
ANA15
ANA16
ANA17
ANA18
ANA19
ANA20
ANA21
ANA22
ANA23
AN24
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC A analog input
eQADC analog input
eQADC analog input
eQADC analog input
eQADC analog input
eQADC analog input
eQADC analog input
eQADC analog input
eQADC analog input
eQADC analog input
eQADC analog input
eQADC analog input
ANA10
ANA11
ANA12
ANA13
ANA14
ANA15
ANA16
ANA17
ANA18
ANA19
ANA20
ANA21
ANA22
ANA23
AN24
B7
B7
A7
A7
D8
D8
C8
C8
B8
B8
A8
A8
D9
D9
C9
C9
D10
C10
D11
C11
D12
C12
B12
D13
C13
B13
A13
B14
C14
D14
A14
B15
C15
D10
C10
D11
C11
C12
D12
B12
C13
D13
B13
A13
A14
B14
C14
B15
D14
C15
AN25
AN25
AN25
AN25
AN26
AN26
AN26
AN26
AN27
AN27
AN27
AN27
AN28
AN28
AN28
AN28
AN29
AN29
AN29
AN29
AN30
AN30
AN30
AN30
AN31
AN31
AN31
AN31
AN32
AN32
AN32
AN32
AN33
AN33
AN33
AN33
AN34
AN34
AN34
AN34
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
P
P
P
P
P
—
—
—
—
—
—
AN35
AN36
AN37
AN38
AN39
ANB0
AN35
eQADC analog input
I
I
I
I
I
I
AE
AE
AE
AE
AE
VDDA_B0
VDDA_B1
VDDA_B0
VDDA_B0
VDDA_B0
AN35
AN36
AN37
AN38
AN39
ANB0
AN35
AN36
AN37
AN38
AN39
ANB0
D15
A15
C16
C17
D16
C18
D15
A15
C17
D16
C16
C18
AN36
AN37
AN38
AN39
ANB0
eQADC analog input
eQADC analog input
eQADC analog input
eQADC analog input
eQADC B shared analog input
AE/up- VDDA_B0
down
P
P
P
P
P
P
P
—
—
—
—
—
—
—
ANB1
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
ANB1
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
eQADC B shared analog input
eQADC B shared analog input
eQADC B shared analog input
eQADC B shared analog input
eQADC B shared analog input
eQADC B shared analog input
eQADC B shared analog input
I
I
I
I
I
I
I
AE/up- VDDA_B0
down
ANB1
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
ANB1
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
D17
D18
D19
C19
C20
B19
A20
D17
D18
D19
B19
A20
C20
C19
AE/up- VDDA_B0
down
AE/up- VDDA_B0
down
AE/up- VDDA_B0
down
AE/up- VDDA_B0
down
AE/up- VDDA_B0
down
AE/up- VDDA_B0
down
P
P
P
P
P
P
P
P
P
—
—
—
—
—
—
—
—
—
ANB8
ANB9
ANB8
eQADC B analog input
eQADC B analog input
eQADC B analog input
eQADC B analog input
eQADC B analog input
eQADC B analog input
eQADC B analog input
eQADC B analog input
eQADC B analog input
I
I
I
I
I
I
I
I
I
AE
AE
AE
AE
AE
AE
AE
AE
AE
VDDA_B0
VDDA_B0
VDDA_B0
VDDA_B0
VDDA_B0
VDDA_B0
VDDA_B0
VDDA_B0
VDDA_B0
ANB8
ANB9
ANB8
ANB9
B20
D20
B21
A21
C21
D21
A22
B22
C22
B20
A21
B21
C21
A22
B22
D20
C22
D21
ANB9
ANB10
ANB11
ANB12
ANB13
ANB14
ANB15
ANB16
ANB10
ANB11
ANB12
ANB13
ANB14
ANB15
ANB16
ANB10
ANB11
ANB12
ANB13
ANB14
ANB15
ANB16
ANB10
ANB11
ANB12
ANB13
ANB14
ANB15
ANB16
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANB17
ANB17
eQADC B analog input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AE
AE
VDDA_B0
VDDA_B0
VDDA_B0
VDDA_B0
VDDA_B0
VDDA_B0
VDDA_B0
VRH_A
ANB17
ANB18
ANB17
ANB18
A23
B23
C23
D22
A24
B24
A25
A12
A11
A19
A18
B18
B11
A9
D22
A23
B23
C23
A24
B24
E20
A12
A11
A19
A18
B18
B11
A9
ANB18
ANB18
eQADC B analog input
ANB19
ANB19
eQADC B analog input
AE
ANB19
ANB19
ANB20
ANB20
eQADC B analog input
AE
ANB20
ANB20
ANB21
ANB21
eQADC B analog input
AE
ANB21
ANB21
ANB22
ANB22
eQADC B analog input
AE
ANB22
ANB22
ANB23
ANB23
eQADC B analog input
AE
ANB23
ANB23
VRH_A
VRH_A
ADC A Voltage reference high
ADC A Voltage reference low
ADC B Voltage reference high
ADC B Voltage reference low
ADC B Reference bypass capacitor
ADC A Reference bypass capacitor
Internal logic supply input
Internal logic supply input
ADC A Reference bypass capacitor
Ground
VDDINT
VSSINT
VDDINT
VSSINT
AE
VRH_A
VRH_A
VRL_A
VRL_A
VRL_A
VRL_A
VRL_A
VRH_B
VRH_B
VRH_B
VRH_B
VRH_B
VRL_B
VRL_B
VRL_B
VRL_B
VRL_B
REFBYPCB
REFBYPCA
VDDA_A0
VDDA_A1
REFBYPCA1
VSSA_A1
VDDA_B0
VDDA_B1
VSSA_B0
REFBYPCB1
REFBYPCB
REFBYPCA
VDDA_A
VDDA_A
REFBYPCA1
VSSA_A
VDDA_B
VDDA_B
VSSA_B
REFBYPCB1
VDDA_B0
VDDA_A1
REFBYPCB
REFBYPCA
VDDA_A0
VDDA_A1
REFBYPCB
REFBYPCA
VDDA_A0
VDDA_A1
AE
VDDE VDDA_A0
VDDE VDDA_A1
B9
B9
AE
VDDA_A1 REFBYPCA1 REFBYPCA1
A10
B10
A16
B16
B17
A17
A10
B10
A16
B16
B17
A17
VSSE
VSSA_A1
VSSA_A1
VDDA_B0
VDDA_B1
VSSA_B0
VSSA_A1
VDDA_B0
VDDA_B1
VSSA_B0
Internal logic supply input
Internal logic supply input
Ground
VDDE VDDA_B0
VDDE VDDA_B1
VSSE
AE
VSSA_B0
ADC B Reference bypass capacitor
VDDA_B0 REFBYPCB1 REFBYPCB1
FlexRay
P
248 FR_A_TX_
GPIO248
FR_A_TX
—
FlexRay A transfer
O
—
—
I/O
FS
VDDE2
—/Up
—/Up
AD4
AD4
(–/– for Rev.1 (–/– for Rev.1
of the device) of the device)
A1
A2
G
—
—
—
GPIO248
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
249 FR_A_RX_
FR_A_RX
FlexRay A receive
I
FS
FS
FS
FS
FS
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
—/Up
—/Up
AE3
AF3
AD5
AE4
AF4
AE3
AF3
AD5
AE4
AF4
GPIO249
(–/– for Rev.1 (–/– for Rev.1
of the device) of the device)
A1
A2
G
—
—
—
—
I/O
O
—
—
GPIO249
GPIO
P
250 FR_A_TX_EN_
GPIO250
FR_A_TX_EN
FlexRay A transfer enable
—/Up
—/Up
(–/– for Rev.1 (–/– for Rev.1
of the device) of the device)
A1
A2
G
—
—
—
—
I/O
O
—
—
GPIO250
FR_B_TX
—
GPIO
P
251 FR_B_TX_
GPIO251
FlexRay B transfer
—/Up
—/Up
(–/– for Rev.1 (–/– for Rev.1
of the device) of the device)
A1
A2
G
—
—
—
I/O
I
—
—
GPIO251
FR_B_RX
—
GPIO
P
252 FR_B_RX_
GPIO252
FlexRay B receive
—/Up
—/Up
(–/– for Rev.1 (–/– for Rev.1
of the device) of the device)
A1
A2
G
—
—
—
I/O
O
—
—
GPIO252
FR_B_TX_EN
—
GPIO
P
253 FR_B_TX_EN_
GPIO253
FlexRay B transfer enable
—/Up
—/Up
(–/– for Rev.1 (–/– for Rev.1
of the device) of the device)
A1
A2
G
—
—
—
I/O
—
—
GPIO253
GPIO
FlexCAN
P
83 CNTXA_TXDA_
GPIO83
CNTXA
TXDA
—
FlexCAN A transmit
O
O
MH
VDDEH4
—/Up
—/Up
AF19 AE19
A1
A2
G
eSCI A transmit
—
—
I/O
GPIO83
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
84 CNRXA_RXDA_
CNRXA
FlexCAN A receive
I
MH
MH
MH
MH
MH
MH
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
VDDEH4
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
AE19 AD19
AD19 AC19
AC19 AA19
AF20 AF20
AE20 AE20
AD20 AD20
GPIO84
A1
A2
G
RXDA
—
eSCI A receive
I
—
—
I/O
O
GPIO84
CNTXB
PCSC3
—
GPIO
P
85 CNTXB_PCSC3_
GPIO85
FlexCAN B transmit
A1
A2
G
DSPI C peripheral chip select
O
—
—
I/O
I
GPIO85
CNRXB
PCSC4
—
GPIO
P
86 CNRXB_PCSC4_
GPIO86
FlexCAN B receive
A1
A2
G
DSPI C peripheral chip select
O
—
—
I/O
O
GPIO86
CNTXC
PCSD3
—
GPIO
P
87 CNTXC_PCSD3_
GPIO87
FlexCAN C transmit
A1
A2
G
DSPI D peripheral chip select
O
—
—
I/O
I
GPIO87
CNRXC
PCSD4
—
GPIO
P
88 CNRXC_PCSD4_
GPIO88
FlexCAN C receive
A1
A2
G
DSPI D peripheral chip select
O
—
—
I/O
O
GPIO88
CNTXD
—
GPIO
P
246 CNTXD_
GPIO246
FlexCAN D transmit
A1
A2
G
—
—
—
I/O
—
—
GPIO246
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
247 CNRXD_
CNRXD
FlexCAN D receive
I
MH
VDDEH4
—/Up
—/Up
AC20 AC20
GPIO247
A1
A2
G
—
—
—
—
I/O
—
—
GPIO247
GPIO
eSCI
P
89 TXDA_
GPIO89
TXDA
—
eSCI A transmit
O
—
—
I/O
I
MH
MH
MH
MH
MH
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH4
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
M2
M3
P1
N1
K2
K3
K1
L5
A1
A2
G
—
—
—
GPIO89
RXDA
—
GPIO
P
90 RXDA _
GPIO90
eSCI A receive
A1
A2
G
—
—
—
I
—
—
GPIO90
TXDB
PCSD1
—
GPIO
P
91 TXDB_PCSD1_
GPIO91
eSCI B transmit
O
A1
A2
G
DSPI D peripheral chip select
O
—
—
I/O
I
GPIO91
RXDB
PCSD5
—
GPIO
P
92 RXDB_PCSD5_
GPIO92
eSCI B receive
A1
A2
G
DSPI D peripheral chip select
O
—
—
I/O
O
GPIO92
TXDC
ETRIG0
—
GPIO
P
244 TXDC_ETRIG0_
GPIO244
eSCI C transmit
AF23 AF23
A1
A2
G
eQADC trigger input
I
—
—
I/O
GPIO244
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
245 RXDC_
RXDC
eSCI C receive
I
MH
VDDEH5
—/Up
—/Up
AD22 AD22
GPIO245
A1
A2
G
—
—
—
—
I/O
—
—
GPIO245
GPIO
DSPI
P
93 SCKA_PCSC1_
GPIO93
SCKA
PCSC1
—
DSPI A clock
I/O
O
MH
MH
MH
MH
MH
VDDEH3
VDDEH3
VDDEH3
VDDEH3
VDDEH3
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
AD8
AF7
AD7
AE6
AC6
AB8
AE7
AC7
AD6
AC6
A1
A2
G
DSPI C peripheral chip select
—
—
I/O
I
GPIO93
SINA
GPIO
P
94 SINA_PCSC2_
GPIO94
DSPI A data input
A1
A2
G
PCSC2
—
DSPI C peripheral chip select
O
—
—
I/O
O
GPIO94
SOUTA
PCSC5
—
GPIO
P
95 SOUTA_PCSC5_
GPIO95
DSPI A data output
A1
A2
G
DSPI C peripheral chip select
O
—
—
I/O
I/O
O
GPIO95
PCSA0
PCSD2
—
GPIO
P
96 PCSA0_PCSD2_
GPIO96
DSPI A peripheral chip select
A1
A2
G
DSPI D peripheral chip select
—
—
I/O
O
GPIO96
PCSA1
GPIO
P
97 PCSA1_
DSPI A peripheral chip select
PCSE0_GPIO97
A1
A2
G
DSPI E peripheral chip select
—
—
—
GPIO97
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
98 PCSA2_
SOUTE_GPIO98
PCSA2
DSPI A peripheral chip select
O
MH
MH
MH
MH
MH
MH
VDDEH3
VDDEH3
VDDEH3
VDDEH3
VDDEH3
VDDEH3
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
AC7
AE7
AE5
AD6
AE8
AE9
AF6
AD7
AE5
AA8
AC8
AB9
A1
A2
G
DSPI E data output
—
—
—
I/O
O
GPIO98
PCSA3
GPIO
P
99 PCSA3_
SINE_GPIO99
DSPI A peripheral chip select
A1
A2
G
DSPI E data input
—
—
—
I/O
O
GPIO99
PCSA4
GPIO
P
100 PCSA4_
SCKE_GPIO100
DSPI A peripheral chip select
A1
A2
G
DSPI E clock
—
—
—
I/O
O
GPIO100
PCSA5
ETRIG1
—
GPIO
P
101 PCSA5_ETRIG1_
GPIO101
DSPI A peripheral chip select
A1
A2
G
eQADC trigger input
I
—
—
I/O
I/O
—
—
I/O
I
GPIO101
SCKB
—
GPIO
P
102 SCKB_
GPIO102
DSPI B clock
A1
A2
G
—
—
—
GPIO102
SINB
—
GPIO
P
103 SINB_
GPIO103
DSPI B data input
A1
A2
G
—
—
—
I/O
—
—
GPIO103
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
104 SOUTB_
SOUTB
DSPI B data output
O
—
—
I/O
I/O
O
MH
MH
MH
MH
MH
MH
VDDEH3
VDDEH3
VDDEH3
VDDEH3
VDDEH3
VDDEH3
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
AF9 AA10
GPIO104
A1
A2
G
—
—
—
—
GPIO104
PCSB0
PCSD2
—
GPIO
P
105 PCSB0_PCSD2_
GPIO105
DSPI B peripheral chip select
AD9
AC9
AF8
AF8
AE8
AD8
A1
A2
G
DSPI D peripheral chip select
—
—
I/O
O
GPIO105
PCSB1
PCSD0
—
GPIO
P
106 PCSB1_PCSD0_
GPIO106
DSPI B peripheral chip select
A1
A2
G
DSPI D peripheral chip select
I/O
—
I/O
O
—
GPIO106
PCSB2
SOUTC
—
GPIO
P
107 PCSB2_SOUTC_
GPIO107
DSPI B peripheral chip select
A1
A2
G
DSPI C data output
O
—
—
I/O
O
GPIO107
PCSB3
SINC
GPIO
P
108 PCSB3_SINC_
GPIO108
DSPI B peripheral chip select
AD10 AC9
A1
A2
G
DSPI C data input
I
—
—
—
I/O
O
GPIO108
PCSB4
SCKC
—
GPIO
P
109 PCSB4_SCKC_
GPIO109
DSPI B peripheral chip select
AC8
AF7
A1
A2
G
DSPI C clock
I/O
—
I/O
—
GPIO109
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
110 PCSB5_PCSC0_
PCSB5
DSPI B peripheral chip select
O
I/O
—
MH
VDDEH3
—/Up
—/Up
AF6
AE6
GPIO110
A1
A2
G
PCSC0
—
DSPI C peripheral chip select
—
GPIO110
SCKC
GPIO
I/O
I/O
O
P
235 SCKC_SCK_C_LVDSP_
GPIO235
DSPI C clock
MH+
LVDS
VDDEH4
—/Up
—/Up
AD21 AD21
AE22 AE22
AF21 AF21
AE21 AE21
AC22 AC22
A1
SCK_C_LVDSP
LVDS+ downstream signal positive
output clock
A2
G
—
—
—
I/O
I
GPIO235
SINC
GPIO
P
236 SINC_SCK_C_LVDSM_
GPIO236
DSPI C data input
MH+
LVDS
VDDEH4
VDDEH4
VDDEH4
VDDEH4
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
A1
SCK_C_LVDSM
LVDS– downstream signal negative
output clock
O
A2
G
—
—
—
I/O
O
GPIO236
SOUTC
GPIO
P
237 SOUTC_SOUT_C_LVDSP_
GPIO237
DSPI C data output
MH+
LVDS
A1
SOUT_C_LVDSP
LVDS+ downstream signal positive
output data
O
A2
G
—
—
—
I/O
I/O
O
GPIO237
PCSC0
GPIO
P
238 PCSC0_SOUT_C_LVDSM_
GPIO238
DSPI C peripheral chip select
MH+
LVDS
A1
SOUT_C_LVDSM
LVDS– downstream signal negative
output data
A2
G
—
—
—
I/O
O
GPIO238
PCSC1
—
GPIO
P
239 PCSC1_
GPIO239
DSPI C peripheral chip select
MH
A1
A2
G
—
—
—
—
—
GPIO239
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
240 PCSC2_GPIO240
PCSC2
DSPI C peripheral chip select
O
—
—
I/O
O
MH
MH
MH
MH
VDDEH5
VDDEH5
VDDEH5
VDDEH5
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
AE23 AE23
AD23 AD23
AF24 AF24
AE24 AE24
A1
A2
G
—
—
—
—
GPIO240
PCSC3
—
GPIO
P
241 PCSC3_GPIO241
242 PCSC4_GPIO242
243 PCSC5_GPIO243
DSPI C peripheral chip select
A1
A2
G
—
—
—
I/O
O
—
—
GPIO241
PCSC4
—
GPIO
P
DSPI C peripheral chip select
A1
A2
G
—
—
—
I/O
O
—
—
GPIO242
PCSC5
—
GPIO
P
DSPI C peripheral chip select
A1
A2
G
—
—
—
I/O
—
—
GPIO243
GPIO
EBI
P
256 D_CS0_
GPIO256
D_CS0
—
EBI chip select 0
O
—
F
F
VDDE9
—/Up
—/Up
—/Up
—/Up
—
—
AD9
U1
A1
A2
G
—
—
—
—
GPIO256
D_CS2
D_ADD_DAT31
—
GPIO
I/O
O
P
257 D_CS2_D_ADD_DAT31_
GPIO257
EBI chip select 2
VDDE8
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO257
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
258 D_CS3_D_TEA_
D_CS3
EBI chip select 3
O
I/O
—
I/O
O
F
F
F
F
F
F
VDDE8
VDDE8
VDDE8
VDDE8
VDDE8
VDDE8
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—
—
—
—
—
—
T6
R1
R2
R3
R4
R5
GPIO258
A1
A2
G
D_TEA
—
EBI transfer error acknowledge
—
GPIO258
D_ADD12
—
GPIO
P
259 D_ADD12_
GPIO259
EBI address bus
A1
A2
G
—
—
—
I/O
O
—
—
GPIO259
D_ADD13
—
GPIO
P
260 D_ADD13_
GPIO260
EBI address bus
A1
A2
G
—
—
—
I/O
O
—
—
GPIO260
D_ADD14
—
GPIO
P
261 D_ADD14_
GPIO261
EBI address bus
A1
A2
G
—
—
—
I/O
O
—
—
GPIO261
D_ADD15
—
GPIO
P
262 D_ADD15_
GPIO262
EBI address bus
A1
A2
G
—
—
—
I/O
O
—
—
GPIO262
D_ADD16
D_ADD_DAT16
—
GPIO
P
263 D_ADD16_D_ADD_DAT16_
GPIO263
EBI address bus
A1
A2
G
Address and data in mux mode.
I/O
—
I/O
—
GPIO263
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
264 D_ADD17_D_ADD_DAT17_
GPIO264
D_ADD17
EBI address bus
O
I/O
—
F
F
F
F
F
F
VDDE8
VDDE8
VDDE8
VDDE8
VDDE9
VDDE9
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—
—
—
—
—
—
T5
T2
A1
A2
G
D_ADD_DAT17
—
Address and data in mux mode.
—
GPIO264
D_ADD18
D_ADD_DAT18
—
GPIO
I/O
O
P
265 D_ADD18_D_ADD_DAT18_
GPIO265
EBI address bus
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO265
D_ADD19
D_ADD_DAT19
—
GPIO
I/O
O
P
266 D_ADD19_D_ADD_DAT19_
GPIO266
EBI address bus
T3
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO266
D_ADD20
D_ADD_DAT20
—
GPIO
I/O
O
P
267 D_ADD20_D_ADD_DAT20_
GPIO267
EBI address bus
T4
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO267
D_ADD21
D_ADD_DAT21
—
GPIO
I/O
O
P
268 D_ADD21_D_ADD_DAT21_
GPIO268
EBI address bus
AB11
AD10
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO268
D_ADD22
D_ADD_DAT22
—
GPIO
I/O
O
P
269 D_ADD22_D_ADD_DAT22_
GPIO269
EBI address bus
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO269
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
270 D_ADD23_D_ADD_DAT23_
GPIO270
D_ADD23
EBI address bus
O
I/O
—
F
F
F
F
F
F
VDDE9
VDDE9
VDDE9
VDDE9
VDDE9
VDDE9
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—
—
—
—
—
—
AE10
A1
A2
G
D_ADD_DAT23
—
Address and data in mux mode.
—
GPIO270
D_ADD24
D_ADD_DAT24
—
GPIO
I/O
O
P
271 D_ADD24_D_ADD_DAT24_
GPIO271
EBI address bus
AF10
AD11
AE11
AF11
AD12
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO271
D_ADD25
D_ADD_DAT25
—
GPIO
I/O
O
P
272 D_ADD25_D_ADD_DAT25_
GPIO272
EBI address bus
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO272
D_ADD26
D_ADD_DAT26
—
GPIO
I/O
O
P
273 D_ADD26_D_ADD_DAT26_
GPIO273
EBI address bus
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO273
D_ADD27
D_ADD_DAT27
—
GPIO
I/O
O
P
274 D_ADD27_D_ADD_DAT27_
GPIO274
EBI address bus
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO274
D_ADD28
D_ADD_DAT28
—
GPIO
I/O
O
P
275 D_ADD28_D_ADD_DAT28_
GPIO275
EBI address bus
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO275
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
276 D_ADD29_D_ADD_DAT29_
GPIO276
D_ADD29
EBI address bus
O
F
F
F
VDDE9
VDDE9
VDDE10
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—
—
—
AB12
A1
A2
G
D_ADD_DAT29
—
Address and data in mux mode.
I/O
—
—
GPIO276
D_ADD30
D_ADD_DAT30
—
GPIO
I/O
O
P
277 D_ADD30_D_ADD_DAT30_
GPIO277
EBI address bus
AE12
P25
A1
A2
G
Address and data in mux mode.
I/O
—
—
GPIO277
D_ADD_DAT0
GPIO
I/O
I/O
P
278 D_ADD_DAT0_
GPIO278
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO278
D_ADD_DAT1
GPIO
I/O
I/O
P
279 D_ADD_DAT1_
GPIO279
EBI data only in non-mux mode.
Address and data in mux mode.
F
F
F
VDDE10
VDDE10
VDDE10
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—
—
—
P26
N24
N25
A1
A2
G
—
—
—
—
—
—
GPIO279
D_ADD_DAT2
GPIO
I/O
I/O
P
280 D_ADD_DAT2_
GPIO280
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO280
D_ADD_DAT3
GPIO
I/O
I/O
P
281 D_ADD_DAT3_
GPIO281
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO281
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
282 D_ADD_DAT4_
D_ADD_DAT4
EBI data only in non-mux mode.
Address and data in mux mode.
I/O
F
F
F
F
F
VDDE10
VDDE10
VDDE10
VDDE10
VDDE10
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—
—
—
—
—
N26
M25
N22
M24
M23
GPIO282
A1
A2
G
—
—
—
—
—
—
GPIO282
D_ADD_DAT5
GPIO
I/O
I/O
P
283 D_ADD_DAT5_
GPIO283
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO283
D_ADD_DAT6
GPIO
I/O
I/O
P
284 D_ADD_DAT6_
GPIO284
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO284
D_ADD_DAT7
GPIO
I/O
I/O
P
285 D_ADD_DAT7_
GPIO285
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO285
D_ADD_DAT8
GPIO
I/O
I/O
P
286 D_ADD_DAT8_
GPIO286
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO286
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
287 D_ADD_DAT9_
D_ADD_DAT9
EBI data only in non-mux mode.
Address and data in mux mode.
I/O
F
F
F
F
F
VDDE10
VDDE10
VDDE10
VDDE10
VDDE10
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—
—
—
—
—
M22
L26
L25
L24
L23
GPIO287
A1
A2
G
—
—
—
—
—
—
GPIO287
D_ADD_DAT10
GPIO
I/O
I/O
P
288 D_ADD_DAT10_
GPIO288
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO288
D_ADD_DAT11
GPIO
I/O
I/O
P
289 D_ADD_DAT11_
GPIO289
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO289
D_ADD_DAT12
GPIO
I/O
I/O
P
290 D_ADD_DAT12_
GPIO290
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO290
D_ADD_DAT13
GPIO
I/O
I/O
P
291 D_ADD_DAT13
_GPIO291
EBI data only in non-mux mode.
Address and data in mux mode.
A1
A2
G
—
—
—
—
—
—
GPIO291
GPIO
I/O
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
292 D_ADD_DAT14_GPIO292
D_ADD_DAT14
EBI data only in non-mux mode.
Address and data in mux mode.
I/O
F
F
VDDE10
—/Up
—/Up
—
L22
A1
A2
G
—
—
—
—
—
—
GPIO292
D_ADD_DAT15
GPIO
I/O
I/O
P
293 D_ADD_DAT15_GPIO293
EBI data only in non-mux mode.
Address and data in mux mode.
VDDE10
—/Up
—/Up
—
K26
A1
A2
G
—
—
—
—
I/O
O
—
—
GPIO293
D_RD_WR
—
GPIO
P
294 D_RD_WR_GPIO294
295 D_WE0_GPIO295
296 D_WE1_GPIO296
297 D_OE_GPIO297
EBI read/write
F
F
F
F
VDDE10
VDDE8
VDDE8
VDDE10
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—
—
—
—
R26
N1
A1
A2
G
—
—
—
I/O
O
—
—
GPIO294
D_WE0
—
GPIO
P
EBI write enable
A1
A2
G
—
—
—
I/O
O
—
—
GPIO295
D_WE1
—
GPIO
P
EBI write enable
P5
A1
A2
G
—
—
—
I/O
O
—
—
GPIO296
D_OE
—
GPIO
P
EBI output enable
P23
A1
A2
G
—
—
—
I/O
—
—
GPIO297
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
298 D_TS_GPIO298
D_TS
EBI transfer start
O
—
—
I/O
O
F
F
F
F
F
F
VDDE9
VDDE10
VDDE9
VDDE9
VDDE8
VDDE8
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—
—
—
—
—
—
AE9
P24
AF9
AB10
M2
A1
A2
G
—
—
—
—
GPIO298
D_ALE
—
GPIO
P
299 D_ALE_GPIO299
300 D_TA_GPIO300
301 D_CS1_GPIO301
302 D_BDIP_GPIO302
303 D_WE2_GPIO303
EBI Address Latch Enable
A1
A2
G
—
—
—
I/O
I/O
—
—
I/O
O
—
—
GPIO299
D_TA
—
GPIO
P
EBI transfer acknowledge
A1
A2
G
—
—
—
GPIO300
D_CS1
—
GPIO
P
EBI chip select
A1
A2
G
—
—
—
I/O
O
—
—
GPIO301
D_BDIP
—
GPIO
P
EBI burst data in progress
A1
A2
G
—
—
—
I/O
O
—
—
GPIO302
D_WE2
—
GPIO
P
EBI write enable
N2
A1
A2
G
—
—
—
I/O
—
—
GPIO303
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
304 D_WE3_GPIO304
D_WE3
EBI write enable
O
—
—
I/O
O
F
F
F
F
VDDE8
VDDE8
VDDE8
VDDE8
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—/Up
—
—
—
—
N3
P1
P2
P3
A1
A2
G
—
—
—
—
GPIO304
D_ADD9
—
GPIO
P
305 D_ADD9_GPIO305
306 D_ADD10_GPIO306
307 D_ADD11_GPIO307
EBI address bus
A1
A2
G
—
—
—
I/O
O
—
—
GPIO305
D_ADD10
—
GPIO
P
EBI address bus
A1
A2
G
—
—
—
I/O
O
—
—
GPIO306
D_ADD11
—
GPIO
P
EBI address bus
A1
A2
G
—
—
—
I/O
—
—
GPIO307
GPIO
Reset and Clocks
P
P
—
RESET
RESET
External reset input
External reset output
I
MH
MH
VDDEH1
RESET/Up
RESET/Up
R2
A3
N5
A3
230 RSTOUT
RSTOUT
O
VDDEH1 RSTOUT/Low
RSTOUT/
High
P
211 BOOTCFG0_IRQ2_
GPIO211
BOOTCFG0
IRQ2
Boot configuration
I
I
MH
VDDEH1
BOOTCFG/
Down
—/Down
—
L4
A1
A2
G
—
—
—
I/O
GPIO211
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
P
212 BOOTCFG1_IRQ3_
GPIO212
BOOTCFG1
Boot configuration
I
I
MH
MH
MH
MH
MH
VDDEH1
VDDEH1
VDDEH1
VDDEH1
VDDEH1
BOOTCFG/
Down
—/Down
N2
N3
R3
P2
P3
L3
M5
M3
L1
A1
A2
G
IRQ3
External interrupt request
—
—
—
I/O
I
GPIO212
WKPCFG
GPIO
P
213 WKPCFG_NMI_
GPIO21310
Weak pull configuration input
WKPCFG/Up
PLLCFG/Up
PLLCFG/Up
—/Up
A1
A2
G
—
—
—
GPIO213
PLLCFG0
IRQ4
GPIO
I
I
P
208 PLLCFG0_IRQ4_
GPIO208
FMPLL mode configuration input
External interrupt request
—
—/Up
A1
A2
G
I
—
—
I/O
I
GPIO208
PLLCFG1
IRQ5
GPIO
P
209 PLLCFG1_IRQ5_GPIO209
FMPLL mode configuration input
External interrupt request
DSPI D data output
GPIO
—/Up
A1
A2
G
I
SOUTD
GPIO209
PLLCFG2
O
I/O
I
P
—
PLLCFG2
FMPLL mode configuration input
PLLCFG/
Down
—
/
L2
Down
P
P
P
—
—
XTAL
XTAL
Crystal oscillator output
Crystal oscillator input
EBI system clock output
O
I
AE
AE
F
VDD33
VDD33
VDDE9
XTAL
XTAL
AC26 AC26
AB26 AB26
EXTAL
EXTAL
EXTAL
EXTAL
229 D_CLKOUT
D_CLKOUT
O
CLKOUT/
Enabled
CLKOUT/
Enabled
—
AF12
P
214 ENGCLK
ENGCLK
EBI engineering clock output
O
F
VDDE2
ENGCLK/
Enabled
ENGCLK/
Enabled
AD1
AD1
Note: EXTCLK (External clock input)
selected through SIU register)
JTAG and Nexus
(see footnote11 about resets)
12
–
—
EVTI
EVTI
Nexus event in
I
F
VDDE2
—/Up
EVTI/Up
T4
V1
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
12
–
227 EVTO
EVTO
Nexus event out
O
F
VDDE2
ABS/Up
EVTO/HI
U1
V2
(the BAM uses this pin to
select if auto baud rate is on
or off)
12
12
–
219 MCKO
MCKO
MDO014
—
Nexus message clock out
O
O
F
F
VDDE2
VDDE2
O/Low
Disabled13
See Note15
T2
U3
U4
V3
220 MDO0_GPIO220
221 MDO1_GPIO221
222 MDO2_GPIO222
223 MDO3_GPIO223
75 MDO4_GPIO75
Nexus message data out
See Note15
–
A1
A2
G
—
—
—
I/O
O
—
—
GPIO220
MDO114
—
GPIO
12
–
Nexus message data out
F
F
F
F
VDDE2
VDDE2
VDDE2
VDDE2
O/Low
O/Low
O/Low
O/Low
—/Down
—/Down
—/Down
—/Down
U4
V1
V2
V3
W6
V4
A1
A2
G
—
—
—
I/O
O
—
—
GPIO221
MDO214
—
GPIO
12
–
Nexus message data out
A1
A2
G
—
—
—
I/O
O
—
—
GPIO222
MDO314
—
GPIO
12
–
Nexus message data out
V5
A1
A2
G
—
—
—
I/O
O
—
—
GPIO223
MDO414
—
GPIO
12
–
Nexus message data out
W1
A1
A2
G
—
—
—
I/O
—
—
GPIO75
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
12
–
76 MDO5_GPIO76
MDO514
Nexus message data out
O
—
—
I/O
O
F
F
F
F
F
F
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
O/Low
O/Low
O/Low
O/Low
O/Low
O/Low
—/Down
—/Down
—/Down
—/Down
—/Down
—/Down
V4
W1
W2
W3
Y1
W2
W3
Y1
A1
A2
G
—
—
—
—
GPIO76
MDO614
—
GPIO
12
–
77 MDO6_GPIO77
78 MDO7_GPIO78
79 MDO8_GPIO79
80 MDO9_GPIO80
81 MDO10_GPIO81
Nexus message data out
A1
A2
G
—
—
—
I/O
O
—
—
GPIO77
MDO714
—
GPIO
12
–
Nexus message data out
A1
A2
G
—
—
—
I/O
O
—
—
GPIO78
MDO814
—
GPIO
12
–
Nexus message data out
W5
Y2
A1
A2
G
—
—
—
I/O
O
—
—
GPIO79
MDO914
—
GPIO
12
–
Nexus message data out
A1
A2
G
—
—
—
I/O
O
—
—
GPIO80
MDO1014
—
GPIO
12
–
Nexus message data out
Y2
Y3
A1
A2
G
—
—
—
I/O
—
—
GPIO81
GPIO
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
12
–
82 MDO11_GPIO82
MDO1114
Nexus message data out
O
—
—
I/O
O
F
F
F
F
F
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
O/Low
O/Low
O/Low
O/Low
O/Low
—/Down
—/Down
—/Down
—/Down
—/Down
Y3
AA1
AA2
AA3
Y4
Y4
Y5
A1
A2
G
—
—
—
—
GPIO82
MDO1214
—
GPIO
12
–
231 MDO12_GPIO231
232 MDO13_GPIO232
233 MDO14_GPIO233
234 MDO15_GPIO234
Nexus message data out
A1
A2
G
—
—
—
I/O
O
—
—
GPIO231
MDO1314
—
GPIO
12
–
Nexus message data out
AA1
AA2
AA3
A1
A2
G
—
—
—
I/O
O
—
—
GPIO232
MDO1414
—
GPIO
12
–
Nexus message data out
A1
A2
G
—
—
—
I/O
O
—
—
GPIO233
MDO1514
—
GPIO
12
–
Nexus message data out
—
A1
A2
G
—
—
I/O
O
—
—
GPIO234
MSEO014
MSEO114
RDY
GPIO
12
–
–
–
–
–
–
–
224 MSEO0
225 MSEO1
226 RDY
Nexus message start/end out
Nexus message start/end out
Nexus ready output
JTAG test clock input
JTAG test data input
JTAG test data output
JTAG test mode select input
F
F
F
F
F
F
F
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
O/Low
O/Low
MSEO/HI
MSEO/HI
RDY/HI
U2
T3
U6
U5
12
12
12
12
12
12
O
O
O/Low
R4
U3
—
—
TCK
TDI
TCK
I
TCK/Down
TDI/Up
TCK/Down
TDI/Up
AB2
AC2
AB1
AB3
AB2
AC2
AB1
AB3
TDI
I
228 TDO
TMS
TDO
O
TDO/Up
TMS/Up
TDO/Up
TMS/Up
—
TMS
I
Table 39. Signal Properties and Muxing Summary (continued)
Package
Location
State
after
Stateduring
RESET7
Signal Name2
Function4
Function Summary
RESET8
12
–
—
—
JCOMP
JCOMP
JTAG TAP controller enable
I
I
F
F
VDDE2
JCOMP/Down JCOMP/Down
R1
B4
U2
B4
—
TEST
TEST
Test mode select (not for customer
use)
VDDEH1
TEST/Down
TEST/Down
—
—
—
—
—
—
—
—
VDDSYN
VSSSYN
VSTBY
VDDSYN
VSSSYN
VSTBY
Clock synthesizer power input
Clock synthesizer ground input
SRAM standby power input
I/O VDDE
VDDSYN
VDDSYN
VDDEH1
VDDREG
VDDSYN
VSSSYN
VSTBY
VDDSYN
VSSSYN
VSTBY
AD26 AD26
AA26 AA26
I
I
I
VSSE
VHV
AE
M4
M4
REGSEL
REGSEL
Selects regulator mode
(Linear/Switch mode)
REGSEL
REGSEL
W23 W23
—
—
REGCTL
REGCTL
Regulator controller output to
base/gate of power transistor
O
AE
VDDREG
REGCTL
REGCTL
Y26
Y26
—
—
—
—
VSSFL
VSSFL
Tie to VSS
I
I
VSS
VDDREG
VSSFL
VSSFL
AB25 AB25
AA25 AA25
VDDREG
VDDREG
Source voltage for on-chip regulators
and Low voltage detect circuits
VDDINT VDDREG
VDDREG
VDDREG
1
2
The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not
have GPIO functionality, this number is the PCR number.
The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices
and is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type.
3
4
P/A/G stands for Primary/Alternate/GPIO . This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO.
Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions
are designated in the PA field of the SIU_PCRn registers except where explicitly noted.
5
MH = High voltage, medium speed
F = Fast speed
FS = Fast speed with slew
AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad)
VHV = Very high voltage
6
7
VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V
(+5%/–10%) power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply.
All pins are sampled after the internal POR is negated. The terminology used in this column is: O – output, I – input, Up – weak pull up enabled, Down – weak
pulldown enabled, Low – output driven low, High – output driven high, ABS — Auto Baud Select (during Reset or until JCOMP assertion). A dash on the left side
of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down
enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled.
8
The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin
are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.
9
During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the
system clock propagates through the device.
10 NMI function is selected using the SIU_IREER/SIU_IFEER registers and has priority over any other function on this pin.
11 Nexus reset is different than system reset; MDO0-11 are enabled in RPM or FPM trace modes, while MDO12-15 are enabled in FPM trace mode only. MSEO
and MCKO are also dependent on trace (RPM or FPM) being enabled.
12 The Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC. SIU
values have no effect on the function of these pins once enabled.
13 MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register).
14 Do not connect pin directly to a power supply or ground.
15 While JCOMP is negated, the MDO0 pad is pulled up because of the default values in its SIU PCR. When JCOMP is asserted, the MDO0 pad is enabled as an
output and goes low when the system clock is present.
Revision History
Appendix B Revision History
Table 40 describes the changes made to this document between revisions.
Table 40. Revision History
Revision
Date
Description
Rev 1
Rev 2
5 Aug 2011
Initial customer release
21 Dec 2011
Added information about specs 1a through 1d in the PMC Electrical Specifications table.
Updated the footnote reference (changed from 13 to 14) of spec 18 of the PMC Electrical
Specifications table.
Updated the Operating Current 5.0 V Supplies @ fsys = 180MHz VDDA Max value
(changed from 30 to 50).
Updated footnote 1 of the VDD33 Pad Average DC Current table (changed IDDE to
IDD33).
Updated the pF value of 11 SRC/DSC Fast with Slew Rate (changed from 2.6 to 200) in
the Pad AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V) table.
Added a footnote for ANA0-ANA7 (9) functions in the “Signal Properties and Muxing
Summary” table.
Added a footnote for MDO0-MDO15 (14) and MSEO0 functions in the “Signal Properties
and Muxing Summary” table.
Updated figure numbers 25, 27, 29, and 31: Added specs 1-4.
Changed the title of the “PFCPR1 Settings” table to “BIUCR1/BIUCR3”.
Added a new row “Load” under “Termination” in the “DSPI LVDS Pad Specification” table.
Updated the “Max” and “Typical” values of “Delay, Z to Normal”, “Rise/Fall Time”, and “Data
Frequency” in the “DSPI LVDS Pad Specification” table.
Changed “VDDE” to “VDDEH” in footnote 10 of the “DC Electrical Specifications” table.
Made the following changes in the “DSPI Timing” table:
• Update the minimum peripheral bus frequencies for “Data Setup Time for Inputs” and
“Data Hold Time for Outputs”.
• Updated the maximum peripheral bus frequencies for “Data Valid (after SCK edge)”.
• Added “Master (LVDS)” information for “Data Valid (after SCK edge)” and “Data Hold
Time for Outputs”.
Changed the minimum voltage value of the “I/O Supply Voltage (fast I/O pads)” from
“1.62 V” to “3.0 V” in the “DC Electrical Specifications” table.
Changed “VDDE” values from “1.62 V to 1.98 V” to “3.0 V to 3.6 V” in footnote 1 of the “Pad
AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V)” table.
Removed voltage ranges “1.62 V–1.98 V” and “2.25 V–2.75 V” from “Fast I/O Weak Pull
Up/Down Current” in the “DC Electrical Specifications” table.
MPC5676R Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
109
Revision History
Table 40. Revision History (continued)
Description
Revision
Date
Rev 3
10 August 2012 Added minimum and maximum “Nominal bandgap reference voltage” values in the “PMC
Electrical Specifications” table.
Updated the maximum “Medium I/O Output Low Voltage” value (changed from 0.2 x VDDEH
to 0.2 x VDDEH and 0.15 x VDDEH ) in the “DC Electrical Specifications” table, moved
reference to the footnote 10 (IOH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O
with VDDEH = 4.5 V; IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDEH
= 3.0 V) to “0.2 x VDDEH”, and added a new footnote 11(IOL_S=2 mA) to “0.15 x VDDEH”.
Updated footnote9 (IOH_F = {12,20,30,40} mA and IOL_F = {24,40,50,65} mA for
{00,01,10,11} drive mode with VDDE = 3.0 V): Removed “IOH_F = {7,13,18,25} mA and
IOL_F = {18,30,35,50} mA for {00,01,10,11} drive mode with VDDE = 2.25 V;
IOH_F = {3,7,10,16}mA and IOL_F = {12,20,27,35} mA for {00,01,10,11} drive mode with
VDDE = 1.62 V”.
Added minimum and maximum values to all rows of the “Power Management Control
(PMC) Specification” table.
Updated the “Accuracy” temperature values in the “Temperature Sensor Electrical
Specifications” table: Changed “–40 C to 100 C to 40 C to 150 C, removed the
correspnding “Typ” value, removed “100 C to 150 C, and added minimum (10) and
maximum (+10) values.
Added a new section “ADC Internal Resource Measurements” and moved “Power
Management Control (PMC) Specification”, “Standby RAM Regulator Electrical
Specifications”, “ADC Band Gap Reference / LVI Electrical Specifications”, and
“Temperature Sensor Electrical Specifications” tables to the section.
Changed “Minimum Data Retention at 25 °C ambient temperature” to “Minimum Data
Retention at 85 °C ambient temperature” in the “Flash EEPROM Module Life” table.
Added the following note after “Flash Program and Erase Specifications (Pending Si
characterization)” table in the “C90 Flash Memory Electrical Characteristics” section:
“The low, mid, and high address blocks of the flash arrays are erased (all bits set to 1)
before leaving the factory.
Updated the “DSPI LVDS Pad Specification” table: Changed maximum “Load” value from
“25” to “32”; minimum values for “Differential Output Voltage SRC=0b00 or 0b11,
SRC=0b01, SRC=0b10” from “150, 90, 160” to “215, 170, 260”; “Transmission lines
(Differential) to “Termination Resistance”; “Zc” to “RLoad”; and added the following
footnote: “The termination resistance spec is not meant to specify the receiver
termination requirements. They are there to establish the measurement criteria for the
specs in this table. As per the TIA/EIA-644A standard, the LVDS receiver termination
resistance can vary from 90 to 132 .
Rev 4
21 January 2016 Added a table “Flash Memory AC Timing Specifications”.
Updated the min and max values from -10 and +10 to -20 and +20 for “Accuracy” in the
“Temperature Sensor Electrical Specifications” table.
MPC5676R Microcontroller Data Sheet, Rev. 4
110
Freescale Semiconductor
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Document Number: MPC5676R
Rev. 4
16 Feb 2016
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