PRT306FCVJ5A [NXP]
i.MX RT1064 Crossover Processors for Industrial Products;![PRT306FCVJ5A](http://pdffile.icpdf.com/pdf2/p00353/img/icpdf/PRT305ACAF4A_2172784_icpdf.jpg)
型号: | PRT306FCVJ5A |
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描述: | i.MX RT1064 Crossover Processors for Industrial Products |
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Document Number: IMXRT1064IEC
Rev. 2, 08/2020
NXP Semiconductors
Data Sheet: Technical Data
MIMXRT1064CVL5A
MIMXRT1064CVJ5A
MIMXRT1064CVL5B
MIMXRT1064CVJ5B
i.MX RT1064 Crossover
Processors for Industrial
Products
Package Information
Plastic Package
196-pin MAPBGA, 10 x 10 mm, 0.65 mm pitch
196-pin MAPBGA, 12 x 12 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 7
1 i.MX RT1064 Introduction
The i.MX RT1064 is a new processor family featuring
NXP’s advanced implementation of the Arm
1. i.MX RT1064 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1. Special signal considerations . . . . . . . . . . . . . . . 17
3.2. Recommended connections for unused analog
®
Cortex -M7 core, which operates at speeds up to 528
MHz to provide high CPU performance and best
real-time response.
The i.MX RT1064 processor has 4 MB on chip Flash and
1 MB on-chip RAM. 512 KB SRAM can be flexibly
configured as TCM or general-purpose on-chip RAM,
while the other 512 KB SRAM is general-purpose
on-chip RAM. The i.MX RT1064 integrates advanced
power management module with DCDC and LDO that
reduces complexity of external power supply and
simplifies power sequencing. The i.MX RT1064 also
provides various memory interfaces, including SDRAM,
RAW NAND FLASH, NOR FLASH, SD/eMMC, Quad
SPI, and a wide range of other interfaces for connecting
peripherals, such as WLAN, Bluetooth™, GPS,
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1. Chip-Level conditions . . . . . . . . . . . . . . . . . . . . . 20
4.2. System power and clocks . . . . . . . . . . . . . . . . . . 27
4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.5. External memory interface . . . . . . . . . . . . . . . . . 44
4.6. Display and graphics . . . . . . . . . . . . . . . . . . . . . . 54
4.7. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.8. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.9. Communication interfaces . . . . . . . . . . . . . . . . . . 67
4.10. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5. Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 83
6.1. Boot mode configuration pins . . . . . . . . . . . . . . . 83
6.2. Boot device interface allocation . . . . . . . . . . . . . . 83
7. Package information and contact assignments . . . . . . . 88
7.1. 10 x 10 mm package information . . . . . . . . . . . . 88
7.2. 12 x 12 mm package information . . . . . . . . . . . 100
8. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
displays, and camera sensors. The i.MX RT1064 has rich
audio and video features, including LCD display, basic
2D graphics, camera interface, SPDIF, and I2S audio
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
i.MX RT1064 Introduction
interface. The i.MX RT1064 has analog interfaces, such as ADC, ACMP, and TSC.
The i.MX RT1064 is specifically useful for applications such as:
•
•
•
Industrial Human Machine Interfaces (HMI)
Motor Control
Home Appliance
1.1
Features
The i.MX RT1064 processors are based on Arm Cortex-M7 Core Platform, which has the following
features:
•
Supports single Arm Cortex-M7 Core with:
— 32 KB L1 Instruction Cache
— 32 KB L1 Data Cache
— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture
— Support the Armv7-M Thumb instruction set
Integrated MPU, up to 16 individual protection regions
Tightly coupled GPIOs, operating at the same frequency as Arm core
Up to 512 KB I-TCM and D-TCM in total
•
•
•
•
•
•
Frequency of 600/528 MHz
Cortex M7 CoreSight™ components integration for debug
Frequency of the core, as per Table 10, "Operating ranges," on page 22.
The SoC-level memory system consists of the following additional components:
— Boot ROM (128 KB)
— On-chip Flash (4 MB)
— On-chip RAM (1 MB)
– 512 KB OCRAM shared between ITCM/DTCM and OCRAM
– Dedicate 512 KB OCRAM
•
•
External memory interfaces:
— 8/16-bit SDRAM, up to SDRAM-133/SDRAM-166
— 8/16-bit SLC NAND FLASH, with ECC handled in software
— SD/eMMC
— SPI NOR/NAND FLASH
— Parallel NOR FLASH with XIP support
— Two single/dual channel Quad SPI FLASH with XIP support
Timers and PWMs:
— Two General Programmable Timers (GPT)
– 4-channel generic 32-bit resolution timer
– Each support standard capture and compare operation
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i.MX RT1064 Introduction
— Four Periodical Interrupt Timers (PIT)
– Generic 32-bit resolution timer
– Periodical interrupt generation
— Four Quad Timers (QTimer)
– 4-channel generic 16-bit resolution timer for each
– Each support standard capture and compare operation
– Quadrature decoder integrated
— Four FlexPWMs
– Up to 8 individual PWM channels per each
– 16-bit resolution PWM suitable for Motor Control applications
— Four Quadrature Encoder/Decoders
Each i.MX RT1064 processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
•
Display Interface:
— Parallel RGB LCD interface
– Support 8/16/24 bit interface
– Support up to WXGA resolution
– Support Index color with 256 entry x 24 bit color LUT
– Smart LCD display with 8/16-bit MPU/8080 interface
Audio:
•
•
— S/PDIF input and output
— Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and
codec/DSP interfaces
— MQS interface for medium quality audio via GPIO pads
Generic 2D graphics engine:
— BitBlit
— Flexible image composition options—alpha, chroma key
— Porter-duff blending
— Image rotation (90, 180, 270)
— Image size
— Color space conversion
— Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400)
— Standard 2D-DMA operation
•
•
Camera sensors:
— Support 24-bit, 16-bit, and 8-bit CSI input
Connectivity:
— Two USB 2.0 HS OTG controllers with integrated PHY interfaces
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i.MX RT1064 Introduction
— Two Ultra Secure Digital Host Controller (uSDHC) interfaces
– MMC 4.5 compliance with HS200 support up to 200 MB/sec
– SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec
– Support for SDXC (extended capacity)
— Two 10/100M Ethernet controller with support for IEEE1588
— Eight universal asynchronous receiver/transmitter (UARTs) modules
— Four I2C modules
— Four SPI modules
— Two FlexCAN modules
— FlexCAN (with Flexible Data-Rate supported)
— Three FlexIO modules
•
GPIO and Pin Multiplexing:
— General-purpose input/output (GPIO) modules with interrupt capability
— Input/output multiplexing controller (IOMUXC) to provide centralized pad control
The i.MX RT1064 processors integrate advanced power management unit and controllers:
•
•
•
Full PMIC integration, including on-chip DCDC and LDO
Temperature sensor with programmable trim points
GPC hardware power management controller
The i.MX RT1064 processors support the following system debug:
•
•
•
•
Arm CoreSight debug and trace architecture
Trace Port Interface Unit (TPIU) to support off-chip real-time trace
Cross Triggering Interface (CTI)
Support for 5-pin (JTAG) and SWD debug interfaces
The i.MX RT1064 processors support the following analog interfaces:
•
•
•
Two Analog-Digital-Converters (ADC), 16-channel for each, 20-channel in total, 1MSPS
Two Digital-Analog-Converters (DAC)
Four Analog Comparators (ACMP)
Security functions are enabled and accelerated by the following hardware:
•
High Assurance Boot (HAB)
•
Data Co-Processor (DCP):
— AES-128, ECB, and CBC mode
— SHA-1 and SHA-256
— CRC-32
•
•
Bus Encryption Engine (BEE)
— AES-128, ECB, and CTR mode
— On-the-fly QSPI Flash decryption
True random number generation (TRNG)
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i.MX RT1064 Introduction
•
•
Secure Non-Volatile Storage (SNVS)
— Secure real-time clock (RTC)
— Zero Master Key (ZMK)
Secure JTAG Controller (SJC)
NOTE
The actual feature set depends on the part numbers as described in Table 1.
Functions such as display and camera interfaces, connectivity interfaces,
and security features are not offered on all derivatives.
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5
i.MX RT1064 Introduction
1.2
Ordering information
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i.MX RT1064 Introduction
Table 1 provides examples of orderable part numbers covered by this Data Sheet.
Table 1. Ordering information
Junction
Temperature Tj
(C)
Part Number
Features
Package
MIMXRT1064CVL5A Features supports:
MIMXRT1064CVL5B • 528 MHz, industrial
grade for general
purpose, with
• XBAR/AOI
• Ethernet x2
• UART x8
10 x 10 mm, 0.65 mm
pitch, 196-pin MAPBGA
-40 to +105
• I2C x4
MPU/FPU
• FlexSPI x1
• 4 MB Flash
• CAN x2
• eDMA
• FlexCAN (with Flexible
Data-Rate supported)
• FlexIO x3
• 127 GPIOs (124 tightly
coupled)
• Boot ROM (128 KB)
• On-chip RAM (1 MB)
• SEMC
• GPT x2
• 4-channel PIT
• Qtimer x4
• HAB/DCP/BEE/CSU
• TRNG
• PWM x4
• ENC x4
• SNVS (with RTC
supported)
• WDOG x4
• SJC
• LCD/CSI/PXP
• SPDIF x1
• ADC x2
• ACMP x4
• SAI x3
• TSC
• MQS x1
• DCDC
• USB OTG x2
• eMMC 4.5/SD 3.0 x2
• KPP x1
• Temperature sensor
• GPC hardware power
management controller
• SPI x4
MIMXRT1064CVJ5A Features supports:
MIMXRT1064CVJ5B • 528 MHz, industrial
grade for general
purpose, with
• XBAR/AOI
• Ethernet x2
• UART x8
12 x 12 mm, 0.8 mm pitch,
196-pin MAPBGA
-40 to +105
• I2C x4
MPU/FPU
• FlexSPI x1
• 4 MB Flash
• CAN x2
• eDMA
• FlexCAN (with Flexible
Data-Rate supported)
• FlexIO x3
• 127 GPIOs (124 tightly
coupled)
• Boot ROM (128 KB)
• On-chip RAM (1 MB)
• SEMC
• GPT x2
• 4-channel PIT
• Qtimer x4
• HAB/DCP/BEE/CSU
• TRNG
• PWM x4
• ENC x4
• SNVS (with RTC
supported)
• WDOG x4
• SJC
• LCD/CSI/PXP
• SPDIF x1
• ADC x2
• ACMP x4
• SAI x3
• TSC
• MQS x1
• DCDC
• USB OTG x2
• eMMC 4.5/SD 3.0 x2
• KPP x1
• Temperature sensor
• GPC hardware power
management controller
• SPI x4
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NXP Semiconductors
7
i.MX RT1064 Introduction
Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be
identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The
primary characteristic which describes which data sheet applies to a specific part is the temperature grade
(junction) field.
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/IMXRT or
contact an NXP representative for details.
M
IMX X X
@
##
%
+
VV
$
A
Qualification Level
M
Silicon Rev
A
A
B
Prototype Samples
Mass Production
Special
P
M
S
A0
A1
Core Frequency
400 MHz
$
4
5
6
Part # series
XX
i.MX RT
RT
500 MHz
@
1
Family
600 MHz
First Generation RT family
Reserved
2-8
Package Type
VV
196MAPBGA, 12 x 12 mm, 0.8 mm pitch
196MAPBGA, 10 x 10 mm, 0.65 mm pitch
144LQFP, 20 x 20 mm, 0.5 mm pitch
100LQFP, 14 x 14 mm, 0.5 mm pitch
80LQFP, 12 x 12 mm, 0.5 mm pitch
VJ
VL
AG
AF
AE
Sub-Family
RT101x
##
01
02
05
06
RT102x
Tie
%
1
RT105x
Standard Feature
Full Feature
RT106x
2
Temperature (Tj)
+
4MB Flash SIP
Enhanced Feature
4
Consumer: 0 to + 95 °C
Industrial: -40 to +105 °C
D
C
5
Far Field AFE (e.g. for Alexa Voice Service)
Facial Recognition
A
F
L
Local Voice Control
Figure 1. Part number nomenclature—i.MX RT1064
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Architectural Overview
2 Architectural Overview
The following subsections provide an architectural overview of the i.MX RT1064 processor system.
2.1
Block diagram
Figure 2 shows the functional modules in the i.MX RT1064 processor system.
System Control
CPU Platform
Connectivity
Secure JTAG
Arm Cortex-M7
PLL / OSC
eMMC 4.5 / SD 3.0 x2
UART x8
8 x 8 Keypad
I2C x4
32 KB D-cache
32 KB I-cache
RTC and Reset
NVIC
FPU MPU
Enhanced DMA
IOMUX
512 KB TCM/OCRAM
FlexIO
HS_GPIO
GP Timer x6
SPI x4
FlexIO x2
GPIO
Quadrature ENC x4
QuadTimer x4
Multimedia
8 / 16 / 24-bit Parallel CSI
24-bit Parallel LCD
FlexPWM x4
XBAR/AOI
I2S / SAI x3
S/PDIF Tx / Rx
PXP
Watch Dog x4
2D Graphics Acceleration
Resize, CSC, Overlay, Rotation
Internal Memory
512 KB SRAM
FlexCAN x2 + FlexCAN ( with
Flexible Data-Rate supported)
External Memory
4 MB Flash
USB 2.0 OTG with PHY x2
Dual-channel QuadSPI
Octal/Hyper Flash/RAM x1
128 KB ROM
10 / 100 ENET x2
with IEEE 1588
Power Management
DCDC
External Memory Controller
8-bit / 16-bit SDRAM
Parallel NOR FLASH
NAND FLASH
ADC
ADC x2 (16-Channel)
20-Channel in total
LDO
PSRAM
Temp Monitor
ACMP x4
HAB
Security
Ciphers and RNG
Secure RTC
eFuse
.
Figure 2. i.MX RT1064 system block diagram
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9
Modules List
3 Modules List
The i.MX RT1064 processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX RT1064 modules list
Block Mnemonic
Block Name
Subsystem
Brief Description
ACMP1
ACMP2
ACMP3
ACMP4
Analog Comparator
Analog
The comparator (CMP) provides a circuit for comparing
two analog input voltages. The comparator circuit is
designed to operate across the full range of the supply
voltage (rail-to-rail operation).
ADC1
ADC2
Analog to Digital
Converter
Analog
The ADC is a 12-bit general purpose analog to digital
converter.
AOI
Arm
And-Or-Inverter
Cross Trigger
The AOI provides a universal boolean function
generator using a four team sum of products expression
with each product term containing true or complement
values of the four selected inputs (A, B, C, D).
Arm Platform
Arm
The Arm Core Platform includes one Cortex-M7 core. It
includes associated sub-blocks, such as Nested
Vectored Interrupt Controller (NVIC), Floating-Point
Unit (FPU), Memory Protection Unit (MPU), and
CoreSight debug modules.
BEE
Bus Encryption Engine
Security
On-The-Fly FlexSPI Flash Decryption
CCM
GPC
SRC
Clock Control Module, Clocks, Resets, and These modules are responsible for clock and reset
General Power
Controller, System Reset
Controller
Power Control
distribution in the system, and also for the system
power management.
CSI
Parallel CSI
Multimedia
Peripherals
The CSI IP provides parallel CSI standard camera
interface port. The CSI parallel data ports are up to 24
bits. It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB,
and 8-bit/10-bit/16-bit Bayer data input.
CSU
DAP
Central Security Unit
Debug Access Port
Security
The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
RT1064 platform.
System Control
Peripherals
The DAP provides real-time access for the debugger
without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-M7
Core Platform.
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Modules List
Table 2. i.MX RT1064 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
DCDC
DCDC Converter
Analog
The DCDC module is used for generating power supply
for core logic. Main features are:
• Adjustable high efficiency regulator
• Supports 3.3 V input voltage
• Supports nominal run and low power standby modes
• Supports at 0.9 ~ 1.3 V output in run mode
• Supports at 0.9 ~ 1.0 V output in standby mode
• Over current and over voltage detection
eDMA
enhanced Direct Memory
Access
System Control
Peripherals
There is an enhanced DMA (eDMA) engine and two
DMA_MUX.
• The eDMA is a 32 channel DMA engine, which is
capable of performing complex data transfers with
minimal intervention from a host processor.
• The DMA_MUX is capable of multiplexing up to 128
DMA request sources to the 32 DMA channels of
eDMA.
ENC
Quadrature
Encoder/Decoder
Timer Peripherals The enhanced quadrature encoder/decoder module
provides interfacing capability to position/speed
sensors. There are five input signals: PHASEA,
PHASEB, INDEX, TRIGGER, and HOME. This module
is used to decode shaft position, revolution count, and
speed.
ENET1
ENET2
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is
designed to support 10/100 Mbit/s Ethernet/IEEE 802.3
networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the reference manual for details.
EWM
External Watchdog
Monitor
Timer Peripherals The EWM modules is designed to monitor external
circuits, as well as the software flow. This provides a
back-up mechanism to the internal WDOG that can
reset the system. The EWM differs from the internal
WDOG in that it does not reset the system. The EWM,
if allowed to time-out, provides an independent trigger
pin that when asserted resets or places an external
circuit into a safe mode.
FLEXCAN1
FLEXCAN2
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed
to be used as a vehicle serial data bus, meeting the
specific requirements of this field: real-time processing,
reliable operation in the Electromagnetic interference
(EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full
implementation of the CAN protocol specification,
Version 2.0 B, which supports both standard and
extended message frames.
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Modules List
Table 2. i.MX RT1064 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
FLEXCAN (FD)
Flexible Controller Area
Network
Connectivity
Peripherals
The CAN with Flexible Data-Rate protocol and the CAN
2.0 version B protocol supports both standard and
extended message frames, both of them have long
payloads up to 64 bytes transferred at faster rates up to
8 Mbps.
FlexIO1
FlexIO2
FlexIO3
Flexible Input/output
Pulse Width Modulation
RAM
Connectivity and The FlexIO is capable of supporting a wide range of
Communications protocols including, but not limited to: UART, I2C, SPI,
I2S, camera interface, display interface, PWM
waveform generation, etc. The module can remain
functional when the chip is in a low power mode
provided the clock it is using remain active.
FlexPWM1
FlexPWM2
FlexPWM3
FlexPWM4
Timer Peripherals The pulse-width modulator (PWM) contains four PWM
sub-modules, each of which is set up to control a single
half-bridge power stage. Fault channel support is
provided. The PWM module can generate various
switching patterns, including highly sophisticated
waveforms.
FlexRAM
Memories
The i.MX RT1064 has 1 MB of on-chip RAM which
could be flexible allocated to I-TCM, D-TCM, and
on-chip RAM (OCRAM) in a 32 KB granularity. The
FlexRAM is the manager of the on-chip RAM array.
Major functions of this blocks are: interfacing to I-TCM
and D-TCM of Arm core and OCRAM controller;
dynamic RAM arrays allocation for I-TCM, D-TCM, and
OCRAM.
FlexSPI
Quad Serial Peripheral
Interface
Connectivity and FlexSPI acts as an interface to one or two external
Communications serial flash devices, each with up to four bidirectional
data lines.
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
General Purpose I/O
Modules
System Control
Peripherals
Used for general purpose input/output to external ICs.
Each GPIO module supports up to 32 bits of I/O.
GPT1
GPT2
General Purpose Timer
Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
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Modules List
Table 2. i.MX RT1064 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
The KPP is a 16-bit peripheral that can be used as a
keypad matrix interface or as general purpose
input/output (I/O). It supports 8 x 8 external key pad
matrix. Main features are:
KPP
Keypad Port
Human Machine
Interfaces
• Multiple-key detection
• Long key-press detection
• Standby key-press detection
• Supports a 2-point and 3-point contact key matrix
LCDIF
LCD interface
Multimedia
Peripherals
The LCDIF is a general purpose display controller used
to drive a wide range of display devices varying in size
and capabilities. The LCDIF is designed to support
dumb (synchronous 24-bit Parallel RGB interface) and
smart (asynchronous parallel MPU interface) LCD
devices.
LPI2C1
LPI2C2
LPI2C3
LPI2C4
Low Power
Inter-integrated Circuit
Connectivity and The LPI2C is a low power Inter-Integrated Circuit (I2C)
Communications module that supports an efficient interface to an I2C bus
as a master.
The I2C provides a method of communication between
a number of external devices. More detailed
information, see Section 4.9.2, LPI2C module timing
parameters.
LPSPI1
LPSPI2
LPSPI3
LPSPI4
Low Power Serial
Peripheral Interface
Connectivity and The LPSPI is a low power Serial Peripheral Interface
Communications (SPI) module that support an efficient interface to an
SPI bus as a master and/or a slave.
• It can continue operating while the chip is in stop
modes, if an appropriate clock is available
• Designed for low CPU overhead, with DMA off
loading of FIFO register access
LPUART1
LPUART2
LPUART3
LPUART4
LPUART5
LPUART6
LPUART7
LPUART8
UART Interface
Connectivity
Peripherals
Each of the UART modules support the following serial
data transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 5 Mbps.
MQS
Medium Quality Sound
Multimedia
Peripherals
MQS is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
PXP
Pixel Processing Pipeline
Multimedia
Peripherals
A high-performance pixel processor capable of 1
pixel/clock performance for combined operations, such
as color-space conversion, alpha blending, and
rotation. The PXP is enhanced
with features specifically for gray scale applications. In
addition, the PXP supports traditional pixel/frame
processing paths for still-image and video processing
applications.
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Modules List
Table 2. i.MX RT1064 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
QuadTimer1
QuadTimer2
QuadTimer3
QuadTimer4
QuadTimer
Timer Peripherals The quad-timer provides four time channels with a
variety of controls affecting both individual and
multi-channel features.Specific features include
up/down count, cascading of counters, programmable
module, count once/repeated, counter preload,
compare registers with preload, shared use of input
signals, prescaler controls, independent
capture/compare, fault input control, programmable
input filters, and multi-channel synchronization.
ROMCP
RTC OSC
RTWDOG
ROM Controller with
Patch
Memories and
The ROMCP acts as an interface between the Arm
Memory Controllers advanced high-performance bus and the ROM. The
on-chip ROM is only used by the Cortex-M7 core during
boot up. Size of the ROM is 96 KB.
Real Time Clock
Oscillator
Clock Sources and The RTC OSC provides the clock source for the
Control
Real-Time Clock module. The RTC OSC module, in
conjunction with an external crystal, generates a 32.768
kHz reference clock for the RTC.
Watch Dog
Timer Peripherals The RTWDG module is a high reliability independent
timer that is available for system to use. It provides a
safety feature to ensure software is executing as
planned and the CPU is not stuck in an infinite loop or
executing unintended code. If the WDOG module is not
serviced (refreshed) within a certain period, it resets the
MCU. Windowed refresh mode is supported as well.
SAI1
SAI2
SAI3
Synchronous Audio
Interface
Multimedia
Peripherals
The SAI module provides a synchronous audio
interface (SAI) that supports full duplex serial interfaces
with frame synchronization, such as I2S, AC97, TDM,
and codec/DSP interfaces.
SA-TRNG
SEMC
StandaloneTrueRandom
Number Generator
Security
The SA-TRNG is hardware accelerator that generates
a 512-bit entropy as needed by an entropy consuming
module or by other post processing functions.
Smart External Memory
Controller
Memory and
The SEMC is a multi-standard memory controller
Memory Controller optimized for both high-performance and low pin-count.
It can support multiple external memories in the same
application with shared address and data pins. The
interface supported includes SDRAM, NOR Flash,
SRAM, and NAND Flash, as well as 8080 display
interface.
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Modules List
Table 2. i.MX RT1064 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
SJC
System JTAG Controller
System Control
Peripherals
The SJC provides JTAG interface, which complies with
JTAG TAP standards, to internal logic. The i.MX
RT1064 processors use JTAG port for production,
testing, and system debugging. In addition, the SJC
provides BSR (Boundary Scan Register) standard
support, which complies with IEEE 1149.1 and IEEE
1149.6 standards.
The JTAG port is accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX RT1064 SJC incorporates
three security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
SNVS
SPDIF
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, and Master Key
Control.
Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
A standard audio file transfer format, developed jointly
by the Sony and Phillips corporations. Has Transmitter
and Receiver functionality.
Temp Monitor
Temperature Monitor
Analog
The temperature sensor implements a temperature
sensor/conversion function based on a
temperature-dependent voltage to time conversion.
TSC
Touch Screen
Human Machine
Interfaces
With touch controller to support 4-wire and 5-wire
resistive touch panel.
USBO2
Universal Serial Bus 2.0
Connectivity
Peripherals
USBO2 (USB OTG1 and USB OTG2) contains:
• Two high-speed OTG 2.0 modules with integrated
HS USB PHYs
• Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0
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Modules List
Table 2. i.MX RT1064 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
uSDHC1
uSDHC2
SD/MMC and SDXC
Enhanced Multi-Media
Card / Secure Digital Host
Controller
Connectivity
Peripherals
i.MX RT1064 specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and
are based on the uSDHC IP. They are:
• Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia
Card System Specification, v4.5/4.2/4.3/4.4/4.41/
including high-capacity (size > 2 GB) cards HC
MMC.
• Fully compliant with SD command/response sets
and Physical Layer as defined in the SD Memory
Card Specifications, v3.0 including high-capacity
SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC
chips up to 200 MHz in HS200 mode (200 MB/s max)
WDOG1
WDOG2
Watch Dog
Cross BAR
Timer Peripherals The watchdog (WDOG) Timer supports two comparison
points during each counting period. Each of the
comparison points is configurable to evoke an interrupt
to the Arm core, and a second point evokes an external
event on the WDOG line.
XBAR
Cross Trigger
Each crossbar switch is an array of muxes with shared
inputs. Each mux output provides one output of the
crossbar. The number of inputs and the number of
muxes/outputs are user configurable and registers are
provided to select which of the shared inputs are routed
to each output.
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3.1
Special signal considerations
Table 3 lists special signal considerations for the i.MX RT1064 processors. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 7, Package information and contact
assignments.” Signal descriptions are provided in the i.MX RT1064 Reference Manual
(IMXRT1064RM).
Table 3. Special signal considerations
Signal Name
Remarks
CCM_CLK1_P/
CCM_CLK1_N
One general purpose differential high speed clock Input/output (LVDS I/O) is provided.
It can be used:
• To feed external reference clock to the PLLs and further to the modules inside SoC.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a
functional clock for peripherals.
See the i.MX RT1064 Reference Manual (IMXRT1064RM) for details on the respective clock trees.
Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding
CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.
Termination should be provided in case of high frequency signals.
After initialization, the CLK1 input/output can be disabled (if not used). If unused either or both of
the CLK1_N/P pairs may remain unconnected.
DCDC_PSWITCH
PAD is in DCDC_IN domain and connected the ground to bypass DCDC.
To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge.
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup
margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin must
remain unconnected or driven with a complimentary signal. The logic level of this forcing clock
should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical
conditions.
In case when high accuracy real time clock are not required system may use internal low frequency
ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO
unconnected.
XTALI/XTALO
A 24.0 MHz crystal should be connected between XTALI and XTALO.
The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series
resistance) of typical 80 is recommended. NXP SDK software requires 24 MHz on
XTALI/XTALO.
The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this
case, XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pF
capacitor. The logic level of this forcing clock cannot exceed NVCC_PLL level.
If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter
requirements. See OSC24M chapter and relevant interface specifications chapters for details.
GPANAIO
This signal is reserved for NXP manufacturing use only. This output must remain unconnected.
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Modules List
Table 3. Special signal considerations (continued)
Remarks
Signal Name
JTAG_nnnn
The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,
if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is
followed. For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated
if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and
should be avoided.
JTAG_MOD is referenced as SJC_MOD in the i.MX RT1064 reference manual. Both names refer
to the same signal. JTAG_MOD must be externally connected to GND for normal operation.
Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD
set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD
set to low configures the JTAG interface for common SW debug adding all the system TAPs to the
chain.
NC
These signals are No Connect (NC) and should be disconnected by the user.
POR_B
This cold reset negative logic input resets all modules and logic in the IC.
May be used in addition to internally generated power on reset signal (logical AND, both internal
and external signals are considered active low).
ONOFF
ONOFF can be configured in debounce, off to on time, and max time-out configurations. The
debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to
generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than the
debounce time, the power off interrupt is generated. Off to on time supports the time it takes to
request power on after a configured button press time has been reached. While in the OFF state,
if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON.
Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out configuration
supports the time it takes to request power down after ONOFF button has been pressed for the
defined time.
TEST_MODE
WAKEUP
TEST_MODE is for NXP factory use. The user must tie this pin directly to GND.
A GPIO powered by SNVS domain power supply which can be configured as wakeup source in
SNVS mode.
Table 4. JTAG Controller interface summary
JTAG
I/O Type
On-chip Termination
JTAG_TCK
JTAG_TMS
JTAG_TDI
Input
Input
100 kpull-down
47 kpull-up
47 kpull-up
Keeper
Input
JTAG_TDO
JTAG_TRSTB
JTAG_MOD
3-state output
Input
47 kpull-up
100 kpull-down
Input
3.2
Recommended connections for unused analog interfaces
Table 5 shows the recommended connections for unused analog interfaces.
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Table 5. Recommended connections for unused analog interfaces
Pad Name
Recommendations
if Unused
Module
CCM
USB
CCM_CLK1_N, CCM_CLK1_P
Not connected
Not connected
USB_OTG1_CHD_B, USB_OTG1_DN, USB_OTG1_DP, USB_OTG1_VBUS,
USB_OTG2_DN, USB_OTG2_DP, USB_OTG2_VBUS
ADC
VDDA_ADC_3P3
VDDA_ADC_3P3
must be powered
even if the ADC is
not used.
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Electrical Characteristics
4 Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX RT1064
processors.
4.1
Chip-Level conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
Table 6. i.MX RT1064 chip-Level conditions
For these characteristics
Topic appears
Absolute maximum ratings
Thermal resistance
on page 20
on page 21
on page 22
on page 23
on page 24
on page 26
on page 26
Operating ranges
External clock sources
Maximum supply currents
Low power mode supply currents
USB PHY current consumption
4.1.1
Absolute maximum ratings
CAUTION
Stress beyond those listed under Table 7 may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
Table 7 shows the absolute maximum operating ratings.
Table 7. Absolute maximum ratings
Parameter Description
Core supplies input voltage
Symbol
Min
Max
Unit
VDD_SOC_IN
VDD_HIGH_IN
DCDC_IN
-0.3
-0.3
-0.3
-0.3
1.6
3.7
3.6
3.6
V
V
V
V
VDD_HIGH_IN supply voltage
Power for DCDC
Supply input voltage to Secure Non-Volatile Storage
and Real Time Clock
VDD_SNVS_IN
USB VBUS supply
USB_OTG1_VBUS
USB_OTG2_VBUS
—
5.5
3.6
V
V
Supply for 12-bit ADC
VDDA_ADC
-0.3
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Electrical Characteristics
Table 7. Absolute maximum ratings (continued)
IO supply for GPIO in SDIO1 bank (3.3 V mode)
NVCC_SD0
NVCC_SD1
NVCC_EMC
Vesd
-0.3
3.6
1.95
3.6
V
V
V
V
V
V
IO supply for GPIO in SDIO1 bank (1.8 V mode)
IO supply for GPIO in SDIO2 bank (3.3 V mode)
IO supply for GPIO in SDIO2 bank (1.8 V mode)
IO supply for GPIO in EMC bank (3.3 V mode)
IO supply for GPIO in EMC bank (1.8 V mode)
ESD damage Immunity:
-0.3
-0.3
-0.3
-0.3
-0.3
1.95
3.6
1.95
Human Body Model (HBM)
Charge Device Model (CDM)
—
—
1000
500
V
Input/Output Voltage range
Storage Temperature range
Vin/Vout
-0.5
-40
OVDD + 0.31
150
V
TSTORAGE
o C
1
OVDD is the I/O supply voltage.
4.1.2
Thermal resistance
4.1.2.1
10 x 10 mm thermal resistance
Table 9 shows the 10 x 10 mm package thermal resistance data.
Table 8. 10 x 10 mm thermal resistance data
Rating
Board type1
JESD51-9, 2S2P
Symbol
Value
Unit
Junction to Ambient
RJA
39.5
oC/W
Thermal Resistance2
Junction-to-Top of Package Thermal
Characterization Parameter2
JESD51-9, 2S2P
JT
2.65
oC/W
1
Thermal test board meets JEDEC specification for this package (JESD51-9).
2
Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not
meant to predict the performance of a package in an application-specific environment.
4.1.2.2
12 x 12 mm thermal resistance
Table 9 shows the 12 x 12 mm package thermal resistance data.
Table 9. 12 x 12 mm thermal resistance data
Rating
Board type1
JESD51-9, 2S2P
Symbol
Value
Unit
Junction to Ambient
RJA
39.0
oC/W
Thermal Resistance2
Junction-to-Top of Package Thermal
Characterization Parameter2
JESD51-9, 2S2P
JT
2.75
oC/W
1
Thermal test board meets JEDEC specification for this package (JESD51-9).
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Electrical Characteristics
2
Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not
meant to predict the performance of a package in an application-specific environment.
4.1.3
Operating ranges
Table 10 provides the operating ranges of the i.MX RT1064 processors. For details on the chip's power
structure, see the “Power Management Unit (PMU)” chapter of the i.MX RT1064 Reference Manual
(IMXRT1064RM).
Table 10. Operating ranges
Parameter
Description
Operating
Conditions
Symbol
Min
Typ Max1 Unit
Comment
Run Mode
VDD_SOC_IN
M7 core at 528
MHz
1.15
—
—
—
—
1.26
1.26
1.26
1.26
V
—
—
M7 core at 132
MHz
1.15
0.925
1.15
M7 core at 24
MHz
IDLE Mode
VDD_SOC_IN
VDD_SOC_IN
M7 core
operation at 528
MHz or below
V
V
SUSPEND (DSM)
Mode
—
0.925
—
1.26
Refer to Table 13 Low power mode
current and power consumption
SNVS Mode
VDD_SOC_IN
DCDC_IN
—
—
—
0
—
—
—
1.26
3.6
V
V
V
—
—
Power for DCDC
3.0
3.0
VDD_HIGH
VDD_HIGH_IN2
3.6
Must match the range of voltages
that the rechargeable backup
battery supports.
internal Regulator
Backup battery
supply range
VDD_SNVS_IN3
—
2.40
—
3.6
V
Can be combined with
VDD_HIGH_IN, if the system does
not require keeping real time and
other data on OFF state.
USB supply
voltages
USB_OTG1_VBUS
USB_OTG2_VBUS
NVCC_GPIO
—
—
—
—
4.40
4.40
3.0
—
5.5
5.5
V
V
V
V
V
V
V
V
V
—
—
—
GPIO supplies
3.3
1.8
3.3
1.8
3.3
1.8
3.3
3.6
All digital I/O supplies
(NVCC_xxxx) must be powered
(unless otherwise specified in this
data sheet) under normal
conditions whether the associated
I/O pins are in use or not.
NVCC_SD0
1.65
3.0
1.95
3.6
NVCC_SD1
NVCC_EMC
—
—
1.65
3.0
1.95
3.6
1.65
3.0
1.95
1.95
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Table 10. Operating ranges (continued)
3.0 3.3 3.6
A/D converter
VDDA_ADC_3P3
—
V
VDDA_ADC_3P3 must be
powered even if the ADC is not
used.
VDDA_ADC_3P3 cannot be
powered when the other SoC
supplies (except VDD_SNVS_IN)
are off.
Temperature Operating Ranges
Junction
temperature
Tj
Standard
Commercial
-40
—
105
oC See the application note, i.MX
RT1064 Product Lifetime Usage
Estimates for information on
product lifetime (power-on years)
for this processor.
1
Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set
point = (Vmin + the supply tolerance). This result in an optimized power/speed ratio.
2
3
Applying the maximum voltage results in shorten lifetime. 3.6 V usage limited to < 1% of the use profile. Reset of profile limited
to below 3.49 V.
In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX RT1064 Hardware
Development Guide (IMXRT1064HDG).
4.1.4
External clock sources
Each i.MX RT1064 processor has two external input system clocks: a low frequency (RTC_XTALI) and
a high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, and slow system and watch-dog counters. The clock input can be
connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is
an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either external oscillator or a crystal using internal
oscillator amplifier.
Table 11 shows the interface frequency requirements.
Table 11. External input clock frequency
Parameter Description
Symbol
Min
Typ
Max
Unit
RTC_XTALI Oscillator1,2
XTALI Oscillator2,4
fckil
fxtal
—
—
32.7683/32.0
24
—
—
kHz
MHz
1
External oscillator or a crystal with internal oscillator amplifier.
2
The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware
Development Guide for i.MX RT1064 Crossover Processors (IMXRT1064HDG).
3
4
Recommended nominal frequency 32.768 kHz.
External oscillator or a fundamental frequency crystal with internal oscillator amplifier.
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Electrical Characteristics
The typical values shown in Table 11 are required for use with NXP SDK to ensure precise time keeping
and USB operation. For RTC_XTALI operation, two clock sources are available.
•
On-chip 40 kHz ring oscillator—this clock source has the following characteristics:
— Approximately 25 µA more Idd than crystal oscillator
— Approximately ±50% tolerance
— No external component required
— Starts up quicker than 32 kHz crystal oscillator
External crystal oscillator with on-chip support circuit:
•
— At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit
switches over to the crystal oscillator automatically.
— Higher accuracy than ring oscillator
— If no external crystal is present, then the ring oscillator is utilized
The decision of choosing a clock source should be taken based on real-time clock use and precision
time-out.
4.1.5
Maximum supply currents
The data shown in Table 12 represent a use case designed specifically to show the maximum current
consumption possible. All cores are running at the defined maximum frequency and are limited to L1
cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited
practical use case, if at all, and be limited to an extremely low duty cycle unless the intention were to
specifically show the worst case power consumption.
See the i.MX RT1064 Power Consumption Measurement Application Note for more details on typical
power consumption under various use case definitions.
Table 12. Maximum supply currents
Power Rail
Conditions
Max Current
Unit
DCDC_IN
Max power for chip at 105 oC with core
mark run on FlexRAM
110
mA
VDD_HIGH_IN
VDD_SNVS_IN
Include internal loading in analog
—
50
250
50
mA
A
USB_OTG1_VBUS
USB_OTG2_VBUS
25 mA for each active USB interface
mA
VDDA_ADC_3P3
3.3 V power supply for 12-bit ADC, 600
A typical, 750 A max, for each ADC.
100 Ohm max loading for touch panel,
cause 33 mA current.
40
mA
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Table 12. Maximum supply currents (continued)
Conditions
Power Rail
Max Current
Unit
NVCC_GPIO
NVCC_SD0
NVCC_SD1
NVCC_EMC
Imax = N x C x V x (0.5 x F)
Where:
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 x F)—Data change rate. Up to 0.5 of the clock rate (F)
In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.
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Electrical Characteristics
4.1.6
Low power mode supply currents
Table 13 shows the current core consumption (not including I/O) of i.MX RT1064 processors in selected
low power modes.
Table 13. Low power mode current and power consumption
Mode
Test Conditions
Supply
Typical1
Units
SYSTEM IDLE
• LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V
• CPU in WFI, CPU clock gated
• 24 MHz XTAL is ON
• System PLL is active, other PLLs are power down
• Peripheral clock gated, but remain powered
DCDC_IN (3.3 V)
VDD_HIGH_IN (3.3 V)
VDD_SNVS_IN (3.3 V)
Total
4.04
7.66
mA
0.032
38.72
1.11
mW
mA
LOW POWER IDLE • LDO_2P5 and LDO_1P1 are set to Weak mode
• WFI, half FlexRAM power down in power gate
mode
DCDC_IN (3.3 V)
VDD_HIGH_IN (3.3 V)
VDD_SNVS_IN (3.3 V)
Total
0.309
0.048
4.84
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC used as
clock source
mW
mA
• Peripheral clock gated, but remain powered
SUSPEND
(DSM)
• LDO_2P5 and LDO_1P1 are shut off
• CPU in Power Gate mode
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC is off
• All clocks are shut off, except 32 kHz RTC
• Peripheral clock gated, but remain powered
DCDC_IN (3.3 V)
VDD_HIGH_IN (3.3 V)
VDD_SNVS_IN (3.3 V)
Total
0.19
0.029
0.020
0.789
0
mW
mA
SNVS (RTC)
• All SOC digital logic, analog module are shut off
• 32 kHz RTC is alive
DCDC_IN (0 V)
VDD_HIGH_IN (0 V)
VDD_SNVS_IN (3.3 V)
Total
0
0.02
0.066
mW
1
The typical values shown here are for information only and are not guaranteed. These values are average values measured
on a typical process wafer at 25oC.
4.1.7
USB PHY current consumption
Power down mode
4.1.7.1
In power down mode, everything is powered down, including the USB VBUS valid detectors in typical
condition. Table 14 shows the USB interface current consumption in power down mode.
Table 14. USB PHY current consumption in power down mode
VDD_USB_CAP (3.0 V)
VDD_HIGH_CAP (2.5 V)
NVCC_PLL (1.1 V)
Current
5.1 A
1.7 A
< 0.5 A
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NOTE
The currents on the VDD_HIGH_CAP and VDD_USB_CAP were
identified to be the voltage divider circuits in the USB-specific level
shifters.
4.2
System power and clocks
This section provide the information about the system power and clocks.
4.2.1
Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
•
•
•
Excessive current during power-up phase
Prevention of the device from booting
Irreversible damage to the processor (worst-case scenario)
4.2.1.1
Power-up sequence
The below restrictions must be followed:
•
•
•
•
•
VDD_SNVS_IN supply must be turned on before any other power supply or be connected
(shorted) with VDD_HIGH_IN supply.
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other
supply is switched on.
When internal DCDC is enabled, external delay circuit is required to delay the
“DCDC_PSWITCH” signal 1 ms after DCDC_IN is stable.
Need to ensure DCDC_IN ramps to 3.0 V within 0.2 x RC, RC is from external delay circuit used
for DCDC_PSWITCH and must be longer than 1 ms.
POR_B should be held low during the entire power up sequence.
NOTE
The POR_B input (if used) must be immediately asserted at power-up and
remain asserted until after the last power rail reaches its working voltage. In
the absence of an external reset feeding the POR_B input, the internal POR
module takes control. See the i.MX RT1064 Reference Manual
(IMXRT1064RM) for further details and to ensure that all necessary
requirements are being met.
NOTE
Need to ensure that there is no back voltage (leakage) from any supply on
the board towards the 3.3 V supply (for example, from the external
components that use both the 1.8 V and 3.3 V supplies).
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NOTE
USB_OTG1_VBUS, USB_OTG2_VBUS, and VDDA_ADC_3P3 are not
part of the power supply sequence and may be powered at any time.
4.2.1.2
Power-down sequence
The following restrictions must be followed:
•
VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted)
with VDD_HIGH_IN supply.
•
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply
is switched off.
4.2.1.3
Power supplies usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.
This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O
power supply of each pin, see “Power Rail” columns in pin list tables of Section 7, Package information
and contact assignments.”
4.2.2
Integrated LDO voltage regulator parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins
named *_CAP must be connected to external capacitors. The on-board LDOs are intended for internal use
only and should not be used to power any external circuitry. See the i.MX RT1064 Reference Manual
(IMXRT1064RM) for details on the power tree scheme.
NOTE
The *_CAP signals should not be powered externally. These signals are
intended for internal LDO operation only.
4.2.2.1
Digital regulators (LDO_SNVS)
There are one digital LDO regulator (“Digital”, because of the logic loads that they drive, not because of
their construction). The advantages of the regulator is to reduce the input supply variation because of its
input supply ripple rejection and its on-die trimming. This translates into more stable voltage for the
on-chip logics.
The regulator has two basic modes:
•
Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.
The analog part of the regulator is powered down here limiting the power consumption.
•
Analog regulation mode. The regulation FET is controlled such that the output voltage of the
regulator equals the target voltage.
For additional information, see the i.MX RT1064 Reference Manual (IMXRT1064RM).
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4.2.2.2
Regulators for analog modules
LDO_1P1
4.2.2.2.1
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0
V to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB Phy, and PLLs. A
programmable brown-out detector is included in the regulator that can be used by the system to determine
when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting
can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can
also be enabled for systems requiring this feature.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX RT1064 Crossover Processors (IMXRT1064HDG).
For additional information, see the i.MX RT1064 Reference Manual (IMXRT1064RM).
4.2.2.2.2
LDO_2P5
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 10 for minimum and maximum input requirements). Typical Programming Operating Range is
2.25 V to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the USB PHY, E-fuse
module, and PLLs. A programmable brown-out detector is included in the regulator that can be used by
the system to determine when the load capability of the regulator is being exceeded, to take the necessary
steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.
Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased
low-precision weak-regulator is included that can be enabled for applications needing to keep the output
voltage alive during low-power modes where the main regulator driver and its associated global bandgap
reference module are disabled. The output of the weak-regulator is not programmable and is a function of
the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output
is 2.525 V and its output impedance is approximately 40 .
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX RT1064 Crossover Processors (IMXRT1064HDG).
For additional information, see the i.MX RT1064 Reference Manual (IMXRT1064RM).
4.2.2.2.3
LDO_USB
The LDO_USB module implements a programmable linear-regulator function from the USB VUSB
voltages (4.4 V–5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector
is included in the regulator that can be used by the system to determine when the load capability of the
regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows
the user to select to run the regulator from either USB VBUS supply, when both are present. If only one
of the USB VBUS voltages is present, then, the regulator automatically selects this supply. Current limit
is also included to help the system meet in-rush current targets.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX RT1064 Crossover Processors (IMXRT1064HDG).
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For additional information, see the i.MX RT1064 Reference Manual (IMXRT1064RM).
4.2.2.2.4
DCDC
DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During
the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a
minimum quiescent current to maintain high efficiency.
DCDC can detect the peak current in the P-channel switch. When the peak current exceeds the threshold,
DCDC will give an alert signal, and the threshold can be configured. By this way, DCDC can roughly
detect the current loading.
DCDC also includes the following protection functions:
•
Over current protection. In run mode, DCDC shuts down when detecting abnormal large current in
the P-type power switch.
•
•
Over voltage protection. DCDC shuts down when detecting the output voltage is too high.
Low voltage detection. DCDC shuts down when detecting the input voltage is too low.
For additional information, see the i.MX RT1064 Reference Manual (IMXRT1064RM).
4.2.3
PLL’s electrical characteristics
This section provides PLL electrical characteristics.
4.2.3.1 Audio/Video PLL’s electrical parameters
Table 15. Audio/Video PLL’s electrical parameters
Parameter
Value
Clock output range
Reference clock
Lock time
650 MHz ~1.3 GHz
24 MHz
< 11250 reference cycles
4.2.3.2
System PLL
Table 16. System PLL’s electrical parameters
Parameter
Value
Clock output range
Reference clock
Lock time
528 MHz PLL output
24 MHz
< 11250 reference cycles
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4.2.3.3
4.2.3.4
4.2.3.5
Ethernet PLL
Table 17. Ethernet PLL’s electrical parameters
Parameter
Value
Clock output range
Reference clock
Lock time
1 GHz
24 MHz
< 11250 reference cycles
USB PLL
Table 18. USB PLL’s electrical parameters
Parameter
Value
Clock output range
Reference clock
Lock time
480 MHz PLL output
24 MHz
< 383 reference cycles
Arm PLL
Table 19. Arm PLL’s electrical parameters
Parameter
Value
Clock output range
Reference clock
Lock time
648 MHz ~ 1296 MHz
24 MHz
< 2250 reference cycles
4.2.4
On-chip oscillators
OSC24M
4.2.4.1
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement an oscillator. The oscillator is powered from NVCC_PLL.
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight
forward biased-inverter implementation is used.
4.2.4.2
OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement a low power oscillator. It also implements a power mux such that it can be powered
from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes
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power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when
VDD_HIGH_IN is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K
will automatically switch to a crude internal ring oscillator. The frequency range of this block is
approximately 10–45 kHz. It highly depends on the process, voltage, and temperature.
The OSC32k runs from VDD_SNVS_CAP supply, which comes from the
VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type
is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when
connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For
example, for Panasonic ML621:
•
•
Average Discharge Voltage is 2.5 V
Maximum Charge Current is 0.6 mA
For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k.
Table 20. OSC32K main characteristics
Min
Typ
Max Comments
Fosc
—
32.768 KHz
—
—
This frequency is nominal and determined mainly by the crystal selected.
32.0 K would work as well.
Current consumption
—
4 A
The 4 A is the consumption of the oscillator alone (OSC32k). Total supply
consumption will depend on what the digital portion of the RTC consumes.
The ring oscillator consumes 1 A when ring oscillator is inactive, 20 A
when the ring oscillator is running. Another 1.5 A is drawn from vdd_rtc in
the power_detect block. So, the total current is 6.5 A on vdd_rtc when the
ring oscillator is not running.
Bias resistor
—
14 M
—
—
This integrated bias resistor sets the amplifier into a high gain state. Any
leakage through the ESD network, external board leakage, or even a
scope probe that is significant relative to this value will debias the amp. The
debiasing will result in low gain, and will impact the circuit's ability to start
up and maintain oscillations.
Crystal Properties
Cload
ESR
—
—
10 pF
Usually crystals can be purchased tuned for different Cloads. This Cload
value is typically 1/2 of the capacitances realized on the PCB on either side
of the quartz. A higher Cload will decrease oscillation margin, but
increases current oscillating through the crystal.
50 k
100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher
value will decrease the oscillating margin.
4.3
I/O parameters
This section provide parameters on I/O interfaces.
4.3.1
I/O DC parameters
This section includes the DC parameters of the following I/O types:
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•
•
•
XTALI and RTC_XTALI (Clock Inputs) DC Parameters
General Purpose I/O (GPIO)
LVDS I/O DC Parameters
NOTE
The term ‘NVCC_XXXX’in this section refers to the associated supply rail
of an input or output.
Figure 3. Circuit for parameters Voh and Vol for I/O cells
4.3.1.1
XTALI and RTC_XTALI (clock inputs) DC parameters
Table 21 shows the DC parameters for the clock inputs.
1
Table 21. XTALI and RTC_XTALI DC parameters
Symbol Test Conditions Min
Parameter
Max
Unit
XTALI high-level DC input voltage
XTALI low-level DC input voltage
Vih
Vil
—
—
—
—
0.8 x NVCC_PLL
NVCC_PLL
V
V
V
V
0
0.8
0
0.2
1.1
0.2
RTC_XTALI high-level DC input voltage
RTC_XTALI low-level DC input voltage
Vih
Vil
1
The DC parameters are for external clock input only.
4.3.1.2
Single voltage general purpose I/O (GPIO) DC parameters
Table 22 shows DC parameters for GPIO pads. The parameters in Table 22 are guaranteed per the
operating ranges in Table 10, unless otherwise noted.
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Table 22. Single voltage GPIO DC parameters
Parameter
Symbol
Test Conditions
Min
Max
Units
High-level output voltage1
VOH
Ioh= -0.1mA (ipp_dse=001,010) NVCC_XXXX-
–
V
Ioh= -1mA
(ipp_dse=011,100,101,110,111)
0.15
–
Low-level output voltage1
High-level output current
VOL
IOH
Iol= 0.1mA (ipp_dse=001,010)
Iol= 1mA
0.15
V
(ipp_dse=011,100,101,110,111)
VDDE = 3.3 V, VOH = VDDE - 0.45
—
—
V, ipp_dse as follows:
001
010
011
110
101
110
111
1
1
2
2
2
4
4
Low-level output current
IOL
VDDE = 3.3 V, VOL = 0.45 V,
—
—
ipp_dse as follows:
001
010
011
110
101
110
111
1
1
2
2
2
4
4
High-Level input voltage1,2
Low-Level input voltage1,2
VIH
VIL
—
0.7 x
NVCC_XXXX
NVCC_XXXX
V
—
0
0.3 x
V
NVCC_XXXX
Input Hysteresis
(NVCC_XXXX= 1.8V)
VHYS_LowVDD
VHYS_HighVDD
VTH+
NVCC_XXXX=1.8V
250
250
—
—
—
mV
mV
mV
mV
Input Hysteresis
(NVCC_XXXX=3.3V)
NVCC_XXXX=3.3V
Schmitt trigger VT+2,3
—
—
0.5 x
NVCC_XXXX
Schmitt trigger VT-2,3
VTH-
—
0.5 x
NVCC_XXXX
Pull-up resistor (22_k PU)
Pull-up resistor (22_k PU)
Pull-up resistor (47_k PU)
Pull-up resistor (47_k PU)
Pull-up resistor (100_k PU)
Pull-up resistor (100_k PU)
RPU_22K
RPU_22K
RPU_47K
RPU_47K
RPU_100K
RPU_100K
Vin=0V
Vin=NVCC_XXXX
Vin=0V
—
—
—
—
—
—
212
1
A
A
A
A
A
A
100
1
Vin=NVCC_XXXX
Vin=0V
48
1
Vin=NVCC_XXXX
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Table 22. Single voltage GPIO DC parameters (continued)
Parameter
Symbol
Test Conditions
Min
Max
Units
Pull-down resistor (100_k
RPD_100K
Vin=NVCC_XXXX
—
48
A
PD)
Pull-down resistor (100_k
RPD_100K
Vin=0V
—
1
A
PD)
Input current (no PU/PD)
Keeper Circuit Resistance
IIN
VI = 0, VI = NVCC_XXXX
-1
1
A
k
R_Keeper
VI =0.3 x NVCC_XXXX, VI = 0.7 x
NVCC_XXXX
105
175
1
Overshoot and undershoot conditions (transitions above NVCC_XXXX and below GND) on switching pads must be held
below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/
undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line
termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage
to the device.
2
3
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4.3.1.3
LVDS I/O DC parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 23 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.
1
Table 23. LVDS I/O DC characteristics
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Differential Voltage
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
VOH
VOL
VOS
Rload-100 Diff
IOH = 0 mA
IOL = 0 mA
—
250
1.25
0.9
350
1.375
1.025
1.2
450
1.6
mV
V
1.25
1.375
V
1.125
V
1
Note: The LVDS interface is limited to CCM_CLK1_P and CCM_CLK1_N.
4.3.2
I/O AC parameters
This section includes the AC parameters of the following I/O types:
General Purpose I/O (GPIO)
•
Figure 4 shows load circuit for output, and Figure 5 show the output transition time waveform.
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From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 4. Load circuit for output
OVDD
0 V
80%
20%
80%
20%
tr
Output (at pad)
tf
Figure 5. Output transition time waveform
4.3.2.1
General purpose I/O AC parameters
The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 24 and Table 25,
respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the
IOMUXC control registers.
Table 24. General purpose I/O AC parameters 1.8 V mode
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times, rise/fall
(Max Drive, ipp_dse=111)
tr, tf
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
2.72/2.79
1.51/1.54
—
—
Output Pad Transition Times, rise/fall
(High Drive, ipp_dse=101)
tr, tf
tr, tf
tr, tf
trm
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
3.20/3.36
1.96/2.07
—
—
—
—
ns
Output Pad Transition Times, rise/fall
(Medium Drive, ipp_dse=100)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
3.64/3.88
2.27/2.53
Output Pad Transition Times, rise/fall
(Low Drive. ipp_dse=011)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
4.32/4.50
3.16/3.17
—
—
—
—
Input Transition Times1
—
25
ns
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
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Table 25. General purpose I/O AC parameters 3.3 V mode
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times, rise/fall
(Max Drive, ipp_dse=101)
tr, tf
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
1.70/1.79
1.06/1.15
—
—
Output Pad Transition Times, rise/fall
(High Drive, ipp_dse=011)
tr, tf
tr, tf
tr, tf
trm
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
2.35/2.43
1.74/1.77
—
—
—
—
ns
Output Pad Transition Times, rise/fall
(Medium Drive, ipp_dse=010)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
3.13/3.29
2.46/2.60
Output Pad Transition Times, rise/fall
(Low Drive. ipp_dse=001)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
5.14/5.57
4.77/5.15
—
—
—
—
ns
ns
Input Transition Times1
—
25
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
4.3.3
Output buffer impedance parameters
This section defines the I/O impedance parameters of the i.MX RT1064 processors for the following I/O
types:
•
Single Voltage General Purpose I/O (GPIO)
NOTE
GPIO I/O output driver impedance is measured with “long” transmission
line of impedance Ztl attached to I/O pad and incident wave launched into
transmission line. Rpu/Rpd and Ztl form a voltage divider that defines
specific voltage of incident wave relative to NVCC_XXXX. Output driver
impedance is calculated from this voltage divider (see Figure 6).
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OVDD
PMOS (Rpu)
Ztl , L = 20 inches
ipp_do
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
VDD
(do)
Vin
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref2
Vref1
Vref
t,(ns)
0
Vref2
Vovdd - Vref1
Vref1
Rpd =
Ztl
Rpu =
Ztl
Vovdd - Vref2
Figure 6. Impedance matching load for measurement
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4.3.3.1
Single voltage GPIO output buffer impedance
Table 26 shows the GPIO output buffer impedance (NVCC_XXXX 1.8 V).
Table 26. GPIO output buffer average impedance (NVCC_XXXX 1.8 V)
Parameter
Symbol
Drive Strength (DSE)
Typ Value
Unit
001
010
011
100
101
110
111
260
130
88
65
52
Output Driver
Impedance
Rdrv
43
37
Table 27 shows the GPIO output buffer impedance (NVCC_XXXX 3.3 V).
Table 27. GPIO output buffer average impedance (NVCC_XXXX 3.3 V)
Parameter
Symbol
Drive Strength (DSE)
Typ Value
Unit
001
010
011
100
101
110
111
157
78
53
39
32
26
23
Output Driver
Impedance
Rdrv
4.4
System modules
This section contains the timing and electrical parameters for the modules in the i.MX RT1064 processor.
4.4.1
Reset timings parameters
Figure 7 shows the reset timing and Table 28 lists the timing parameters.
POR_B
(Input)
CC1
Figure 7. Reset timing diagram
Table 28. Reset timing parameters
ID
Parameter
Min Max
Unit
CC1
Duration of POR_B to be qualified as valid.
1
—
RTC_XTALI cycle
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4.4.2
WDOG reset timing parameters
Figure 8 shows the WDOG reset timing and Table 29 lists the timing parameters.
WDOGn_B
(Output)
CC3
Figure 8. WDOGn_B timing diagram
Table 29. WDOGn_B timing parameters
ID
Parameter
Duration of WDOGn_B Assertion
Min
Max
Unit
CC3
1
—
RTC_XTALI cycle
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 s.
NOTE
WDOGn_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
4.4.3
SCAN JTAG Controller (SJC) timing parameters
Figure 9 depicts the SJC test clock input timing. Figure 10 depicts the SJC boundary scan timing.
Figure 11 depicts the SJC test access port. Signal parameters are listed in Table 30.
SJ1
SJ2
SJ2
JTAG_TCK
(Input)
VM
VM
VIH
VIL
SJ3
SJ3
Figure 9. Test clock input timing diagram
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JTAG_TCK
(Input)
VIH
SJ5
VIL
SJ4
Input Data Valid
Data
Inputs
SJ6
Data
Outputs
Output Data Valid
SJ7
SJ6
Data
Outputs
Data
Outputs
Output Data Valid
Figure 10. Boundary Scan (JTAG) timing diagram
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JTAG_TCK
(Input)
VIH
VIL
SJ8
Input Data Valid
SJ9
JTAG_TDI
JTAG_TMS
(Input)
SJ10
SJ11
SJ10
JTAG_TDO
(Output)
Output Data Valid
JTAG_TDO
(Output)
JTAG_TDO
(Output)
Output Data Valid
Figure 11. Test access port timing diagram
JTAG_TCK
(Input)
SJ13
JTAG_TRST_B
(Input)
SJ12
Figure 12. JTAG_TRST_B timing diagram
Table 30. JTAG timing
All Frequencies
ID
Parameter1,2
Unit
Min
Max
1
SJ0
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
SJ7
SJ8
JTAG_TCK frequency of operation 1/(3•TDC
)
0.001
45
22.5
—
22
—
—
3
MHz
ns
JTAG_TCK cycle time in crystal mode
2
JTAG_TCK clock pulse width measured at VM
JTAG_TCK rise and fall times
ns
ns
Boundary scan input data set-up time
Boundary scan input data hold time
JTAG_TCK low to output data valid
JTAG_TCK low to output high impedance
JTAG_TMS, JTAG_TDI data set-up time
5
—
—
40
40
—
ns
24
—
ns
ns
—
ns
5
ns
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Table 30. JTAG timing (continued)
Parameter1,2
All Frequencies
ID
Unit
Min
Max
SJ9
JTAG_TMS, JTAG_TDI data hold time
JTAG_TCK low to JTAG_TDO data valid
JTAG_TCK low to JTAG_TDO high impedance
JTAG_TRST_B assert time
25
—
—
44
44
—
—
ns
ns
ns
ns
ns
SJ10
SJ11
SJ12
SJ13
—
100
40
JTAG_TRST_B set-up time to JTAG_TCK low
1
2
T
= target frequency of SJC
DC
VM = mid-point voltage
4.4.4
Debug trace timing specifications
Table 31. Debug trace operating behaviors
Symbol
Description
Min
Max
Unit
T1
T2
T3
T4
T5
T6
T7
T8
ARM_TRACE_CLK frequency of operation
ARM_TRACE_CLK period
Low pulse width
—
1/T1
6
70
—
—
—
1
MHz
MHz
ns
High pulse width
6
ns
Clock and data rise time
Clock and data fall time
Data setup
—
—
2
ns
1
ns
—
—
ns
Data hold
0.7
ns
!2-?42!#%?#,+
4ꢀ
T6
T4
4ꢂ
4ꢁ
Figure 13. ARM_TRACE_CLK specifications
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ARM_TRACE_CLK
ARM_TRACE0-3
T7
T8
T7
T8
Figure 14. Trace data specifications
4.5
External memory interface
The following sections provide information about external memory interfaces.
4.5.1
SEMC specifications
The following sections provide information on SEMC interface.
Measurements are with a load of 15 pf and an input slew rate of 1 V/ns.
4.5.1.1
SEMC output timing
There are ASYNC and SYNC mode for SEMC output timing.
4.5.1.1.1
SEMC output timing in ASYNC mode
Table 32 shows SEMC output timing in ASYNC mode.
Table 32. SEMC output timing in ASYNC mode
Symbol
Parameter
Min.
Max.
Unit
Comment
Frequency of operation
Internal clock period
Address output valid time
Address output hold time
ADV# low time
—
6
166
—
2
MHz
ns
TCK
TAVO
TAHO
TADVL
TDVO
TDHO
TWEL
—
ns
These timing parameters
apply to Address and ADV#
for NOR/PSRAM in ASYNC
mode.
(TCK - 2) 1
(TCK - 1) 2
—
—
ns
Data output valid time
Data output hold time
WE# low time
2
ns
ns
ns
These timing parameters
apply to Data/CLE/ALE and
WE# for NAND, apply to
Data/DM/CRE for
NOR/PSRAM, apply to
Data/DCX and WRX for DBI
interface.
(TCK - 2) 3
(TCK - 1) 4
—
1
Address output hold time is configurable by SEMC_*CR0.AH. AH field setting value is 0x0 in above table. When AH is set
with value N, TAHO min time should be ((N + 1) x TCK). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more
detail about SEMC_*CR0.AH register field.
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2
3
4
ADV# low time is configurable by SEMC_*CR0.AS. AS field setting value is 0x0 in above table. When AS is set with value N,
T
ADL min time should be ((N + 1) x TCK - 1). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more detail about
SEMC_*CR0.AS register field.
Data output hold time is configurable by SEMC_*CR0.WEH. WEH field setting value is 0x0 in above table. When WEH is set
with value N, TDHO min time should be ((N + 1) x TCK). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more
detail about SEMC_*CR0.WEH register field.
WE# low time is configurable by SEMC_*CR0.WEL. WEL field setting value is 0x0 in above table. When WEL is set with value
N, TWEL min time should be ((N + 1) x TCK - 1). See the i.MX RT1064 Reference Manual (IMXRT1064RM) for more detail
about SEMC_*CR0.WEL register field.
Figure 15 shows the output timing in ASYNC mode.
4#+
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$
4!(/
4$(/
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4$6/
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7%ꢃ
Figure 15. SEMC output timing in ASYNC mode
4.5.1.1.2
SEMC output timing in SYNC mode
Table 33 shows SEMC output timing in SYNC mode.
Table 33. SEMC output timing in SYNC mode
Symbol
Parameter
Min.
Max.
Unit
Comment
Frequency of operation
Internal clock period
Data output valid time
Data output hold time
—
6
166
—
1
MHz
ns
—
—
TCK
TDVO
TDHO
—
-1
ns
These timing parameters apply to
Address/Data/DM/CKE/control
signals with SEMC_CLK for
SDRAM.
—
ns
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Figure 16 shows the output timing in SYNC mode.
3%-#?#,+
4$6/
4
$(/
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Figure 16. SEMC output timing in SYNC mode
4.5.1.2
SEMC input timing
There are ASYNC and SYNC mode for SEMC input timing.
4.5.1.2.1
SEMC input timing in ASYNC mode
Table 34 shows SEMC output timing in ASYNC mode.
Table 34. SEMC output timing in ASYNC mode
Symbol
Parameter
Min.
Max.
Unit
Comment
TIS
TIH
Data input setup
Data input hold
8.67
0
—
—
ns
ns
ForNAND/NOR/PSRAM/DBI,
thesetimingparametersapply
to RE# and Read Data.
Figure 17 shows the input timing in ASYNC mode.
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Figure 17. SEMC input timing in ASYNC mode
4.5.1.2.2
SEMC input timing in SYNC mode
Table 35 and Table 36 show SEMC input timing in SYNC mode.
Table 35. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x0)
Symbol
Parameter
Min.
Max.
Unit
Comment
TIS
TIH
Data input setup
Data input hold
8.67
0
—
—
ns
ns
—
Table 36. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x1)
Symbol
Parameter
Min.
Max.
Unit
Comment
TIS
TIH
Data input setup
Data input hold
0.6
1
—
—
ns
ns
—
Figure 18 shows the input timing in SYNC mode.
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3%-#?#,+
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Figure 18. SEMC input timing in SYNC mode
4.5.2
FlexSPI parameters
Measurements are with a load 15 pf and input slew rate of 1 V/ns.
4.5.2.1 FlexSPI input/read timing
There are four sources for the internal sample clock for FlexSPI read data:
• Dummy read strobe generated by FlexSPI controller and looped back internally
(FlexSPIn_MCR0[RXCLKSRC] = 0x0)
• Dummy read strobe generated by FlexSPI controller and looped back through the
DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)
• Read strobe provided by memory device and input from DQS pad
(FlexSPIn_MCR0[RXCLKSRC] = 0x3)
The following sections describe input signal timing for each of these four internal sample clock sources.
4.5.2.1.1
SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 37. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
8.67
0
60
—
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
ns
Table 38. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X1
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
2
133
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
1
—
ns
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SCK
TIS
TIH
TIS
TIH
SIO[0:7]
Internal Sample Clock
Figure 19. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge, and FlexSPI controller sampling read data on the falling edge.
4.5.2.1.2
SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in SDR mode:
• A1—Memory generates both read data and read strobe on SCK rising edge (or falling
edge)
• A2—Memory generates read data on SCK falling edge and generates read strobe on
SCK rising edgeSCK rising edge
Table 39. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A1)
Value
Symbol
Parameter
Unit
Min
Max
Frequency of operation
—
—
—
-2
166
—
—
2
MHz
ns
TSCKD
Time from SCK to data valid
Time from SCK to DQS
TSCKDQS
ns
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
ns
SCK
TSCKD
TSCKD
SIO[0:7]
TSCKDQS
TSCKDQS
DQS
Figure 20. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A1)
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NOTE
Timing shown is based on the memory generating read data and read strobe
on the SCK rising edge. The FlexSPI controller samples read data on the
DQS falling edge.
Table 40. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A2)
Value
Symbol
Parameter
Unit
Min
Max
Frequency of operation
—
—
—
-2
166
—
—
2
MHz
ns
TSCKD
Time from SCK to data valid
Time from SCK to DQS
TSCKDQS
ns
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
ns
SCK
TSCKD
TSCKD
TSCKD
SIO[0:7]
TSCKDQS
TSCKDQS
TSCKDQS
DQS
Internal Sample Clock
Figure 21. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A2)
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge and read strobe on the SCK rising edge. The FlexSPI controller
samples read data on a half cycle delayed DQS falling edge.
4.5.2.1.3
DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 41. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
8.67
0
30
—
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
ns
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Table 42. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
2
66
—
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
1
ns
SCLK
TIS
TIH
TIS
TIH
SIO[0:7]
Internal Sample Clock
Figure 22. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
4.5.2.1.4
DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in DDR mode:
• B1—Memory generates both read data and read strobe on SCK edge
• B2—Memory generates read data on SCK edge and generates read strobe on SCK2
edge
Table 43. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
—
—
-1
166
—
—
1
MHz
ns
TSCKD
Time from SCK to data valid
Time from SCK to DQS
TSCKDQS
ns
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
ns
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SCK
TSCKD
SIO[0:7]
TSCKDQS
DQS
Figure 23. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)
Table 44. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
—
-1
166
—
1
MHz
ns
TSCKD
Time from SCK to data valid
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
ns
SCK
SIO[0:7]
SCK2
TSCKD
TSCK2DQS
DQS
Figure 24. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)
4.5.2.2
FlexSPI output/write timing
The following sections describe output signal timing for the FlexSPI controller including control signals
and data outputs.
4.5.2.2.1
SDR mode
Table 45. FlexSPI output timing in SDR mode
Parameter Min
Symbol
Max
Unit
Frequency of operation
SCK clock period
—
6.0
—
-1
1661
—
MHz
ns
Tck
TDVO
TDHO
Output data valid time
Output data hold time
1
ns
—
ns
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Table 45. FlexSPI output timing in SDR mode (continued)
Symbol
Parameter
Min
Max
Unit
TCSS
TCSH
Chip select output setup time
Chip select output hold time
3 x TCK - 1
3 x TCK + 2
—
—
ns
ns
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX
RT1064 Reference Manual (IMXRT1064RM) for more details.
SCK
TCSH
T
CSS
T
CK
CS
TDVO
TDVO
SIO[0:7]
TDHO
TDHO
Figure 25. FlexSPI output timing in SDR mode
4.5.2.2.2
SDR mode
Table 46. FlexSPI output timing in SDR mode
Symbol
Parameter
Min
Max
Unit
MHz
Frequency of operation1
—
166
—
Tck
SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
Output data valid time
6.0
—
ns
ns
ns
ns
ns
TDVO
TDHO
TCSS
TCSH
2.2
—
Output data hold time
0.8
Chip select output setup time
Chip select output hold time
3 x TCK /2 - 0.7
3 x TCK /2 + 0.8
—
—
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX
RT1064 Reference Manual (IMXRT1064RM) for more details.
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SCK
T
CSS
T
CK
TCSH
CS
TDVO
TDVO
SIO[0:7]
TDHO
TDHO
Figure 26. FlexSPI output timing in DDR mode
4.6
Display and graphics
The following sections provide information on display and graphic interfaces.
4.6.1
CMOS Sensor Interface (CSI) timing parameters
The following sections describe the CSI timing in gated and ungated clock modes.
4.6.1.0.1 Gated clock mode timing
Figure 27 and Figure 28 shows the gated clock mode timings for CSI, and Table 47 describes the timing
parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC
(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,
CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P5 P6
CSI_PIXCLK
P3 P4
CSI_DATA[23:00]
Figure 27. CSI Gated clock mode—sensor data at falling edge, latch data at rising edge
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CSI_VSYNC
CSI_HSYNC
P1
P7
P2
P6 P5
CSI_PIXCLK
P3 P4
CSI_DATA[23:00]
Figure 28. CSI Gated clock mode—sensor data at rising edge, latch data at falling edge
Table 47. CSI gated clock mode timing parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
P2
P3
P4
P5
P6
P7
CSI_VSYNC to CSI_HSYNC time
CSI_HSYNC setup time
CSI DATA setup time
tV2H
tHsu
tDsu
tDh
33.5
1
—
—
—
—
—
—
80
ns
ns
1
ns
CSI DATA hold time
1
ns
CSI pixel clock high time
CSI pixel clock low time
CSI pixel clock frequency
tCLKh
tCLKl
fCLK
3.75
3.75
—
ns
ns
MHz
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4.6.1.0.2
Ungated clock mode timing
Figure 29 shows the ungated clock mode timings of CSI, and Table 48 describes the timing parameters
(P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are
used, and the CSI_HSYNC signal is ignored.
CSI_VSYNC
P1
P6
P4 P5
CSI_PIXCLK
P2 P3
CSI_DATA[23:00]
Figure 29. CSI ungated clock mode—sensor data at falling edge, latch data at rising edge
Table 48. CSI ungated clock mode timing parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
P2
P3
P4
P5
P6
CSI_VSYNC to pixel clock time
CSI DATA setup time
tVSYNC
tDsu
33.5
1
—
—
—
—
—
80
ns
ns
CSI DATA hold time
tDh
1
ns
CSI pixel clock high time
CSI pixel clock low time
CSI pixel clock frequency
tCLKh
tCLKl
fCLK
3.75
3.75
—
ns
ns
MHz
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
•
Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
•
Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
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4.6.2
LCD Controller (LCDIF) timing parameters
Figure 30 shows the LCDIF timing and Table 49 lists the timing parameters.
L1
L2
L3
LCDn_CLK
(falling edge capture)
LCDn_CLK
(rising edge capture)
LCDn_DATA[23:00]
LCDn Control Signals
L4
L5
L6
L7
Figure 30. LCD timing
Table 49. LCD timing parameters
Parameter
ID
Symbol
Min
Max
Unit
L1
L2
L3
L4
L5
L6
L7
LCD pixel clock frequency
tCLK(LCD)
tCLKH(LCD)
tCLKL(LCD)
td(CLKH-DV)
td(CLKL-DV)
—
3
75
—
—
1
MHz
ns
LCD pixel clock high (falling edge capture)
LCD pixel clock low (rising edge capture)
3
ns
LCD pixel clock high to data valid (falling edge capture)
LCD pixel clock low to data valid (rising edge capture)
-1
-1
-1
-1
ns
1
ns
LCD pixel clock high to control signal valid (falling edge capture) td(CLKH-CTRLV)
1
ns
LCD pixel clock low to control signal valid (rising edge capture)
td(CLKL-CTRLV)
1
ns
4.7
Audio
This section provide information about SAI/I2S and SPDIF.
4.7.1
SAI/I2S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
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Num
Table 50. Master mode SAI timing
Characteristic Min
Max
Unit
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
SAI_MCLK cycle time
15
40%
40
40%
—
—
ns
SAI_MCLK pulse width high/low
SAI_BCLK cycle time
60%
—
MCLK period
ns
SAI_BCLK pulse width high/low
SAI_BCLK to SAI_FS output valid
SAI_BCLK to SAI_FS output invalid
SAI_BCLK to SAI_TXD valid
60%
15
BCLK period
ns
ns
ns
ns
ns
ns
0
—
—
15
SAI_BCLK to SAI_TXD invalid
0
—
SAI_RXD/SAI_FS input setup before SAI_BCLK
SAI_RXD/SAI_FS input hold after SAI_BCLK
15
0
—
—
Figure 31. SAI timing—Master modes
Table 51. Slave mode SAI timing
Num
Characteristic
SAI_BCLK cycle time (input)
Min
Max
Unit
S11
S12
S13
S14
S15
S16
40
40%
10
2
—
ns
SAI_BCLK pulse width high/low (input)
SAI_FS input setup before SAI_BCLK
SAI_FA input hold after SAI_BCLK
60%
—
BCLK period
ns
ns
ns
ns
—
SAI_BCLK to SAI_TXD/SAI_FS output valid
SAI_BCLK to SAI_TXD/SAI_FS output invalid
—
0
20
—
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Table 51. Slave mode SAI timing
Characteristic Min
Num
Max
Unit
S17
S18
SAI_RXD setup before SAI_BCLK
SAI_RXD hold after SAI_BCLK
10
2
—
—
ns
ns
Figure 32. SAI timing—Slave mode
4.7.2
SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 52 and Figure 33 and Figure 34 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 52. SPDIF timing parameters
Timing Parameter Range
Characteristics
Symbol
Unit
Min
Max
SPDIF_IN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
ns
SPDIF_OUT output (Load = 50pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
SPDIF_OUT1 output (Load = 30pf)
—
—
—
ns
ns
• Skew
• Transition rising
• Transition falling
—
—
—
1.5
13.6
18.0
Modulating Rx clock (SPDIF_SR_CLK) period
srckp
40.0
—
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Table 52. SPDIF timing parameters (continued)
Timing Parameter Range
Characteristics
Symbol
Unit
Min
Max
SPDIF_SR_CLK high period
srckph
srckpl
stclkp
16.0
16.0
40.0
16.0
16.0
—
—
—
—
—
ns
ns
ns
ns
ns
SPDIF_SR_CLK low period
Modulating Tx clock (SPDIF_ST_CLK) period
SPDIF_ST_CLK high period
stclkph
stclkpl
SPDIF_ST_CLK low period
srckp
srckpl
VM
srckph
VM
SPDIF_SR_CLK
(Output)
Figure 33. SPDIF_SR_CLK timing diagram
stclkp
stclkpl
VM
stclkph
VM
SPDIF_ST_CLK
(Input)
Figure 34. SPDIF_ST_CLK timing diagram
4.8
Analog
The following sections provide information about analog interfaces.
4.8.1
DCDC
Table 53 introduces the DCDC electrical specifications.
Table 53. DCDC electrical specifications
Buck mode, one output
3.3 V
Mode
Notes
Min = 2.8 V, Max = 3.6 V
Input voltage
Output voltage
1.1 V
Configurable 0.8 - 1.575 with 25 mV one step
in Run mode
Max loading
500 mA
—
—
Loading in low power modes
200 A ~ 30 mA
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Notes
Table 53. DCDC electrical specifications (continued)
Buck mode, one output
Mode
Efficiency
90% max
@150 mA
Low power mode
Run mode
Open loop mode
Ripple is about 15 mV in Run mode
Configurable by register
• Always continuous mode
• Support discontinuous mode
Inductor
4.7 H
33 F
1.55 V
—
—
Capacitor
Over voltage protection
Detect VDDSOC, when the voltage is higher
than 1.6 V, shutdown DCDC.
Over Current protection
1 A
Detect the peak current
• Run mode: when the current is larger than
1 A, shutdown DCDC.
Low DCDC_IN detection
2.6 V
Detect the DCDC_IN, when battery is lower
than 2.6 V, shutdown DCDC.
4.8.2
A/D converter
This section introduces information about A/D converter.
4.8.2.1
12-bit ADC electrical characteristics
The section provide information about 12-bit ADC electrical characteristics.
4.8.2.1.1
12-bit ADC operating conditions
Table 54. 12-bit ADC operating conditions
Typ1
Characteristic
Conditions
Absolute
Symb
Min
Max
Unit
Comment
Supply voltage
VDDA
3.0
-
3.6
V
—
—
Delta to
VDDA
-100
-100
0
100
100
mV
VDDA_ADC_3P3
2
(VDD-VDDA
)
Ground voltage
Delta to VSS
VSSAD
0
mV
—
(VSS-VSSAD)
Ref Voltage High
Ref Voltage Low
Input Voltage
—
VDDA
VSS
1.13
VSS
VSS
—
VDDA
VSS
—
VDDA
VSS
VDDA
2
V
—
—
—
—
—
—
—
—
V
—
VADIN
CADIN
RADIN
V
Input Capacitance
Input Resistance
8/10/12 bit modes
ADLPC=0, ADHSC=1
ADLPC=0, ADHSC=0
ADLPC=1, ADHSC=0
1.5
5
pF
—
7
kohms
kohms
kohms
—
12.5
25
15
—
30
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Characteristic
Table 54. 12-bit ADC operating conditions (continued)
Typ1
Conditions
Symb
Min
Max
Unit
kohms
Comment
Analog Source
Resistance
12 bit mode fADCK = 40 RAS
MHz ADLSMP=0,
—
—
1
Tsamp=150
ns
ADSTS=10, ADHSC=1
RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum
Sample Time vs RAS
ADC Conversion Clock ADLPC=0, ADHSC=1
fADCK
4
4
4
—
—
—
40
30
20
MHz
MHz
MHz
—
—
—
Frequency
12 bit mode
ADLPC=0, ADHSC=0
12 bit mode
ADLPC=1, ADHSC=0
12 bit mode
1
2
Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
DC potential differences
Figure 35. 12-bit ADC input impedance equivalency diagram
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12-bit ADC characteristics
Table 55. 12-bit ADC characteristics (V
= V
, V
= V
)
SSAD
REFH
DDA
REFL
Characteristic
Conditions1
Symb
IDDA
Min
Typ2
Max
Unit
Comment
ADLSMP=0
Supply Current
ADLPC=1,
ADHSC=0
—
350
460
750
1.4
—
µA
ADSTS=10 ADCO=1
ADLPC=0,
ADHSC=0
ADLPC=0,
ADHSC=1
Supply Current
Stop, Reset, Module IDDA
Off
—
2
µA
—
ADC Asynchronous ADHSC=0
fADACK
—
—
—
10
20
2
—
—
—
MHz
tADACK = 1/fADACK
Clock Source
ADHSC=1
Sample Cycles
ADLSMP=0,
ADSTS=00
Csamp
cycles
—
ADLSMP=0,
ADSTS=01
4
ADLSMP=0,
ADSTS=10
6
ADLSMP=0,
ADSTS=11
8
ADLSMP=1,
ADSTS=00
12
16
20
24
ADLSMP=1,
ADSTS=01
ADLSMP=1,
ADSTS=10
ADLSMP=1,
ADSTS=11
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Table 55. 12-bit ADC characteristics (V
= V
, V
= V
) (continued)
SSAD
REFH
DDA
REFL
Characteristic
Conditions1
Symb
Cconv
Min
Typ2
Max
Unit
cycles
Comment
Conversion Cycles
ADLSMP=0
—
28
30
32
34
38
42
46
50
—
—
ADSTS=00
ADLSMP=0
ADSTS=01
ADLSMP=0
ADSTS=10
ADLSMP=0
ADSTS=11
ADLSMP=1
ADSTS=00
ADLSMP=1
ADSTS=01
ADLSMP=1
ADSTS=10
ADLSMP=1,
ADSTS=11
Conversion Time
ADLSMP=0
ADSTS=00
Tconv
—
0.7
—
µs
Fadc=40 MHz
ADLSMP=0
ADSTS=01
0.75
0.8
ADLSMP=0
ADSTS=10
ADLSMP=0
ADSTS=11
0.85
0.95
1.05
1.15
1.25
ADLSMP=1
ADSTS=00
ADLSMP=1
ADSTS=01
ADLSMP=1
ADSTS=10
ADLSMP=1,
ADSTS=11
Total Unadjusted
Error
12 bit mode
10 bit mode
8 bit mode
TUE
DNL
—
—
—
3.4
1.5
1.2
—
—
—
LSB
1 LSB = 11
(VREFH
VREFL)/2
N
AVGE = 1, AVGS =
-
Differential
Non-Linearity
12 bit mode
10bit mode
8 bit mode
—
—
—
0.76
0.36
0.14
—
—
—
LSB
AVGE = 1, AVGS =
11
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) (continued)
Table 55. 12-bit ADC characteristics (V
= V
, V
= V
REFL SSAD
REFH
DDA
Characteristic
Integral
Conditions1
12 bit mode
Symb
INL
Min
Typ2
2.78
Max
Unit
LSB
Comment
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AVGE = 1, AVGS =
11
Non-Linearity
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
0.61
0.14
Zero-Scale Error
EZS
-1.14
-0.25
-0.19
-1.06
-0.03
-0.02
10.7
LSB
LSB
AVGE = 1, AVGS =
11
Full-Scale Error
EFS
AVGE = 1, AVGS =
11
Effective Number of 12 bit mode
Bits
ENOB
SINAD
10.1
Bits
dB
AVGE = 1, AVGS =
11
Signal to Noise plus See ENOB
Distortion
SINAD = 6.02 x ENOB + 1.76
AVGE = 1, AVGS =
11
1
2
All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
Typical values assume VDDA = 3.0 V, Temp = 25°C, Fadck = 20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
NOTE
The ADC electrical spec is met with the calibration enabled configuration.
Figure 36. Minimum Sample Time Vs Ras (Cas = 2 pF)
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Figure 37. Minimum Sample Time Vs Ras (Cas = 5 pF)
Figure 38. Minimum Sample Time Vs Ras (Cas = 10 pF)
4.8.3
ACMP
Table 56 lists the ACMP electrical specifications.
Table 56. Comparator and 6-bit DAC electrical specifications
Description Min. Typ. Max.
Supply voltage
Symbol
Unit
VDD
3.0
—
—
3.6
—
V
IDDHS
Supply current, High-speed mode
(EN = 1, PMODE = 1)
347
A
IDDLS
Supply current, Low-speed mode
(EN = 1, PMODE = 0)
—
42
—
A
VAIN
VAIO
Analog input voltage
VSS
—
—
—
VDD
21
V
Analog input offset voltage
mV
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Table 56. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
VH
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
Output high
mV
—
—
—
—
1
2
21
42
64
—
—
25
54
108
184
—
VCMPOH
VCMPOI
tDHS
VDD - 0.5
V
Output low
—
—
0.5
40
V
Propagation delay, high-speed
mode (EN = 1, PMODE = 1)2
ns
tDLS
Propagation delay, low-speed
mode (EN = 1, PMODE = 0)2
—
—
50
90
—
ns
tDInit
Analog comparator initialization
delay3
1.5
s
IDAC6b
6-bit DAC current adder (enabled) —
5
—
A
RDAC6b
6-bit DAC reference inputs
—
VDD
—
—
—
V
INLDAC6b
DNLDAC6b
6-bit DAC integral non-linearity
-0.3
0.3
0.15
LSB4
LSB4
6-bit DAC differential non-linearity -0.15
1
2
3
Typical hysteresis is measured with input voltage range limited to 0.7 to VDD - 0.7 V in high speed mode.
Signal swing is 100 mV.
Comparator initialization delay is defined as the time between software writes to the enable comparator module and the
comparator output setting to a stable level.
4
1 LSB = Vreference / 64
4.9
Communication interfaces
The following sections provide the information about communication interfaces.
4.9.1
LPSPI timing parameters
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables provide timing
characteristics for classic LPSPI timing modes.
All timing is shown with respect to 20% V and 80% V thresholds, unless noted, as well as input
DD
DD
signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.
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Table 57. LPSPI Master mode timing
Number
Symbol
Description
Frequency of operation
Min.
Max.
Units
Note
1
1
2
3
4
5
6
7
8
9
fSCK
tSCK
tLead
tLag
tWSCK
tSU
—
fperiph / 2
Hz
ns
2
SCK period
2 x tperiph
—
—
—
—
—
—
8
Enable lead time
1
tperiph
tperiph
ns
—
—
—
—
—
—
—
Enable lag time
1
Clock (SCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SCK edge)
Data hold time (outputs)
tSCK / 2 - 3
10
2
ns
tHI
ns
tV
—
0
ns
tHO
—
ns
1
2
Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be
guaranteed this limit is not exceeded.
tperiph = 1 / fperiph
1
PCS
(OUTPUT)
3
2
4
SCK
(CPOL=0)
(OUTPUT)
5
5
SCK
(CPOL=1)
(OUTPUT)
6
7
SIN
(INPUT)
2
LSB IN
BIT 6 . . . 1
MSB IN
8
9
SOUT
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 39. LPSPI Master mode timing (CPHA = 0)
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1
PCS
(OUTPUT)
2
4
3
SCK
(CPOL=0)
(OUTPUT)
5
5
SCK
(CPOL=1)
(OUTPUT)
6
7
SIN
(INPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
9
8
MASTER MSB OUT2
SOUT
(OUTPUT)
PORT DATA
BIT 6 . . . 1
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 40. LPSPI Master mode timing (CPHA = 1)
s
Table 58. LPSPI Slave mode timing
Number
Symbol
Description
Frequency of operation
Min.
Max.
Units
Note
1
1
2
fSCK
tSCK
tLead
tLag
tWSCK
tSU
0
fperiph / 2
—
Hz
ns
2
SCK period
2 x tperiph
3
Enable lead time
1
—
tperiph
tperiph
ns
—
—
—
—
4
Enable lag time
1
—
5
Clock (SCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time
tSCK / 2 - 5
—
6
2.7
3.8
—
—
—
0
—
ns
7
tHI
—
ns
—
3
8
ta
tperiph
tperiph
14.5
—
ns
4
9
tdis
Slave MISO disable time
Data valid (after SCK edge)
Data hold time (outputs)
ns
10
11
tV
ns
—
—
tHO
ns
1
Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be
guaranteed this limit is not exceeded.
2
3
4
tperiph = 1 / fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
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PCS
(INPUT)
2
4
SCK
(CPOL=0)
(INPUT)
5
5
3
SCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
SEE
NOTE
SIN
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
note
6
SOUT
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 41. LPSPI Slave mode timing (CPHA = 0)
PCS
(INPUT)
4
2
3
SCK
(CPOL=0)
(INPUT)
5
5
SCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
SIN
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
SOUT
MSB IN
(INPUT)
Figure 42. LPSPI Slave mode timing (CPHA = 1)
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4.9.2
LPI2C module timing parameters
This section describes the timing parameters of the LPI2C module.
Table 59. LPI2C module timing parameters
Symbol
Description
Standard mode (Sm)
Min
Max
100
Unit
Notes
1, 2
fSCL
SCL clock frequency
0
0
0
0
0
kHz
Fast mode (Fm)
400
Fast mode Plus (Fm+)
Ultra Fast mode (UFm)
High speed mode (Hs-mode)
1000
5000
3400
1
Hs-mode is only supported in slave mode.
See General switching specifications.
2
4.9.3
Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single
Data Rate) timing, eMMC4.4/4.41/4.5 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.
4.9.3.1
SD/eMMC4.3 (single data rate) AC timing
Figure 43 depicts the timing of SD/eMMC4.3, and Table 60 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2
SD1
SD5
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure 43. SD/eMMC4.3 timing
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Table 60. SD/eMMC4.3 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
1
SD1 Clock Frequency (Low Speed)
fPP
0
0
400
25/50
20/52
400
—
kHz
MHz
MHz
kHz
ns
2
Clock Frequency (SD/SDIO Full Speed/High Speed)
Clock Frequency (MMC Full Speed/High Speed)
Clock Frequency (Identification Mode)
fPP
3
fPP
0
fOD
tWL
100
7
SD2 Clock Low Time
SD3 Clock High Time
SD4 Clock Rise Time
SD5 Clock Fall Time
tWH
tTLH
tTHL
7
—
ns
—
—
3
ns
3
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6 uSDHC Output Delay tOD -6.6
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
3.6
ns
SD7 uSDHC Input Setup Time
SD8 uSDHC Input Hold Time4
tISU
tIH
2.5
1.5
—
—
ns
ns
1
2
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3
4
In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4.9.3.2
eMMC4.4/4.41 (dual data rate) AC timing
Figure 44 depicts the timing of eMMC4.4/4.41. Table 61 lists the eMMC4.4/4.41 timing characteristics.
Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).
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SD1
SDx_CLK
SD2
SD2
Output from eSDHCv3 to card
SDx_DATA[7:0]
......
......
SD3
SD4
Input from card to eSDHCv3
SDx_DATA[7:0]
Figure 44. eMMC4.4/4.41 timing
Table 61. eMMC4.4/4.41 interface timing specification
ID
Parameter
Symbols
Card Input Clock
Min
Max
Unit
SD1 Clock Frequency (eMMC4.4/4.41 DDR)
SD1 Clock Frequency (SD3.0 DDR)
fPP
fPP
0
0
52
50
MHz
MHz
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2 uSDHC Output Delay tOD 2.5 7.1
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
ns
SD3 uSDHC Input Setup Time
SD4 uSDHC Input Hold Time
tISU
tIH
1.7
1.5
—
—
ns
ns
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4.9.3.3
SDR50/SDR104 AC timing
Figure 45 depicts the timing of SDR50/SDR104, and Table 62 lists the SDR50/SDR104 timing
characteristics.
SD1
SD2
SD3
SD7
SCK
4-bit output from uSDHC to card
4-bit input from card to uSDHC
SD4/SD5
SD6
SD8
Figure 45. SDR50/SDR104 timing
Table 62. SDR50/SDR104 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1 Clock Frequency Period
SD2 Clock Low Time
tCLK
tCL
5.0
—
ns
ns
ns
0.46 x tCLK
0.46 x tCLK
0.54 x tCLK
0.54 x tCLK
SD3 Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4 uSDHC Output Delay tOD –3
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
uSDHC Output Delay tOD –1.6
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
1
ns
ns
1
SD5
uSDHC Input Setup Time
uSDHC Input Hold Time
tISU
tIH
2.5
1.5
—
—
ns
ns
SD6
SD7
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
Card Output Data Window tODW 0.5 x tCLK
—
ns
SD8
1Data window in SDR104 mode is variable.
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4.9.3.4
HS200 mode timing
Figure 46 depicts the timing of HS200 mode, and Table 63 lists the HS200 timing characteristics.
SD1
SD2
SD3
SCK
SD4/SD5
8-bit output from uSDHC to eMMC
8-bit input from eMMC to uSDHC
SD8
Figure 46. HS200 mode timing
Table 63. HS200 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1 Clock Frequency Period
SD2 Clock Low Time
tCLK
tCL
5.0
—
ns
ns
ns
0.46 x tCLK
0.46 x tCLK
0.54 x tCLK
0.54 x tCLK
SD3 Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
uSDHC Output Delay tOD –1.6 0.74
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
Card Output Data Window tODW 0.5 x tCLK
ns
ns
SD5
—
SD8
1HS200 is for 8 bits while SDR104 is for 4 bits.
4.9.3.5
Bus operation condition for 3.3 V and 1.8 V signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50
mode is 1.8 V. The DC parameters for the NVCC_SD1 supply are identical to those shown in Table 22,
"Single voltage GPIO DC parameters," on page 34.
4.9.4
Ethernet controller (ENET) AC electrical specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the physical interface.
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4.9.4.1
ENET MII mode timing
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
4.9.4.1.1
MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER, and ENET_RX_CLK)
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET_RX_CLK frequency.
Figure 47 shows MII receive signal timings. Table 64 describes the timing parameters (M1–M4) shown in
the figure.
M3
ENET_RX_CLK (input)
M4
ENET_RX_DATA3,2,1,0
(inputs)
ENET_RX_EN
ENET_RX_ER
M1
M2
Figure 47. MII receive signal timing diagram
Table 64. MII receive signal timing
ID
Characteristic1
Min.
Max.
Unit
M1
M2
ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
5
—
ns
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
5
—
ns
M3
M4
ENET_RX_CLK pulse width high
ENET_RX_CLK pulse width low
35%
35%
65%
65%
ENET_RX_CLK period
ENET_RX_CLK period
1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
4.9.4.1.2
MII transmit signal timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET_TX_CLK frequency.
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Figure 48 shows MII transmit signal timings. Table 65 describes the timing parameters (M5–M8) shown
in the figure.
M7
ENET_TX_CLK (input)
M5
M8
ENET_TX_DATA3,2,1,0
(outputs)
ENET_TX_EN
ENET_TX_ER
M6
Figure 48. MII transmit signal timing diagram
Table 65. MII transmit signal timing
ID
Characteristic1
Min.
Max.
Unit
M5
M6
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER invalid
5
—
ns
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER valid
—
20
ns
M7
M8
ENET_TX_CLK pulse width high
ENET_TX_CLK pulse width low
35%
35%
65%
65%
ENET_TX_CLK period
ENET_TX_CLK period
1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
4.9.4.1.3
MII asynchronous inputs signal timing (ENET_CRS and ENET_COL)
Figure 49 shows MII asynchronous input timings. Table 66 describes the timing parameter (M9) shown in
the figure.
ENET_CRS, ENET_COL
M9
Figure 49. MII asynchronous inputs timing diagram
Table 66. MII asynchronous inputs signal timing
ID
M91
Characteristic
Min.
Max.
Unit
ENET_CRS to ENET_COL minimum pulse width
1.5
—
ENET_TX_CLK period
1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode.
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4.9.4.1.4
MII serial management channel timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 50 shows MII asynchronous input timings. Table 67 describes the timing parameters (M10–M15)
shown in the figure.
M14
M15
ENET_MDC (output)
M10
ENET_MDIO (output)
M11
ENET_MDIO (input)
M12
M13
Figure 50. MII serial management channel timing diagram
Table 67. MII serial management channel timing
ID
M10
Characteristic
Min.
Max.
Unit
ENET_MDC falling edge to ENET_MDIO output invalid (min.
propagation delay)
0
—
ns
M11
ENET_MDC falling edge to ENET_MDIO output valid (max.
propagation delay)
—
5
ns
M12
M13
M14
M15
ENET_MDIO (input) to ENET_MDC rising edge setup
ENET_MDIO (input) to ENET_MDC rising edge hold
ENET_MDC pulse width high
18
0
—
—
ns
ns
40%
40%
60%
60%
ENET_MDC period
ENET_MDC period
ENET_MDC pulse width low
4.9.4.2
RMII mode timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER.
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Figure 51 shows RMII mode timings. Table 68 describes the timing parameters (M16–M21) shown in the
figure.
M16
M17
ENET_CLK (input)
M18
ENET_TX_DATA (output)
ENET_TX_EN
M19
ENET_RX_EN (input)
ENET_RX_DATA[1:0]
ENET_RX_ER
M20
M21
Figure 51. RMII mode signal timing diagram
Table 68. RMII signal timing
ID
M16
Characteristic
Min.
Max.
Unit
ENET_CLK pulse width high
ENET_CLK pulse width low
35%
35%
4
65%
65%
—
ENET_CLK period
M17
M18
M19
M20
ENET_CLK period
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid
ns
ns
ns
—
13
ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER
to ENET_CLK setup
2
—
M21
ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER
hold
2
—
ns
4.9.5
Flexible Controller Area Network (FLEXCAN) AC electrical
specifications
Please refer to Section 4.3.2.1, General purpose I/O AC parameters.
4.9.6
LPUART electrical specifications
Please refer to Section 4.3.2.1, General purpose I/O AC parameters.
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4.9.7
USB PHY parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
2.0 OTG with the following amendments.
•
USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0 plus errata and ecn June 4, 2010
Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
•
•
— Portable device only
4.10 Timers
This section provide information on timers.
4.10.1 Pulse Width Modulator (PWM) characteristics
This section describes the electrical information of the PWM.
Table 69. PWM timing parameters
Parameter
PWM Clock Frequency
Symbo
Min
Typ
Max
Unit
—
—
—
150
MHz
4.10.2 Quad timer timing
Table 70 listed the timing parameters.
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Table 70. Quad timer timing
Characteristic
Timer input period
Symbol
Min1
Max
Unit
See Figure
TIN
2T + 6
1T + 3
33
—
—
—
—
ns
ns
ns
ns
Timer input high/low period
Timer output period
TINHL
TOUT
Timer output high/low period
TOUTHL
16.7
1
T = clock cycle. For 60 MHz operation, T = 16.7 ns.
4IMER )NPUTS
4
4
).(,
).(,
4
).
4IMER /UTPUTS
4
4
/54(,
/54(,
4
/54
Figure 52. Quad timer timing
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Flash
5 Flash
This section introduces the on-chip flash electrical parameters.
Table 71 shows the operating ranges of on-chip flash power supply by NVCC_GPIO.
Table 71. Operating ranges
Spec.
Parameter
Symbol
Conditions
Unit
Min
Max
Supply voltage
NVCC_GPIO
FR = 133 MHz, fR = 50 MHz
3.0
3.6
V
For details about the flash AC parameters, refer to the following link.
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Boot mode configuration
6 Boot mode configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
6.1
Boot mode configuration pins
Table 72 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX RT1064
Fuse Map document and the System Boot chapter in i.MX RT1064 Reference Manual (IMXRT1064RM).
Table 72. Fuses and associated pins used for boot
Pad
Default setting on reset
eFuse name
Details
GPIO_AD_B0_04
GPIO_AD_B0_05
GPIO_B0_04
GPIO_B0_05
GPIO_B0_06
GPIO_B0_07
GPIO_B0_08
GPIO_B0_09
GPIO_B0_10
GPIO_B0_11
GPIO_B0_12
GPIO_B0_13
GPIO_B0_14
GPIO_B0_15
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
BOOT_MODE0
BOOT_MODE1
BT_CFG[0]
BT_CFG[1]
BT_CFG[2]
BT_CFG[3]
BT_CFG[4]
BT_CFG[5]
BT_CFG[6]
BT_CFG[7]
BT_CFG[8]
BT_CFG[9]
BT_CFG[10]
BT_CFG[11]
Boot Options, Pin value overrides
fuse settings for BT_FUSE_SEL =
‘0’. Signal Configuration as Fuse
Override Input at Power Up.
These are special I/O lines that
control the boot up configuration
during product development. In
production, the boot configuration
can be controlled by fuses.
6.2
Boot device interface allocation
The following tables list the interfaces that can be used by the boot process in accordance with the specific
boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 73. Boot trough NAND
PAD Name
IO Function
ALT
Comments
GPIO_EMC_00
GPIO_EMC_01
GPIO_EMC_02
semc.DATA[0]
semc.DATA[1]
semc.DATA[2]
ALT 0
ALT 0
ALT 0
—
—
—
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Table 73. Boot trough NAND
GPIO_EMC_03
GPIO_EMC_04
GPIO_EMC_05
GPIO_EMC_06
GPIO_EMC_07
GPIO_EMC_30
GPIO_EMC_31
GPIO_EMC_32
GPIO_EMC_33
GPIO_EMC_34
GPIO_EMC_35
GPIO_EMC_36
GPIO_EMC_37
GPIO_EMC_18
GPIO_EMC_19
GPIO_EMC_20
GPIO_EMC_22
GPIO_EMC_41
semc.DATA[3]
semc.DATA[4]
semc.DATA[5]
semc.DATA[6]
semc.DATA[7]
semc.DATA[8]
semc.DATA[9]
semc.DATA[10]
semc.DATA[11]
semc.DATA[12]
semc.DATA[13]
semc.DATA[14]
semc.DATA[15]
semc.ADDR[9]
semc.ADDR[11]
semc.ADDR[12]
semc.BA1
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
semc.CSX[0]
Table 74. Boot trough NOR
IO Function
PAD Name
ALT
Comments
GPIO_EMC_00
GPIO_EMC_01
GPIO_EMC_02
GPIO_EMC_03
GPIO_EMC_04
GPIO_EMC_05
GPIO_EMC_06
GPIO_EMC_07
GPIO_EMC_30
GPIO_EMC_31
GPIO_EMC_32
GPIO_EMC_33
semc.DATA[0]
semc.DATA[1]
semc.DATA[2]
semc.DATA[3]
semc.DATA[4]
semc.DATA[5]
semc.DATA[6]
semc.DATA[7]
semc.DATA[8]
semc.DATA[9]
semc.DATA[10]
semc.DATA[11]
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
—
—
—
—
—
—
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Table 74. Boot trough NOR
GPIO_EMC_34
GPIO_EMC_35
GPIO_EMC_36
GPIO_EMC_37
GPIO_EMC_09
GPIO_EMC_10
GPIO_EMC_11
GPIO_EMC_12
GPIO_EMC_13
GPIO_EMC_14
GPIO_EMC_15
GPIO_EMC_16
GPIO_EMC_19
GPIO_EMC_20
GPIO_EMC_21
GPIO_EMC_22
GPIO_EMC_41
semc.DATA[12]
semc.DATA[13]
semc.DATA[14]
semc.DATA[15]
semc.ADDR[0]
semc.ADDR[1]
semc.ADDR[2]
semc.ADDR[3]
semc.ADDR[4]
semc.ADDR[5]
semc.ADDR[6]
semc.ADDR[7]
semc.ADDR[11]
semc.ADDR[12]
semc.BA0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
semc.BA1
semc.CSX[0]
Table 75. Boot through FlexSPI
IO Function
PAD Name
Mux Mode
Comments
GPIO_SD_B1_00
GPIO_SD_B1_01
GPIO_SD_B1_02
GPIO_SD_B1_03
GPIO_SD_B1_04
GPIO_SD_B0_05
GPIO_SD_B0_04
GPIO_SD_B0_01
GPIO_SD_B1_05
GPIO_SD_B1_06
GPIO_SD_B0_00
GPIO_SD_B1_07
GPIO_SD_B1_08
GPIO_SD_B1_09
flexspi.B_DATA[3]
flexspi.B_DATA[2]
flexspi.B_DATA[1]
flexspi.B_DATA[0]
flexspi.B_SCLK
flexspi.B_DQS
ALT 1
ALT 1
ALT 1
ALT 1
ALT 1
ALT 4
ALT 4
ALT 6
ALT 1
ALT 1
ALT 6
ALT 1
ALT 1
ALT 1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
flexspi.B_SS0_B
flexspi.B_SS1_B
flexspi.A_DQS
flexspi.A_SS0_B
flexspi.A_SS1_B
flexspi.A_SCLK
flexspi.A_DATA[0]
flexspi.A_DATA[1]
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PAD Name
Table 75. Boot through FlexSPI (continued)
IO Function
Mux Mode
Comments
GPIO_SD_B1_10
GPIO_SD_B1_11
flexspi.A_DATA[2]
flexspi.A_DATA[3]
ALT 1
ALT 1
—
—
Table 76. Boot through SD1
IO Function
PAD Name
Mux Mode
Comments
GPIO_SD_B0_00
GPIO_SD_B0_01
GPIO_SD_B0_02
GPIO_SD_B0_03
GPIO_SD_B0_04
GPIO_SD_B0_05
usdhc1.CMD
usdhc1.CLK
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
usdhc1.DATA0
usdhc1.DATA1
usdhc1.DATA2
usdhc1.DATA3
Table 77. Boot through SD2
IO Function
PAD Name
Mux Mode
Comments
GPIO_SD_B1_00
GPIO_SD_B1_01
GPIO_SD_B1_02
GPIO_SD_B1_03
GPIO_SD_B1_04
GPIO_SD_B1_05
GPIO_SD_B1_06
GPIO_SD_B1_08
GPIO_SD_B1_09
GPIO_SD_B1_10
GPIO_SD_B1_11
usdhc2.DATA3
usdhc2.DATA2
usdhc2.DATA1
usdhc2.DATA0
usdhc2.CLK
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
—
—
—
—
—
usdhc2.CMD
usdhc2.RESET_B
usdhc2.DATA4
usdhc2.DATA5
usdhc2.DATA6
usdhc2.DATA7
Table 78. Boot through SPI-1
IO Function
PAD Name
Mux Mode
Comments
GPIO_SD_B0_00
GPIO_SD_B0_02
GPIO_SD_B0_03
GPIO_SD_B0_01
lpspi1.SCK
lpspi1.SDO
lpspi1.SDI
ALT 4
ALT 4
ALT 4
ALT 4
—
—
—
—
lpspi1.PCS0
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Comments
Table 79. Boot through SPI-2
IO Function
PAD Name
Mux Mode
GPIO_SD_B1_07
GPIO_SD_B1_08
GPIO_SD_B1_09
GPIO_SD_B1_06
lpspi2.SCK
lpspi2.SDO
lpspi2.SDI
ALT 4
ALT 4
ALT 4
ALT 4
—
—
—
—
lpspi2.PCS0
Table 80. Boot through SPI-3
IO Function
PAD Name
Mux Mode
Comments
GPIO_AD_B0_00
GPIO_AD_B0_01
GPIO_AD_B0_02
GPIO_SD_B0_03
lpspi3.SCK
lpspi3.SDO
lpspi3.SDI
ALT 7
ALT 7
ALT 7
ALT 7
—
—
—
—
lpspi3.PCS0
Table 81. Boot through SPI-4
IO Function
PAD Name
Mux Mode
Comments
GPIO_B0_03
GPIO_B0_02
GPIO_B0_01
GPIO_B0_00
lpspi4.SCK
lpspi4.SDO
lpspi4.SDI
ALT 3
ALT 3
ALT 3
ALT 3
—
—
—
—
lpspi4.PCS0
Table 82. Boot through UART1
IO Function
PAD Name
Mux Mode
Comments
GPIO_AD_B0_12
GPIO_AD_B0_13
lpuart1.TX
lpuart1.RX
ALT 2
ALT 2
—
—
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Package information and contact assignments
7 Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing.
7.1
10 x 10 mm package information
7.1.1
10 x 10 mm, 0.65 mm pitch, ball matrix
Figure 53 shows the top, bottom, and side views of the 10 x 10 mm MAPBGA package.
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Package information and contact assignments
Figure 53. 10 x 10 mm BGA, case x package top, bottom, and side Views
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Package information and contact assignments
7.1.2
10 x 10 mm supplies contact assignments and functional contact
assignments
Table 83 shows the device connection list for ground, sense, and reference contact signals.
Table 83. 10 x 10 mm supplies contact assignment
Supply Rail Name
Ball(s) Position(s)
Remark
DCDC_IN
DCDC_IN_Q
DCDC_GND
DCDC_LP
L1, L2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
K4
N1, N2
M1, M2
DCDC_PSWITCH
DCDC_SENSE
GPANAIO
K3
J5
N10
NGND_KEL0
NVCC_EMC
NVCC_GPIO
NVCC_PLL
K9
E6, F5
E9, F10, J10
P10
NVCC_SD0
J6
NVCC_SD1
K5
VDDA_ADC_3P3
VDD_HIGH_CAP
VDD_HIGH_IN
VDD_SNVS_CAP
VDD_SNVS_IN
VDD_SOC_IN
VDD_USB_CAP
VSS
N14
P8
P12
M10
M9
F6, F7, F8, F9, G6, G9, H6, H9, J9
K8
A1, A14, B5, B10, E2, E13, G7, G8, H7, H8, J7, J8, K2, K13, L9, N5, N8, P1, P14
Table 84 shows an alpha-sorted list of functional contact assignments for the 10 x 10 mm package.
Table 84. 10 x 10 mm functional contact assignments
Default Setting
10 x 10
Ball
Power
Group
Ball
Type
Ball Name
Default
Mode
Default
Function
Input/
Output
Value
CCM_CLK1_N
CCM_CLK1_P
P13
N13
—
—
—
—
—
—
CCM_CLK1_N
CCM_CLK1_P
—
—
—
—
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Package information and contact assignments
Table 84. 10 x 10 mm functional contact assignments (continued)
GPIO_AD_B0_00
GPIO_AD_B0_01
GPIO_AD_B0_02
GPIO_AD_B0_03
GPIO_AD_B0_04
GPIO_AD_B0_05
GPIO_AD_B0_06
GPIO_AD_B0_07
GPIO_AD_B0_08
GPIO_AD_B0_09
GPIO_AD_B0_10
GPIO_AD_B0_11
GPIO_AD_B0_12
GPIO_AD_B0_13
GPIO_AD_B0_14
GPIO_AD_B0_15
GPIO_AD_B1_00
GPIO_AD_B1_01
GPIO_AD_B1_02
GPIO_AD_B1_03
GPIO_AD_B1_04
M14
H10
M11
G11
F11
G14
E14
F12
F13
F14
G13
G10
K14
L14
H14
L10
J11
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO1.IO[0]
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Digital
GPIO
GPIO1.IO[1]
Digital
GPIO
GPIO1.IO[2]
Digital
GPIO
GPIO1.IO[3]
Digital
GPIO
SRC.BOOT.MODE[0]
SRC.BOOT.MODE[1]
JTAG.MUX.TMS
JTAG.MUX.TCK
JTAG.MUX.MOD
JTAG.MUX.TDI
JTAG.MUX.TDO
JTAG.MUX.TRSTB
GPIO1.IO[12]
Input 100 K PD
Input 100 K PD
Digital
GPIO
Digital
GPIO
Input
Input
47 K PU
47 K PU
Digital
GPIO
Digital
GPIO
Input 100 K PU
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
47 K PU
Keeper
47 K PU
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
GPIO1.IO[13]
Digital
GPIO
GPIO1.IO[14]
Digital
GPIO
GPIO1.IO[15]
Digital
GPIO
GPIO1.IO[16]
K11
L11
Digital
GPIO
GPIO1.IO[17]
Digital
GPIO
GPIO1.IO[18]
M12
L12
Digital
GPIO
GPIO1.IO[19]
Digital
GPIO
GPIO1.IO[20]
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Package information and contact assignments
Table 84. 10 x 10 mm functional contact assignments (continued)
GPIO_AD_B1_05
GPIO_AD_B1_06
GPIO_AD_B1_07
GPIO_AD_B1_08
GPIO_AD_B1_09
GPIO_AD_B1_10
GPIO_AD_B1_11
GPIO_AD_B1_12
GPIO_AD_B1_13
GPIO_AD_B1_14
GPIO_AD_B1_15
GPIO_B0_00
K12
J12
K10
H13
M13
L13
J13
H12
H11
G12
J14
D7
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO1.IO[21]
GPIO1.IO[22]
GPIO1.IO[23]
GPIO1.IO[24]
GPIO1.IO[25]
GPIO1.IO[26]
GPIO1.IO[27]
GPIO1.IO[28]
GPIO1.IO[29]
GPIO1.IO[30]
GPIO1.IO[31]
GPIO2.IO[0]
GPIO2.IO[1]
GPIO2.IO[2]
GPIO2.IO[3]
GPIO2.IO[4]
GPIO2.IO[5]
GPIO2.IO[6]
GPIO2.IO[7]
GPIO2.IO[8]
GPIO2.IO[9]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
GPIO_B0_01
E7
Digital
GPIO
GPIO_B0_02
E8
Digital
GPIO
GPIO_B0_03
D8
Digital
GPIO
GPIO_B0_04
C8
Digital
GPIO
GPIO_B0_05
B8
Digital
GPIO
GPIO_B0_06
A8
Digital
GPIO
GPIO_B0_07
A9
Digital
GPIO
GPIO_B0_08
B9
Digital
GPIO
GPIO_B0_09
C9
Digital
GPIO
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Table 84. 10 x 10 mm functional contact assignments (continued)
GPIO_B0_10
GPIO_B0_11
GPIO_B0_12
GPIO_B0_13
GPIO_B0_14
GPIO_B0_15
GPIO_B1_00
GPIO_B1_01
GPIO_B1_02
GPIO_B1_03
GPIO_B1_04
GPIO_B1_05
GPIO_B1_06
GPIO_B1_07
GPIO_B1_08
GPIO_B1_09
GPIO_B1_10
GPIO_B1_11
GPIO_B1_12
GPIO_B1_13
GPIO_B1_14
D9
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO2.IO[10]
GPIO2.IO[11]
GPIO2.IO[12]
GPIO2.IO[13]
GPIO2.IO[14]
GPIO2.IO[15]
GPIO2.IO[16]
GPIO2.IO[17]
GPIO2.IO[18]
GPIO2.IO[19]
GPIO2.IO[20]
GPIO2.IO[21]
GPIO2.IO[22]
GPIO2.IO[23]
GPIO2.IO[24]
GPIO2.IO[25]
GPIO2.IO[26]
GPIO2.IO[27]
GPIO2.IO[28]
GPIO2.IO[29]
GPIO2.IO[30]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
A10
C10
D10
E10
E11
A11
B11
C11
D11
E12
D12
C12
B12
A12
A13
B13
C13
D13
D14
C14
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
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Package information and contact assignments
Table 84. 10 x 10 mm functional contact assignments (continued)
GPIO_B1_15
B14
E3
F3
F4
G4
F2
G5
H5
H4
H3
C2
G1
G3
H1
A6
B6
B1
A5
A4
B2
B4
NVCC_GPIO
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO2.IO[31]
GPIO4.IO[0]
GPIO4.IO[1]
GPIO4.IO[2]
GPIO4.IO[3]
GPIO4.IO[4]
GPIO4.IO[5]
GPIO4.IO[6]
GPIO4.IO[7]
GPIO4.IO[8]
GPIO4.IO[9]
GPIO4.IO[10]
GPIO4.IO[11]
GPIO4.IO[12]
GPIO4.IO[13]
GPIO4.IO[14]
GPIO4.IO[15]
GPIO4.IO[16]
GPIO4.IO[17]
GPIO4.IO[18]
GPIO4.IO[19]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
GPIO_EMC_00
GPIO_EMC_01
GPIO_EMC_02
GPIO_EMC_03
GPIO_EMC_04
GPIO_EMC_05
GPIO_EMC_06
GPIO_EMC_07
GPIO_EMC_08
GPIO_EMC_09
GPIO_EMC_10
GPIO_EMC_11
GPIO_EMC_12
GPIO_EMC_13
GPIO_EMC_14
GPIO_EMC_15
GPIO_EMC_16
GPIO_EMC_17
GPIO_EMC_18
GPIO_EMC_19
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
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Table 84. 10 x 10 mm functional contact assignments (continued)
GPIO_EMC_20
GPIO_EMC_21
GPIO_EMC_22
GPIO_EMC_23
GPIO_EMC_24
GPIO_EMC_25
GPIO_EMC_26
GPIO_EMC_27
GPIO_EMC_28
GPIO_EMC_29
GPIO_EMC_30
GPIO_EMC_31
GPIO_EMC_32
GPIO_EMC_33
GPIO_EMC_34
GPIO_EMC_35
GPIO_EMC_36
GPIO_EMC_37
GPIO_EMC_38
GPIO_EMC_39
GPIO_EMC_40
A3
C1
F1
G2
D3
D2
B3
A2
D1
E1
C6
C5
D5
C4
D4
E5
C3
E4
D6
B7
A7
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO4.IO[20]
GPIO4.IO[21]
GPIO4.IO[22]
GPIO4.IO[23]
GPIO4.IO[24]
GPIO4.IO[25]
GPIO4.IO[26]
GPIO4.IO[27]
GPIO4.IO[28]
GPIO4.IO[29]
GPIO4.IO[30]
GPIO4.IO[31]
GPIO3.IO[18]
GPIO3.IO[19]
GPIO3.IO[20]
GPIO3.IO[21]
GPIO3.IO[22]
GPIO3.IO[23]
GPIO3.IO[24]
GPIO3.IO[25]
GPIO3.IO[26]
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Input 100 K PD
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
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Package information and contact assignments
Table 84. 10 x 10 mm functional contact assignments (continued)
GPIO_EMC_41
GPIO_SD_B0_00
GPIO_SD_B0_01
GPIO_SD_B0_02
GPIO_SD_B0_03
GPIO_SD_B0_04
GPIO_SD_B0_05
GPIO_SD_B1_00
GPIO_SD_B1_01
GPIO_SD_B1_02
GPIO_SD_B1_03
GPIO_SD_B1_04
GPIO_SD_B1_05
GPIO_SD_B1_06
GPIO_SD_B1_07
GPIO_SD_B1_08
GPIO_SD_B1_09
GPIO_SD_B1_10
GPIO_SD_B1_11
ONOFF
C7
NVCC_EMC
NVCC_SD0
NVCC_SD0
NVCC_SD0
NVCC_SD0
NVCC_SD0
NVCC_SD0
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
VDD_SNVS_IN
VDD_SNVS_IN
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
GPIO3.IO[27]
GPIO3.IO[12]
GPIO3.IO[13]
GPIO3.IO[14]
GPIO3.IO[15]
GPIO3.IO[16]
GPIO3.IO[17]
GPIO3.IO[0]
GPIO3.IO[1]
GPIO3.IO[2]
GPIO3.IO[3]
GPIO3.IO[4]
GPIO3.IO[5]
GPIO3.IO[6]
GPIO3.IO[7]
GPIO3.IO[8]
GPIO3.IO[9]
GPIO3.IO[01]
GPIO3.IO[11]
ONOFF
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
J4
Digital
GPIO
J3
Digital
GPIO
J1
Digital
GPIO
K1
H2
J2
Digital
GPIO
Digital
GPIO
Digital
GPIO
L5
M5
M3
M4
P2
N3
L3
L4
P3
N4
P4
P5
M6
K7
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Input 100 K PU
PMIC_ON_REQ
Digital
GPIO
ALT0 SNVS_LP.PMIC_ON_RE Output 100 K PU
Q
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Package information and contact assignments
Table 84. 10 x 10 mm functional contact assignments (continued)
PMIC_STBY_REQ
POR_B
L7
VDD_SNVS_IN
Digital
GPIO
ALT0
CCM.PMIC_VSTBY_RE Output 100 K PU
Q
(PKE
disabled)
M7
VDD_SNVS_IN
Digital
GPIO
ALT0
SRC.POR_B
Input 100 K PU
RTC_XTALI
RTC_XTALO
TEST_MODE
N9
P9
K6
—
—
—
—
—
—
—
—
—
—
—
—
VDD_SNVS_IN
Digital
GPIO
ALT0
TCU.TEST_MODE
Input 100 K PU
USB_OTG1_CHD_B
USB_OTG1_DN
USB_OTG1_DP
USB_OTG1_VBUS
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_VBUS
XTALI
N12
M8
L8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N6
N7
P7
—
—
—
—
—
—
—
—
—
P6
—
—
—
P11
N11
L6
—
—
—
—
—
XTALO
—
WAKEUP
VDD_SNVS_IN
Digital
GPIO
ALT5
GPIO5.IO[0]
Input 100 K PU
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Package information and contact assignments
7.1.3
10 x 10 mm, 0.65 mm pitch, ball map
Table 85 shows the 10 x 10 mm, 0.65 mm pitch ball map for the i.MX RT1064.
Table 85. 10x10 mm, 0.65 mm pitch, ball map
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Package information and contact assignments
Table 85. 10x10 mm, 0.65 mm pitch, ball map (continued)
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Package information and contact assignments
7.2
12 x 12 mm package information
12 x 12 mm, 0.8 mm pitch, ball matrix
7.2.1
Figure 54 shows the top, bottom, and side views of the 12 x 12 mm MAPBGA package.
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Package information and contact assignments
Figure 54. 12 x 12 mm BGA, case x package top, bottom, and side Views
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Package information and contact assignments
7.2.2
12 x 12 mm supplies contact assignments and functional contact
assignments
Table 86 shows the device connection list for ground, sense, and reference contact signals.
Table 86. 12 x 12 mm supplies contact assignment
Supply Rail Name
Ball(s) Position(s)
Remark
DCDC_IN
DCDC_IN_Q
DCDC_GND
DCDC_LP
L1, L2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
K4
N1, N2
M1, M2
DCDC_PSWITCH
DCDC_SENSE
GPANAIO
K3
J5
N10
NGND_KEL0
NVCC_EMC
NVCC_GPIO
NVCC_PLL
K9
E6, F5
E9, F10, J10
P10
NVCC_SD0
J6
NVCC_SD1
K5
VDDA_ADC_3P3
VDD_HIGH_CAP
VDD_HIGH_IN
VDD_SNVS_CAP
VDD_SNVS_IN
VDD_SOC_IN
VDD_USB_CAP
VSS
N14
P8
P12
M10
M9
F6, F7, F8, F9, G6, G9, H6, H9, J9
K8
A1, A14, B5, B10, E2, E13, G7, G8, H7, H8, J7, J8, K2, K13, L9, N5, N8, P1, P14
Table 87 shows an alpha-sorted list of functional contact assignments for the 12 x 12 mm package.
Table 87. 12 x 12 mm functional contact assignments
Default Setting
12 x 12
Ball
Power
Group
Ball
Type
Ball Name
Default
Mode
Default
Function
Input/
Output
Value
CCM_CLK1_N
CCM_CLK1_P
P13
N13
—
—
—
—
—
—
CCM_CLK1_N
CCM_CLK1_P
—
—
—
—
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Package information and contact assignments
Table 87. 12 x 12 mm functional contact assignments (continued)
GPIO_AD_B0_00
GPIO_AD_B0_01
GPIO_AD_B0_02
GPIO_AD_B0_03
GPIO_AD_B0_04
GPIO_AD_B0_05
GPIO_AD_B0_06
GPIO_AD_B0_07
GPIO_AD_B0_08
GPIO_AD_B0_09
GPIO_AD_B0_10
GPIO_AD_B0_11
GPIO_AD_B0_12
GPIO_AD_B0_13
GPIO_AD_B0_14
GPIO_AD_B0_15
GPIO_AD_B1_00
GPIO_AD_B1_01
GPIO_AD_B1_02
GPIO_AD_B1_03
GPIO_AD_B1_04
M14
H10
M11
G11
F11
G14
E14
F12
F13
F14
G13
G10
K14
L14
H14
L10
J11
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO1.IO[0]
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Digital
GPIO
GPIO1.IO[1]
Digital
GPIO
GPIO1.IO[2]
Digital
GPIO
GPIO1.IO[3]
Digital
GPIO
SRC.BOOT.MODE[0]
SRC.BOOT.MODE[1]
JTAG.MUX.TMS
JTAG.MUX.TCK
JTAG.MUX.MOD
JTAG.MUX.TDI
JTAG.MUX.TDO
JTAG.MUX.TRSTB
GPIO1.IO[12]
Input 100 K PD
Input 100 K PD
Digital
GPIO
Digital
GPIO
Input
Input
47 K PU
47 K PU
Digital
GPIO
Digital
GPIO
Input 100 K PU
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
47 K PU
Keeper
47 K PU
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
GPIO1.IO[13]
Digital
GPIO
GPIO1.IO[14]
Digital
GPIO
GPIO1.IO[15]
Digital
GPIO
GPIO1.IO[16]
K11
L11
Digital
GPIO
GPIO1.IO[17]
Digital
GPIO
GPIO1.IO[18]
M12
L12
Digital
GPIO
GPIO1.IO[19]
Digital
GPIO
GPIO1.IO[20]
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Package information and contact assignments
Table 87. 12 x 12 mm functional contact assignments (continued)
GPIO_AD_B1_05
GPIO_AD_B1_06
GPIO_AD_B1_07
GPIO_AD_B1_08
GPIO_AD_B1_09
GPIO_AD_B1_10
GPIO_AD_B1_11
GPIO_AD_B1_12
GPIO_AD_B1_13
GPIO_AD_B1_14
GPIO_AD_B1_15
GPIO_B0_00
K12
J12
K10
H13
M13
L13
J13
H12
H11
G12
J14
D7
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO1.IO[21]
GPIO1.IO[22]
GPIO1.IO[23]
GPIO1.IO[24]
GPIO1.IO[25]
GPIO1.IO[26]
GPIO1.IO[27]
GPIO1.IO[28]
GPIO1.IO[29]
GPIO1.IO[30]
GPIO1.IO[31]
GPIO2.IO[0]
GPIO2.IO[1]
GPIO2.IO[2]
GPIO2.IO[3]
GPIO2.IO[4]
GPIO2.IO[5]
GPIO2.IO[6]
GPIO2.IO[7]
GPIO2.IO[8]
GPIO2.IO[9]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
GPIO_B0_01
E7
Digital
GPIO
GPIO_B0_02
E8
Digital
GPIO
GPIO_B0_03
D8
Digital
GPIO
GPIO_B0_04
C8
Digital
GPIO
GPIO_B0_05
B8
Digital
GPIO
GPIO_B0_06
A8
Digital
GPIO
GPIO_B0_07
A9
Digital
GPIO
GPIO_B0_08
B9
Digital
GPIO
GPIO_B0_09
C9
Digital
GPIO
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Package information and contact assignments
Table 87. 12 x 12 mm functional contact assignments (continued)
GPIO_B0_10
GPIO_B0_11
GPIO_B0_12
GPIO_B0_13
GPIO_B0_14
GPIO_B0_15
GPIO_B1_00
GPIO_B1_01
GPIO_B1_02
GPIO_B1_03
GPIO_B1_04
GPIO_B1_05
GPIO_B1_06
GPIO_B1_07
GPIO_B1_08
GPIO_B1_09
GPIO_B1_10
GPIO_B1_11
GPIO_B1_12
GPIO_B1_13
GPIO_B1_14
D9
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO2.IO[10]
GPIO2.IO[11]
GPIO2.IO[12]
GPIO2.IO[13]
GPIO2.IO[14]
GPIO2.IO[15]
GPIO2.IO[16]
GPIO2.IO[17]
GPIO2.IO[18]
GPIO2.IO[19]
GPIO2.IO[20]
GPIO2.IO[21]
GPIO2.IO[22]
GPIO2.IO[23]
GPIO2.IO[24]
GPIO2.IO[25]
GPIO2.IO[26]
GPIO2.IO[27]
GPIO2.IO[28]
GPIO2.IO[29]
GPIO2.IO[30]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
A10
C10
D10
E10
E11
A11
B11
C11
D11
E12
D12
C12
B12
A12
A13
B13
C13
D13
D14
C14
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
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Package information and contact assignments
Table 87. 12 x 12 mm functional contact assignments (continued)
GPIO_B1_15
B14
E3
F3
F4
G4
F2
G5
H5
H4
H3
C2
G1
G3
H1
A6
B6
B1
A5
A4
B2
B4
NVCC_GPIO
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO2.IO[31]
GPIO4.IO[0]
GPIO4.IO[1]
GPIO4.IO[2]
GPIO4.IO[3]
GPIO4.IO[4]
GPIO4.IO[5]
GPIO4.IO[6]
GPIO4.IO[7]
GPIO4.IO[8]
GPIO4.IO[9]
GPIO4.IO[10]
GPIO4.IO[11]
GPIO4.IO[12]
GPIO4.IO[13]
GPIO4.IO[14]
GPIO4.IO[15]
GPIO4.IO[16]
GPIO4.IO[17]
GPIO4.IO[18]
GPIO4.IO[19]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
GPIO_EMC_00
GPIO_EMC_01
GPIO_EMC_02
GPIO_EMC_03
GPIO_EMC_04
GPIO_EMC_05
GPIO_EMC_06
GPIO_EMC_07
GPIO_EMC_08
GPIO_EMC_09
GPIO_EMC_10
GPIO_EMC_11
GPIO_EMC_12
GPIO_EMC_13
GPIO_EMC_14
GPIO_EMC_15
GPIO_EMC_16
GPIO_EMC_17
GPIO_EMC_18
GPIO_EMC_19
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
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Package information and contact assignments
Table 87. 12 x 12 mm functional contact assignments (continued)
GPIO_EMC_20
GPIO_EMC_21
GPIO_EMC_22
GPIO_EMC_23
GPIO_EMC_24
GPIO_EMC_25
GPIO_EMC_26
GPIO_EMC_27
GPIO_EMC_28
GPIO_EMC_29
GPIO_EMC_30
GPIO_EMC_31
GPIO_EMC_32
GPIO_EMC_33
GPIO_EMC_34
GPIO_EMC_35
GPIO_EMC_36
GPIO_EMC_37
GPIO_EMC_38
GPIO_EMC_39
GPIO_EMC_40
A3
C1
F1
G2
D3
D2
B3
A2
D1
E1
C6
C5
D5
C4
D4
E5
C3
E4
D6
B7
A7
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
NVCC_EMC
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO4.IO[20]
GPIO4.IO[21]
GPIO4.IO[22]
GPIO4.IO[23]
GPIO4.IO[24]
GPIO4.IO[25]
GPIO4.IO[26]
GPIO4.IO[27]
GPIO4.IO[28]
GPIO4.IO[29]
GPIO4.IO[30]
GPIO4.IO[31]
GPIO3.IO[18]
GPIO3.IO[19]
GPIO3.IO[20]
GPIO3.IO[21]
GPIO3.IO[22]
GPIO3.IO[23]
GPIO3.IO[24]
GPIO3.IO[25]
GPIO3.IO[26]
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Input 100 K PD
Digital
GPIO
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
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Package information and contact assignments
Table 87. 12 x 12 mm functional contact assignments (continued)
GPIO_EMC_41
GPIO_SD_B0_00
GPIO_SD_B0_01
GPIO_SD_B0_02
GPIO_SD_B0_03
GPIO_SD_B0_04
GPIO_SD_B0_05
GPIO_SD_B1_00
GPIO_SD_B1_01
GPIO_SD_B1_02
GPIO_SD_B1_03
GPIO_SD_B1_04
GPIO_SD_B1_05
GPIO_SD_B1_06
GPIO_SD_B1_07
GPIO_SD_B1_08
GPIO_SD_B1_09
GPIO_SD_B1_10
GPIO_SD_B1_11
ONOFF
C7
NVCC_EMC
NVCC_SD0
NVCC_SD0
NVCC_SD0
NVCC_SD0
NVCC_SD0
NVCC_SD0
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
VDD_SNVS_IN
VDD_SNVS_IN
Digital
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
GPIO3.IO[27]
GPIO3.IO[12]
GPIO3.IO[13]
GPIO3.IO[14]
GPIO3.IO[15]
GPIO3.IO[16]
GPIO3.IO[17]
GPIO3.IO[0]
GPIO3.IO[1]
GPIO3.IO[2]
GPIO3.IO[3]
GPIO3.IO[4]
GPIO3.IO[5]
GPIO3.IO[6]
GPIO3.IO[7]
GPIO3.IO[8]
GPIO3.IO[9]
GPIO3.IO[01]
GPIO3.IO[11]
ONOFF
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
J4
Digital
GPIO
J3
Digital
GPIO
J1
Digital
GPIO
K1
H2
J2
Digital
GPIO
Digital
GPIO
Digital
GPIO
L5
M5
M3
M4
P2
N3
L3
L4
P3
N4
P4
P5
M6
K7
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Input 100 K PU
PMIC_ON_REQ
Digital
GPIO
ALT0 SNVS_LP.PMIC_ON_RE Output 100 K PU
Q
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NXP Semiconductors
Package information and contact assignments
Table 87. 12 x 12 mm functional contact assignments (continued)
PMIC_STBY_REQ
POR_B
L7
VDD_SNVS_IN
Digital
GPIO
ALT0
CCM.PMIC_VSTBY_RE Output 100 K PU
Q
(PKE
disabled)
M7
VDD_SNVS_IN
Digital
GPIO
ALT0
SRC.POR_B
Input 100 K PU
RTC_XTALI
RTC_XTALO
TEST_MODE
N9
P9
K6
—
—
—
—
—
—
—
—
—
—
—
—
VDD_SNVS_IN
Digital
GPIO
ALT0
TCU.TEST_MODE
Input 100 K PU
USB_OTG1_CHD_B
USB_OTG1_DN
USB_OTG1_DP
USB_OTG1_VBUS
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_VBUS
XTALI
N12
M8
L8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N6
N7
P7
—
—
—
—
—
—
—
—
—
P6
—
—
—
P11
N11
L6
—
—
—
—
—
XTALO
—
WAKEUP
VDD_SNVS_IN
Digital
GPIO
ALT5
GPIO5.IO[0]
Input 100 K PU
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Package information and contact assignments
7.2.3
12 x 12 mm, 0.8 mm pitch, ball map
Table 88 shows the 10 x 10 mm, 0.8 mm pitch ball map for the i.MX RT1064.
Table 88. 12 x 12 mm, 0.8 mm pitch, ball map
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NXP Semiconductors
Package information and contact assignments
Table 88. 12 x 12 mm, 0.8 mm pitch, ball map (continued)
i.MX RT1064 Crossover Processors for Industrial Products, Rev. 2, 08/2020
NXP Semiconductors
111
Revision history
8 Revision history
Table 89 provides a revision history for this data sheet.
Table 89. i.MX RT1064 Data Sheet document revision history
Rev.
Number
Date
Substantive Change(s)
Rev. 2
08/2020 • Changed the MPCore to core in the Section 1.1, Features
• Added new part numbers in the Table 1, Ordering information
• Updated the Figure 1, "Part number nomenclature—i.MX RT1064"
• Updated the frequency of RTC OSC in the Table 2, i.MX RT1064 modules list
• Updated conditions and maximum current of DCDC_IN in the Table 12, Maximum supply currents
• Added a restrictions in the Section 4.2.1.1, Power-up sequence
• Added IOH and IOL in the Table 22, Single voltage GPIO DC parameters
• Updated the minimum and maximum values in the Table 33, SEMC output timing in SYNC mode
• Updated the VDDAD to VDDA in the Table 54, 12-bit ADC operating conditions and Table 55, 12-bit
ADC characteristics (VREFH = VDDA, VREFL = VSSAD)
Rev. 1
12/2019 • Updated SPI NAND Flash in the Section 1.1, Features
• Updated FlexSPI, LCD/CSI/PXP, and SNVS in the Table 1, Ordering information; added KPP, SPI,
XBAR/AOI, and CSU in the Table 1, Ordering information
• Updated RAM in the Figure 2, "i.MX RT1064 system block diagram"
• Updated the Section 4.1.2, Thermal resistance
• Updated the Table 82, Boot through UART1 and removed the Table, Booth through UART2
• Updated the Figure 53, "10 x 10 mm BGA, case x package top, bottom, and side Views" and
Figure 54, "12 x 12 mm BGA, case x package top, bottom, and side Views"
Rev. 0
05/2019 • Initial version
i.MX RT1064 Crossover Processors for Industrial Products, Rev. 2, 08/2020
112
NXP Semiconductors
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EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE
CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT,
MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,
TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior,
ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV,
mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Ready Play,
SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit,
BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower,
TurboLink, UMEMS, EdgeScale, EdgeLock, eIQ, and Immersive3D are trademarks of NXP B.V.
All other product or service names are the property of their respective owners. AMBA, Arm, Arm7,
Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart,
DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore,
Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision,
Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. The related technology may be protected by any or all of patents, copyrights,
designs and trade secrets. All rights reserved. Oracle and Java are registered trademarks of
Oracle and/or its affiliates. The Power Architecture and Power.org word marks and the Power and
Power.org logos and related marks are trademarks and service marks licensed by Power.org.
© 2019-2020 NXP B.V.
Document Number: IMXRT1064IEC
Rev. 2
08/2020
相关型号:
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