PSMN4R3-80BS,118 [NXP]
N-channel 80 V, 4.3 mGäª standard level MOSFET in D2PAK, SOT404 Package, Standard Marking, Reel Pack, SMD, 13";型号: | PSMN4R3-80BS,118 |
厂家: | NXP |
描述: | N-channel 80 V, 4.3 mGäª standard level MOSFET in D2PAK, SOT404 Package, Standard Marking, Reel Pack, SMD, 13" |
文件: | 总14页 (文件大小:183K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSMN4R3-80BS
AK
D2P
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
Rev. 01 — 27 December 2010
Objective data sheet
1. Product profile
1.1 General description
Standard level N-channel MOSFET in D2PAK package qualified to 175C. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
High efficiency due to low switching
Suitable for standard level gate drive
and condition losses
1.3 Applications
DC-to-DC converters
Load switch
Motor control
Server power supplies
1.4 Quick reference data
Table 1.
Symbol
VDS
Quick reference data
Parameter
Conditions
Min Typ Max Unit
drain-source
voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
-
-
-
80
V
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1
-
120
306
A
Ptot
Tj
total power
dissipation
Tmb = 25 °C; see Figure 2
-
W
junction
-55
175 °C
temperature
Static characteristics
RDSon drain-source
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 13
-
-
3.7
-
4.3
6.9
mΩ
mΩ
on-state
resistance
[1]
VGS = 10 V; ID = 25 A;
Tj = 100 °C; see Figure 12
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
Table 1.
Symbol
Dynamic characteristics
Quick reference data …continued
Parameter Conditions
Min Typ Max Unit
QGD
gate-drain charge VGS = 10 V; ID = 75 A;
-
-
28.4
111
-
-
nC
nC
VDS = 40 V; see Figure 14;
QG(tot)
total gate charge
see Figure 15
Avalanche ruggedness
EDS(AL)S
non-repetitive
drain-source
VGS = 10 V; Tj(init) = 25 °C;
ID = 120 A; Vsup ≤ 80 V;
-
-
676 mJ
avalanche energy RGS = 50 Ω; unclamped
[1] Measured 3 mm from package.
2. Pinning information
Table 2.
Pinning information
Symbol Description
Pin
1
Simplified outline
Graphic symbol
G
D
S
D
gate
mb
D
S
2
drain
source
drain
3
G
mb
mbb076
2
1
3
SOT404 (D2PAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN4R3-80BS
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
2 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
80
Unit
V
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
VDGR
VGS
-
80
V
-20
20
V
ID
VGS = 10 V; Tmb = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1
-
-
-
120
120
736
A
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C;
A
see Figure 3
Ptot
Tstg
Tj
total power dissipation
storage temperature
Tmb = 25 °C; see Figure 2
-
306
175
175
260
W
-55
-55
-
°C
°C
°C
junction temperature
Tsld(M)
peak soldering temperature
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
120
736
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
VGS = 10 V; Tj(init) = 25 °C; ID = 120 A;
-
676
mJ
avalanche energy
Vsup ≤ 80 V; RGS = 50 Ω; unclamped
003aaf630
03aa16
120
200
I
D
(A)
P
der
(%)
160
120
80
40
0
80
(1)
40
0
0
50
100
150
200
0
50
100
150
200
T
( C)
°
T
(°C)
mb
mb
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
3 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
003aaf676
104
ID
(A)
103
Limit R
= V / I
DS D
DSon
t =10
s
μ
p
102
10
100
s
μ
1 ms
DC
1
10 ms
100 ms
10-1
10-2
10-1
1
10
102
103
V
(V)
DS
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain source voltage
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from
junction to mounting base
see Figure 4
-
0.22
0.49
K/W
Rth(j-a)
thermal resistance from
junction to ambient
Vertical in free air
-
60
-
K/W
003aaf629
1
Z
th(j-mb)
(K/W)
δ = 0.5
10-1
0.2
0.1
0.05
0.02
tp
10-2
P
δ =
T
single shot
t
tp
T
10-3
10-6
10-5
10-4
10-3
10-2
10-1
1
t (s)
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
4 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
73
80
1
-
-
-
-
-
-
V
V
V
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 175 °C;
voltage
see Figure 10
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 10
-
-
4.6
4
V
V
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 10; see Figure 11
2
3
IDSS
drain leakage current
gate leakage current
VDS = 80 V; VGS = 0 V; Tj = 25 °C
VDS = 80 V; VGS = 0 V; Tj = 175 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
0.02
1
µA
µA
nA
nA
mΩ
-
500
100
100
9
IGSS
-
-
[1]
[1]
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 25 A; Tj = 175 °C;
see Figure 12
7.7
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 13
-
-
-
3.7
-
4.3
6.9
-
mΩ
mΩ
Ω
VGS = 10 V; ID = 25 A; Tj = 100 °C;
see Figure 12
RG
internal gate resistance f = 1 MHz
(AC)
0.9
Dynamic characteristics
QG(tot)
total gate charge
ID = 0 A; VDS = 0 V; VGS = 10 V
-
-
-
-
104
111
-
-
-
-
nC
nC
nC
nC
ID = 75 A; VDS = 40 V; VGS = 10 V;
see Figure 14; see Figure 15
QGS
gate-source charge
38.2
24.1
QGS(th)
pre-threshold
gate-source charge
QGS(th-pl)
post-threshold
-
14.1
-
nC
gate-source charge
QGD
gate-drain charge
-
-
28.4
6.1
-
-
nC
V
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 40 V; see Figure 14;
see Figure 15
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 40 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
-
-
-
8161
701
-
-
-
pF
pF
pF
reverse transfer
capacitance
337
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 40 V; RL = 0.53 Ω; VGS = 10 V;
RG(ext) = 4.7 Ω; ID = 75 A
-
-
-
-
38.3
28.6
94.1
33.2
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
5 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
Table 6.
Symbol
Characteristics …continued
Parameter
Conditions
Min
Typ
Max
Unit
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 17
-
0.8
1.2
V
trr
reverse recovery time IS = 25 A; dIS/dt = 100 A/µs; VGS = 0 V;
-
-
59
-
-
ns
VDS = 20 V
Qr
recovered charge
109
nC
[1] Measured 3 mm from package.
003aaf619
003aaf620
250
80
60
40
20
0
g
I
fs
D
(S)
(A)
200
150
100
50
T = 175
j
C
T = 25 C
°
j
°
0
0
15
30
45
60
75
0
2
4
6
V
(V)
I
(A)
GS
D
Fig 5. Forward transconductance as a function of
drain current; typical values
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aaf621
003aaf622
25
100
R
I
DSon
D
(m
)
Ω
(A)
8.0 6.0
20
15
10
5
80
5.5
20.0
V
(V) = 4.5
4.4
60
40
20
0
GS
4.2
4.0
0
0
5
10
15
20
0
0.5
1
1.5
V
(V)
DS
V
(V)
GS
Fig 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
Fig 8. Output characteristics: drain current as a
function of drain-source voltage; typical values
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
6 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
003aaf623
003aad280
5
1E+5
V
GS(th)
(V)
C
(pF)
4
3
2
1
0
max
104
103
102
C
iss
C
rss
typ
min
10-1
1
10
102
−60
0
60
120
180
V
(V)
GS
T (°C)
j
Fig 9. Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
Fig 10. Gate-source threshold voltage as a function of
junction temperature
03aa35
003aae090
−1
10
3
I
D
a
(A)
min
typ
max
−2
−3
−4
−5
−6
10
2.4
10
10
10
10
1.8
1.2
0.6
0
-60
0
60
120
180
0
2
4
6
T ( C)
°
V
(V)
j
GS
Fig 11. Sub-threshold drain current as a function of
gate-source voltage
Fig 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
7 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
003aaf628
18
V
DS
4.4
V
(V) = 4.5
GS
R
DSon
(mΩ)
I
D
12
V
GS(pl)
V
GS(th)
GS
V
6
0
Q
Q
GS1
GS2
6.0
Q
Q
GD
GS
20.0
Q
G(tot)
003aaa508
0
20
40
60
80
I
(A)
D
Fig 13. Drain-source on-state resistance as a function
of drain current; typical values
Fig 14. Gate charge waveform definitions
003aaf626
003aaf625
1E+5
12
V
GS
(V)
C
10
(pF)
40V
104
103
102
8
6
4
2
0
C
iss
V
= 16V
DS
64V
C
C
oss
rss
10-1
1
10
102
0
30
60
90
120
V
(V)
Q
(nC)
DS
G
Fig 15. Gate-source voltage as a function of gate
charge; typical values
Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
8 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
003aaf627
80
I
S
(A)
60
40
20
0
T = 175
j
C
T = 25 C
°
j
°
0
0.3
0.6
0.9
1.2
V
(V)
SD
Fig 17. Source current as a function of source-drain voltage; typical values
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
9 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
7. Package outline
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-02-11
06-03-16
SOT404
Fig 18. Package outline SOT404 (D2PAK)
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
10 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN4R3-80BS v.1
20101227
Objective data sheet
-
-
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
11 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
9. Legal information
9.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
9.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
9.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
12 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
non-automotive qualified products in automotive equipment or applications.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN4R3-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 December 2010
13 of 14
PSMN4R3-80BS
NXP Semiconductors
N-channel 80 V, 4.3 mΩ standard level MOSFET in D2PAK
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
9.1
9.2
9.3
9.4
10
Contact information. . . . . . . . . . . . . . . . . . . . . .13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 December 2010
Document identifier: PSMN4R3-80BS
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