PTN3460BS/F1,518_技术文档

PTN3460

eDP to LVDS bridge IC

Rev. 4 — 12 March 2014

Product data sheet

1. General description

PTN3460 is an (embedded) DisplayPort to LVDS bridge device that enables connectivity

between an (embedded) DisplayPort (eDP) source and LVDS display panel. It processes

the incoming DisplayPort (DP) stream, performs DP to LVDS protocol conversion and

transmits processed stream in LVDS format.

PTN3460 has two high-speed ports: Receive port facing DP Source (for example,

CPU/GPU/chip set), Transmit port facing the LVDS receiver (for example., LVDS display

panel controller). The PTN3460 can receive DP stream at link rate 1.62 Gbit/s or

2.7 Gbit/s and it can support 1-lane or 2-lane DP operation. It interacts with DP source via

DP Auxiliary (AUX) channel transactions for DP link training and setup.

It supports single bus or dual bus LVDS signaling with color depths of 18 bits per pixel or

24 bits per pixel and pixel clock frequency up to 112 MHz. The LVDS data packing can be

done either in VESA or JEIDA format. Also, the DP AUX interface transports

I²C-over-AUX commands and support EDID-DDC communication with LVDS panel. To

support panels without EDID ROM, the PTN3460 can emulate EDID ROM behavior

avoiding specific changes in system video BIOS.

PTN3460 provides high flexibility to optimally fit under different platform environments. It

supports three configuration options: multi-level configuration pins, DP AUX interface, and

I²C-bus interface.

PTN3460 can be powered by either 3.3 V supply only or dual supplies (3.3 V/1.8 V) and is

available in the HVQFN56 7 mm  7 mm package with 0.4 mm pitch.

2. Features and benefits

2.1 Device features

 Embedded microcontroller and on-chip Non-Volatile Memory (NVM) allow for flexibility

in firmware updates

 LVDS panel power-up (/down) sequencing control

 Firmware controlled panel power-up (/down) sequence timing parameters

 No external timing reference needed

 EDID ROM emulation to support panels with no EDID ROM

 Supports EDID structure v1.3

 On-chip EDID emulation up to seven different EDID data structures

 eDP complying PWM signal generation or PWM signal pass through from eDP source

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

2.2 DisplayPort receiver features

 Compliant to DP v1.2 and v1.1a

 Compliant to eDP v1.2 and v1.1

 Supports Main Link operation with 1 or 2 lanes (default mode is 2-lane operation)

 Supports Main Link rate: Reduced Bit Rate (1.62 Gbit/s) and High Bit Rate (2.7 Gbit/s)

 Supports 1 Mbit/s AUX channel

 Supports Native AUX and I²C-over-AUX transactions

 Supports down spreading to minimize EMI

 Integrated 50  termination resistors provide impedance matching on both Main Link

lanes and AUX channel

 High performance Auto Receive Equalization enabling optimal channel compensation,

device placement flexibility and power saving at CPU/GPU

 Supports eDP authentication options: Alternate Scrambler Seed Reset (ASSR) and

Alternate Framing

 Supports Fast Link training and Full Link training

 Supports DisplayPort symbol error rate measurements

2.3 LVDS transmitter features

 Compatible with ANSI/TIA/EIA-644-A-2001 standard

 Supports RGB data packing as per JEIDA and VESA data formats

 Supports pixel clock frequency from 25 MHz to 112 MHz

 Supports single LVDS bus operation up to 112 mega pixels per second

 Supports dual LVDS bus operation up to 224 mega pixels per second

 Supports color depth options: 18 bpp, 24 bpp

 Programmable center spreading of pixel clock frequency to minimize EMI

 Supports 1920  1200 at 60 Hz resolution in dual LVDS bus mode

 Programmable LVDS signal swing to pre-compensate for channel attenuation or allow

for power saving

 Supports PCB routing flexibility by programming for:

 LVDS bus swapping

 Channel swapping

 Differential signal pair swapping

 Supports Data Enable polarity programming

 DDC control for EDID ROM access – I²C-bus interface up to 400 kbit/s

2.4 Control and system features

 Device programmability

 Multi-level configuration pins enabling wider choice

 I²C-bus slave interface supporting Standard-mode (100 kbit/s) and

Fast-mode (400 kbit/s)

 Power management

 Low-power state: DP AUX command-based Low-power mode (SET POWER)

 Deep power-saving state via a dedicated pin

PTN3460

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Product data sheet

Rev. 4 — 12 March 2014

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PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

2.5 General

 Power supply: with on-chip regulator

 3.3 V  10 % (integrated regulator switched on)

 3.3 V  10 %, 1.8 V  5 % (integrated regulator switched off)

 ESD: 8 kV HBM, 1 kV CDM

 Operating temperature range: 0 C to 70 C

 HVQFN56 package 7 mm  7 mm, 0.4 mm pitch; exposed center pad for thermal relief

and electrical ground

3. Applications

 AIO platforms

 Notebook platforms

 Netbooks/net tops

4. System context diagram

Figure 1 illustrates the PTN3460 usage.

notebook or AIO platform

LVDS PANEL

PTN3460

DP to LVDS

BRIDGE

eDP

LVDS

CPU/GPU/

CHIP SET

cable

MOTHERBOARD

002aaf831

Fig 1. PTN3460 context diagram

5. Ordering information

Table 1.

Ordering information

Type number

Topside mark Package

Name

Description

Version

PTN3460BS/Fx^[1][2]

PTN3460BS^[3]HVQFN56

plastic thermal enhanced very thin quad flat package; SOT949-2

no leads; 56 terminals; body 7  7  0.85 mm^[4];

0.4 mm pitch

[1] PTN3460BS/Fx is firmware-specific, where the ‘x’ indicates the firmware version.

[2] Notes on firmware and marking:

a) Firmware versions are not necessarily backwards compatible.

b) Box/reel labels will indicate the firmware version via the orderable part number (for example, labeling will indicate PTN3460BS/F1 for

firmware version 1). A sample label is illustrated in Figure 8.

[3] Topside marking is limited to PTN3460BS and will not indicate the firmware version.

[4] Maximum package height is 1 mm.

PTN3460

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Product data sheet

Rev. 4 — 12 March 2014

3 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

7. Pinning information

7.1 Pinning

terminal 1

index area

AUX_N

AUX_P

GND

DP0_P

DP0_N

1

2

3

4

5

6

7

8

9

42 LVSAE_N

41 LVSAE_P

40 LVSBE_N

39 LVSBE_P

38

V

DD(3V3)

V

37 LVSCE_N

36 LVSCE_P

35 LVSCKE_N

34 LVSCKE_P

33 PVCCEN

32 LVSDE_N

31 LVSDE_P

30 DDC_SDA

29 DDC_SCL

DD(1V8)

DP1_P

PTN3460BS

DP1_N

RST_N

PD_N 10

HPDRX 11

DEV_CFG 12

(1)

V

13

14

DD(3V3)

002aaf833

Transparent top view

(1) Center pad is connected to PCB ground plane for electrical grounding and thermal relief.

Fig 3. Pin configuration for HVQFN56

Refer to Section 13 “Package outline” for package and pin dimensions.

PTN3460

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Product data sheet

Rev. 4 — 12 March 2014

5 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

7.2 Pin description

Table 2.

Symbol

Pin description

Pin Type

Description

DisplayPort interface signals

DP0_P

DP0_N

DP1_P

DP1_N

AUX_P

AUX_N

HPDRX

4

self-biasing

differential input

Differential signal from DP source. DP0_P makes a differential pair with DP0_N.

The input to this pin must be AC-coupled externally.

5

self-biasing

differential input

Differential signal from DP source. DP0_N makes a differential pair with DP0_P.

The input to this pin must be AC-coupled externally.

7

self-biasing

differential input

Differential signal from DP source. DP1_P makes a differential pair with DP1_N.

The input to this pin must be AC-coupled externally.

8

self-biasing

differential input

Differential signal from DP source. DP1_N makes a differential pair with DP1_P.

The input to this pin must be AC-coupled externally.

2

self-biasing

differential I/O

Differential signal towards DP source. AUX_P makes a differential pair with

AUX_N. The pin must be AC-coupled externally.

1

self-biasing

differential I/O

Differential signal towards DP source. AUX_N makes a differential pair with

AUX_P. The pin must be AC-coupled externally.

11

single-ended

3.3 V CMOS

output

Hot Plug Detect signal to DP source.

LVDS interface signals

LVSAE_P

LVSAE_N

LVSBE_P

LVSBE_N

LVSCE_P

LVSCE_N

41

42

39

40

36

37

LVDS output

Even bus, Channel A differential signal to LVDS receiver. LVSAE_P makes a

differential pair with LVSAE_N.

Even bus, Channel A differential signal to LVDS receiver. LVSAE_N makes a

differential pair with LVSAE_P.

Even bus, Channel B differential signal to LVDS receiver. LVSBE_P makes a

differential pair with LVSBE_N.

Even bus, Channel B differential signal to LVDS receiver. LVSBE_N makes a

differential pair with LVSBE_P.

Even bus, Channel C differential signal to LVDS receiver. LVSCE_P makes a

differential pair with LVSCE_N.

Even bus, Channel C differential signal to LVDS receiver. LVSCE_N makes a

differential pair with LVSCE_P.

LVSCKE_P 34

LVSCKE_N 35

LVDS clock

output

Even bus, clock differential signal to LVDS receiver. LVSCKE_P makes a

differential pair with LVSCKE_N.

LVDS clock

output

Even bus, clock differential signal to LVDS receiver. LVSCKE_N makes a

differential pair with LVSCKE_P.

LVSDE_P

LVSDE_N

LVSAO_P

LVSAO_N

LVSBO_P

LVSBO_N

31

32

53

54

51

52

LVDS output

Even bus, Channel D differential signal to LVDS receiver. LVSDE_P makes a

differential pair with LVSDE_N.

Even bus, Channel D differential signal to LVDS receiver. LVSDE_N makes a

differential pair with LVSDE_P.

Odd bus, Channel A differential signal to LVDS receiver. LVSAO_P makes a

differential pair with LVSAO_N.

Odd bus, Channel A differential signal to LVDS receiver. LVSAO_N makes a

differential pair with LVSAO_P.

Odd bus, Channel B differential signal to LVDS receiver. LVSBO_P makes a

differential pair with LVSBO_N.

Odd bus, Channel B differential signal to LVDS receiver. LVSBO_N makes a

differential pair with LVSBO_P.

PTN3460

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Product data sheet

Rev. 4 — 12 March 2014

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PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

Table 2.

Symbol

LVSCO_P

Pin description …continued

Type

Description

48

LVDS output

Odd bus, Channel C differential signal to LVDS receiver. LVSCO_P makes a

differential pair with LVSCO_N.

LVSCO_N

49

LVDS output

Odd bus, Channel C differential signal to LVDS receiver. LVSCO_N makes a

differential pair with LVSCO_P.

LVSCKO_P 46

LVSCKO_N 47

LVDS clock

output

Odd bus, clock differential signal to LVDS receiver. LVSCKO_P makes a

differential pair with LVSCKO_N.

LVDS clock

output

Odd bus, clock differential signal to LVDS receiver. LVSCKO_N makes a

differential pair with LVSCKO_P.

LVSDO_P

LVSDO_N

DDC_SDA

DDC_SCL

43

44

30

29

LVDS output

Odd bus, Channel D differential signal to LVDS receiver. LVSDO_P makes a

differential pair with LVSDO_N.

LVDS output

Odd bus, Channel D differential signal to LVDS receiver. LVSDO_N makes a

differential pair with LVSDO_P.

open-drain

DDC data I/O

DDC data signal connection to display panel. Pulled-up by external termination

resistor (5 V tolerant).

open-drain

DDC clock I/O

DDC clock signal connection to display panel. Pulled-up by external termination

resistor (5 V tolerant).

Panel and backlight interface signals

PVCCEN

PWMO

33

28

26

CMOS output

Panel power (V_CC) enable output.

PWM output signal to display panel.

Backlight enable output.

BKLTEN

Control interface signals

PD_N

10

CMOS input

Chip power-down input (active LOW). If PD_N is LOW, then the device is in

Deep power-down completely, even if supply rail is ON; for the device to be able

to operate, the PD_N pin must be HIGH.

RST_N

9

CMOS input

Chip reset pin (active LOW); internally pulled-up. The pin is meant to reset the

device and all its internal states/logic; all internal registers are taken to default

value after RST_N is applied and made HIGH.

If RST_N is LOW, the device stays in reset condition and for the device to be

able to operate, RST_N must be HIGH.

DEV_CFG

12

CMOS I/O

I²C-bus address/mode selection pin.

TESTMODE 20

CMOS input

If TESTMODE is left open or pulled HIGH, CFG[4:1] operate as JTAG pins. If

TESTMODE is pulled LOW, these pins serve as configuration pins.

CFG1

CFG2

21

22

input

Behavior defined by TESTMODE pin.

If TESTMODE is left open or pulled HIGH, this pin functions as JTAG TEST

CLOCK input. If TESTMODE is pulled LOW, this pin acts as configuration input.

Behavior defined by TESTMODE pin.

If TESTMODE is left open or pulled HIGH, this pin functions as JTAG MODE

SELECT input. If TESTMODE is pulled LOW, this pin acts as configuration

input.

CFG3

CFG4

23

27

input

I/O

Behavior defined by TESTMODE pin.

If TESTMODE is left open or pulled HIGH, this pin functions as JTAG TEST

DATA INPUT. If TESTMODE is pulled LOW, this pin acts as configuration input.

Behavior defined by TESTMODE pin value.

If TESTMODE is left open or pulled HIGH, this pin functions as JTAG TEST

DATA OUTPUT. If TESTMODE is pulled LOW, this pin acts as configuration

input.

PTN3460

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Product data sheet

Rev. 4 — 12 March 2014

7 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

Table 2.

Symbol

MS_SDA

Pin description …continued

Type

Description

I²C-bus data signal connection to I²C-bus master or slave. Pulled up by external

24

open-drain (I²C)

data input/output resistor.

MS_SCL

25

open-drain (I²C)

I²C-bus clock signal connection to I²C-bus master or slave. Pulled up by

clock input/output external resistor.

n.c.

55

56

-

not connected; reserved.

EPS_N

input

Can be left open or pulled HIGH for 3.3 V supply only option relying on internal

regulator for 1.8 V generation.

Should be pulled down to GND for dual supply (3.3 V/1.8 V) option.

Supply, ground and decoupling

V_DD(3V3)

13, 14, power

38, 50

3.3 V supply input.

V_DD(1V8)

n.c.

6, 45

19

power

1.8 V supply input.

1.8 V regulator supply output.

Not connected.

15, 16 power

power

GND

3

Ground.

GNDREG

GND

17, 18 power

Ground for regulator.

center power

pad

The center pad must be connected to motherboard GND plane for both

electrical ground and thermal relief.

8. Functional description

PTN3460 is an (Embedded) DisplayPort to LVDS bridge IC that processes the incoming

DisplayPort (DP) stream, performs DP to LVDS protocol conversion and transmits

processed stream in LVDS format. Refer to Figure 2 “Block diagram of PTN3460”.

The PTN3460 consists of:

• DisplayPort receiver

• LVDS transmitter

• System control and operation

The following sections describe individual sub-systems and their capabilities in more

detail.

8.1 DisplayPort receiver

PTN3460 implements a DisplayPort receiver consisting of 2-lane Main Link and AUX

channel.

With its advanced signal processing capability, it can handle Fast Link training or Full Link

training scheme. PTN3460 implements a high-performance Auto Receive Equalizer and

Clock Data Recovery (CDR) algorithm, with which it identifies and selects an optimal

operational setting for given channel environment. Given that the device is targeted

primarily for embedded Display connectivity, both Display Authentication and Copy

Protection Method 3a (Alternate Scrambler Seed Reset) and Method 3b (Enhanced

Framing) are supported, as per eDP 1.2.

PTN3460

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Product data sheet

Rev. 4 — 12 March 2014

8 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

The PTN3460 DPCD registers can be accessed by DP source through AUX channel. It

supports both Native AUX transactions and I²C-over-AUX transactions.

Native AUX transactions are used to access PTN3460 DisplayPort Configuration Data

(DPCD) registers (e.g., to facilitate Link training, check error conditions, etc.) and

I²C-over-AUX transactions are used to perform any required access to DDC bus

(e.g., EDID reads).

Given that the HPDRX pin is internally connected to GND through an integrated pull-down

resistor (> 100 k), the DP source will see HPDRX pin as LOW indicating that the

DisplayPort receiver is not ready when the device is not powered. This helps avoid raising

false events to the source. After power-up, PTN3460 continues to drive HPDRX pin LOW

until completion of internal initialization. After this, PTN3460 generates HPD signal to

notify DP source and take corrective action(s).

8.1.1 DP Link

PTN3460 is capable of operating either in DP 2-lane or 1-lane mode. The default is 2-lane

mode of operation (in alignment with PTN3460 DCPD register 00002h,

MAX_LANE_COUNT = 2).

There are two ways to enable 1-lane operation in an application:

• Connect both DP lanes of PTN3460 to the DP source. This enables the DP source to

decide/use only required number of lanes based on display resolution.

• Connect only 1 lane (DP0_P, DP0_N) to DP source and modify the DPCD register

00002h, MAX_LANE_COUNT to ‘1’ through NXP I²C configuration utility to modify the

internal configuration table. Please consult NXP for more details regarding the

Flash-over-AUX and DOS utilities.

8.1.2 DPCD registers

DPCD registers are described in VESA DisplayPort v1.1a/1.2 specifications in detail and

PTN3460 supports DPCD version 1.2.

PTN3460 configuration registers can be accessed through DP AUX channel from the

GPU/CPU, if required. They are defined under vendor-specific region starting at base

address 0x00510h. So any configuration register can be accessed at DPCD address

obtained by adding the register offset and base address.

PTN3460 supports down spreading on DP link and this is reflected in DPCD register

MAX_DOWNSPREAD at address 0003h. Further, the DP source could control

down spreading and inform PTN3460 via DOWNSPREAD_CTRL register at DPCD

register 00107h.

The key aspect is that the system designer must take care that the Input video payload fits

well within both DP link bandwidth and LVDS bandwidth (for a given pixel frequency,

SSC depths) when clock spreading is enabled. Also, another aspect for the system

designer is to ensure LVDS (panel) TCONs are capable of handling SSC modulated LVDS

signaling.

PTN3460

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Product data sheet

Rev. 4 — 12 March 2014

9 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

8.2 LVDS transmitter

The LVDS interface can operate either in Single or Dual LVDS Bus mode at pixel clock

frequencies over the range of 25 MHz to 112 MHz and color depths of 18 bpp or 24 bpp.

Each LVDS bus consists of 3/4 differential data pairs and one clock pair. PTN3460 can

packetize RGB video data, HSYNC, VSYNC, DE either in VESA or JEIDA format. To

enable system EMI reduction, the device can be programmed for center spreading of

LVDS channel clock outputs.

The LVDS interface can be flexibly configured using multi-level configuration pins (CFG1,

CFG2, CFG3, CFG4) or via register interface. The configuration pins and the

corresponding definitions are described in Table 3 through Table 6. Nevertheless, as the

configuration pins are designed for general purpose, their definitions can be modified and

they can be used for any other purposes. However, this can be achieved through firmware

upgrade only.

Table 3.

CFG1 configuration options

Configuration input setting

Number of LVDS links

single LVDS bus

LOW

HIGH

dual LVDS bus

Table 4.

CFG2 configuration options

3-level configuration input setting

Data format

VESA

Number of bits per pixel (bpp)

LOW

open

HIGH

24 bpp

18 bpp

JEIDA

JEIDA or VESA

Table 5.

CFG3 configuration options^[1]

3-level configuration input setting

LVDS clock frequency spread depth control

LOW

open

HIGH

0 %

1 %

0.5 %

[1] LVDS center spreading modulation frequency is kept at 32.9 kHz.

Table 6.

CFG4 configuration options

3-level configuration input setting

pull-down resistor^[1]to GND

open

LVDS output swing (typical value)

250 mV

300 mV

400 mV

pull-up resistor^[1]to V_DD(3V3)

[1] Pull-up/down resistor value in the range of 1 k to 10 k.

PTN3460

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Product data sheet

Rev. 4 — 12 March 2014

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PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

The VESA and JEIDA data format definitions are described in Table 7 to Table Table 13.

Table 7.

Channel

LVDS single bus, 18 bpp, VESA or JEIDA data packing

Bit position

6

5

4

3

2

1

0

LVDS odd differential channel A

LVDS odd differential channel B

LVDS odd differential channel C

bit 0

bit 1

DE

bit 5

bit 4

bit 3

bit 4

bit 5

bit 2

bit 3

bit 4

bit 1

bit 2

bit 3

bit 0

bit 1

bit 2

bit 0

bit 5

VSYNC

HSYNC

Table 8.

Channel

LVDS single bus, 24 bpp, VESA data packing

Bit position

6

bit 0

5

4

3

2

1

0

LVDS odd differential channel A

LVDS odd differential channel B

LVDS odd differential channel C

LVDS odd differential channel D

bit 5

bit 4

bit 3

bit 4

bit 5

bit 7

bit 2

bit 3

bit 4

bit 6

bit 1

bit 2

bit 3

bit 7

bit 0

bit 1

bit 2

bit 6

bit 1

bit 0

bit 5

DE

VSYNC

bit 7

HSYNC

bit 6

don’t care

Table 9.

Channel

LVDS dual bus, 18 bpp, VESA data packing

Bit position

3

6

5

4

2

1

0

LVDS odd differential channel A

LVDS odd differential channel B

LVDS odd differential channel C

LVDS even differential channel A

LVDS even differential channel B

LVDS even differential channel C

bit 0

bit 1

DE

bit 5

bit 4

bit 3

bit 2

bit 3

bit 4

bit 2

bit 3

bit 4

bit 1

bit 2

bit 3

bit 1

bit 2

bit 3

bit 0

bit 1

bit 2

bit 0

bit 1

bit 2

bit 0

bit 5

bit 4

VSYNC

bit 5

HSYNC

bit 4

bit 5

bit 0

bit 1

DE

bit 3

bit 0

bit 5

bit 4

VSYNC

HSYNC

bit 5

Table 10. LVDS dual bus, 24 bpp, VESA data packing

Channel

Bit position

3

6

bit 0

5

4

2

1

0

LVDS odd differential channel A

LVDS odd differential channel B

LVDS odd differential channel C

LVDS odd differential channel D

LVDS even differential channel A

LVDS even differential channel B

LVDS even differential channel C

LVDS even differential channel D

bit 5

bit 4

bit 3

bit 2

bit 3

bit 4

bit 6

bit 2

bit 3

bit 4

bit 6

bit 1

bit 2

bit 3

bit 7

bit 1

bit 2

bit 3

bit 7

bit 0

bit 1

bit 2

bit 6

bit 0

bit 1

bit 2

bit 6

bit 1

bit 0

bit 5

bit 4

DE

VSYNC

bit 7

HSYNC

bit 6

bit 5

don’t care

bit 0

bit 7

bit 5

bit 4

bit 3

bit 1

bit 0

bit 5

bit 4

DE

VSYNC

bit 7

HSYNC

bit 6

bit 5

don’t care

bit 7

PTN3460

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Product data sheet

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PTN3460

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eDP to LVDS bridge IC

Table 11. LVDS single bus, 24 bpp, JEIDA data packing

Channel

Bit position

6

bit 2

5

4

3

2

1

0

LVDS odd differential channel A

LVDS odd differential channel B

LVDS odd differential channel C

LVDS odd differential channel D

bit 7

bit 6

bit 5

bit 6

bit 7

bit 1

bit 4

bit 5

bit 6

bit 0

bit 3

bit 4

bit 5

bit 1

bit 2

bit 3

bit 4

bit 0

bit 3

bit 2

bit 7

DE

VSYNC

bit 1

HSYNC

bit 0

don’t care

Table 12. LVDS dual bus, 18 bpp, JEIDA data packing

Channel

Bit position

3

6

5

4

2

1

0

LVDS odd differential channel A

LVDS odd differential channel B

LVDS odd differential channel C

LVDS even differential channel A

LVDS even differential channel B

LVDS even differential channel C

bit 0

bit 1

DE

bit 5

bit 4

bit 3

bit 2

bit 3

bit 4

bit 2

bit 3

bit 4

bit 1

bit 2

bit 3

bit 1

bit 2

bit 3

bit 0

bit 1

bit 2

bit 0

bit 1

bit 2

bit 0

bit 5

bit 4

VSYNC

bit 5

HSYNC

bit 4

bit 5

bit 0

bit 1

DE

bit 3

bit 0

bit 5

bit 4

VSYNC

HSYNC

bit 5

Table 13. LVDS dual bus, 24 bpp, JEIDA data packing

Channel

Bit position

3

6

bit 2

5

4

2

1

0

LVDS odd differential channel A

LVDS odd differential channel B

LVDS odd differential channel C

LVDS odd differential channel D

LVDS even differential channel A

LVDS even differential channel B

LVDS even differential channel C

LVDS even differential channel D

bit 7

bit 6

bit 5

bit 4

bit 5

bit 6

bit 0

bit 4

bit 5

bit 6

bit 0

bit 3

bit 4

bit 5

bit 1

bit 3

bit 4

bit 5

bit 1

bit 2

bit 3

bit 4

bit 0

bit 2

bit 3

bit 4

bit 0

bit 3

bit 2

bit 7

bit 6

DE

VSYNC

bit 1

HSYNC

bit 0

bit 7

don’t care

bit 2

bit 1

bit 7

bit 6

bit 5

bit 3

bit 2

bit 7

bit 6

DE

VSYNC

bit 1

HSYNC

bit 0

bit 7

don’t care

bit 1

PTN3460 delivers great flexibility by supporting more programmable options via I²C-bus

or AUX interface. Please refer to Section 8.3.8 for more details.

PTN3460

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Product data sheet

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12 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

8.3 System control and operation

With its combination of embedded microcontroller, non-volatile memory, DPCD AUX and

I²C-bus interfaces, PTN3460 delivers significant value for customer applications by

providing higher degree of control and programmability.

By default, all user controllable registers can be accessed through DPCD AUX interface.

This interface is always enabled. This AUX interface delivers seamless access of

PTN3460 registers to system/platform (GPU) firmware driver. Nevertheless, use of

I²C-bus interface for configuring PTN3460 is left to the choice of system integrator.

DEV_CFG (pin 12) sets up I²C-bus configuration mode:

• Pull-down resistor to GND — PTN3460 operates as I²C-bus slave, low address

(0x40h)

• Open — PTN3460 operates as I²C-bus slave, high address (0xC0h)

• Pull-up resistor to V_DD(3V3)— PTN3460 operates as I²C-bus master capable of

reading from external EEPROM

8.3.1 Reset, power-down and power-on initialization

The device has a built-in reset circuitry that generates internal reset signal after power-on.

All the internal registers and state machines are initialized and the registers take default

values. In addition, PTN3460 has a dedicated control pin RST_N. This serves the same

purpose as power-on reset, but without power cycling of the device/platform.

PTN3460 starts up in a default condition after power-on or after RST_N is toggled from

LOW to HIGH. The configuration pins are sampled at power-on, or external reset, or when

returning from Deep Sleep.

PTN3460 goes into Deep power-saving when PD_N is LOW. This will trigger a

power-down sequence. To leave Deep power-saving state, the system needs to drive

PD_N back to HIGH. If PD_N pin is open, the device will not enter Deep power-saving

state. Once the device is in Deep power-saving condition, the HPDRX pin will go LOW

automatically and this can be used by the system to remove the 3.3 V supply, if required.

Remark: The device will not respect the Panel power-down sequence if PD_N is asserted

LOW while video is being streamed to the display. So the system is not supposed to

toggle PD_N and RST_N pins asynchronously while the LVDS output is streaming video

to the display panel, but instead follow the panel powering sequence as described in

Section 8.3.3.

PTN3460

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Product data sheet

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13 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

8.3.2 LVDS panel control

PTN3460 implements eDPv1.2 specific DPCD registers that concern panel power,

backlight and PWM controls and the DP source can issue AUX commands to initiate

panel power-up/down sequence as required. Also, PTN3460 supports LVDS panel control

pins — backlight enable, panel power enable and PWM — that can be set via AUX

commands.

• PVCCEN pin — the signal output is set based on SET_POWER DPCD register

00600h and SET_POWER_CAPABLE bit of

EDP_GENERAL_CAPABILITY_REGISTER_1 DPCD register 00701h and detection

and handling of video data stream by PTN3460

• BKLTEN pin — the signal output is set based on

BACKLIGHT_PIN_ENABLE_CAPABLE bit of

EDP_GENERAL_CAPABILITY_REGISTER_1 DPCD register 00701h and

BACKLIGHT_ENABLE bit of EDP_DISPLAY_CONTROL_REGISTER DPCD register

00720h

• PWMO pin — the PWM signal generated by PTN3460 based on controls set in

DPCD registers. In addition, PTN3460 can pass through PWM signal from eDP

source as well. Please refer to Ref. 2 for more information.

All the panel control enable and signal outputs from PTN3460 are aligned with panel

power-on sequence timing including LVDS video output generation. It is important to note

that the Panel power must be delivered by the system platform and it should be gated by

PVCCEN signal.

PTN3460

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Product data sheet

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PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

8.3.3 Panel power sequencing

Figure 4 illustrates an example of panel power-up/power-down sequence for PTN3460.

Depending on the source behavior and PTN3460 firmware version, the powering

sequence/timing could have some slight differences.

T12 > 500 ms

V

DD(3V3)

LCDVCC

PVCCEN

black video

from PTN3460

T2 < 50 ms

T5 < 50 ms

LVDS interface

video from source

SINK_STATUS

HPDRX

eDP AUX channel

AUX channel operational

valid video data

eDP Main Link

Link Training

disabled

idle

video or IDLE stream

from DP source

enabled

display backlight

T3 > 200 ms

to 1000 ms

T4 > 200 ms

002aaf839

T2: Time interval between panel power enable signal (PVCCEN) going HIGH and video data/clock driven on LVDS interface.

T3: Time interval between valid video data/clock on LVDS interface and backlight enable signal (BKLTEN) going HIGH.

T4: Time interval between backlight enable signal (BKLTEN) made LOW and stopping of video data/clock on LVDS interface.

T5: Time interval between stopping of video data/clock on LVDS interface and panel power enable signal (PVCCEN) made

LOW.

T12: Time interval for which PVCCEN is held LOW before it can be made HIGH.

Fig 4. Panel power-up/power-down sequence example

When working with eDP capable DP sources, PTN3460 supports the following (for

specific sequence, refer to Figure 4):

• After power-on/startup, HPDRX is asserted HIGH, DP source will start AUX

communication for initialization, perform Link Training and starts the video data

stream. Once presence of video data is detected, PTN3460 will assert PVCCEN to

HIGH, synchronize to video stream, output LVDS data and assert rise the Sink_status

lock as indicated in DPCD register (0x00205h). PTN3460 will wait for Backlight

enabling delay (T3) to avoid visual artifacts and program the BKLTEN HIGH.

• While transitioning out of Active state by receiving DPCD 0x600 to set PTN3460 in

D3 mode, PTN3460 will disable BKLTEN prior to cutting off Video streaming to avoid

visible artifacts following specific panel specifications. PTN3460 will assert PVCCEN

to LOW after T5 delay as long as either if the video stream is stopped or video

synchronization is lost. This is to avoid driving the LVDS panel with illegal stream for

long periods of time. It is good practice for sources to keep video data or at least

DP-idle stream active during T4 + T5.

• When PTN3460 is in Low-power state (DisplayPort D3 power state), the LVDS

differential I/Os are weakly pulled down to 0 V. In this state, PVCCEN and BKLTEN

are pulled LOW.

• When PD_N is LOW, which sets PTN3460 in Deep power-saving state, the BKLTEN

pin is set to LOW. LVDS differential I/Os are pulled LOW via the weak pull-downs.

PTN3460

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Product data sheet

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15 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

8.3.4 Termination resistors

The device provides integrated and calibrated 50  termination resistors on both

DisplayPort Main Link lanes and AUX channel.

8.3.5 Reference clock input

PTN3460 does not require an external clock. It relies fully on the clock derived internally

from incoming DP stream or on-chip clock generator.

8.3.6 Power supply

PTN3460 can be flexibly supplied with either 3.3 V supply only or dual supplies

(3.3 V/1.8 V). When supplied with 3.3 V supply only, the integrated regulator is used to

generate 1.8 V for internal circuit operation. In this case, the EPS_N pin must be pulled

HIGH or left open. For optimal power consumption, dual supply option (3.3 V and 1.8 V) is

recommended.

8.3.7 Power management

In tune with the system application needs, PTN3460 implements aggressive techniques to

support system power management and conservation. The device can exist in one of the

three different states as described below:

• Active state when the device is fully operational.

• Low-power state when DP source issues AUX SET_POWER command on DPCD

register 00600h. In this state, AUX and HPD circuits are operational but the main

DP Link and LVDS Bus are put to high-impedance condition. The device will transition

back to Active state when the DP source sets the corresponding DPCD register bits to

‘DisplayPort D0/Normal Operation mode’. The I²C-bus interface will not be

operational in this state.

• Deep power-saving state: In this state PTN3460 is put to ultra low-power condition.

This is effected when PD_N is LOW. To get back to Active state, PD_N must be made

HIGH. The external interfaces (like I²C, AUX, DP, LVDS, configuration pins) will not be

operational.

8.3.8 Register interface — control and programmability

PTN3460 has a register interface that can be accessed by CPU/GPU or System

Controller to choose settings suitably for the System application needs. The registers can

be read/written either via DP AUX or I²C-bus interface. It is left to system integrator choice

to use an interface to configure PTN3460.

PTN3460 provides greater level of configurability of certain parameters (e.g., LVDS output

swing, spreading depth, etc.) via registers beyond what is available through pins. The

register settings override the pin values. All registers must be configured during power-on

initialization after HPDRX is HIGH. The registers and bit definitions are described in

“I²C-bus utility and programming guide for firmware and EDID update” (Ref. 3).

8.3.9 EDID handling

The DP source issues EDID reads using I²C-over-AUX transactions and PTN3460, in

turn, reads from the panel EDID ROM and passes back to the source. To support

seamless functioning of panels without EDID ROM, the PTN3460 can be programmed to

emulate EDID ROM and delivers internally stored EDID information to the source. Given

PTN3460

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Product data sheet

Rev. 4 — 12 March 2014

16 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

that EDID is specific to panels, PTN3460 enables system integrator to program EDID

information into embedded memory through DP AUX and I²C-bus interfaces. The

supported EDID ROM emulation size is 896 bytes (seven EDID data structures, each of

128 bytes).

9. Application design-in information

Figure 5 illustrates PTN3460 usage in a system context. The eDP inputs are connected to

DP source port on CPU/GPU and the LVDS outputs are connected to LVDS panel TCON.

PTN3460

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Product data sheet

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PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

10. Limiting values

Table 14. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

0.3

65

-

Max

Unit

V

[1]

supply voltage

input voltage

+4.6

V_I

3.3 V CMOS inputs

V_DD+ 0.5

+150

V

T_stg

storage temperature

C

V

[2]

[3]

V_ESD

electrostatic discharge

voltage

HBM

CDM

8000

-

1000

V

[1] All voltage values, except differential voltages, are with respect to network ground terminal.

[2] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model

– Component level; Electrostatic Discharge Association, Rome, NY, USA.

[3] Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing,

Charged-Device Model – Component level; Electrostatic Discharge Association, Rome, NY, USA.

11. Recommended operating conditions

Table 15. Operating conditions

Over operating free-air temperature range, unless otherwise noted.

Symbol Parameter

Conditions

Min

3.0

1.7

0

Typ

3.3

1.8

3.3

5

Max

3.6

1.9

3.6

5.5

Unit

V

V_DD(3V3)supply voltage (3.3 V)

V_DD(1V8)supply voltage (1.8 V)

V

V_I

input voltage

3.3 V CMOS inputs

V

open-drain I/O with

respect to ground

(e.g., DDC_SCL,

DDC_SDA, MS_SDA,

MS_SCL)

0

V

T_amb

ambient temperature operating in free air

0

-

70

C

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Product data sheet

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PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

12. Characteristics

12.1 Device characteristics

Table 16. Device characteristics

Over operating free-air temperature range, unless otherwise noted.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_startup

start-up time

device start-up time from power-on and

RST_N = HIGH; supply voltage within

operating range to specified operating

characteristics

-

90

ms

t_w(rst)

t_d(rst)

reset pulse width

reset delay time^[1]

device is supplied with valid supply voltage

10

-

s

90

ms

t_{d(pwrsave-act)}delay time from

power-save to active

time between PD_N going HIGH and HPD

raised HIGH by PTN3460; RST_N is HIGH.

-

Device is supplied with valid supply voltage.

[1] Time for device to be ready after rising edge of RST_N.

12.2 Power consumption

Table 17. Power consumption

At operating free-air temperature of 25 C and under nominal supply value (unless otherwise noted).

Symbol Parameter

Conditions

Single supply mode Dual supply mode Unit

EPS_N = HIGH

or open

EPS_N = LOW

Min

Typ

Max

Min

Typ

Max

[1]

P_cons

power

consumption

Active mode;

1440  900 at 60 Hz;

24 bits per pixel; dual LVDS bus

-

430

-

290

-

mW

Active mode;

1600  900 at 60 Hz;

24 bits per pixel; dual LVDS bus

448

570

27

305

380

15

Active mode;

1920  1200 at 60 Hz;

24-bits per pixel; dual LVDS bus

D3 mode/Power-saving mode;

when PTN3460 is set to

Power-saving mode via

‘SET_POWER’ AUX command by

eDP source; AUX and HPDRX

circuitry are only kept active

Deep power-saving/Shutdown mode;

when PD_N is LOW and the device is

supplied with valid supply voltage

-

5

-

2

-

mW

[1] For Active mode power consumption, LVDS output swing of 300 mV is considered.

PTN3460

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Product data sheet

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PTN3460

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eDP to LVDS bridge IC

12.3 DisplayPort receiver characteristics

Table 18. DisplayPort receiver main channel characteristics

Over operating free-air temperature range (unless otherwise noted).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

[2]

UI

unit interval

high bit rate

(2.7 Gbit/s per lane)

-

370

-

ps

reduced bit rate

(1.62 Gbit/s per lane)

-

617

-

ps

f_{DOWN_SPREAD}

C_RX

link clock down spreading

AC coupling capacitor

0

-

0.5

%

75

200

nF

V_{RX_DIFFp-p}

differential input peak-to-peak

voltage

at receiver package pins

[3]

high bit rate

120

40

-

mV

(2.7 Gbit/s per lane)

reduced bit rate

(1.62 Gbit/s per lane)

[4]

[5]

[6]

V_{RX_DC_CM}

I_{RX_SHORT}

RX DC common mode voltage

RX short-circuit current limit

0

-

2.0

50

-

V

-

mA

MHz

dB

f_{RX_TRACKING_BW}jitter tracking bandwidth

G_eq(max)maximum equalization gain

20

-

at 1.35 GHz

15

-

[1] Range is nominal 350 ppm. DisplayPort channel RX does not require local crystal for channel clock generation.

[2] Up to 0.5 % down spreading is supported. Modulation frequency range of 30 kHz to 33 kHz is supported.

[3] Informative; refer to Figure 6 for definition of differential voltage.

[4] Common-mode voltage is equal to V_{bias_RX}voltage.

[5] Total drive current of the input bias circuit when it is shorted to its ground.

[6] Minimum CDR tracking bandwidth at the receiver when the input is repetition of D10.2 symbols without scrambling.

V

D+

V

DIFF

V

DIFF_PRE

CM

V

D−

002aaf363

pre-emphasis = 20Log(V_{DIFF_PRE}/ V_DIFF

)

Fig 6. Definition of pre-emphasis and differential voltage

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Product data sheet

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21 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

12.4 DisplayPort AUX characteristics

Table 19. DisplayPort AUX characteristics

Symbol

UI

Parameter

Conditions

Min

Typ

Max

0.6

Unit

s

UI

V

[1]

[2]

[3]

[4]

unit interval

0.4

0.5

t_jit(cc)

cycle-to-cycle jitter time

transmitting device

receiving device

transmitting device

receiving device

informative

-

0.04

0.05

1.38

1.36

-

V_{AUX_DIFFp-p}

AUX differential peak-to-peak voltage

0.39

-

0.32

-

V

R_{AUX_TERM(DC)}AUX CH termination DC resistance

V_{AUX_DC_CM}AUX DC common-mode voltage

V_{AUX_TURN_CM}AUX turnaround common-mode voltage

-

100



[5]

[6]

[7]

[8]

0

-

2.0

V

0.3

V

I_{AUX_SHORT}

C_AUX

AUX short-circuit current limit

AUX AC coupling capacitor

-

90

mA

nF

75

200

[1] Results in the bit rate of 1 Mbit/s including the overhead of Manchester II coding.

[2] Maximum allowable UI variation within a single transaction at connector pins of a transmitting device. Equal to 24 ns maximum.

The transmitting device is a source device for a request transaction and a sink device for a reply transaction.

[3] Maximum allowable UI variation within a single transaction at connector pins of a receiving device. Equal to 30 ns maximum.

The transmitting device is a source device for a request transaction and a sink device for a reply transaction.

[4] V_{AUX_DIFFp-p}= 2  V_{AUX_P} V_{AUX_N}.

[5] Common-mode voltage is equal to V_{bias_TX}(or V_{bias_RX}) voltage.

[6] Steady-state common-mode voltage shift between transmit and receive modes of operation.

[7] Total drive current of the transmitter when it is shorted to its ground.

[8] The AUX channel AC-coupling capacitor placed both on the DisplayPort source and sink devices.

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Product data sheet

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PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

12.5 LVDS interface characteristics

Table 20. LVDS interface characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_o(dif)(p-p)

peak-to-peak differential

output voltage

R_L= 100 ;

CFG4 pin is open and LVDS interface

250

300

350

mV

control 2 register in default value

V_o(dif)

differential output voltage

variation

R_L= 100 ;

change in differential output voltage

-

50

mV

between complementary output states

V_cm

I_OS

I_OZ

common-mode voltage

output short-circuit current

OFF-state output current

R_L= 100 

1.125 1.2

1.375

24

V

-

mA

A

output 3-state circuit current;

R_L= 100 ; LVDS outputs are 3-stated;

receiver biasing at 1.2 V

20

t_r

rise time

fall time

R_L= 100 ; from 20 % to 80 %

R_L= 100 ; from 80 % to 20 %

-

390

50

ps

t_f

t_sk

skew time

intra-pair skew between differential

pairs

inter-pair skew between 2 adjacent

LVDS channels

-

200

ps

m

modulation index

for center spreading

minimum modulation depth

maximum modulation depth

center spreading

-

0

-

%

-

2.5

-

%

f_mod

modulation frequency

30

100

kHz

12.6 Control inputs and outputs

Table 21. Control input and output characteristics

Symbol Parameter Conditions

Signal output pins — PVCCEN, BKLTEN, HPDRX, PWMO

Min

Typ

Max

Unit

V_OH

V_OL

HIGH-level output voltage

LOW-level output voltage

I_OH= 2 mA

2.4

-

V

I_OL= 2 mA

0.4

Control input pins — RST_N, PD_N, TESTMODE, DEV_CFG, CFG[4:1]

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

0.7V_DD(3V3)

-

V

0.3V_DD(3V3)

Control input pin — EPS_N

V_IH

V_IL

HIGH-level input voltage

0.7V_DD(3V3)

-

V

LOW-level input voltage

0.2V_DD(3V3)

DDC_SDA, DDC_SCL, MS_SDA, MS_SCL^[1]

V_IH

V_IL

I_OL

HIGH-level input voltage

LOW-level input voltage

LOW-level output current

0.7V_DD(3V3)

-

5.25

V

-

0.3V_DD(3V3)

-

V

static output; V_OL= 0.4 V

3.0

mA

[1] For DDC_SCL, DDC_SDA, MS_SCL, MS_SDA characteristics, please refer to UM10204, “I²C-bus specification and user manual”

(Ref. 11).

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Product data sheet

Rev. 4 — 12 March 2014

23 of 32

PTN3460

NXP Semiconductors

eDP to LVDS bridge IC

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627ꢃꢄꢃꢅꢆ

02ꢅꢆꢆꢇ

Fig 7. Package outline SOT949-2 (HVQFN56)

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Product data sheet

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eDP to LVDS bridge IC

14. Packing information

Figure 8 is an example of the label that would be placed on the product shipment box and

the tape/reel.

002aag652

Fig 8. Packing label example

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

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Product data sheet

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15.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

15.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 9) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 22 and 23

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Product data sheet

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PTN3460

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Table 22. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

 350

220

< 2.5

235

220

 2.5

220

Table 23. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 9.

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 9. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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Product data sheet

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16. Abbreviations

Table 24. Abbreviations

Acronym

AIO

Description

All In One

AUX

BIOS

bpp

Auxiliary channel

Basic Input/Output System

bits per pixel

CDM

CDR

CPU

DDC

DP

Charged-Device Model

Clock Data Recovery

Central Processing Unit

Data Display Channel

DisplayPort

DPCD

EDID

eDP

EMI

DisplayPort Configuration Data

Extended Display Identification Data

embedded DisplayPort

ElectroMagnetic Interference

ElectroStatic Discharge

Graphics Processor Unit

Human Body Model

ESD

GPU

HBM

HBR

HPD

I/O

High Bit Rate (2.7 Gbit/s) of DisplayPort specification

Hot Plug Detect signal of DisplayPort or LVDS interface

Input/Output

I²C-bus

Inter-Integrated Circuit bus

Integrated Circuit

IC

LVDS

NVM

PCB

POR

PWM

RBR

RGB

ROM

Rx

Low-Voltage Differential Signaling

Non-Volatile Memory

Printed-Circuit Board

Power-On Reset

Pulse Width Modulation (or Modulator)

Reduced Bit Rate (1.62 Gbit/s) of DisplayPort specification

Red/Green/Blue

Read-Only Memory

Receive

SSC

TCON

Tx

Spread Spectrum Clock

Timing CONtroller

Transmit

UI

Unit Interval

VESA

Video Electronics Standards Association

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Product data sheet

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17. References

[1] UM10492, PTN3460 eDP to LVDS bridge IC application board user manual —

2011

[2] AN11088, PTN3460 system design and PCB layout guidelines — 2011

[3] AN11128, PTN3460 programming guide — 2011

[4] AN11133, PTN3460 FoA (Flash-over-AUX) utility user’s guide — 2011

[5] AN11134, PTN3460 DPCD utility user’s guide — 2011

[6] VESA DisplayPort standard — version 1, revision 1a; January 11, 2008

[7] VESA DisplayPort standard — version 1, revision 2; January 5, 2010

[8] VESA embedded DisplayPort standard — version 1.2; May 5, 2010

[9] VESA embedded DisplayPort standard — version 1.1, October 23, 2009

[10] ANSI/TIA/EIA-644-A-2001, Electrical characteristics of Low Voltage Differential

Signaling (LVDS) Interface Circuits — approved: January 30, 2001

[11] UM10204, I²C-bus specification and user manual — NXP Semiconductors

18. Revision history

Table 25. Revision history

Document ID

PTN3460 v.4

Modifications:

Release date

20140312

Data sheet status

Change notice

Supersedes

Product data sheet

-

PTN3460 v.3

• Section 8.3.3 “Panel power sequencing”, third paragraph, fourth bullet item changed

from “... the BKLTEN and PVCCEN pins are set to LOW.”

to “... the BKLTEN pin is set to LOW.”

PTN3460 v.3

PTN3460 v.2

PTN3460 v.1

20140213

20130320

20120109

Product data sheet

-

PTN3460 v.2

PTN3460 v.1

-

PTN3460

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Rev. 4 — 12 March 2014

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PTN3460

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

19.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Product data sheet

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PTN3460

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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Product data sheet

Rev. 4 — 12 March 2014

31 of 32

PTN3460

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eDP to LVDS bridge IC

21. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

15.2

15.3

15.4

Wave and reflow soldering. . . . . . . . . . . . . . . 26

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 26

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 26

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Device features. . . . . . . . . . . . . . . . . . . . . . . . . 1

DisplayPort receiver features . . . . . . . . . . . . . . 2

LVDS transmitter features. . . . . . . . . . . . . . . . . 2

Control and system features. . . . . . . . . . . . . . . 2

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1

2.2

2.3

2.4

2.5

16

17

18

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 28

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . 29

19

Legal information . . . . . . . . . . . . . . . . . . . . . . 30

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3

4

5

6

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

System context diagram . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

19.1

19.2

19.3

19.4

20

21

Contact information . . . . . . . . . . . . . . . . . . . . 31

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

8

8.1

8.1.1

8.1.2

8.2

Functional description . . . . . . . . . . . . . . . . . . . 8

DisplayPort receiver . . . . . . . . . . . . . . . . . . . . . 8

DP Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DPCD registers. . . . . . . . . . . . . . . . . . . . . . . . . 9

LVDS transmitter. . . . . . . . . . . . . . . . . . . . . . . 10

System control and operation. . . . . . . . . . . . . 13

Reset, power-down and

8.3

8.3.1

power-on initialization. . . . . . . . . . . . . . . . . . . 13

LVDS panel control. . . . . . . . . . . . . . . . . . . . . 14

Panel power sequencing . . . . . . . . . . . . . . . . 15

Termination resistors . . . . . . . . . . . . . . . . . . . 16

Reference clock input. . . . . . . . . . . . . . . . . . . 16

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power management . . . . . . . . . . . . . . . . . . . . 16

Register interface —

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

8.3.7

8.3.8

control and programmability . . . . . . . . . . . . . . 16

EDID handling . . . . . . . . . . . . . . . . . . . . . . . . 16

8.3.9

9

Application design-in information . . . . . . . . . 17

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19

Recommended operating conditions. . . . . . . 19

10

11

12

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 20

Device characteristics. . . . . . . . . . . . . . . . . . . 20

Power consumption . . . . . . . . . . . . . . . . . . . . 20

DisplayPort receiver characteristics . . . . . . . . 21

DisplayPort AUX characteristics. . . . . . . . . . . 22

LVDS interface characteristics . . . . . . . . . . . . 23

Control inputs and outputs . . . . . . . . . . . . . . . 23

12.1

12.2

12.3

12.4

12.5

12.6

13

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24

Packing information . . . . . . . . . . . . . . . . . . . . 25

Soldering of SMD packages . . . . . . . . . . . . . . 25

Introduction to soldering . . . . . . . . . . . . . . . . . 25

14

15

15.1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 March 2014

Document identifier: PTN3460


型号：	PTN3460BS/F1,518
厂家：	NXP
描述：	PTN3460 - eDP to LVDS bridge IC QFN 56-Pin
文件：	总32页 (文件大小：442K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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