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PUMD3,165 [NXP]

PEMD3; PIMD3; PUMD3 - NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ TSSOP 6-Pin;
PUMD3,165
型号： PUMD3,165
厂家： NXP    NXP
描述：

PEMD3; PIMD3; PUMD3 - NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ TSSOP 6-Pin

开关 光电二极管 晶体管
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PEMD3; PIMD3; PUMD3  
NPN/PNP resistor-equipped transistors;  
R1 = 10 kΩ, R2 = 10 kΩ  
Rev. 10 — 15 November 2009  
Product data sheet  
1. Product profile  
1.1 General description  
NPN/PNP Resistor-Equipped Transistors (RET).  
Table 1. Product overview  
Type number  
Package  
NXP  
PNP/PNP  
complement  
NPN/NPN  
complement  
JEITA  
-
PEMD3  
PIMD3  
PUMD3  
SOT666  
SOT457  
SOT363  
PEMB11  
-
PEMH11  
-
SC-74  
SC-88  
PUMB11  
PUMH11  
1.2 Features  
„ Built-in bias resistors  
„ Simplifies circuit design  
„ Reduces component count  
„ Reduces pick and place costs  
1.3 Applications  
„ Low current peripheral driver  
„ Control of IC inputs  
„ Replaces general-purpose transistors in digital applications  
1.4 Quick reference data  
Table 2.  
Symbol  
VCEO  
IO  
Quick reference data  
Parameter  
Conditions  
Min  
Typ  
Max  
50  
Unit  
V
collector-emitter voltage  
output current (DC)  
bias resistor 1 (input)  
bias resistor ratio  
open base  
-
-
-
-
100  
13  
mA  
kΩ  
R1  
7
10  
1
R2/R1  
0.8  
1.2  
 
 
 
 
 
PEMD3; PIMD3; PUMD3  
NXP Semiconductors  
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ  
2. Pinning information  
Table 3.  
Pinning  
Pin  
1
Description  
Simplified outline  
Symbol  
GND (emitter) TR1  
input (base) TR1  
output (collector) TR2  
GND (emitter) TR2  
input (base) TR2  
output (collector) TR1  
6
5
4
6
5
4
2
3
R1  
R2  
4
TR2  
5
TR1  
1
2
3
6
001aab555  
R2  
R1  
1
2
3
006aaa143  
3. Ordering information  
Table 4.  
Ordering information  
Type number Package  
Name  
Description  
Version  
SOT666  
SOT457  
SOT363  
PEMD3  
PIMD3  
PUMD3  
-
plastic surface mounted package; 6 leads  
plastic surface mounted package; 6 leads  
plastic surface mounted package; 6 leads  
SC-74  
SC-88  
4. Marking  
Table 5.  
Marking codes  
Type number  
PEMD3  
Marking code[1]  
D3  
PIMD3  
M7  
D*3  
PUMD3  
[1] * = -: made in Hong Kong  
* = p: made in Hong Kong  
* = t: made in Malaysia  
* = W: made in China  
PEMD3_PIMD3_PUMD3_10  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 10 — 15 November 2009  
2 of 11  
 
 
 
 
PEMD3; PIMD3; PUMD3  
NXP Semiconductors  
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ  
5. Limiting values  
Table 6.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
Per transistor; for the PNP transistor with negative polarity  
VCBO  
VCEO  
VEBO  
VI  
collector-base voltage  
collector-emitter voltage  
emitter-base voltage  
input voltage TR1  
positive  
open emitter  
open base  
-
-
-
50  
50  
10  
V
V
V
open collector  
-
-
+40  
V
V
negative  
−10  
input voltage TR2  
positive  
-
-
-
-
+10  
−40  
100  
100  
V
negative  
V
IO  
output current (DC)  
peak collector current  
total power dissipation  
SOT363  
mA  
mA  
ICM  
Ptot  
Tamb ≤ 25 °C  
[1]  
[2]  
-
200  
mW  
mW  
mW  
°C  
SOT457  
-
300  
[1][3]  
SOT666  
-
200  
Tstg  
storage temperature  
junction temperature  
ambient temperature  
−65  
-
+150  
150  
Tj  
°C  
Tamb  
−65  
+150  
°C  
Per device  
Ptot  
total power dissipation  
SOT363  
Tamb ≤ 25 °C  
[1]  
[2]  
-
-
-
300  
600  
300  
mW  
mW  
mW  
SOT457  
[1][3]  
SOT666  
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard  
footprint.  
[2] Device mounted on an FR4 PCB with 65 μm copper strip line, standard footprint.  
[3] Reflow soldering is the only recommended soldering method.  
PEMD3_PIMD3_PUMD3_10  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 10 — 15 November 2009  
3 of 11  
 
 
 
 
PEMD3; PIMD3; PUMD3  
NXP Semiconductors  
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ  
6. Thermal characteristics  
Table 7.  
Thermal characteristics  
Symbol Parameter  
Per transistor  
Conditions  
Min  
Typ  
Max  
Unit  
Rth(j-a)  
thermal resistance from in free air  
junction to ambient  
[1]  
[2]  
SOT363  
SOT457  
SOT666  
-
-
-
-
-
-
625  
417  
625  
K/W  
K/W  
K/W  
[1][3]  
Per device  
Rth(j-a)  
thermal resistance from in free air  
junction to ambient  
[1]  
[2]  
SOT363  
SOT457  
SOT666  
-
-
-
-
-
-
416  
208  
416  
K/W  
K/W  
K/W  
[1][3]  
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.  
[2] Device mounted on an FR4 PCB with 65 μm copper strip line, standard footprint.  
[3] Reflow soldering is the only recommended soldering method.  
7. Characteristics  
Table 8.  
Characteristics  
Tamb = 25 °C unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Per transistor; for the PNP transistor with negative polarity  
ICBO  
collector-base cut-off VCB = 50 V; IE = 0 A  
current  
-
-
100  
nA  
ICEO  
collector-emitter  
cut-off current  
VCE = 30 V; IB = 0 A  
-
-
-
-
1
μA  
μA  
VCE = 30 V; IB = 0 A;  
50  
Tj = 150 °C  
IEBO  
emitter-base cut-off  
current  
VEB = 5 V; IC = 0 A  
-
-
400  
μA  
hFE  
DC current gain  
VCE = 5 V; IC = 5 mA  
30  
-
-
-
-
VCEsat  
collector-emitter  
IC = 10 mA; IB = 0.5 mA  
150  
mV  
saturation voltage  
VI(off)  
VI(on)  
R1  
off-state input voltage VCE = 5 V; IC = 100 μA  
on-state input voltage VCE = 0.3 V; IC = 10 mA  
bias resistor 1 (input)  
-
1.1  
1.8  
10  
1
0.8  
-
V
2.5  
7
V
13  
1.2  
-
kΩ  
R2/R1  
Cc  
bias resistor ratio  
0.8  
-
collector capacitance VCB = 10 V; IE = ie = 0 A;  
f = 1 MHz  
-
TR1 (NPN)  
TR2 (PNP)  
-
-
-
-
2.5  
3
pF  
pF  
PEMD3_PIMD3_PUMD3_10  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 10 — 15 November 2009  
4 of 11  
 
 
 
 
 
PEMD3; PIMD3; PUMD3  
NXP Semiconductors  
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ  
006aaa034  
006aaa035  
3
10  
1
(1)  
(2)  
(3)  
h
FE  
V
CEsat  
(V)  
2
10  
(1)  
(2)  
(3)  
−1  
10  
10  
−2  
1
10  
10  
−1  
2
2
1
10  
10  
1
10  
10  
I
(mA)  
I (mA)  
C
C
VCE = 5 V  
IC/IB = 20  
(1) Tamb = 150 °C  
(2) Tamb = 25 °C  
(3) Tamb = −40 °C  
(1) Tamb = 100 °C  
(2) Tamb = 25 °C  
(3) Tamb = −40 °C  
Fig 1. TR1 (NPN): DC current gain as a function of  
collector current; typical values  
Fig 2. TR1 (NPN): Collector-emitter voltage as a  
function of collector current; typical values  
006aaa036  
006aaa037  
10  
10  
V
I(on)  
V
I(off)  
(V)  
(V)  
(1)  
(2)  
(1)  
(2)  
(3)  
1
1
(3)  
−1  
10  
−1  
10  
10  
10  
−1  
2
−2  
−1  
10  
1
10  
10  
1
10  
I
(mA)  
I (mA)  
C
C
VCE = 0.3 V  
VCE = 5 V  
(1) Tamb = −40 °C  
(2) Tamb = 25 °C  
(3) Tamb = 100 °C  
(1) Tamb = −40 °C  
(2) Tamb = 25 °C  
(3) Tamb = 100 °C  
Fig 3. TR1 (NPN): On-state input voltage as a  
function of collector current; typical values  
Fig 4. TR1 (NPN): Off-state input voltage as a  
function of collector current; typical values  
PEMD3_PIMD3_PUMD3_10  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 10 — 15 November 2009  
5 of 11  
PEMD3; PIMD3; PUMD3  
NXP Semiconductors  
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ  
006aaa046  
006aaa047  
3
−10  
−1  
h
FE  
V
CEsat  
(V)  
(1)  
(3)  
2
−10  
(2)  
−1  
−10  
(1)  
(3)  
(2)  
−10  
−1  
−2  
−1  
−10  
−1  
2
2
−10  
−1  
−10  
−10  
−10  
−10  
I
(mA)  
I (mA)  
C
C
VCE = −5 V  
IC/IB = 20  
(1) Tamb = 150 °C  
(2) Tamb = 25 °C  
(3) Tamb = −40 °C  
(1) Tamb = 100 °C  
(2) Tamb = 25 °C  
(3) Tamb = −40 °C  
Fig 5. TR2 (PNP): DC current gain as a function of  
collector current; typical values  
Fig 6. TR2 (PNP): Collector-emitter voltage as a  
function of collector current; typical values  
006aaa049  
006aaa048  
2
−10  
−10  
V
I(on)  
(V)  
V
I(off)  
(V)  
−10  
(1)  
(2)  
(3)  
−1  
(2)  
(1)  
(3)  
−1  
−1  
−1  
−10  
−10  
−10  
−2  
−1  
−1  
2
−10  
−1  
−10  
−10  
−1  
−10  
−10  
I
C
(mA)  
I
(mA)  
C
VCE = −0.3 V  
VCE = −5 V  
(1) Tamb = −40 °C  
(2) Tamb = 25 °C  
(3) Tamb = 100 °C  
(1) Tamb = −40 °C  
(2) Tamb = 25 °C  
(3) Tamb = 100 °C  
Fig 7. TR2 (PNP): On-state input voltage as a  
function of collector current; typical values  
Fig 8. TR2 (PNP): Off-state input voltage as a  
function of collector current; typical values  
PEMD3_PIMD3_PUMD3_10  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 10 — 15 November 2009  
6 of 11  
PEMD3; PIMD3; PUMD3  
NXP Semiconductors  
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ  
8. Package outline  
2.2  
1.8  
1.1  
0.8  
3.1  
2.7  
1.1  
0.9  
0.45  
0.15  
6
5
4
6
5
4
0.6  
0.2  
2.2 1.35  
2.0 1.15  
3.0 1.7  
2.5 1.3  
pin 1  
index  
pin 1 index  
1
2
3
1
2
3
0.25  
0.10  
0.3  
0.2  
0.26  
0.10  
0.40  
0.25  
0.65  
0.95  
1.3  
1.9  
Dimensions in mm  
06-03-16  
Dimensions in mm  
04-11-08  
Fig 9. Package outline SOT363 (SC-88)  
Fig 10. Package outline SOT457 (SC-74)  
1.7  
1.5  
0.6  
0.5  
6
5
4
0.3  
0.1  
1.7 1.3  
1.5 1.1  
pin 1 index  
1
2
3
0.18  
0.08  
0.27  
0.17  
0.5  
1
Dimensions in mm  
04-11-08  
Fig 11. Package outline SOT666  
PEMD3_PIMD3_PUMD3_10  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 10 — 15 November 2009  
7 of 11  
 
 
PEMD3; PIMD3; PUMD3  
NXP Semiconductors  
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ  
9. Packing information  
Table 9.  
Packing methods  
The indicated -xxx are the last three digits of the 12NC ordering code.[1]  
Type number Package Description Packing quantity  
3000 4000 8000 10000  
PEMD3  
PIMD3  
PUMD3  
SOT666 2 mm pitch, 8 mm tape and reel  
-
-
-315  
-
4 mm pitch, 8 mm tape and reel  
SOT457 4 mm pitch, 8 mm tape and reel; T1  
4 mm pitch, 8 mm tape and reel; T2  
-
-115  
-
-
-
-
-
-
[2]  
[3]  
[2]  
[3]  
-115  
-125  
-115  
-125  
-
-
-
-
-135  
-165  
-135  
-165  
SOT363 4 mm pitch, 8 mm tape and reel; T1  
4 mm pitch, 8 mm tape and reel; T2  
[1] For further information and the availability of packing methods, see Section 12.  
[2] T1: normal taping  
[3] T2: reverse taping  
PEMD3_PIMD3_PUMD3_10  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 10 — 15 November 2009  
8 of 11  
 
 
 
 
PEMD3; PIMD3; PUMD3  
NXP Semiconductors  
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ  
10. Revision history  
Table 10. Revision history  
Document ID  
Release date  
Data sheet status  
Change notice Supersedes  
- PEMD3_PIMD3_ PUMD3_9  
PEMD3_PIMD3_ PUMD3_10 20091115  
Product data sheet  
Modifications:  
• This data sheet was changed to reflect the new company name NXP Semiconductors,  
including new legal definitions and disclaimers. No changes were made to the technical  
content.  
• Figure 9 “Package outline SOT363 (SC-88)”: updated  
PEMD3_PIMD3_ PUMD3_9 20050518  
Product data sheet  
-
PEMD3_PIMD3_ PUMD3_8  
PEMD3_PUMD3_7  
PEMD3_PIMD3_ PUMD3_8 20041206  
Product data sheet  
-
PEMD3_PIMD3_PUMD3_10  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 10 — 15 November 2009  
9 of 11  
 
PEMD3; PIMD3; PUMD3  
NXP Semiconductors  
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ  
11. Legal information  
11.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
11.2 Definitions  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
11.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
11.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
12. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
PEMD3_PIMD3_PUMD3_10  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 10 — 15 November 2009  
10 of 11  
 
 
 
 
 
 
PEMD3; PIMD3; PUMD3  
NXP Semiconductors  
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ  
13. Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
General description . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data . . . . . . . . . . . . . . . . . . . . 1  
1.1  
1.2  
1.3  
1.4  
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Thermal characteristics . . . . . . . . . . . . . . . . . . 4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Packing information . . . . . . . . . . . . . . . . . . . . . 8  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9  
3
4
5
6
7
8
9
10  
11  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 10  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
11.1  
11.2  
11.3  
11.4  
12  
13  
Contact information. . . . . . . . . . . . . . . . . . . . . 10  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2009.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 15 November 2009  
Document identifier: PEMD3_PIMD3_PUMD3_10  
 

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