PX1041A-EL1/G [NXP]
IC DATACOM, INTERFACE CIRCUIT, PBGA208, 15 X 15 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, MO-205, SOT631-4, LFBGA-208, Network Interface;型号: | PX1041A-EL1/G |
厂家: | NXP |
描述: | IC DATACOM, INTERFACE CIRCUIT, PBGA208, 15 X 15 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, MO-205, SOT631-4, LFBGA-208, Network Interface 电信 电信集成电路 |
文件: | 总36页 (文件大小:180K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PX1041A
PCI Express stand-alone X4 PHY
Rev. 01 — 21 June 2007
Objective data sheet
1. General description
The PX1041A is a high-performance, low-power, four-lane PCI Express electrical
PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The
PX1041A PCI Express PHY is compliant to the PCI Express Base Specification,
Rev. 1.0a, and Rev. 1.1. The PX1041A includes features such as Clock and Data
Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers,
elastic buffer and receiver detection, and provides superior performance to the Media
Access Control (MAC) layer devices.
The PX1041A is a 2.5 Gbit/s PCI Express PHY with 4 × 8-bit data PXPIPE interface. Its
PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE)
specification, enhanced and adapted for off-chip applications with the introduction of a
source synchronous clock for transmit and receive data. The 4 × 8-bit data interface
operates at 250 MHz with SSTL Class I signaling at 2.5 V or 1.8 V. The SSTL signaling is
compatible with the I/O interfaces available in FPGA products.
The PX1041A PCI Express PHY supports advanced power management functions. The
PX1041AI is for the industrial temperature range (−40 °C to +85 °C).
2. Features
2.1 PCI Express interface
I Compliant to PCI Express Base Specification 1.0a and 1.1
I Four PCI Express 2.5 Gbit/s lane
I Data and clock recovery from serial stream
I Serializer and De-serializer (SerDes)
I Receiver detection
I 8b/10b coding and decoding, elastic buffer and word alignment
I Supports direct disparity control for use in transmitting compliance pattern
I Supports lane polarity inversion
I Low jitter and Bit Error Rate (BER)
I Supports PCI Express-side parallel loopback
I Supports PXPIPE-side parallel loopback
I Supports receiver lane-to-lane deskew (optional)
I Supports lane reversal (optional)
2.2 PHY/MAC interface
I Based on Intel PHY Interface for PCI Express architecture v2.0 (PIPE)
I Adapted for off-chip with additional synchronous clock signals (PXPIPE)
PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
I PIPE mode selectable
I 4 × 8-bit parallel data interface for transmit and receive at 250 MHz
I SSTL Class I signaling at 2.5 V or 1.8 V, without select pin
2.3 JTAG interface
I JTAG (IEEE 1149.1) boundary scan interface
I Built-In Self Test (BIST) controller tests SerDes and I/O blocks at speed
I 3.3 V CMOS signaling
2.4 Power management
I Dissipates < 1 W in L0 normal mode
I Support power management of L0, L0s, L1, and L2
2.5 Clock
I 100 MHz external reference clock with ±300 ppm tolerance
I Supports spread spectrum clock to reduce EMI
I On-chip reference clock termination
2.6 Miscellaneous
I LFBGA208 lead free package
I Operating ambient temperature
N PX1041A for commercial range: 0 °C to +70 °C
N PX1041AI for industrial range: −40 °C to +85 °C
I ESD protection voltage for Human Body Model (HBM): 2000 V
3. Quick reference data
Table 1.
Symbol Parameter
VDDD1 digital supply voltage 1
VDDD2
Quick reference data
Conditions
for JTAG I/O
for SSTL_18 I/O
for SSTL_2 I/O
for core
Min
3.0
Typ
3.3
1.8
2.5
1.2
1.2
Max
3.6
Unit
V
[1]
[1]
digital supply voltage 2
1.7
1.9
V
2.3
2.7
V
VDDD3
VDD
digital supply voltage 3
supply voltage
1.15
1.15
1.25
1.25
V
for high-speed
V
serial I/O and PVT
VDDA1
VDDA2
fclk(ref)
Tamb
analog supply voltage 1
analog supply voltage 2
reference clock frequency
ambient temperature
for serializer
for serializer
1.15
3.0
1.2
3.3
100
1.25
3.6
V
V
99.97
100.03 MHz
operating
commercial
industrial
0
-
-
+70
+85
°C
°C
−40
[1] No select pin needed.
PX1041A_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 21 June 2007
2 of 36
PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
4. Ordering information
Table 2.
Ordering information
Solder process
Type number
Package
Name
Description
Version
PX1041A-EL1/G Pb-free (SnAgCu
solder ball compound)
LFBGA208 plastic low profile fine-pitch ball grid array package; SOT631-4
208 balls; body 15 × 15 × 1 mm
PX1041AI-EL1/G Pb-free (SnAgCu
solder ball compound)
LFBGA208 plastic low profile fine-pitch ball grid array package; SOT631-4
208 balls; body 15 × 15 × 1 mm
5. Marking
Table 3.
Line
A
Lead-free package marking
Marking
Description
PX1041A-EL1/G
PX1041AI-EL1/G[1]
xxxxxxx
full basic type number
B
C
diffusion lot number
manufacturing code:
2 = diffusion site
P = assembly site
G = lead-free
2PGyyww
yy = year code
ww = week code
[1] Industrial temperature range.
PX1041A_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 21 June 2007
3 of 36
PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
6. Block diagram
PCI Express MAC
Ln_TxData0
Ln_TxData1
REGISTER
8
PCI Express PHY
10b/8b
DECODE
LANE 0
8b/10b
ENCODE
ELASTIC
BUFFER
PARALLEL
TO
10
SERIAL
K28.5
DETECTION
SERIAL
TO
LANE 1
LANE 2
LANE 3
PARALLEL
250 MHz
clock
DATA
RECOVERY
CIRCUIT
CLOCK RECOVERY
CIRCUIT PLL
TX I/O
RX I/O
bit stream at 2.5 Gbit/s
CLK
GENERATOR
REFCLK I/O
002aac432
Fig 1. Block diagram of PX1041A
PX1041A_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 21 June 2007
4 of 36
PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
7. Pinning information
7.1 Pinning
ball A1
index area
2
4
6
8
10 12 14 16
9 11 13 15 17
1
3
5
7
A
B
C
D
E
F
G
H
J
K
L
PX1041A-EL1/G
PX1041AI-EL1/G
M
N
P
R
T
U
002aac433
Transparent top view
Fig 2. Pin configuration for LFBGA208
PX1041A_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 21 June 2007
5 of 36
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
L0_
RXDATA7
L0_
RXDATA5
L0_
RXDATA4
L0_
RXDATA2
L0_
RXDATA0
L0_
TXDATA7
L0_
TXDATA5
L0_
TXDATA4
L0_
TXDATA2
L1_
RXDATA7
L1_
RXDATA6
REFCLK_P
A
B
C
D
E
F
TMS
TDI
RESET_N
RXCLK
TXCLK
L0_
RXDATA6
L0_
RXDATA3
L0_
RXDATA1
L0_
TXDATA6
L0_
TXDATA3
L0_
TXDATA1
DESKEW_
START
L1_
RXDATA5
REFCLK_N
TRST_N
TCK
TDO
PVT
V
SS
V
SS
V
SS
V
SS
PWRDWN1
V
SS
L0_
L0_
L0_
L0_
L0_
RXPOL
L0_
TXCOMP
L0_
TXDATAK
L0_
TXIDLE
L0_
TXDATA0
DESKEW_
VALID
L1_
RXDATAK
L1_
RXDATA4
V
SS
V
DDD1
PIPELOOPB PWRDWN0
RXDATAK RXSTATUS1 RXSTATUS0 RXVALID
L0_
RXIDLE
L0_
RXSTATUS2
ENCODING PIPEMODE
L1_
RXIDLE
L1_
RXDATA3
L0_RX_P
L0_RX_N
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDD2
V
DDD2
V
V
DDD2
V
DDD2
V
SS
PHYSTATUS
SS
EN
SEL
LANE
REVERSAL
RXDET_
LOOPB
L1_
RXDATA2
V
SS
V
DDA2
V
SS
L1_
L1_
L1_
L1_
RXDATA0
V
SS
L0_TX_P
L0_TX_N
V
DD
V
DD
V
DD
RXVALID RXSTATUS2 RXDATA1
L1_
L1_
TXDATA7
L1_RX_P
L1_RX_N
G
H
J
V
V
V
V
V
SS
DDD2
DDD2
DDD2
RXSTATUS1
L1_
L1_
L1_
TXDATA6
V
SS
RXSTATUS0 TXDATA5
L1_
RXPOL
L1_
TXDATA3
L1_
TXDATA4
V
SS
L1_TX_P
L1_TX_N
V
DDA1
DDA1
DDA1
DDA1
DDA1
L1_
TXDATAK
L1_
TXDATA2
L2_RX_P
L2_RX_N
K
L
V
V
V
V
V
SS
DDD2
L1_
TXCOMP
L1_
TXIDLE
L1_
TXDATA1
L1_
TXDATA0
V
SS
L2_
RXVALID
L2_
RXIDLE
L2_
RXDATAK
L2_
RXDATA7
V
SS
M
N
P
R
T
L2_TX_P
L2_TX_N
L2_
RXPOL
L2_
RXSTATUS2
L2_
RXDATA6
L3_RX_P
L3_RX_N
V
SS
L2_
L2_
L2_
RXDATA5
L3_
TXCOMP
L3_
RXPOL
L2_
TXCOMP
V
SS
V
SS
V
DDD3
V
DDD3
V
SS
V
DDD2
V
DDD2
V
DDD2
V
SS
RXSTATUS1 RXDATA4
L2_ L2_
TXDATA4 RXSTATUS0 RXDATA2
L3_
TXDATA0
L3_
TXIDLE
L3_
TXDATAK
L3_
L3_
L3_
L3_
L3_
L3_
RXIDLE
L2_
TXDATAK
L2_
TXIDLE
L2_
L2_
RXDATA3
V
SS
RXVALID RXSTATUS0 RXSTATUS1 RXSTATUS2 RXDATAK
L3_
TXDATA1
L3_
TXDATA4
L3_
TXDATA6
L3_
RXDATA2
L3_
RXDATA3
L3_
RXDATA6
L2_
TXDATA1
L2_
TXDATA3
L2_
TXDATA6
L2_
RXDATA1
V
SS
L3_TX_P
L3_TX_N
V
SS
V
SS
V
SS
V
SS
L3_
TXDATA2
L3_
TXDATA3
L3_
TXDATA5
L3_
TXDATA7
L3_
RXDATA0
L3_
RXDATA1
L3_
RXDATA4
L3_
RXDATA5
L3_
RXDATA7
L2_
TXDATA0
L2_
TXDATA2
L2_
TXDATA5
L2_
TXDATA7
L2_
RXDATA0
U
VREFS
002aac434
Transparent top view.
Fig 3. Ball mapping
PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
7.2 Pin description
The PHY input and output pins are described in Table 4 to Table 11. Note that input and
output is defined from the perspective of the PHY. Thus a signal on a pin described as an
output is driven by the PHY and a signal on a pin described as an input is received by the
PHY. A basic description of each pin is provided.
Signals named Lx_*, designate the per-lane signal where x = (0 to 3). For example,
Lx_RX_P expands to the following signals L0_RX_P, L1_RX_P, L2_RX_P and L3_RX_P.
All SSTL signaling is 2.5 V or 1.8 V selectable.
Table 4.
PCI Express serial data lines
Symbol
Pin
D1
E1
F3
G3
G1
H1
J3
Type
input
Signaling
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
PCIe I/O
Description
L0_RX_P
L0_RX_N
L0_TX_P
L0_TX_N
L1_RX_P
L1_RX_N
L1_TX_P
L1_TX_N
L2_RX_P
L2_RX_N
L2_TX_P
L2_TX_N
L3_RX_P
L3_RX_N
L3_TX_P
L3_TX_N
lane 0 differential input receive pair
with 50 Ω on-chip termination[1]
input
output
output
input
lane 0 differential output transmit pair
with 50 Ω on-chip termination[1]
lane 1 differential input receive pair
with 50 Ω on-chip termination
input
output
output
input
lane 1 differential output transmit pair
with 50 Ω on-chip termination
K3
K1
L1
lane 2 differential input receive pair
with 50 Ω on-chip termination
input
M3
N3
N1
P1
T1
U1
output
output
input
lane 2 differential output transmit pair
with 50 Ω on-chip termination
lane 3 differential input receive pair
with 50 Ω on-chip termination
input
output
output
lane 3 differential output transmit pair
with 50 Ω on-chip termination
[1] As PCIe specification defined.
Table 5.
Symbol
PXPIPE interface transmit data signals
Pin
Type
Signaling
Description
L0_TXDATA[7:0] A9, B9, A10,
A11, B11,
input
SSTL
8-bit transmit data input from the MAC
to the PHY lane 0
A12, B12, C12
L0_TXDATAK
C10
input
input
input
SSTL
SSTL
SSTL
selection input for the symbols of
transmit data at lane 0;
LOW = data byte; HIGH = control byte
L1_TXDATA[7:0] G17, H17,
H16, J17, J16,
8-bit transmit data input from the MAC
to the PHY lane 1
K17, L16, L17
L1_TXDATAK
K15
selection input for the symbols of
transmit data at lane 1;
LOW = data byte; HIGH = control byte
PX1041A_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 21 June 2007
7 of 36
PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
Table 5.
Symbol
PXPIPE interface transmit data signals …continued
Pin
Type
Signaling
Description
L2_TXDATA[7:0] U16, T15,
U15, R14,
input
SSTL
8-bit transmit data input from the MAC
to the PHY lane 2
T14, U13,
T12, U12
L2_TXDATAK
R12
input
input
input
SSTL
SSTL
SSTL
selection input for the symbols of
transmit data at lane 2;
LOW = data byte; HIGH = control byte
L3_TXDATA[7:0] U6, T6, U5,
T5, U4, U3,
8-bit transmit data input from the MAC
to the PHY lane 3
T3, R3
L3_TXDATAK
R5
selection input for the symbols of
transmit data at lane 3;
LOW = data byte; HIGH = control byte
Table 6.
Symbol
PXPIPE interface receive data signals
Pin
Type
Signaling
Description
L0_RXDATA[7:0] A4, B5, A5,
A6, B6, A7,
output
SSTL
8-bit receive data output from the PHY
lane 0 to the MAC
B8, A8
L0_RXDATAK
C4
output
output
SSTL
SSTL
selection output for the symbols of
receive data at lane 0;
LOW = data byte; HIGH = control byte
L1_RXDATA[7:0] A16, A17,
B17, C17,
8-bit receive data output from the PHY
lane 1 to the MAC
D17, E17,
F16, F17
L1_RXDATAK
C16
output
output
SSTL
SSTL
selection output for the symbols of
receive data at lane 1;
LOW = data byte; HIGH = control byte
L2_RXDATA[7:0] M17, N17,
P17, P16,
8-bit receive data output from the PHY
lane 2 to the MAC
R17, R16,
T17, U17
L2_RXDATAK
M16
output
output
output
SSTL
SSTL
SSTL
selection output for the symbols of
receive data at lane 2;
LOW = data byte; HIGH = control byte
L3_RXDATA[7:0] U11, T11,
U10, U9, T9,
8-bit receive data output from the PHY
lane 3 to the MAC
T8, U8, U7
L3_RXDATAK
R10
selection output for the symbols of
receive data at lane 3;
LOW = data byte; HIGH = control byte
PX1041A_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 21 June 2007
8 of 36
PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
Table 7.
PXPIPE interface command signals
Symbol
Pin
Type
Signaling
Description
L0_TXIDLE
C11 input
SSTL
forces lane 0 TX output to electrical idle (see
Table 13)
L1_TXIDLE
L2_TXIDLE
L3_TXIDLE
L0_TXCOMP
L15
input
SSTL
SSTL
SSTL
SSTL
forces lane 1 TX output to electrical idle (see
Table 13)
R13 input
forces lane 2 TX output to electrical idle (see
Table 13)
R4
C9
input
input
forces lane 3 TX output to electrical idle (see
Table 13)
used when transmitting the compliance
pattern at lane 0; HIGH-level sets the running
disparity to negative
L1_TXCOMP
L2_TXCOMP
L3_TXCOMP
L0_RXPOL
L14
P13
P4
input
input
input
input
SSTL
SSTL
SSTL
SSTL
used when transmitting the compliance
pattern at lane 1; HIGH-level sets the running
disparity to negative
used when transmitting the compliance
pattern at lane 2; HIGH-level sets the running
disparity to negative
used when transmitting the compliance
pattern at lane 3; HIGH-level sets the running
disparity to negative
C8
signals the PHY to perform a polarity
inversion on the receive data at lane 0;
LOW = PHY does no polarity inversion;
HIGH = PHY does polarity inversion
L1_RXPOL
L2_RXPOL
L3_RXPOL
J15
input
SSTL
SSTL
SSTL
signals the PHY to perform a polarity
inversion on the receive data at lane 1;
LOW = PHY does no polarity inversion;
HIGH = PHY does polarity inversion
N14 input
signals the PHY to perform a polarity
inversion on the receive data at lane 2;
LOW = PHY does no polarity inversion;
HIGH = PHY does polarity inversion
P5
input
signals the PHY to perform a polarity
inversion on the receive data at lane 3;
LOW = PHY does no polarity inversion;
HIGH = PHY does polarity inversion
RESET_N
A13
E15
input
input
SSTL
SSTL
PHY reset input; active LOW
RXDET_ LOOPB
instructs the PHY to begin a receiver
detection operation or to begin loopback;
LOW = reset state
PWRDWN0
PWRDWN1
C14 input
SSTL
SSTL
SSTL
transceiver power-up and power-down inputs
(see Table 12); 0x2 = reset state
B14
input
input
DESKEW_ START B15
signals the PHY to start a lane to lane
deskew (see Table 15); LOW = reset state
LANEREVERS E14
input
SSTL
signals the PHY to perform lane reversal
(see Table 15), LOW = reset state
PX1041A_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 21 June 2007
9 of 36
PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
Table 7.
PXPIPE interface command signals …continued
Symbol
Pin
Type
Signaling
Description
PIPELOOPB
C13 input
D13 input
D12 input
SSTL
signals the PHY to do loopback at PXPIPE
side (see Table 15), LOW = reset state
PIPESEL
SSTL
SSTL
signals the PHY to switch from PXPIPE to
PIPE interface, LOW = reset state
ENCODEN
enable the internal encoder to replace
side-band signals to perform selected
functions (see Table 15)
Table 8.
PXPIPE interface status signals
Symbol
Pin
Type
Signaling
Description
L0_RXVALID
C7
output
SSTL
indicates symbol lock and valid data on
RX_DATA and RX_DATAK at lane 0
L1_RXVALID
L2_RXVALID
L3_RXVALID
L0_RXIDLE
L1_RXIDLE
L2_RXIDLE
L3_RXIDLE
F14
output
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
indicates symbol lock and valid data on
RX_DATA and RX_DATAK at lane 1
M14 output
indicates symbol lock and valid data on
RX_DATA and RX_DATAK at lane 2
R6
D4
output
output
indicates symbol lock and valid data on
RX_DATA and RX_DATAK at lane 3
indicates receiver detection of an electrical
idle at lane 0; this is an asynchronous signal
D16 output
M15 output
R11 output
indicates receiver detection of an electrical
idle at lane 1; this is an asynchronous signal
indicates receiver detection of an electrical
idle at lane 2; this is an asynchronous signal
indicates receiver detection of an electrical
idle at lane 3; this is an asynchronous signal
L0_RXSTATUS0
L0_RXSTATUS1
L0_RXSTATUS2
L1_RXSTATUS0
L1_RXSTATUS1
L1_RXSTATUS2
L2_RXSTATUS0
L2_RXSTATUS1
L2_RXSTATUS2
L3_RXSTATUS0
L3_RXSTATUS1
L3_RXSTATUS2
C6
C5
D5
output
output
output
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
encodes receiver status and error codes for
the received data stream and receiver
detection at lane 0 (see Table 14)
H15 output
G15 output
encodes receiver status and error codes for
the received data stream and receiver
detection at lane 1 (see Table 14)
F15
R15 output
P15 output
N15 output
output
encodes receiver status and error codes for
the received data stream and receiver
detection at lane 2 (see Table 14)
R7
R8
R9
output
output
output
encodes receiver status and error codes for
the received data stream and receiver
detection at lane 3 (see Table 14)
DESKEW_VALID C15 output
indicates the lane deskew is completed and
passed (see Table 15)
PHYSTATUS D15 output
SSTL
used to communicate completion of several
PHY functions including power management
state transitions and receiver detection
PX1041A_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 21 June 2007
10 of 36
PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
Table 9.
Clock and reference signals
Symbol
Pin
Type
Signaling
Description
TXCLK
A15
input
SSTL
source synchronous 250 MHz transmit clock
input from MAC. All input data and signals to the
PHY are synchronized to this clock.
RXCLK
A14
output
SSTL
source synchronous 250 MHz clock output for
received data and status signals bound for the
MAC.
REFCLK_P
REFCLK_N
A1
B1
input
input
PCIe I/O
PCIe I/O
100 MHz reference clock input. This is the
spread spectrum source clock for PCI Express.
Differential pair input with 50 Ω on-chip
termination.
PVT
D3
-
analog I/O input or output to create a compensation signal
internally that will adjust the I/O pads
characteristics as PVT drifts. Connect to VDD
through a 49.9 Ω resistor.
VREFS
U14 input
reference voltage input for SSTL signaling.
Connect to 900 mV for SSTL_18, to 1.25 V for
SSTL_2.
Table 10. 3.3 V JTAG signals
Symbol
TMS
Pin
A2
B2
Type
input
input
Signaling
Description
3.3 V CMOS test mode select input
TRST_N
3.3 V CMOS test reset input for the JTAG interface;
active LOW. pull-down required for normal
operation
TCK
TDI
B3
A3
C3
input
input
output
3.3 V CMOS test clock input for the JTAG interface
3.3 V CMOS test data input
TDO
3.3 V CMOS test data output
Table 11. PCI Express PHY power supplies
Symbol Pin
VDDA1 J4, K4, L4, M4, N4
Type
Signaling Description
1.2 V analog power supply for
power
serializer and de-serializer
VDDA2
E4
power
power
3.3 V analog power supply for
serializer and de-serializer
VDDD1
VDDD2
C2
3.3 V power supply for JTAG I/O
D7, D8, D10, D11, G14, power
H14, J14, K14, P10,
P11, P12
2.5 V or 1.8 V power supply for SSTL
I/O
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PCI Express stand-alone X4 PHY
Table 11. PCI Express PHY power supplies …continued
Symbol Pin
Type
Signaling Description
VDDD3
VDD
P7, P8
power
power
1.2 V power supply for core
F4, G4, H4
1.2 V power supply for high-speed
serial PCI Express I/O pads and PVT
VSS
B4, B7, B10, B13, B16, ground
C1, D2, D6, D9, D14,
ground
E2, E3, E16, F1, F2, G2,
G16, H2, H3, J1, J2, K2,
K16, L2, L3, M1, M2, N2,
N16, P2, P3, P6, P9,
P14, R1, R2, T2, T4, T7,
T10, T13, T16, U2
8. Functional description
The main function of the PHY is to convert digital data into electrical signals and vice
versa. The PCI Express PHY handles the low level PCI Express protocol and signaling.
The PX1041A PCI Express PHY consists of the Physical Coding Sub-layer (PCS), a
Serializer and De-serializer (SerDes) and a set of I/Os (pads). The PCI Express PHY
handles the low level PCI Express protocol and signaling. This includes features such as
Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding,
analog buffers, elastic buffer and receiver detection.
The PXPIPE interface between the MAC and PX1041A is a superset of the PHY Interface
for the PCI Express (PIPE) specification. The following feature have been added:
• Source synchronous clocks for RX and TX data to simplify timing closure.
The 4 × 8-bit data width PXPIPE interface operates at 250 MHz with SSTL Class I
signaling at 2.5 V or 1.8 V. PX1041A does not integrate SSTL termination resistors inside
the IC.
Each PCI Express lane consists of a differential input pair and a differential output pair.
The data rate per lane is 2.5 Gbit/s.
8.1 Receiving data
Incoming data enters the chip at the RX interface. The receiver converts these signals
from small-amplitude differential signals into rail-to-rail digital signals. The carrier detect
circuit detects whether data is present on the line and passes this information through to
the SerDes and PCS.
If a valid stream of data is present the Clock and Data Recovery unit (CDR) first recovers
the clock from the data and then uses this clock for re-timing the data (i.e., recovering the
data).
The de-serializer or Serial-to-Parallel converter (S2P) de-serializes this data into 10-bits
parallel data.
Since the S2P has no knowledge about the data, the word alignment is still random. This
is fixed in the digital domain by the PCS block. It first detects a 10-bit comma character
(K28.5) from the random data stream and aligns the bits. Then it converts the 10-bit raw
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data into 8-bit words using 8b/10b decoding. An elastic buffer and FIFO brings the
resulting data to the right clock domain, which is the RX source synchronous clock
domain.
8.2 Transmitting data
When the PHY transmits, it receives 4 × 8-bit data from the MAC. This data is encoded
using an 8b/10b encoding algorithm. The 2 bits overhead of the 8b/10b encoding ensures
the serial data will be DC-balanced and has a sufficient 0-to-1 and 1-to-0 transition density
for clock recovery at the receiver side.
The serializer or Parallel-to-Serial converter (P2S) serializes the 10 bits data into serial
data streams. These data streams are latched into the transmitter, where they are
converted into small amplitude differential signals. The transmitter has built-in
de-emphasis for a larger eye opening at the receiver side.
The PLL has a sufficiently high bandwidth to handle a 100 MHz reference clock with a
30 kHz to 33 kHz spread spectrum modulation.
8.3 Clocking
There are three clock signals used by the PX1041A:
• REFCLK is a 100 MHz external reference clock that the PHY uses to generate the
250 MHz data clock and the internal bit rate clock. This clock may have
30 kHz to 33 kHz Spread Spectrum Clock (SSC) modulation.
• TXCLK is a reference clock that the PHY uses to clock the TXDATA and command.
This source synchronous clock is provided by the MAC. The PHY expects that the
rising edge of TXCLK is centered to the data. The TXCLK has to be the same
frequency as RXCLK.
• RXCLK is a source synchronous clock provided by the PHY. The RXDATA and status
signals are synchronous to this clock. The PHY aligns the rising edge of RXCLK to
the center of the data. RXCLK may be used by the MAC to clock its internal logic.
8.4 Reset
The PHY must be held in reset until power and REFCLK are stable. It takes the PHY
64 µs maximum to stabilize its internal clocks. RXCLK frequency is the same as REFCLK
frequency, 100 MHz, during this time. The PHY de-asserts PHYSTATUS when internal
clocks are stable.
The PIPE specification recommends that while RESET_N is asserted, the MAC should
have RXDET_LOOPB de-asserted, TXIDLE asserted, TXCOMP de-asserted, RXPOL
de-asserted and power state P1. The MAC can also assert a reset if it receives a physical
layer reset packet.
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PCI Express stand-alone X4 PHY
RXCLK
RESET_N
PHYSTATUS
100 MHz
250 MHz
002aac172
Fig 4. Reset
8.5 Power management
The power management signals allow the PHY to manage power consumption. The PHY
meets all timing constraints provided in the PCI Express base specification regarding
clock recovery and link training for the various power states.
Four power states are defined: P0, P0s, P1 and P2. P0 state is the normal operational
state for the PHY. When directed from P0 to a lower power state, the PHY can
immediately take whatever power saving measures are appropriate.
In states P0, P0s and P1, the PHY keeps internal clocks operational. For all state
transitions between these three states, the PHY indicates successful transition into the
designated power state by a single cycle assertion of PHYSTATUS. For all power state
transitions, the MAC must not begin any operational sequences or further power state
transitions until the PHY has indicated that the initial state transition is completed. TXIDLE
should be asserted while in power states P0s and P1.
• P0 state: All internal clocks in the PHY are operational. P0 is the only state where the
PHY transmits and receives PCI Express signaling. P0 is the appropriate PHY power
management state for most states in the Link Training and Status State Machine
(LTSSM). Exceptions are listed for each lower power PHY state (P0s, P1 and P2).
• P0s state: The MAC will move the PHY to this state only when the transmit channel is
idle.
While the PHY is in either P0 or P0s power states, if the receiver is detecting an electrical
idle, the receiver portion of the PHY can take appropriate power saving measures. Note
that the PHY is capable of obtaining bit and symbol lock within the PHY-specified time
(N_FTS with or without common clock) upon resumption of signaling on the receive
channel. This requirement only applies if the receiver had previously been bit and symbol
locked while in P0 or P0s states.
• P1 state: Selected internal clocks in the PHY are turned off. The MAC will move the
PHY to this state only when both transmit and receive channels are idle. The PHY
indicates a successful entry into P1 (by asserting PHYSTATUS). P1 should be used
for the disabled state, all detect states, and L1.idle state of the Link Training and
Status State Machine (LTSSM).
• P2 state: PHY will enter P2 and power down the TX and the RX PLLs. RXCLK is
turned off and the PHY interface is in asynchronous mode. The PHY still uses main
power and cannot receive or transmit beacon.
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PCI Express stand-alone X4 PHY
Table 12. Summary of power management state
PWRDWN[1:0]
Power management state
P0, normal operation
Transmitter
on[1]
idle[2]
idle[2]
idle[2]
Receiver
on
TX PLL
on
RXCLK
on
RX PLL/CDR
00b
01b
10b
11b
on
on
off
off
P0s, power saving state
P1, lower power state
P2, lowest power state
idle
on
on
idle
on
on
idle
off
off
[1] TXIDLE = 0
[2] TXIDLE = 1
8.6 Receiver detect
When the PHY is in the P1 state, it can be instructed to perform a receiver detection
operation to determine if there is a receiver at the other end of the link. Basic operation of
receiver detection is that the MAC requests the PHY to do a receiver detect sequence by
asserting RXDET_LOOPB. When the PHY has completed the receiver detect sequence,
each lane drives its own RXSTATUS signals to the value of 011b if a receiver is present, or
to 000b if there is no receiver. Then the PHY will assert PHYSTATUS to indicate the
completion of receiver detect operation. The MAC uses the rising edge of PHYSTATUS to
sample each lane’s RXSTATUS signals and then de-asserts RXDET_LOOPB. A few
cycles after the RXDET_LOOPB de-asserts, the PHYSTATUS is also de-asserted.
TXCLK
RXDET_LOOPB
PWRDWN1,
10b
PWRDWN0
RXCLK
PHYSTATUS
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
000b
011b
000b
002aac173
Fig 5. Receiver detect - receiver present
PX1041A_1
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PCI Express stand-alone X4 PHY
8.7 Loopback
The PHY supports an internal loopback from the PCI Express receiver to the transmitter
of every lane with the following characteristics.
The PHY retransmits each 10-bit data and control symbol exactly as received, without
applying scrambling or descrambling or disparity corrections, with the following rules:
• If a received 10-bit symbol is determined to be an invalid 10-bit code (i.e., no legal
translation to a control or data value possible), the PHY still retransmits the symbol
exactly as it was received.
• If a SKP ordered set retransmission requires adding a SKP symbol to accommodate
timing tolerance correction, any disparity can be chosen for the SKP symbol.
• The PHY continues to provide the received data on the PXPIPE interface, behaving
exactly like normal data reception.
• The PHY transitions from normal transmission of data from the PXPIPE interface to
looping back the received data at a symbol boundary.
The PHY begins to loopback data when the MAC asserts RXDET_LOOPB while doing
normal data transmission. The PHY stops transmitting data from the PXPIPE interface,
and begins to loopback received symbols. While doing loopback, the PHY continues to
present received data on the PXPIPE interface.
The PHY stops looping back received data when the MAC de-asserts RXDET_LOOPB.
Transmission of data on the parallel interface begins immediately.
Since RXDET_LOOPB is a share signal, all lanes enter and exit the loopback mode at the
same time.
The timing diagram of Figure 6 shows example timing for beginning loopback. In this
example, the receiver is receiving a repeating stream of bytes, Rx-a through Rx-z.
Similarly, the MAC is causing the PHY to transmit a repeating stream of bytes Tx-a
through Tx-z. When the MAC asserts RXDET_LOOPB to the PHY, the PHY begins to
loopback the received data to the differential TX_P and TX_N lines.
TXCLK
RXDET_LOOPB
TXDATA[7:0]
RXCLK
Tx-m
Rx-c
Tx-n
Rx-d
Tx-o
Rx-e
Tx-p
Rx-f
Tx-q
Rx-g
RXDATA[7:0]
TX_P, TX_N
Tx-m
Tx-n
Rx-e
002aac174
Fig 6. Loopback start
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PCI Express stand-alone X4 PHY
The timing diagram of Figure 7 shows an example of switching from loopback mode to
normal mode. As soon as the MAC detects an electrical idle ordered-set, the MAC
de-asserts RXDET_LOOPB, asserts TXIDLE and changes the POWERDOWN signals to
state P1.
RXCLK
RXDATA[7:0]
TXCLK
COM
IDL
Junk
RXDET_LOOPB
TXIDLE
includes electrical idle
ordered set
TX_P, TX_N
Looped back RX data
Junk
001aac785
Fig 7. Loopback end
8.8 Electrical idle and lane turn off
The PCI Express Base Specification requires that devices send an Electrical Idle
ordered-set before TX goes to the electrical idle state.
The timing diagram of Figure 8 shows an example of timing for entering electrical idle.
TXCLK
TXDATA[7:0]
TXDATAK
TXIDLE
ScZero
COM
IDL
TX_P, TX_N
active (ends with Electrical Idle ordered-set)
002aac175
Fig 8. Electrical idle
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PCI Express stand-alone X4 PHY
Table 13 summarizes the function of some PXPIPE control signals.
Table 13. Control signals function summary
PWRDWN[1:0]
RXDET_LOOPB
TXIDLE
Function description
normal operation
transmitter in idle
loopback mode
illegal
P0: 00b
0
0
1
1
X
0
1
0
1
0
1
0
1
1
X
P0s: 01b
P1: 10b
illegal
transmitter in idle
illegal
X
0
1
X
transmitter in idle
receiver detect
transmitter and receiver turned off.
P2: 11b
Remark: Beacon transmission and
reception are not supported.
The MAC can disable one or more lanes which are not in use. The MAC asserts both
Lx_TXIDLE and Lx_TXCOMP at the same time to instruct the PHY to turn off the
corresponding lane x. The disabled lane(s) of the PHY will ignore all other signals from the
MAC, except RESET_N. The MAC will ignore any signals from the disabled lane(s).
When the MAC wants to turn on the disabled lane(s), it must reset the whole PHY as
described in Section 8.4.
8.9 Clock tolerance compensation
The PHY receiver contains an elastic buffer used to compensate for differences in
frequencies between bit rates at the two ends of a link. The elastic buffer is capable of
holding at least seven symbols to handle worst case differences (600 ppm) in frequency
and worst case intervals between SKP ordered-sets. The PHY is responsible for inserting
or removing SKP symbols in the received data stream to avoid elastic buffer overflow or
underflow. The PHY monitors the receive data stream, and when a Skip ordered-set is
received, the PHY can add or remove one SKP symbol from each SKP ordered-set as
appropriate to manage its elastic buffer. Whenever a SKP symbol is added or removed,
the PHY will signal this to the MAC using the RXSTATUS signals. These signals have a
non-zero value for one clock cycle and indicate whether a SKP symbol was added or
removed from the received SKP ordered-set. RXSTATUS should be asserted during the
clock cycle when the COM symbol of the SKP ordered-set is moved across the parallel
interface. If the removal of a SKP symbol causes no SKP symbols to be transferred across
the parallel interface, then RXSTATUS is asserted at the same time that the COM symbol
(that was part of the received skip ordered-set) is transmitted across the parallel interface.
Figure 9 shows a sequence where the PHY inserted a SKP symbol in the data stream.
Figure 10 shows a sequence where the PHY removed a SKP symbol from a SKP
ordered-set.
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PCI Express stand-alone X4 PHY
RXCLK
RXDATA[7:0]
RXVALID
active
000b
COM
001b
SKP
SKP
active
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
000b
001aac779
Fig 9. Clock correction - insert a SKP
RXCLK
active
000b
COM
010b
SKP
active
RXDATA[7:0]
RXVALID
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
000b
002aac176
Fig 10. Clock correction - remove a SKP
8.10 Error detection
The PHY is capable of detecting receive errors of several types. These errors are signaled
per lane to the MAC layer using the receiver status signals Lx_RXSTATUS.
Table 14. Function table PXPIPE status interface signals
Operating mode
Output pin
RXSTATUS2 RXSTATUS1 RXSTATUS0
Received data OK
One SKP added
L
L
L
L
L
H
L
One SKP removed
Receiver detected
8b/10b decode error
Elastic buffer overflow
Elastic buffer underflow
Receive disparity error
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
Because of higher level error detection mechanisms (like CRC) built into the data link layer
of PCI Express, there is no need to specifically identify symbols with errors. However,
timing information about when the error occurred in the data stream is important. When a
receive error occurs, the appropriate error code is asserted for one clock cycle at the point
closest to where the error actually occurred.
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There are four error conditions that can be encoded on the RXSTATUS signals. If more
than one error should happen to occur on a received byte, the errors are signaled with the
priority shown below.
1. 8b/10b decode error
2. Elastic buffer overflow
3. Elastic buffer underflow
4. Disparity error
8.10.1 8b/10b decode errors
For a detected 8b/10b decode error, the PHY places an EDB (EnD Bad) symbol in the
data stream in place of the bad byte, and encodes RXSTATUS with a decode error during
the clock cycle when the effected byte is transferred across the parallel interface. In
Figure 11 the receiver is receiving a stream of bytes Rx-a through Rx-z, and byte Rx-c has
an 8b/10b decode error. In place of that byte, the PHY places an EDB on the parallel
interface, and sets RXSTATUS to the 8b/10b decode error code. Note that a byte that
cannot be decoded may also have bad disparity, but the 8b/10b error has precedence.
RXCLK
Rx-a
000b
Rx-b
EDB
100b
Rx-d
000b
Rx-e
RXDATA[7:0]
RXVALID
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
001aac780
Fig 11. 8b/10b decode errors
8.10.2 Disparity errors
For a detected disparity error, the PHY asserts RXSTATUS with the disparity error code
during the clock cycle when the effected byte is transferred across the parallel interface. In
Figure 12 the receiver detected a disparity error on Rx-c data byte, and indicates this with
the assertion of RXSTATUS.
RXCLK
Rx-a
000b
Rx-b
Rx-c
111b
Rx-d
000b
Rx-e
RXDATA[7:0]
RXVALID
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
001aac781
Fig 12. Disparity errors
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PCI Express stand-alone X4 PHY
8.10.3 Elastic buffer
For elastic buffer errors, an underflow is signaled during the clock cycle when the spurious
symbol is moved across the parallel interface. The symbol moved across the interface is
the EDB symbol. In the timing diagram Figure 13, the PHY is receiving a repeating set of
symbols Rx-a through Rx-z. The elastic buffer underflow causing the EDB symbol to be
inserted between the Rx-c and Rx-d symbols. The PHY drives RXSTATUS to indicate
buffer underflow during the clock cycle when the EDB is presented on the parallel
interface.
RXCLK
Rx-a
000b
Rx-b
Rx-c
EDB
110b
Rx-d
000b
RXDATA[7:0]
RXVALID
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
001aac782
Fig 13. Elastic buffer underflow
For an elastic buffer overflow, the overflow is signaled during the clock cycle where the
dropped symbol would have appeared in the data stream. In the timing diagram of
Figure 14, the PHY is receiving a repeating set of symbols Rx-a through Rx-z. The elastic
buffer overflows causing the symbol Rx-d to be discarded. The PHY drives RXSTATUS to
indicate buffer overflow during the clock cycle when Rx-d would have appeared on the
parallel interface.
RXCLK
Rx-a
000b
Rx-b
Rx-c
Rx-e
101b
Rx-f
RXDATA[7:0]
RXVALID
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
000b
001aac783
Fig 14. Elastic buffer overflow
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PCI Express stand-alone X4 PHY
8.11 Polarity inversion
The PHY supports lane polarity inversion for each lane. The PHY inverts received data for
the lane which has its corresponding Lx_RXPOL asserted. The PHY begins data
inversion within 20 symbols after RXPOL is asserted.
RXCLK
RXDATA[7:0]
D21.5
D21.5
D10.2
D10.2
RXVALID
RXPOL
001aac786
Fig 15. Polarity inversion
8.12 Setting negative disparity
To set the running disparity to negative, the MAC asserts the corresponding Lx_TXCOMP
for one clock cycle that matches with the data that is to be transmitted with negative
disparity.
TXCLK
data
K28.5
K28.5
K28.5
K28.5
TXDATA[7:0]
TXCOMP
byte transmitted
with negative disparity
valid data
K28.5−
K28.5+
TX_P, TX_N
002aac177
Fig 16. Setting negative disparity
8.13 JTAG boundary scan interface
Joint Test Action Group (JTAG) or IEEE 1149.1 is a standard, specifying how to control
and monitor the pins of compliant devices on a printed-circuit board. This standard is
commonly known as ‘JTAG Boundary Scan’.
This standard defines a 5-pin serial protocol for accessing and controlling the signal levels
on the pins of a digital circuit, and has some extensions for testing the internal circuitry on
the chip itself, which is beyond the scope of this data sheet.
Access to the JTAG interface is provided to the customer for the sole purpose of using
boundary scan for interconnect test verification between other compliant devices that may
reside on the board. Using JTAG for purposes other than boundary scan may produce
undesired effects.
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PCI Express stand-alone X4 PHY
The JTAG interface is a 3.3 V CMOS signaling. JTAG TRST_N must be asserted LOW for
normal device operation. If JTAG is not planned to be used, it is recommended to
pull down TRST_N and other JTAG input signals to VSS via resistors.
8.14 Optional functions
The PHY supports some optional functions:
• Lane-to-lane deskew
• Lane reversal
• PXPIPE-side parallel loopback
• PIPE mode select
These features can be activated by either the side-band signals or the in-band encoded
commands.
When ENCODEN pin is set to LOW, all functions will be controlled by the dedicated
side-band signal pins;
When ENCODEN pin is set to HIGH, the PHY expects encoded commands to activate the
required function. Any activity on the corresponding pins will be ignored.
Table 15 summarizes these optional functions.
Table 15. Optional functions summary
Side-band signals
DESKEW_START
DESKEW_VALID
ENCODEN = 0
ENCODEN = 1
1 = start lane-to-lane deskew
don’t care; PHY expects an encoded command
1 = indicates deskew operation is completed don’t care; PHY expects an encoded command
and passed
LANEREVERS
PIPESEL
1 = causes all lanes to reverse
0 = PXPIPE interface selected
1 = PIPE interface selected
don’t care; PHY expects an encoded command
0 = PXPIPE interface selected
1 = PIPE interface selected
PIPELOOPB
1 = at PXPIPE side, TXDATA[7:0] directly
loopback to RXDATA[7:0]
0 = PHY expects an encoded command
1 = reserved
The principle of the in-band signaling is based on the use of some invalid 8b/10b special
character symbols as encoded commands. Table 16 summarizes the encoded
commands, and Table 17 is for the status signals.
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PCI Express stand-alone X4 PHY
Table 16. Encoded commands
Command
function
Encoded TXDATA[7:0], TXDATAK
TXDATA7 TXDATA6 TXDATA5 TXDATA4 TXDATA3 TXDATA2 TXDATA1 TXDATA0 TXDATAK
Plain
1
0
1
1
1
1
0
0
1
COMMA
COMMA with
lane-to-lane
deskew
1
0
1
1
1
1
0
1
1
COMMA with
lane reversal
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
COMMA with
lane reversal
and
1
lane-to-lane
deskew
start
PXPIPE-side
loopback
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
1
stop
PXPIPE-side
loopback
Table 17. Encoded status
Command
function
Encoded RXDATA[7:0], RXDATAK
RXDATA7 RXDATA6 RXDATA5 RXDATA4 RXDATA3 RXDATA2 RXDATA1 RXDATA0 RXDATAK
lane-to-lane
deskew
completed
and passed
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
lane-to-lane
deskew
completed
but failed
performing
lane-to-lane
deskew
The PHY has priority to choose the physical lane 0 as the master lane, unless the lane
has been turned off. The encoded commands and status signals should go to L0_TXDATA
and L0_RXDATA, and affect all four lanes. If lane 0 is turned off, then the next highest
physical lane becomes the master lane.
8.14.1 Lane-to-lane deskew
Lane-to-lane deskewing is required by PCIe specification, and is typically implemented in
the MAC. When the PHY offers the feature of receiver lane-to-lane deskew, the MAC
needs to instruct the PHY to start the lane deskew function when it is needed. The PHY
will respond with some status signals.
With the side-band signal, the PHY will detect the rising edge of the DESKEW_START to
start the deskew operation. The PHY responds back by asserting DESKEW_VALID for a
single cycle if deskew is completed and passed. The MAC needs a built-in counter to
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check for the assertion of DESKEW_VALID signal, and if the MAC does not see this signal
go valid within the 32 RXCLK cycles time-out period, it considers the deskew failed and
can reinstruct the PHY to perform deskew by deasserting and reasserting
DESKEW_START.
Using in-band signals, the MAC send encoded lane-to-lane deskew command to PHY,
and the PHY will respond with encoded status signal. if deskewing is successful, the MAC
then send the PHY the special COMMA with bit 0 = 0, shown at Table 16, to stop the
deskew. If deskewing fails, the MAC should first stop the deskew, then may resend the
encoded deskew start command to restart the deskew process.
The PHY internally arbitrates to decide the master lane to use for deskewing. All lanes
that are turned off by the MAC, do not take part in arbitration or deskewing. The PHY has
priority to choose lane 0 as the master lane, unless the lane has been turned off. Even
when lane reversal is enabled and physical lane 0 becomes logical lane 3, physical lane 0
still has priority for becoming the master. When the PHY is configured to perform
lane-to-lane deskew the information about SKP insertion and removal from the PHY
should be ignored by the MAC. This is because the deskewing is done by the PHY and
hence the skip insertion and removal information is not required. All other information like
decode error, disparity error, FIFO overflow, FIFO underflow, and OK are valid.
8.14.2 Lane reversal
Lane reversal for multi-lane implementation is particularly useful to ease PCB layout. It
swaps the physical lane0, lane1, lane2, and lane3 to the logical lane3, lane2, lane1, and
lane0, respectively. This feature is typically performed in the MAC. PX1041A has this
optional built-in feature. It is required to have a signal from the MAC to the PHY to enable
it.
When the MAC asserts LANEREVERS, the PHY will enable the feature. Alternatively, the
MAC can send the encoded command listed in Table 16 to enable this feature.
8.14.3 PXPIPE-side parallel loopback
The function of PXPIPE-side parallel loopback is mainly for test debugging purposes to
check the PCB connection between the MAC and the PHY. The PHY will loopback any
data that is present on the Lx_TXDATA and Lx_TXDATAK lines to the corresponding
Lx_RXDATA and Lx_RXDATAK.
PIPELOOPB being HIGH will enable the feature, or the MAC may use the encoded
commands in Table 16. This feature requires the PHY to be in the P1 state.
8.14.4 PIPE Mode
By default, the interface between the MAC and PX1041A is PXPIPE, which has source
synchronous clocks for transmit and receive data. The PIPE mode, which uses a single
clock, RXCLK, for both transmit and receive, is selectable by setting the PIPESEL pin
HIGH.
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9. Limiting values
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
for JTAG I/O
for SSTL I/O
for core
Min
Max
+4.6
+3.75
+1.7
+1.7
Unit
V
VDDD1
VDDD2
VDDD3
VDD
digital supply voltage 1
−0.5
−0.5
−0.5
−0.5
[1]
[1]
digital supply voltage 2
digital supply voltage 3
supply voltage
V
V
for high-speed
V
serial I/O and PVT
VDDA1
VDDA2
Vesd
analog supply voltage 1
analog supply voltage 2
electrostatic discharge voltage
for serializer
for serializer
HBM
−0.5
−0.5
-
+1.7
+4.6
2000
500
V
V
[2]
[3]
V
CDM
-
V
Tstg
Tj
storage temperature
junction temperature
ambient temperature
−55
−55
+150
+125
°C
°C
Tamb
operating
commercial
industrial
0
+70
+85
°C
°C
−40
[1] No select pin needed.
[2] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
[3] Charged Device Model: ANSI/EOS/ESD-S5.3.1-1999, standard for ESD sensitivity testing, Charged Device
Model - component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Thermal characteristics
Table 19. Thermal characteristics
Symbol Parameter
Conditions
Typ
Unit
[1]
[1]
Rth(j-a)
thermal resistance from junction to ambient in free air,
32.6
K/W
JEDEC test
card
Rth(j-c)
thermal resistance from junction to case
in free air,
JEDEC test
card
6.9
K/W
[1] Significant variations can be expected due to system variables, such as adjacent devices, or actual air flow
across the package.
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PCI Express stand-alone X4 PHY
11. Characteristics
Table 20. PCI Express PHY characteristics
Symbol
Supplies
VDDD1
VDDD2
VDDD2
VDDD3
VDD
Parameter
Conditions
Min
Typ
Max
Unit
digital supply voltage 1
digital supply voltage 2
digital supply voltage 2
digital supply voltage 3
supply voltage
for JTAG I/O
for SSTL_18 I/O
for SSTL_2 I/O
for core
3.0
3.3
1.8
2.5
1.2
1.2
3.6
V
V
V
V
V
1.7
1.9
2.3
2.7
1.15
1.15
1.25
1.25
for high-speed
serial I/O and PVT
VDDA1
VDDA2
IDDD1
IDDD2
analog supply voltage 1
analog supply voltage 2
digital supply current 1
digital supply current 2
for serializer
for serializer
for JTAG I/O
1.15
1.2
1.25
3.6
2
V
3.0
3.3
V
-
-
<tbd>
mA
mA
for SSTL I/O;
no load
<tbd> 80
IDDD3
IDD
digital supply current 3
supply current
for core
-
-
<tbd> 60
mA
mA
for high-speed
<tbd> 100
serial I/O and PVT
IDDA1
analog supply current 1
analog supply current 2
for serializer
for serializer
-
-
<tbd> 100
<tbd> 60
mA
mA
IDDA2
Reference clock
fclk(ref)
reference clock frequency
99.97 100
100.03 MHz
∆fmod(clk)(ref)
reference clock SSC modulation
frequency deviation
−0.5
-
+0
33
-
%
fmod(clk)(ref)
reference clock SSC modulation
frequency
30
-
-
kHz
V
VIH(se)REFCLK
VIL(se)REFCLK
REFCLK single-end HIGH-level input
voltage
0.7
0
REFCLK single-end LOW-level input
voltage
-
-
V
Receiver
UI
unit interval
399.88 400
400.12 ps
VRX_DIFFp-p
tRX_MAX_JITTER
differential input peak-to-peak voltage
maximum receiver jitter time
0.175
-
1.2
V
-
-
0.6
UI
mV
Ω
VIDLE_DET_DIFFp-p electrical idle detect threshold
65
40
200
10
6
-
175
ZRX_DC
DC input impedance
50
60
-
ZRX_HIGH_IMP_DC
RLRX_DIFF
RLRX_CM
powered-down DC input impedance
differential return loss
-
kΩ
dB
dB
µs
µs
-
-
common mode return loss
CDR lock time (reference loop)
CDR lock time (data loop)
receiver latency
-
-
tlock(CDR)(ref)
tlock(CDR)(data)
tRX_latency
-
<tbd>
<tbd>
<tbd>
-
-
-
1 clock cycle is
4 ns
-
-
clock
cycle
LRX_SKEW
total skew
-
-
20
ns
PX1041A_1
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PCI Express stand-alone X4 PHY
Table 20. PCI Express PHY characteristics …continued
Symbol
Transmitter
UI
Parameter
Conditions
Min
Typ
Max
Unit
unit interval
399.88 400
400.12 ps
VTX_DIFFp-p
differential peak-to-peak output voltage
0.8
-
-
1.2
V
tTX_EYE_m-mJITTER maximum time between the jitter median
and maximum deviation from the median
<tbd> 50
ps
tTX_JITTER_MAX
VTX_DE_RATIO
maximum transmitter jitter time
-
<tbd> 100
ps
de-emphasized differential output voltage
ratio
−3.0
−3.5
−4.0
dB
tTX_RISE
D+/D− TX output rise time
D+/D− TX output fall time
50
50
-
-
-
-
-
ps
tTX_FALL
-
ps
VTX_CM_ACp
RMS AC peak common mode output
voltage
20
mV
∆VCM_DC_ACT_IDLE absolute delta of DC common mode
0
0
-
-
100
25
mV
mV
voltage during L0 and electrical idle
∆VCM_DC_LINE
absolute delta of DC common mode
voltage between D+ and D−
VTX_CM_DC
ITX_SHORT
RLTX_DIFF
RLTX_CM
ZTX_DC
TX DC common mode voltage
TX short-circuit current limit
differential return loss
common mode return loss
transmitter DC impedance
AC coupling capacitor
PLL lock time
0
-
3.6
90
-
V
-
-
mA
dB
dB
Ω
10
6
-
-
-
40
75
-
50
60
200
50
-
CTX
100
-
nF
µs
tlock(PLL)
tTX_latency
transmitter latency
1 clock cycle is
4 ns
-
<tbd>
clock
cycle
tP0s_exit_latency
tP1_exit_latency
P0s state exit latency
P1 state exit latency
-
-
-
<tbd>
<tbd>
-
-
µs
µs
µs
-
tRESET-PHYSTATUS
RESET_N HIGH to PHYSTATUS LOW
time
64
LTX_SKEW
lane-to-lane output skew
-
-
500 + ps
2UI
PX1041A_1
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28 of 36
PX1041A
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PCI Express stand-alone X4 PHY
Table 21. PXPIPE characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MHz
MHz
mV
V
fRXCLK
RXCLK frequency
249.925
250
250.075
fTXCLK
TXCLK frequency
249.925
250
250.075
[1]
[1]
VVREFS
voltage on pin VREFS
for SSTL_18
for SSTL_2
-
900
-
VVREFS
voltage on pin VREFS
-
1.25
-
VOH(SSTL18)
VOL(SSTL18)
VIH(SSTL18)
VIL(SSTL18)
VOH(SSTL2)
VOL(SSTL2)
VIH(SSTL2)
VIL(SSTL2)
SSTL_18 HIGH-level output voltage
SSTL_18 LOW-level output voltage
SSTL_18 HIGH-level AC input voltage
SSTL_18 LOW-level AC input voltage
SSTL_2 HIGH-level output voltage
SSTL_2 LOW-level output voltage
SSTL_2 HIGH-level AC input voltage
SSTL_2 LOW-level AC input voltage
VTT = 900 mV
VTT = 900 mV
Vref = 900 mV
Vref = 900 mV
VTT = 1.25 V
VTT = 1.25 V
Vref = 1.25 V
Vref = 1.25 V
1.50
-
-
-
-
-
-
-
-
-
V
-
0.30
-
V
1.15
V
-
0.65
-
V
1.85
V
-
0.64
-
V
1.56
-
V
0.94
V
Input signals; measured with respect to TXCLK
tsu(TX)(PXPIPE) setup time of PXPIPE input signal
th(TX)(PXPIPE) hold time of PXPIPE input signal
Output signals; measured with respect to RXCLK
tsu(RX)(PXPIPE) setup time of PXPIPE output signal
th(RX)(PXPIPE) hold time of PXPIPE output signal
see Figure 17
see Figure 17
500
500
-
-
-
-
ps
ps
see Figure 17
see Figure 17
1500
1500
-
-
-
-
ps
ps
[1] Reference voltage for SSTL I/O.
TXCLK
PXPIPE
INPUT
t
su(TX)(PXPIPE)
t
h(TX)(PXPIPE)
RXCLK
PXPIPE
OUTPUT
t
t
h(RX)(PXPIPE)
su(RX)(PXPIPE)
002aac316
Fig 17. Definition of PXPIPE timing
PX1041A_1
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Objective data sheet
Rev. 01 — 21 June 2007
29 of 36
PX1041A
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PCI Express stand-alone X4 PHY
12. Package outline
LFBGA208: plastic low profile fine-pitch ball grid array package; 208 balls; body 15 x 15 x 1 mm
SOT631-4
D
B
A
ball A1
index area
E
A
2
A
1
A
detail X
e
1
C
M
v
C
C
A
B
b
e
y
y
M
w
C
1
U
T
P
M
K
H
F
R
N
L
e
e
2
J
G
E
C
A
D
B
ball A1
index area
1
3
5
7
9
11 13 15 17
10 12 14 16
X
2
4
6
8
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
D
E
e
e
e
2
v
w
y
y
1
1
max
0.4
0.3
1.10
0.95
0.5
0.4
15.1 15.1
14.9 14.9
mm
1.5
0.8
12.8 12.8 0.15 0.08 0.12
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
07-03-09
07-03-19
SOT631-4
MO-205
Fig 18. Package outline SOT631-4 (LFBGA208)
PX1041A_1
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PCI Express stand-alone X4 PHY
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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Objective data sheet
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PCI Express stand-alone X4 PHY
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 22 and 23
Table 22. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 23. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.
PX1041A_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
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32 of 36
PX1041A
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PCI Express stand-alone X4 PHY
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 24. Abbreviations
Acronym
BER
Description
Bit Error Rate
BIST
CMOS
EMI
Built-In Self Test
Complementary Metal Oxide Semiconductor
ElectroMagnetic Interference
ElectroStatic Discharge
Field Programmable Gate Array
Link Training and Status State Machine
Media Access Control
Parallel to Serial
ESD
FPGA
LTSSM
MAC
P2S
PCI
Peripheral Component Interconnect
Physical Coding Sub-layer
PHYsical layer
PCS
PHY
PLL
Phase-Locked Loop
PIPE
PVT
PHY Interface for the PCI Express
Process Voltage Temperature
Receive
RX
S2P
Serial to Parallel
SerDes
SKP
Serializer and De-serializer
SKiP
PX1041A_1
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PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
Table 24. Abbreviations …continued
Acronym
Description
SSC
Spread Spectrum Clock modulation
Stub Series Terminated Logic for 1.8 Volts
Stub Series Terminated Logic for 2.5 Volts
Transmit
SSTL_18
SSTL_2
TX
15. References
[1] PCI Express Base Specification — Rev. 1.1 - PCISIG
[2] PHY Interface for the PCI Express Architecture Version 2.00 — Intel
Corporation
16. Revision history
Table 25. Revision history
Document ID
Release date
20070621
Data sheet status
Change notice
Supersedes
PX1041A_1
Objective data sheet
-
-
PX1041A_1
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Objective data sheet
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PCI Express stand-alone X4 PHY
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
17.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
18. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
PX1041A_1
© NXP B.V. 2007. All rights reserved.
Objective data sheet
Rev. 01 — 21 June 2007
35 of 36
PX1041A
NXP Semiconductors
PCI Express stand-alone X4 PHY
19. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
13.4
14
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 32
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision history . . . . . . . . . . . . . . . . . . . . . . . 34
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PCI Express interface. . . . . . . . . . . . . . . . . . . . 1
PHY/MAC interface. . . . . . . . . . . . . . . . . . . . . . 1
JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . 2
Power management . . . . . . . . . . . . . . . . . . . . . 2
Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1
2.2
2.3
2.4
2.5
2.6
15
16
17
Legal information . . . . . . . . . . . . . . . . . . . . . . 35
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 35
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17.1
17.2
17.3
17.4
3
4
5
6
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 35
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Functional description . . . . . . . . . . . . . . . . . . 12
Receiving data . . . . . . . . . . . . . . . . . . . . . . . . 12
Transmitting data . . . . . . . . . . . . . . . . . . . . . . 13
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power management . . . . . . . . . . . . . . . . . . . . 14
Receiver detect. . . . . . . . . . . . . . . . . . . . . . . . 15
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical idle and lane turn off . . . . . . . . . . . . 17
Clock tolerance compensation . . . . . . . . . . . . 18
Error detection . . . . . . . . . . . . . . . . . . . . . . . . 19
8b/10b decode errors . . . . . . . . . . . . . . . . . . . 20
Disparity errors . . . . . . . . . . . . . . . . . . . . . . . . 20
Elastic buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Polarity inversion. . . . . . . . . . . . . . . . . . . . . . . 22
Setting negative disparity . . . . . . . . . . . . . . . . 22
JTAG boundary scan interface . . . . . . . . . . . . 22
Optional functions. . . . . . . . . . . . . . . . . . . . . . 23
Lane-to-lane deskew . . . . . . . . . . . . . . . . . . . 24
Lane reversal . . . . . . . . . . . . . . . . . . . . . . . . . 25
PXPIPE-side parallel loopback. . . . . . . . . . . . 25
PIPE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.8
8.9
8.10
8.10.1
8.10.2
8.10.3
8.11
8.12
8.13
8.14
8.14.1
8.14.2
8.14.3
8.14.4
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal characteristics. . . . . . . . . . . . . . . . . . 26
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 27
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30
10
11
12
13
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Introduction to soldering . . . . . . . . . . . . . . . . . 31
Wave and reflow soldering . . . . . . . . . . . . . . . 31
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31
13.1
13.2
13.3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 June 2007
Document identifier: PX1041A_1
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