PZ3064I12BB1 [NXP]
64 macrocell CPLD; 64宏单元CPLD
| 型号： | PZ3064I12BB1 |
| 厂家： | 
NXP |
| 描述： | 64 macrocell CPLD |
| 文件： | 总20页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PZ3064
64 macrocell CPLD
Product specification
IC27 Data Handbook
1997 Mar 05
Philips
Semiconductors
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
FEATURES
DESCRIPTION
The PZ3064 CPLD (Complex Programmable Logic Device) is the
second in a family of Fast Zero Power (FZP ) CPLDs from Philips
Semiconductors. These devices combine high speed and zero
power in a 64 macrocell CPLD. With the FZP design technique,
the PZ3064 offers true pin-to-pin speeds of 10ns, while
• Industry’s first TotalCMOS PLD – both CMOS design and
process technologies
• Fast Zero Power (FZP ) design technique provides ultra-low
power and very high speed
simultaneously delivering power that is less than 50µA at standby
without the need for ‘turbo bits’ or other power down schemes. By
replacing conventional sense amplifier methods for implementing
product terms (a technique that has been used in PLDs since the
bipolar era) with a cascaded chain of pure CMOS gates, the
dynamic power is also substantially lower than any competing CPLD
– 70% lower at 50MHz. These devices are the first TotalCMOS
PLDs, as they use both a CMOS process technology and the
patented full CMOS FZP design technique. For 5V applications,
Philips also offers the high speed PZ5064 CPLD that offers these
features in a full 5V implementation.
• High speed pin-to-pin delays of 10ns
• Ultra-low static power of less than 50µA
• Dynamic power that is 70% lower at 50MHz than competing
devices
• 100% routable with 100% utilization while all pins and all
macrocells are fixed
• Deterministic timing model that is extremely simple to use
• 4 clocks with programmable polarity at every macrocell
• Support for complex asynchronous clocking
The Philips FZP CPLDs introduce the new patent-pending XPLA
(eXtended Programmable Logic Array) architecture. The XPLA
architecture combines the best features of both PLA and PAL type
structures to deliver high speed and flexible logic allocation that
results in superior ability to make design changes with fixed pinouts.
The XPLA structure in each logic block provides a fast 10ns PAL
path with 5 dedicated product terms per output. This PAL path is
joined by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can allocate
the PLA product terms to any output in the logic block. This
• Innovative XPLA architecture combines high speed with
extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
2
• Advanced 0.5µ E CMOS process
combination allows logic to be allocated efficiently throughout the
logic block and supports as many as 37 product terms on an output.
The speed with which logic is allocated from the PLA array to an
output is only 2.5ns, regardless of the number of PLA product terms
• Security bit prevents unauthorized access
• Design entry and verification using industry standard and Philips
CAE tools
used, which results in worst case t ’s of only 12.5ns from any pin
PD
to any other pin. In addition, logic that is common to multiple outputs
can be placed on a single PLA product term and shared across
multiple outputs via the OR array, effectively increasing design
density.
• Reprogrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or
product terms in each logic block for:
– Programmable 3-State buffer
The PZ3064 CPLDs are supported by industry standard CAE tools
(Cadence, Mentor, Synopsys, Synario, Viewlogic, MINC), using text
(Abel, VHDL, Verilog) and/or schematic entry. Design verification
uses industry standard simulators for functional and timing
simulation. Development is supported on personal computer, Sparc,
and HP platforms. Device fitting uses either Minc or Philips
Semiconductors-developed tools.
– Asynchronous macrocell register preset/reset
• Programmable global 3-State pin facilitates ‘bed of nails’ testing
without using logic resources
• Available in PLCC, TQFP, and PQFP packages
• Available in both Commercial and Industrial grades
The PZ3064 CPLD is reprogrammable using industry standard
device programmers from vendors such as Data I/O, BP
Microsystems, SMS, and others.
Table 1. PZ3064 Features
PZ3064
Usable gates
2000
68
Maximum inputs
Maximum I/Os
64
Number of macrocells
Propagation delay (ns)
64
10
44-pin PLCC, 44-pin TQFP,
68-pin PLCC, 84-pin PLCC,
100-pin PQFP
Packages
PAL is a registered trademark of Advanced Micro Devices, Inc.
82
1997 Mar 05
853–1891 17824
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
ORDERING INFORMATION
ORDER CODE
PZ3064-10A44
PZ3064-12A44
PZ3064I12A44
PZ3064I15A44
PZ3064-10BC
PZ3064-12BC
PZ3064I12BC
PZ3064I15BC
PZ3064-10A68
PZ3064-12A68
PZ3064I12A68
PZ3064I15A68
PZ3064-10A84
PZ3064-12A84
PZ3064I12A84
PZ3064I15A84
PZ3064-10BB1
PZ3064-12BB1
PZ3064I12BB1
PZ3064I15BB1
DESCRIPTION
DESCRIPTION
DRAWING NUMBER
SOT187-2
SOT187-2
SOT187-2
SOT187-2
SOT376-1
SOT376-1
SOT376-1
SOT376-1
SOT188-3
SOT188-3
SOT188-3
SOT188-3
SOT189-3
SOT189-3
SOT189-3
SOT189-3
SOT382-1
SOT382-1
SOT382-1
SOT382-1
44-pin PLCC, 10ns t
44-pin PLCC, 12ns t
44-pin PLCC, 12ns t
44-pin PLCC, 15ns t
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
PD
PD
PD
PD
PD
PD
PD
PD
44-pin TQFP, 10ns t
44-pin TQFP, 12ns t
44-pin TQFP, 12ns t
44-pin TQFP, 15ns t
68-pin PLCC, 10ns t
68-pin PLCC, 12ns t
68-pin PLCC, 12ns t
68-pin PLCC, 15ns t
84-pin PLCC, 10ns t
84-pin PLCC, 12ns t
84-pin PLCC, 12ns t
84-pin PLCC, 15ns t
PD
PD
PD
PD
PD
PD
PD
PD
100-pin PQFP, 10ns t
100-pin PQFP, 12ns t
100-pin PQFP, 12ns t
100-pin PQFP, 15ns t
PD
PD
PD
PD
XPLA ARCHITECTURE
Logic Block Architecture
Figure 1 shows a high level block diagram of a 64 macrocell device
implementing the XPLA architecture. The XPLA architecture
consists of logic blocks that are interconnected by a Zero-power
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each
logic block is essentially a 36V16 device with 36 inputs from the ZIA
and 16 macrocells. Each logic block also provides 32 ZIA feedback
paths from the macrocells and I/O pins.
Figure 2 illustrates the logic block architecture. Each logic block
contains control terms, a PAL array, a PLA array, and 16 macrocells.
the 6 control terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the preset/reset and
output enables of the 16 macrocells’ flip-flops. The PAL array
consists of a programmable AND array with a fixed OR array, while
the PLA array consists of a programmable AND array with a
programmable OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased product
term density.
From this point of view, this architecture looks like many other CPLD
architectures. What makes the CoolRunner family unique is what
is inside each logic block and the design technique used to
implement these logic blocks. The contents of the logic block will be
described next.
Each macrocell has 5 dedicated product terms from the PAL array.
The pin-to-pin t of the PZ3064 device through the PAL array is
PD
10ns. If a macrocell needs more than 5 product terms, it simply gets
the additional product terms from the PLA array. The PLA array
consists of 32 product terms, which are available for use by all 16
macrocells. The additional propagation delay incurred by a
macrocell using 1 or all 32 PLA product terms is just 2.5ns. So the
total pin-to-pin t for the PZ3064 using 6 to 37 product terms is
PD
12.5ns (10ns for the PAL + 2.5ns for the PLA).
83
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
MC0
MC0
MC1
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
I/O
I/O
MC15
MC15
16
16
16
16
ZIA
MC0
MC1
MC0
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
I/O
I/O
MC15
MC15
16
16
16
16
SP00439
Figure 1. Philips XPLA CPLD Architecture
36 ZIA INPUTS
CONTROL
6
5
PAL
ARRAY
PLA
ARRAY
(32)
SP00435
Figure 2. Philips Logic Block Architecture
84
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
to control the Output Enable of the macrocell’s output buffers. The
reason there are as many control terms dedicated for the Output
Enable of the macrocell is to insure that all CoolRunner devices
are PCI compliant. The macrocell’s output buffers can also be
always enabled or disabled. All CoolRunner devices also provide a
Global Tri-State (GTS) pin, which, when pulled Low, will 3-State all
the outputs of the device. This pin is provided to support “In-Circuit
Testing” or “Bed-of-Nails Testing”.
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the
CoolRunner family. The macrocell consists of a flip-flop that can be
configured as either a D or T type. A D-type flip-flop is generally
more useful for implementing state machines and data buffering. A
T-type flip-flop is generally more useful in implementing counters. All
CoolRunner family members provide both synchronous and
asynchronous clocking and provide the ability to clock off either the
falling or rising edges of these clocks. These devices are designed
such that the skew between the rising and falling edges of a clock
are minimized for clocking integrity. There are 4 clocks available on
the PZ3064 device. Clock 0 (CLK0) is designated as the
There are two feedback paths to the ZIA: one from the macrocell,
and one from the I/O pin. The ZIA feedback path before the output
buffer is the macrocell feedback path, while the ZIA feedback path
after the output buffer is the I/O pin ZIA path. When the macrocell is
used as an output, the output buffer is enabled, and the macrocell
feedback path can be used to feedback the logic implemented in the
macrocell. When the I/O pin is used as an input, the output buffer
will be 3-Stated and the input signal will be fed into the ZIA via the
I/O feedback path, and the logic implemented in the buried
macrocell can be fed back to the ZIA via the macrocell feedback
path. It should be noted that unused inputs or I/Os should be
properly terminated.
“synchronous” clock and must be driven by an external source.
Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3 (CLK3) can either be
used as a synchronous clock (driven by an external source) or as an
asynchronous clock (driven by a macrocell equation).
Two of the control terms (CT0 and CT1) are used to control the
Preset/Reset of the macrocell’s flip-flop. The Preset/Reset feature
for each macrocell can also be disabled. Note that the Power-on
Reset leaves all macrocells in the “zero” state when power is
properly applied. The other 4 control terms (CT2–CT5) can be used
TO ZIA
D/T
Q
INIT
(P or R)
GTS
CLK0
CLK0
GND
CT0
CT1
CT2
CT3
CT4
CT5
CLK1
CLK1
CLK2
CLK2
GND
CLK3
CLK3
V
CC
GND
SP00457
Figure 3. PZ3064 Macrocell Architecture
85
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
5 product terms or less, the t = 10ns, the t
= 6ns, and the
SU_PAL
Simple Timing Model
Figure 4 shows the CoolRunner Timing Model. The CoolRunner
timing model looks very much like a 22V10 timing model in that
PD
t
= 7ns. If an output is using 6 to 37 product terms, an additional
CO
2ns must be added to the t and t timing parameters to account
PD
SU
for the time to propagate through the PLA array.
there are three main timing parameters, including t , t , and t
.
PD SU
CO
In other competing architectures, the user may be able to fit the
design into the CPLD, but is not sure whether system timing
requirements can be met until after the design has been fit into the
device. This is because the timing models of competing
architectures are very complex and include such things as timing
dependencies on the number of parallel expanders borrowed,
sharable expanders, varying number of X and Y routing channels
used, etc. In the XPLA architecture, the user knows up front
whether the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in the
PZ3064 device, the user knows up front that if a given output uses
TotalCMOS Design Technique
for Fast Zero Power
Philips is the first to offer a TotalCMOS CPLD, both in process
technology and design technique. Philips employs a cascade of
CMOS gates to implement its Sum of Products instead of the
traditional sense amp approach. This CMOS gate implementation
allows Philips to offer CPLDs which are both high performance and
low power, breaking the paradigm that to have low power, you must
have low performance. Refer to Figure 5 and Table 2 showing the I
DD
vs. Frequency of our PZ3064 TotalCMOS CPLD.
t
= COMBINATORIAL PAL ONLY
= COMBINATORIAL PAL + PLA
PD_PAL
t
PD_PLA
INPUT PIN
INPUT PIN
OUTPUT PIN
OUTPUT PIN
REGISTERED
= PAL ONLY
t
t
REGISTERED
SU_PAL
= PAL + PLA
t
SU_PLA
CO
D
Q
CLOCK
SP00441
Figure 4. CoolRunner Timing Model
100
80
I
DD
(mA)
TYPICAL
60
40
20
0
0
20
40
60
80
100
FREQUENCY (MHz)
SP00460A
Figure 5.
I vs. Frequency @ V = 3.3V, 25°C
DD DD
Table 2. I vs. Frequency
DD
V
DD
= 3.3V
FREQUENCY (MHz)
0
20
13
40
60
40
80
50
100
Typical I ( mA)
0.04
26
63
DD
86
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
4
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
MIN.
–0.5
–1.2
–0.5
–30
MAX.
7.0
UNIT
V
V
V
V
Supply voltage
Input voltage
Output voltage
Input current
Output current
DD
I
V
DD
V
DD
+0.5
V
+0.5
V
OUT
I
I
30
mA
mA
°C
°C
IN
OUT
–100
–40
100
150
150
T
J
Maximum junction temperature
Storage temperature
T
str
–65
NOTES:
4. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification is not implied.
OPERATING RANGE
PRODUCT GRADE
Commercial
TEMPERATURE
0 to +70°C
VOLTAGE
3.3 ±10% V
3.3 ±10% V
Industrial
–40 to +85°C
87
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ T
≤ +70°C; 3.0V ≤ V ≤ 3.6V
amb
DD
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
V
V
V
V
V
V
Input voltage low
V
DD
V
DD
= 3.0V
= 3.6V
0.8
IL
Input voltage high
2.0
V
IH
I
Input clamp voltage
Output voltage low
V
= 3.0V, I = –18mA
–1.2
0.5
V
DD
IN
V
DD
= 3.0V, I = 8mA
V
OL
OH
OL
Output voltage high
Input leakage current
3-Stated output leakage current
Standby current
V
= 3.0V, I = –8mA
2.4
–10
–10
V
DD
OH
I
I
I
V
= 0 to V
= 0 to V
10
10
50
1
µA
µA
µA
mA
mA
mA
pF
pF
pF
I
IN
IN
DD
DD
V
OZ
V
DD
= 3.6V, T
= 0°C
DDQ
amb
V
= 3.6V, T
= 0°C @ 1MHz
= 0°C @ 50MHz
amb
DD
amb
1
I
I
Dynamic current
DDD
V
DD
= 3.6V, T
40
–100
8
Short circuit output current
Input pin capacitance
Clock input capacitance
I/O pin capacitance
1 pin at a time for no longer than 1 second
–5
5
OS
C
C
C
T
= 25°C, f = 1MHz
= 25°C, f = 1MHz
= 25°C, f = 1MHz
IN
amb
T
amb
12
10
CLK
I/O
T
amb
NOTE:
1. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded.
Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing.
DD
1
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ T
≤ +70°C; 3.0V ≤ V ≤ 3.6V
amb
DD
–10
MAX.
–12
MAX.
SYMBOL
PARAMETER
UNIT
MIN.
2
MIN.
2
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
t
t
t
t
t
t
t
Propagation delay time, input (or feedback node) to output through PAL
10
12.5
7
12
14.5
8
ns
ns
PD_PAL
PD_PLA
CO
Propagation delay time, input (or feedback node) to output through PAL & PLA
3
3
Clock to out delay time
2
2
ns
Setup time (from input or feedback node) through PAL
5.5
8
7
ns
SU_PAL
SU_PLA
H
Setup time (from input or feedback node) through PAL + PLA
9.5
ns
Hold time
0
0
ns
Clock High time
Clock Low time
Input Rise time
4
4
5
5
ns
CH
ns
CL
20
20
20
20
ns
R
Input Fall time
ns
F
2
Maximum FF toggle rate (1/t + t
)
125
91
100
74
MHz
MHz
MHz
ns
MAX1
MAX2
MAX3
BUF
CH
CL
2
Maximum internal frequency (1/t
+ t
)
CF
SUPAL
2
Maximum external frequency (1/t
Output buffer delay time
+ t
)
CO
80
67
SUPAL
1.5
8.5
11
1.5
10.5
13
Input (or feedback node) to internal feedback node delay time through PAL
Input (or feedback node) to internal feedback node delay time through PAL+PLA
Clock to internal feedback node delay time
ns
PDF_PAL
PDF_PLA
CF
ns
5.5
50
6.5
50
ns
Delay from valid V to valid reset
µs
INIT
DD
3
Input to output disable
12.5
12.5
15
14
ns
ER
Input to output valid
Input to register preset
Input to register reset
14
ns
EA
16
ns
RP
15
16
ns
RR
NOTES:
1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output C = 5pF.
L
88
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES
Industrial:
–40°C ≤ T
≤ +85°C; 3.0V ≤ V ≤ 3.6V
amb
DD
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
V
V
V
V
V
V
Input voltage low
V
DD
V
DD
= 3.0V
= 3.6V
0.8
IL
Input voltage high
2.0
V
IH
I
Input clamp voltage
Output voltage low
Output voltage high
Input leakage current
3-Stated output leakage current
Standby current
V
= 3.0V, I = –18mA
–1.2
0.5
V
DD
IN
V
DD
= 3.0V, I = 8mA
V
OL
OH
OL
V
= 3.0V, I = –8mA
2.4
–10
–10
V
DD
OH
I
I
I
V
= 0 to V
= 0 to V
10
10
50
1
µA
µA
µA
mA
mA
mA
pF
pF
pF
I
IN
IN
DD
V
OZ
DD
V
= 3.6V, T = –40°C
amb
DDQ
DD
V
= 3.6V, T
= –40°C @ 1MHz
= –40°C @ 50MHz
amb
DD
amb
1
I
I
Dynamic current
DDD
V
DD
= 3.6V, T
40
–130
8
Short circuit output current
Input pin capacitance
Clock input capacitance
I/O pin capacitance
1 pin at a time for no longer than 1 second
–5
5
OS
C
C
C
T
= 25°C, f = 1MHz
= 25°C, f = 1MHz
= 25°C, f = 1MHz
IN
amb
T
amb
12
10
CLK
I/O
T
amb
NOTE:
1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded.
Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing.
DD
1
AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES
Industrial:
–40°C ≤ T ≤ +85°C; 3.0V ≤ V ≤ 3.6V
amb DD
I12
I15
SYMBOL
PARAMETER
UNIT
MIN.
2
MAX.
12
MIN.
MAX.
15
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
t
t
t
t
t
t
t
Propagation delay time, input (or feedback node) to output through PAL
2
3
ns
ns
PD_PAL
PD_PLA
CO
Propagation delay time, input (or feedback node) to output through PAL & PLA
3
14.5
8
17.5
9
Clock to out delay time
2
2
ns
Setup time (from input or feedback node) through PAL
7
8
ns
SU_PAL
SU_PLA
H
Setup time (from input or feedback node) through PAL + PLA
9.5
10.5
ns
Hold time
0
0
ns
Clock High time
Clock Low time
Input Rise time
5
5
5
5
ns
CH
ns
CL
20
20
20
20
ns
R
Input Fall time
ns
F
2
Maximum FF toggle rate (1/t + t
)
100
74
100
65
MHz
MHz
MHz
ns
MAX1
MAX2
MAX3
BUF
CH
CL
2
Maximum internal frequency (1/t
+ t
)
CF
SUPAL
2
Maximum external frequency (1/t
Output buffer delay time
+ t
)
CO
67
58
SUPAL
1.5
10.5
13
1.5
13.5
16
Input (or feedback node) to internal feedback node delay time through PAL
Input (or feedback node) to internal feedback node delay time through PAL+PLA
Clock to internal feedback node delay time
ns
PDF_PAL
PDF_PLA
CF
ns
6.5
50
7.5
50
ns
Delay from valid V to valid reset
µs
INIT
DD
3
Input to output disable
14
15
ns
ER
Input to output valid
Input to register preset
Input to register reset
14
15
ns
EA
16
17
ns
RP
16
17
ns
RR
NOTES:
1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output C = 5pF.
L
89
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
SWITCHING CHARACTERISTICS
The test load circuit and load values for the AC Electrical Characteristics are illustrated below.
V
DD
COMPONENT
VALUES
390Ω
S1
R1
R2
C1
390Ω
R1
R2
35pF
V
IN
V
OUT
MEASUREMENT
S1
S2
C1
t
Open
Closed
Open
PZH
t
Closed
Closed
PZL
t
P
Closed
S2
NOTE: For t
and t
C = 5pF
PHZ
PLZ
SP00461A
VOLTAGE WAVEFORM
V
= 3.3V, 25°C
DD
10.00
9.80
9.60
9.40
9.20
9.00
8.80
8.60
8.40
8.20
8.00
+3.0V
90%
10%
0V
t
t
F
R
1.5ns
1.5ns
t
PD_PAL
(ns)
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
SP00368
1
2
4
8
12
16
NUMBER OF OUTPUTS SWITCHING
SP00462
Figure 6.
t
vs. Outputs Switching
PD_PAL
Table 3. t
DD
vs. Number of Outputs Switching
PD_PAL
V
= 3.3V
NUMBER OF
OUTPUTS
1
2
4
8
12
16
Typical (ns)
8.0
8.4
8.8
9.2
9.6
10.0
90
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PIN DESCRIPTIONS
PZ3064 – 44-Pin Plastic Leaded Chip Carrier
PZ3064 – 68-Pin Plastic Leaded Chip Carrier
6
1
40
9
1
61
7
39
10
26
60
LCC
LCC
17
44
29
18
28
27
43
Pin Function
Pin Function
Pin Function
Pin Function
Pin Function
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IN1
IN3
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I/O-B10
I/O-B8
I/O-B4
I/O-B3
I/O-B2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O-C13
I/O-C15 (TCK)
I/O-D15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IN1
IN3
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I/O-B10
I/O-B8
GND
I/O-B7
I/O-B5
I/O-B4
I/O-B3
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
I/O-C12
GND
I/O-D13
I/O-C15 (TCK)
I/O-D15
I/O-D13
V
V
DD
DD
I/O-D13
I/O-A0/CK3
I/O-A2
GND
I/O-A3
I/O-A4
I/O-A5
I/O-A7
I/O-A0/CK3
I/O-A2
I/O-A5
I/O-A8 (TDI)
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A15
V
DD
I/O-D12
I/O-D11
I/O-D8 (TDO)
I/O-D7
I/O-D2
I/O-D0
GND
IN0-CK0
IN2-gtsn
I/O-B0/CK2
GND
V
DD
V
I/O-D12
I/O-D11
I/O-D9
I/O-D8 (TDO)
GND
I/O-D7
I/O-D6
I/O-D4
I/O-D3
V
DD
DD
I/O-B2
I/O-B0/CK2
GND
I/O-C0/CK1
I/O-C2
I/O-C3
I/O-C4
I/O-C7
I/O-C8
GND
V
DD
I/O-A8 (TDI)
I/O-A10
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A15
I/O-B15 (TMS)*
I/O-B13
V
DD
I/O-C0/CK1
I/O-C2
GND
I/O-C3
I/O-C4
I/O-C5
I/O-C7
I/O-B15 (TMS)*
I/O-B13
V
DD
*
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
V
DD
I/O-D2
I/O-D0
GND
IN0/CK0
IN2-gtsn
SP00452A
V
DD
V
I/O-C8
I/O-C10
I/O-C11
DD
PZ3064 – 44-Pin Thin Quad Flat Package
I/O-B12
I/O-B11
44
34
*
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
1
33
23
SP00454
QFP
11
12
22
Pin Function
Pin Function
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I/O-A8
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A15
I/O-B15 (TMS)*
I/O-B13
V
DD
I/O-B10
I/O-B8
I/O-B4
I/O-B3
I/O-B2
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O-D11
I/O-D8 (TDO)
I/O-D7
I/O-D2
I/O-D0
GND
IN0/CK0
IN2-gtsn
IN1
V
DD
I/O-C0/CK1
I/O-C2
I/O-C3
I/O-C4
I/O-C7
I/O-C8
GND
I/O-C13
I/O-C15 (TCK)
I/O-D15
IN3
V
DD
I/O-A0/CK3
I/O-A2
I/O-A5
I/O-D13
V
DD
I/O-D12
I/O-B0/CK2
*
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
SP00453
91
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PZ3064 – 84-Pin Plastic Leaded Chip Carrier
PZ3064 – 100-Pin Plastic Quad Flat Package
100
81
11
1
75
1
80
12
32
74
QFP
LCC
51
30
54
31
50
33
53
Pin Function
Pin Function
Pin Function
Pin Function
Pin Function
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
IN1
IN3
V
DD
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
I/O-B10
I/O-B9
I/O-B8
GND
I/O-B7
I/O-B6
I/O-B5
I/O-B4
I/O-B3
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O-C11
I/O-C12
GND
I/O-C13
I/O-C14
I/O-C15 (TCK)
I/O-D15
I/O-D14
I/O-D13
1
2
3
4
5
6
7
8
9
NC
NC
I/O-A6
I/O-A7
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
I/O-B3
69
I/O-D12
I/O-D11
I/O-D10
NC
V
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
DD
I/O-B2
I/O-B1
I/O-B0/CK2
GND
I/O-A0/CK3
I/O-A1
I/O-A2
GND
I/O-A3
I/O-A4
I/O-A5
I/O-A6
I/O-A7
V
DD
I/O-D9
NC
I/O-A8 (TDI)
NC
I/O-A9
V
DD
I/O-D8 (TDO)
GND
I/O-C0/CK1
I/O-C1
I/O-C2
GND
I/O-C3
I/O-C4
I/O-C5
I/O-C6
I/O-C7
NC
NC
I/O-D7
I/O-D6
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I/O-A10
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A14
I/O-A15
I/O-B15 (TMS)*
I/O-B14
I/O-B13
V
V
DD
DD
I/O-B2
I/O-B1
I/O-B0/CK2
GND
I/O-D12
I/O-D11
I/O-D10
I/O-D9
I/O-D8 (TDO)
GND
I/O-D7
I/O-D6
I/O-D5
I/O-D4
NC
V
CC
I/O-D5
I/O-D4
I/O-D3
I/O-A8 (TDI)
I/O-A9
I/O-A10
I/O-A11
I/O-A12
GND
I/O-A13
I/O-A14
I/O-B15
I/O-B15 (TMS)*
I/O-B14
V
DD
I/O-C0/CK1
I/O-C1
I/O-C2
GND
I/O-C3
I/O-C4
I/O-C5
I/O-C6
I/O-C7
V
DD
NC
I/O-D2
I/O-D1
I/O-D0
GND
V
DD
V
DD
I/O-C8
NC
I/O-C9
NC
I/O-C10
I/O-C11
I/O-C12
GND
I/O-C13
I/O-C14
I/O-B12
I/O-B11
I/O-B10
NC
I/O-B9
NC
I/O-B8
GND
NC
I/O-D3
V
IN0/CK0
IN2-gtsn
IN1
DD
I/O-D2
I/O-D1
I/O-D0
GND
IN0/CK0
IN2-gtsn
I/O-B13
V
DD
IN3
V
I/O-C8
I/O-C9
I/O-C10
DD
V
DD
I/O-B12
I/O-B11
I/O-A0/CK3
I/O-A1
I/O-A2
GND
NC
I/O-C15 (TCK)
I/O-D15
I/O-D14
*
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
I/O-B7
I/O-B6
I/O-B5
I/O-B4
I/O-A3
I/O-A4
I/O-D13
SP00455
V
100 I/O-A5
DD
*
THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
SP00456
92
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
Package Thermal Characteristics
0
10
20
30
40
50
Philips Semiconductors uses the Temperature Sensitive Parameter
(TSP) method to test thermal resistance. This method meets
Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC
Package Databook. Thermal resistance varies slightly as a function
of input power. As input power increases, thermal resistance
changes approximately 5% for a 100% change in power.
PERCENTAGE
REDUCTION IN
Θ
(%)
JA
Figure 7 is a derating curve for the change in Θ with airflow based
JA
on wind tunnel measurements. It should be noted that the wind flow
dynamics are more complex and turbulent in actual applications
than in a wind tunnel. Also, the test boards used in the wind tunnel
contribute significantly to forced convection heat transfer, and may
not be similar to the actual circuit board, especially in size.
PLCC/
QFP
Package
44-pin PLCC
Θ
JA
0
1
2
3
4
5
AIR FLOW (m/s)
44.8°C/W
60.8°C/W
44.9°C/W
34.7°C/W
44.5°C/W
SP00419A
44-pin TQFP
68-pin PLCC
84-pin PLCC
100-pin PQFP
Figure 7. Average Effect of Airflow on Θ
JA
93
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
94
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm
SOT376-1
95
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
SOT188-3
96
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
PLCC84: plastic leaded chip carrier; 84 leads; pedestal
SOT189-3
97
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
QFP100: plastic quad flat package; 100 leads (lead length 1.6 mm); body 14 x 20 x 2.8 mm
SOT382-1
98
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
NOTES
99
1997 Mar 05
Philips Semiconductors
Product specification
64 macrocell CPLD
PZ3064
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips
Semiconductors
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