S32R274_技术文档

Document Number S32R274

Rev. 5, 04/2019

NXP Semiconductors

Data Sheet: Technical Data

S32R274

S32R274/S32R264 Series

Data Sheet

Supports S32R274K, S32R274J,

S32R264K and S32R264J

Features

• Functional Safety

– Enables up to ASIL-D applications

– FCCU for fault collection and fault handling

– MEMU for memory error management

– Safe eDMA controller

– Self-Test Control Unit (STCU2)

– Error Injection Module (EIM)

– On-chip voltage monitoring

• On-chip modules available within the device include

the following features:

• Safety core: Power Architecture® e200Z4 32-bit CPU

with checker core

• Dual issue computation cores: Power Architecture®

e200Z7 32-bit CPU

– Clock Monitor Unit (CMU)

• 2 MB on-chip code flash (FMC flash) with ECC

• 1.5 MB on-chip SRAM with ECC

• Security

– Cryptographic Security Engine (CSE2)

– Supports censorship and life-cycle management

• RADAR processing

– Signal Processing Toolbox (SPT) for RADAR signal

processing acceleration

– Cross Timing Engine (CTE) for precise timing

generation and triggering

– Waveform generation module (WGM) for chirp

ramp generation

– 4x 12-bit ΣΔ-ADC with 10 MSps

– One DAC with 10 MSps

• Timers

– Two Periodic Interval Timers (PIT) with 32-bit

counter resolution

– Three System Timer Module (STM)

– Three Software Watchdog Timers (SWT)

– Two eTimer modules with 6 channels each

– One FlexPWM module for 12 PWM signals

• Communication Interfaces

– MIPICSI2 interface to connect external ADCs

– Two Serial Peripheral interface (SPI) modules

– One LINFlexD module

• Memory Protection

– Each core memory protection unit provides 24

entries

– Two inter-IC communication interface (I2C)

modules

– Data and instruction bus system memory protection

unit (SMPU) with 16 region descriptors each

– Register protection

– One dual-channel FlexRay module with 128

message buffers

– Three FlexCAN modules with configurable buffers -

CAN FD optionally supported on 2 FlexCAN

modules

– One ENET MAC supporting MII/RMII/RGMII

interface

– ZipWire high-speed serial communication

• Clock Generation

– 40 MHz external crystal (XOSC)

– 16 MHz Internal oscillator (IRCOSC)

– Dual system PLL with one frequency modulated

phase-locked loop (FMPLL)

– Low-jitter PLL to ΣΔ-ADC and DAC clock

generation (not supported on SC66760x devices)

• Debug Functionality

– 4-pin JTAG interface and Nexus/Aurora interface

for serial high-speed tracing

– e200Z7 core and e200Z4 core: Nexus development

interface (NDI) per IEEE-ISTO 5001-2012 Class 3+

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

• Two analog-to-digital converters (SAR ADC)

– Each ADC supports up to 16 input channels

– Cross Trigger Unit (CTU)

• On-chip voltage DC/DC regulator for core clock (VREG)

• Two Temperature Sensors (TSENS)

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

2

NXP Semiconductors

Table of Contents

1

Introduction........................................................................................4

8.4 Data retention vs program/erase cycles...................................40

8.5 Flash memory AC timing specifications.................................40

8.6 Flash memory read wait-state and address-pipeline control

settings.....................................................................................41

Communication modules................................................................... 42

9.1 Ethernet switching specifications............................................42

9.2 FlexRay timing parameters..................................................... 47

9.3 LVDS Fast Asynchronous Transmission (LFAST) electrical

characteristics..........................................................................50

9.4 Serial Peripheral Interface (SPI) timing specifications...........54

9.5 LINFlexD timing specifications..............................................59

9.6 I2C timing .............................................................................. 59

1.1 Family comparison..................................................................4

1.2 Feature list...............................................................................5

1.3 Block diagram......................................................................... 9

Ordering parts.....................................................................................9

2.1 Determining valid orderable parts...........................................9

Part identification...............................................................................10

3.1 Description.............................................................................. 10

3.2 Fields....................................................................................... 10

General............................................................................................... 11

4.1 Absolute maximum ratings..................................................... 11

4.2 Operating conditions............................................................... 13

4.3 Supply current characteristics................................................. 15

4.4 Voltage regulator electrical characteristics............................. 16

4.5 Electromagnetic Compatibility (EMC) specifications............ 20

4.6 Electrostatic discharge (ESD) characteristics......................... 20

I/O Parameters....................................................................................21

5.1 I/O pad DC electrical characteristics ......................................21

5.2 I/O pad AC specifications....................................................... 22

5.3 Aurora LVDS driver electrical characteristics........................23

5.4 Reset pad electrical characteristics..........................................24

Peripheral operating requirements and behaviours............................26

6.1 Clocks and PLL Specifications............................................... 26

Analog modules................................................................................. 29

7.1 ADC electrical characteristics.................................................29

7.2 Sigma Delta ADC electrical characteristics............................33

7.3 DAC electrical specifications..................................................37

Memory modules............................................................................... 38

8.1 Flash memory program and erase specifications.................... 38

8.2 Flash memory Array Integrity and Margin Read

2

3

9

4

10 Debug modules...................................................................................60

10.1 JTAG/CJTAG interface timing .............................................. 60

10.2 Nexus Aurora debug port timing.............................................63

11 WKUP/NMI timing specifications.....................................................64

12 External interrupt timing (IRQ pin)................................................... 65

13 Temperature sensor electrical characteristics.....................................65

14 Radar module..................................................................................... 66

14.1 MIPICSI2 D-PHY electrical and timing specifications.......... 66

14.2 MIPICSI2 Disclaimer..............................................................69

15 Thermal Specifications.......................................................................71

15.1 Thermal characteristics........................................................... 71

16 Packaging........................................................................................... 73

17 Reset sequence................................................................................... 73

17.1 Reset sequence duration..........................................................74

17.2 Reset sequence description......................................................74

18 Power sequencing requirements.........................................................76

19 Pinouts................................................................................................77

19.1 Package pinouts and signal descriptions................................. 77

20 Revision History.................................................................................77

5

6

7

8

specifications...........................................................................39

8.3 Flash memory module life specifications................................39

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

3

Introduction

1 Introduction

1.1 Family comparison

The following table provides a comparison of the devices: S32R274, S32R264, and

MPC5775K . This information is intended to provide an understanding of the range of

functionality offered by this family. For full details of all of the family derivatives please

contact your marketing representative.

Table 1. S32R274 and S32R264 Family Comparison

Feature

S32R274K

S32R274J

S32R264K

e200z420 lock-step

2x e200z7260

S32R264J

MPC5775K

CPUs

SIMD

SPE2 + EFP2 (z7)

Maximum

Operating

Frequency

240 MHz (z7

cores) / 180 MHz

(z4)

266 MHz (z7

cores) / 133 MHz

(z4)

240 MHz (z7

cores) / 180 MHz

(z4)

266 MHz (z7

cores) / 133 MHz

(z4)

266 MHz (z7

cores) / 133 MHz

(z4)

Flash

EEPROM support

RAM

2 MB with ECC

64 KB (emulation)

1.5 MB with ECC

end-to-end

4 MB with ECC

96 KB (emulation)

ECC

MPU

Core MPU: 24 entries per core, System MPU: 2x16 entries

safe eDMA with 32 channels, 64 triggers

eDMA

Control ADC

2x 12-bit SAR ADC, 1 MSps input mux for 16 external channels

4x 12-bit SAR

ADC, 1 MSps, input

mux for 37 external

channels

SD-ADC

4 channels, 10 MSps

–

8 channels, 10

MSps

SPT

CTE

1x

WGM

CTU

1x

2x

4x

SWT

3x

2x

1x

STM

PIT

CRC

SEMA42

LINFlexD

CAN

3x FlexCAN including 2x FlexCAN-FD

4x FlexCAN + 1x

MCAN-FD

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

4

NXP Semiconductors

Introduction

Table 1. S32R274 and S32R264 Family Comparison (continued)

Feature

SPI

S32R274K

S32R274J

S32R264K

S32R264J

MPC5775K

2x

4x

3x

I²C

Zipwire

FlexRay

Ethernet

1x LFAST+SIPI, 320 MHz

1x dual channel

10/100 and >100 Mbps, RMII/MII/RGMII I/F, AVB support

10/100 Mbps,

RMII/MII I/F, AVB

support

FlexPWM

eTimer

1x, 12 PWM channels

2x, 6 channels each

2x, 12 PWM

channels each

3x, 6 channels

each

External ADC

interface

1x 4 lanes MIPICSI2 Rx, 1 Gbps/lane

1x PDI (16-bit data,

clock, sync)

IRCOSC

XOSC

16 MHz

40 MHz

FMPLL

dual system PLL, 1x FM modulated

1

DAC

1x 12-bit 10 MSps

–

1x 12-bit 2 MSps

SIUL2

1x

BAM

INTC

SSCM

FCCU/FOSU

MEMU

STCU2

CSE

1x

-

PASS/TDM

MC_ME

MC_CGM

MC_RGM

TSENS

1x

2x

Debug

JTAGC, JTAGM, CJTAG, with class3+ Nexus, Aurora only

ISO26262 SEooC ASIL-B to ASIL-D

-40 to 150˚C

Safety level

Temp. range (Tj)

1. DAC is not supported in S32R264x devices. Hence, ignore its occurrences in this document for S32R264K and S32R264J.

1.2 Feature list

On-chip modules available within the device include the following features:

• Safety core: Power Architecture^®e200Z4 32-bit CPU with checker core

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

5

Introduction

• 2 cycle delayed lockstep

• Harvard architecture with 64-bit bus for data and instructions

• Dual issue: up to two instructions per clock cycle

• 8 KB instruction cache and 4 KB data cache

• 64 KB data local memory

• with background load/store: backdoor access

• 0-wait state for all read and 32/64-bit write accesses

• Low number of wait states for backdoor accesses

• Support for decorated storage

• Variable Length Encoding (VLE) compliant for higher code density

• Single precision floating point operations

• Computation cores: Power Architecture^®e200Z7 32-bit CPU

• Dual issue: up to two instructions per clock cycle

• Harvard architecture with 64-bit bus for data instructions

• 16 KB instruction cache and 16 KB data cache

• 64 KB data local memory

• with background load/store: backdoor access

• 0-wait state for all read and 32/64-bit write accesses

• Low number of wait states for backdoor accesses

• Support for decorated storage

• Using variable length encoding (VLE) for higher code density

• 4-way integer processing unit (SPE2)

• 2-way single-precision Floating Point Unit (EFPU2)

• 2 MB on-chip code flash (FMC flash) with ECC

• Three ports (one per CPU) shared between code and data flash with 4 × 256 bit

buffer for code and data flash including prefetch functions

• Data flash is part of the code flash module

• Including 64 KB EEPROM emulation

• 1.5 MB on-chip SRAM with ECC

• Decorated memory controller to support atomic read-modify-write operations

• Single- and double-bit error visibility is supported

• Up to four ports (one per CPU and SPT) and up to 8 banks allow simultaneous

accesses from different masters to different banks

• RADAR processing

• Signal Processing Toolbox (SPT) for RADAR signal processing acceleration

• Cross Timing Engine (CTE) for precise timing generation and triggering

• Waveform generation module (WGM) for chirp ramp generation

• 4x 12-bit ΣΔ-ADC with 10 MSps (not supported on S32R264 devices)

• One DAC with 10 MSps (not supported on S32R264 devices)

• MIPICSI2 interface to connect external ADCs

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

6

NXP Semiconductors

Introduction

• Four data lanes, with up to 1 Gbps per lane and in total

• One clock lane

• Memory Protection

• Each core memory protection unit provides 24 entries

• Data and instruction bus system memory protection Unit (SMPU) with 16 region

descriptors each

• Register protection

• Clock Generation

• 40 MHz external crystal (XOSC)

• 16 MHz Internal oscillator (IRCOSC)

• Dual system PLL with one frequency modulated phase-locked loop (FMPLL)

• Low-jitter PLL to ΣΔ-ADC and DAC clock generation

• Functional Safety

• Enables up to ASIL-D applications

• End to end ECC ensuring full protection of all data accesses throughout the

system, from each of the systems masters through the crossbar and into the

memories and peripherals

• FCCU for fault collection and fault handling

• MEMU for memory error management

• Safe eDMA controller

• User selectable Memory BIST (MBIST) can be enabled to run out of various

reset conditions or during runtime

• Self-Test Control Unit (STCU2)

• Error Injection Module (EIM)

• On-chip voltage monitoring

• Clock Monitor Unit (CMU) to support monitoring of critical clocks

• Security

• Cryptographic Security Engine (CSE2) enabling advanced security management

• Supports censorship and life-cycle management via Password and Device

Security (PASS) module

• Diary control for tamper detection (TDM)

• Support Modules

• Global Interrupt controller (INTC) capable of routing interrupts to any CPU

• Semaphore unit to manage access to shared resources

• Two CRC computation units with four polynomials

• 32-channel eDMA controller with multiple transfer request sources using

DMAMUX

• Boot Assist Module (BAM) supports internal flash programming via a serial link

(LIN / CAN)

• Timers

• Two Periodic Interval Timers (PIT) with 32-bit counter resolution

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

7

Introduction

• Three System Timer Module (STM)

• Three Software Watchdog Timers (SWT)

• Two eTimer modules with 6 channels each

• One FlexPWM module for 12 PWM signals

• Communication Interfaces

• Two Serial Peripheral interface (SPI) module

• Two inter-IC communication interface (I2C) modules

• One LINFlexD module

• One dual-channel FlexRay module with 128 message buffers

• Three FlexCAN modules with configurable buffers

• CAN FD optionally supported on 2 FlexCAN modules

• One ENET MAC supporting MII/RMII/RGMII interface

• Supports 10/100 Mbps (MII/RMII/RGMII) and >100 Mbps (RGMII)

• Supports IEEE1588 timestamps and PTP

• Zipwire high-speed serial communication

• Supports LFAST and SIPI protocol

• Fast interprocessor communication with 320 Mbps gross data rate

• DMA based access to memory resources

• Debug Functionality

• 4-pin JTAG interface and Nexus/Aurora interface for serial high-speed tracing

• e200Z7 core and e200Z4 core: Nexus development interface (NDI) per IEEE-

ISTO 5001-2012 Class 3+

• All platform bus masters except CSE can be monitored via Nexus/Aurora

• Device/board boundary Scan testing supported with per Joint Test Action Group

(JTAG) (IEEE 1149.1) and 1149.7 (cJTAG)

• On-chip control for Nexus development interface by JTAGM module

• Two analog-to-digital converters (SAR ADC)

• Each ADC supports up to 16 input channels

• Cross Trigger Unit to enable synchronization of ADC conversions with eTimer

• On-chip voltage DC/DC regulator for core clock (VREG)

• Two Temperature Sensors (TSENS)

S32R264 feature changes with respect to S32R274 are as follows:

• SD-ADC’s removed

• DAC removed

• SDPLL replaced with AFEPLL

• Improved radiated emissions in the GLONASS band. Full EMC reports are available

from NXP on request for both S32R264, and S32R274 to allow the customer to

select the most suitable part for their usecase.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

8

NXP Semiconductors

Ordering parts

1.3 Block diagram

4x analog

4x lanes

MII/RMII/

RGMII

CJTAG

JTAGC

NPC

NAL

NAP

DTS

FR

diff. input

+ clock

Zipwire

INTC

PIT_1

SWT_1

STM_1

PIT_0

SWT_0

STM_0

4x

MIPICSI2

DMA

SRAM

(ECC)

SWT_2

STM_2

SDADC

Safety Lake

Nexus3+

e200z7260

Core2

e200z7260

Core1

E200z420

e200z419

Core0

VLE

Checker Core0

Acquisition

VLE

SPE2

FFT/

Processing

Sequencer

VLE

SPE2

VFPU

FPU

VLE

VFPU

Delay/

RCCU

FPU

64 KB

DTCM

Delay/

RCCU

64 KB

DTCM

Local

SRAM

(ECC)

16 KB

ICache

64 KB

DTCM

16 KB

Delay/

RCCU

DCache

ICache

DCache

8 KB

4 KB

FastDMA

e2eECC

async

ICache

DCache

Core MPU 24 Entries

BIU e2eECC

Core MPU 24 Entries

BIU e2eECC

Core MPU 24 Entries

BIU e2eECC

Core MPU 24 Entries

Safety Lake

Signal

BIU e2eECC

Processing

Toolbox (SPT)

e2eECC

Nexus Data

Trace

Nexus Data

Trace

Nexus Data

Trace

DAC

SD VREGs

SDPLL

CSE

Data Crossbar Switch (AMBA 2.0 v6 AHB) 64 bit

System memory Protection Unit SMPU_0

Instr. Crossbar Switch (AMBA 2.0 v6 AHB) 64- bit

System memory Protection Unit SMPU_1

IRCOSC

XOSC

TSENS_0/1

LVD

Dual

FMPLL

VREG

Triple

Ported

Flash Controller

(PFLASH)

Quad Ported

SRAM Controller

(PRAM)

Cal

AIPS-Lite_1

e2eECC

AIPS-Lite_0

e2eECC

2 MB Flash memory

up to 64 KB DFlash

ECC

1.5 MB SRAM

8 Banks

ECC

Figure 1. S32R274 block diagram

NOTE

S32R264 devices support AFE PLL while S32R274 devices

support SDPLL.

2 Ordering parts

2.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part

numbers for this device, go to www.nxp.com and perform a part number search for the

device number.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

9

Part identification

3 Part identification

3.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

3.2 Fields

This section lists the possible values for each field in the part number (not all

combinations are valid):

Table 2. Configuration

257MAPBGA

Configuration

Performance

Temperature

FS32R274KSK2MMM

FS32R274KCK2MMM

FS32R274VBK2MMM

FS32R274VCK2MMM

FS32R274KSK2VMM

FS32R274KCK2VMM

FS32R274VBK2VMM

FS32R274VCK2VMM

FS32R274JSK2MMM

FS32R264KBK0MMM

FS32R264KCK0MMM

FS32R264JBK0MMM

FS32R264JCK0MMM

S

C

B

C

S

C

B

C

S

B

C

B

C

K

V

K

V

J

M

V

M

K

J

Table 3. Configuration

Configuration

2 MB Flash

1.5 MB RAM

Yes

CSE

Yes

No

B or S

C

Yes

Table 4. Performance

Perf (MHz)

Z7

Z4

K

240

120

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

10

NXP Semiconductors

General

Table 4. Performance (continued)

Perf (MHz)

Z7

200

266

Z4

100

133

V

J

200

266

100

133

Table 5. Temperature values

Temperature

T_A

M

V

-40 ^oC to 125 ^oC

-40 ^oC to 105 ^oC

4 General

4.1 Absolute maximum ratings

NOTE

Functional operating conditions appear in the DC electrical

characteristics. Absolute maximum ratings are stress ratings

only, and functional operation at the maximum values is not

guaranteed.

Stress beyond the listed maximum values may affect device

reliability or cause permanent damage to the device.

Table 6. Absolute maximum ratings

Symbol

V_{DD_HV_PMU}

V_{DD_HV_REG3V8}

V_{DD_HV_IO*}

Parameter

Conditions

Min

–0.3

Max

Unit

V

3.3 V PMU supply voltage

REG3V8 Supply Voltage

—

4.0^{1, 2}

5.5

3.63^{1, 2}

V

3.3 V Input/Output Supply Voltage, LFAST IO

Supply, RGMII IO Supply and PWM IO Supply

V

V_{SS_HV_IOx}

V_{DD_HV_FLA}

V_{DD_HV_RAW}

V_{DD_HV_DAC}

V_{DD_LV_IO*}

V_DD

Input/output ground voltage

3.3 V flash supply voltage

AFE RAW supply voltage

AFE DAC supply voltage

Aurora supply voltage

1.25 V core supply voltage^{3, 4, 5}

1.25 V core supply ground^{3, 4, 5}

Oscillator amplifier ground

—

–0.1

–0.3

–0.1

–0.3

–0.1

0.1

3.63^{1, 2}

4

V

4

1.5

0.3

0.1

V_SS

V_{SS_LV_OSC}

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

11

General

Table 6. Absolute maximum ratings (continued)

Symbol

V_{DD_LV_PLL0}

Parameter

Conditions

Min

–0.3

–0.1

Max

1.5

5.5

0.1

Unit

V

System PLL supply voltage

—

V_{DD_LV_LFASTPLL}LFAST PLL supply voltage

V

V_{DD_HV_ADCREF0/1}ADC_0 and ADC_1 high reference voltage

V

V_{SS_HV_ADCREF0/1}ADC_0 and ADC_1 ground and low reference

voltage

V

V_{DD_HV_ADC}

V_{SS_HV_ADC}

TV_DD

3.3 V ADC supply voltage

—

–0.3

–0.1

4.0 ^{1, 2}

0.1

V

3.3 V ADC supply ground

Supply ramp rate⁶

0.00005

-0.3

0.1

V/μs

V

V_{IN_XOSC}

V_INA

Voltage on XOSC pins with respect to ground

Voltage on SAR ADC analog pin with respect to

1.47

6.0

–0.3

V

ground (V_{SS_HV_ADCREFx}

)

V_{INA_SD}

Voltage on Sigma-Delta ADC analog pin with

respect to ground⁷

Powered up ⁸

-0.3

–0.3

V_{DD_HV_RAW}

0.3

+

V

Powered down

1.47

9

V_IN

Voltage on any digital pin with respect to

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}+ 0.3

V

10

ground (V_{SS_HV_IOx}

)

V_{DD_LV_DPHY}

V_{SS_LV_DPHY}

I_INJPAD

MIPICSI2 DPHY voltage supply^{3, 4, 5}

MIPICSI2 DPHY supply ground^{3, 4, 5}

—

–0.3

–10

1.5

0.3

10¹²

V

Injected input current on any pin during

overload condition¹¹

mA

I_INJSUM

T_STG

Absolute sum of all injected input currents

during overload condition

—

–50

–55

50

mA

°C

Storage temperature

150

1. 5.3 V for 10 hours cumulative over lifetime of device; 3.3 V +10% for time remaining.

2. Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.

3. 1.45 V to 1.5 V allowed for 60 seconds cumulative time at maximum T_J= 150°C; remaining time as defined in note 5 and

note 6.

4. 1.375 V to 1.45 V allowed for 10 hours cumulative time at maximum T_J= 150°C; remaining time as defined in note 6.

5. 1.32 V to 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at

maximum T_J=150°C.

6. TV_DDis relevant for all external supplies.

7. ADC inputs include an overvoltage detect function that detects any voltage higher than 1.2 V with respect to ground on

either ADC input and open circuit (disconnect) the input in order to prevent damage to the ADC internal circuitry. The ADC

input remains disconnected until the inputs return to the normal operating range.

8. SDADC is powered up and overvoltage protection is ON.

9. SDADC is powered up and overvoltage protection is OFF.

10. Only when V_{DD_HV_IOx}< 3.63 V.

11. No input current injection circuitry on AFE pins.

12. The maximum value of 10 mA applies to pulse injection only. DC current injection is limited to a maximum of 5 mA.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

12

NXP Semiconductors

General

4.2 Operating conditions

The following table describes the operating conditions for the device, and for which all

specifications in the datasheet are valid, except where explicitly noted. The device

operating conditions must not be exceeded, or the functionality of the device is not

guaranteed.

Table 7. Device operating conditions

Symbol

V_{DD_HV_PMU}

V_{DD_HV_REG3V8}

V_DD

Parameter

Conditions

Min

3.13²

3.13

1.19²

3.13²

Typ

3.3

Max¹

3.6

Unit

V

3.3V PMU Supply Voltage

REG3V8 Supply Voltage

Core Supply Voltage

—

3.8

5.5

1.31³

V

1.25

3.3

V

V_{DD_HV_IO*}

Main GPIO 3V Supply

Voltage, LFAST IO Supply,

RGMII IO Supply, PWM IO

Supply Voltage

3.6

V

4

V_{DD_LV_IO_*}

Aurora Supply Voltage

—

1.19

1.19²

1.19

3.13²

1.25

—

1.31

3.6

V

V_{DD_LV_PLL0}

System PLL Supply Voltage

V_{DD_LV_LFASTPLL}LFAST PLL Supply Voltage

—

5

V_{DD_HV_FLA}

Flash Supply Voltage

3.3

V_{DD_HV_ADC}

V_{DD_HV_RAW}

V_{DD_HV_DAC}

SAR ADC Supply Voltage

(HVD supervised)

3.6⁶

3.3V AFE RAW Supply

Voltage

—

3.13

—

3.3

—

3.6

V

3.3V AFE DAC Supply

Voltage

—

V

V_{DD_HV_ADCREF0/1}ADC_0 and ADC_1 high

reference voltage

—

V

V_IN

Voltage on digital pin with

respect to ground (V_{SS_HV_IOx}

—

Differential

—

V_{DD_HV_IOx}

+0.3

)

V_INSDPP

Sigma-Delta ADC Input

Voltage (peak-peak)^{7, 8}

—

1.2

165

40.25

25

V

V_INSR

Sigma-Delta ADC Input Slew

Rate⁷

—

V/μs

kΩ

R_{TRIM_TOL}

R_{TRIM_TEMPCO}

External Trim Resistor

tolerance

0.1%

—

40.16

—

40.2

—

External Trim Resistor

Temperature Coefficient

ppm/°C

V

9

V_INA

Voltage on SAR ADC analog

pin with respect to ground

—

V_{DD_HV_ADCRE}

Fx

(V_{SS_HV_ADCREFx}

)

V_{DD_LV_DPHY}

MIPICSI2 DPHY voltage

supply¹⁰

1.19

–40

1.25

—

1.31

125

V

, 11

T_A

Ambient temperature at full

performance ¹²

—

°C

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

13

General

Table 7. Device operating conditions (continued)

Symbol

Parameter

Conditions

Min

–40

—

Typ

—

Max¹

150

—

Unit

°C

11

T_J

Junction temperature

XOSC Crystal Frequency¹³

—

F_XTAL

—

40

MHz

AFE Bypass Modes Only

Single-Ended External Clock¹⁴

EXTAL_clk

V_inxoscjit

V_inxoscclkvil

V_inxoscclkvih

t_r/t_f

EXTAL external clock

frequency

40

—

MHz

ps

V

EXTAL external clock Cycle to

Cycle Jitter (RMS)

—

0

2.5¹⁵

0.4

1.23

1

EXTAL external clock input

low voltage

EXTAL external clock input

high voltage

1

V

Rise/fall time of EXTAL

external clock input

ns

%

t_dc

Duty Cycle of EXTAL external

clock input

47

50

40

53

Differential LVDS External Clock

LVDS_clk

LVDS external clock

frequency

MHz

V

LVDSV_inxoscclk

LVDS external clock input

voltage

0

1.36

1.12

LVDSV_{inxoscclk(p-p)}LVDS external clock input

voltage (peak-peak)

Voltage driven,

AC coupled

0.45

0.70

3.5

V

Differential

LVDSI_inxoscclk

LVDS external clock input

current

Current driven,

DC coupled.

3.0

4.0

mA

LVDSV_inxoscjit

t_r/t_f

LVDS external clock Jitter

(RMS) ¹⁵

2.5

1.5

53

ps

ns

%

Rise/fall time of LVDS

external clock input

20% - 80%

t_dcLVDS

Duty Cycle of LVDS external

clock input

47

50

1. Full functionality cannot be guaranteed when voltages are out of the recommended operating conditions.

2. Min voltage takes into account the LVD variation.

3. Max voltage takes into account HVD variation.

4. Aurora supply must connect to core supply voltage at board level.

5. The ground connection for the V_{DD_HV_FLA}is shared with V_SS

.

6. Supply range does not take into account HVD levels. Full range can be achieved after power-up, if HVD is disabled. See

Voltage regulator electrical characteristics section for details.

7. Around common mode voltage of 0.7 V. Input voltage cannot exceed 1.4 V prior to AFE start-up completion (VREF and

VREGs on and LVDs cleared).

8. SDADC input voltage full scale is 1.2 Vpp

9. On channels shared between ADC0 and 1, V_{DD_HV_ADCREFx}is the lower of V_{DD_HV_ADCREF0/1.}

10. V_{DD_LV_DPHY}supply should be shorted to core supply voltage VDD on board. Refer to AN5251. Contact your NXP sales

representative for details.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

14

NXP Semiconductors

General

11. While determining if the operating temperature specifications are met, either the ambient temperature or junction

temperature specification can be used. It is critical that the junction temperature specification is not exceeded under any

condition.

12. Full performance means full frequency.

13. Recommended Crystal 40 MHz (ESR≤30 Ω), 8 pF load capacitance.

14. External mode can be used as differential input with EXTAL and XTAL

15. The number is 3.5 ps when SD-ADC and/or DAC is not used in the device.

4.3 Supply current characteristics

Current consumption data is given in the following table. These specifications are design

targets and are subject to change per device characterization.

Table 8. Current consumption characteristics

Symbol

Parameter

Conditions

Min Typ Max Unit

I_{DD_CORE}

Core current in run mode All cores at max frequency. 1.31 V. Tj = 150°C (240

MHz)

-

1480¹mA

1642¹

All cores at max frequency. 1.31 V. Tj = 150°C (266

MHz)

I_{DD_HV_FLA}

Flash operating current

Tj = 150°C. V_{DD_HV_FLA}= 3.6 V

-

3²

-

40³

60

mA

I_{DD_LV_AURORA}Aurora operating current Tj = 150°C. V_{DD_LV_AURORA}= 1.31 V. 4 TX lanes

enabled.

I_{DD_HV_ADC}

ADC operating current

Tj = 150°C. V_{DD_HV_ADC}= 3.6 V. 2 ADCs operating

at 80 MHz.

-

2

5

mA

I_{DD_HV_ADCREF}Reference current per

ADC⁴

Tj = 150°C. V_{DD_HV_ADCREFx}= 3.6 V. ADC operating

at 80 MHz.

-

1.5

0.75

Reference current per

temp sensor⁵

I_{DD_HV_RAW}

I_{DD_HV_DAC}

I_{DD_HV_PMU}

I_{DD_LV_DPHY}

AFE SD and regulator

operating current

Tj = 150°C. V_{DD_HV_RAW}= 3.6 V. SD-PLL, AFE

regulators and 4 SD enabled.

-

70⁶

10

2

75

15

10

mA

AFE DAC operating

current

Tj = 150°C. V_{DD_HV_DAC}= 3.6 V. DAC enabled.

PMU operating current

Tj = 150°C. VDD_HV_PMU = 3.6 V. Internal

regulation enabled.

MIPICSI2 DPHY

operating current in HS-

RX mode

Tj = 150°C, V_{DD_LV_DPHY}=1.31 V

14.9 23.2

1. Strong dependence on use case, cache usage.

2. Measured during flash read.

3. Peak Flash current measured during read while write (RWW) operation.

4. ADC0 and 1 on ADCREF0/1.

5. Temp sensor current when PMC_CTL_TD[TSx_AOUT_EN] = 1. TS0 on ADCREF0/1.

6. Typical number is approximately 10 mA per each SD-ADC enabled, 12 mA for SD-PLL and 15 mA for the AFE regulators.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

15

General

4.4 Voltage regulator electrical characteristics

Table 9. Voltage regulator electrical specifications

Symbol

POR-R

Parameter

Conditions

—

Min

0.97

Typ

1.02

Max

1.06

Unit

V

1.25 V VDD core POR release

1.25 V VDD core POR engage

POR-E

—

0.93

0.98

1.02

V

LVD12R

Low-Voltage Detection 1.25 V release (Core

VDD supply, and PLL0/1 supply LVDs)

Untrimmed

Trimmed

Untrimmed

Trimmed

1.122

1.142

1.102

1.122

1.33

1.157

1.137

1.35

1.192

1.172

1.152

1.37

V

LVD12R-trim

LVD12E

V

Low-Voltage Detection 1.25 V engage (Core

VDD supply and PLL0/1 supply LVDs)

V

LVD12E-trim

HVD12R-trim

V

High-Voltage Detection 1.25 V release

(Core VDD)

V

HVD12E-trim

High-Voltage Detection 1.25 V engage

(Core VDD supply)

Trimmed

1.36

1.130

1.111

2.54

1.38

1.157

1.137

2.645

2.60

1.40

1.184

1.163

2.735

2.695

V

LVD_MIPI12R-trim

LVD_MIPI12E-trim

Low-Voltage Detection 1.25V release

(MIPICSI2 DPHY supply)

—

Low-Voltage Detection 1.25V engage

(MIPICSI2 DPHY supply)

POR-R-

VDD_HV_PMU

3.3 V PMU supply voltage POR release

threshold

POR-E-

VDD_HV_PMU

3.3 V PMU supply voltage POR engage

threshold

2.50

LVD33R

LVD33R-trim

LVD33E

3.3V Low-Voltage Detection Release

Threshold (PMC, FLASH, IO, ADC)

Untrimmed

Trimmed

2.90

3.00

2.86

2.96

3.45

3.47

3.51

2.75

3.02

3.05

2.98

3.01

3.61

3.53

3.65

3.57

2.90

3.13

3.10

3.09

3.06

3.75

3.58

3.79

3.62

3.05

V

3.3V Low-Voltage Detection Engage

Threshold (PMC, FLASH, IO, ADC)

Untrimmed

Trimmed

LVD33E-trim

HVD33R

3.3V High-Voltage Detection Release

Threshold (ADC)

Untrimmed

Trimmed

HVD33R-trim

HVD33E

3.3V High-Voltage Detection Engage

Threshold (ADC)

Untrimmed

Trimmed

HVD33E-trim

UVL30R

SMPS under-voltage lockout release

threshold

Untrimmed

UVL25E

SMPS under-voltage lockout engage

threshold

2.40

2.0

5

2.55

3.5

7

2.7

5

V

DGLITCHE

DGLITCHR

Voltage Detector Deglitcher Filter Time -

Engage

—

µs

Voltage Detector Deglitcher Filter Time -

Release

12

RSTDGLTC

RSTPUP

VREG_POR_B Input Deglitch Filter Time

VREG_POR_B Pin Pull-up Resistance

VREG_SEL Pin Pull-up Resistance

Internal switched regulator output voltage ¹Load Current from 10 1.19

mA to 1.8 A

—

200

37

320

75

500

150

1.35

ns

kΩ

V

REGENPUP

VSMPS

37

75

1.255

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

16

NXP Semiconductors

General

Table 9. Voltage regulator electrical specifications (continued)

Symbol

Parameter

Conditions

Min

0.65

0.93

—

Typ

1.00

7.5

15

Max

1.35

1.07

—

Unit

MHz

%

FSMPS

Internal switched regulator operating

frequency without modulation

Untrimmed

Trimmed

FSMPS-M7.5

FSMPS-M15

FSMPS-M30

VREGSWPUP

Internal switched regulator frequency

modulation

—

%

—

30

—

%

Internal switched regulator gate-driver pull-

up resistance²

—

VREF_BG_T

PMC bandgap reference voltage for

SARADC

Trimmed

—

1.20

1.22

—

1.237

V

Vih (VREG_POR_B)

VREG_POR_B pin High Voltage level

0.7 x

VDD_H

V_PMU

VDD_H

V_PMU

+ 0.3

Vil (VREG_POR_B)

LVDAFER

VREG_POR_B pin Low Voltage level

—

-0.3

2.75

2.68

—

0.3 x

VDD_H

V_PMU

V

Low Voltage Detection 3.3V Release (AFE

VDD_HV_DAC and VDD_HV_RAW

supplies)

2.80

2.77

2.90

2.86

LVDAFEE

Low Voltage Detection 3.3V Engage (AFE

VDD_HV_DAC and VDD_HV_RAW

supplies)

1. Min/Max includes transient load conditions. Steady state voltage is within the core supply operating specifications.

2. There is a strong pull up from VREG_SWP to VDD_HV_REG3V8 which is connected when SMPS is disabled. The pullup

has resistance less than 1 Kohm, therefore VREG_SWP should not be connected to ground if unused.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

17

General

Figure 2. SMPS External Components Configuration

Table 10. SMPS External Components

Ref

M1

L1

Description

SI3443, 2SQ2315

2.2 uH 3A < 100 mΩ series resistance (Ex. Bourns SRU8043-2R2Y)

SS8P3L 8A Schottcky Diode

D1

R1

C1

C2

C3

C4

C5

C6

C7

C8

C9

24 kΩ

10 μF Ceramic

100 nF Ceramic

100 nF Ceramic (place close to inductor)

10 uF Ceramic (place close to inductor)

1 nF Ceramic

4 x 100 nF + 4 x 10nF Ceramic (place close to MCU supply pins)

4 x 10 μF Ceramic (place close to MCU supply pins)

100 nF Ceramic

1 μF Ceramic (Unless C1 is really close to the pin)

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

18

NXP Semiconductors

General

Figure 3. Radar AFE External Components Configuration

Table 11. Radar AFE External Components

Component Component

Value

Tolerance

Placement

Priority of

Placement Special notes

Priority of

larger cap. ¹smaller cap¹

C1

C2

0.47 μF

0.1 μF

1.0 μF

0.1 μF

1.0 μF

0.1 μF

1.0 μF

0.1 μF

1.0 μF

0.1 μF

1.0 μF

0.1 μF

1.0 μF

0.1 μF

1.0 μF

0.1μF

35%

3

—

7

—

1

—

C3

—

4

C4

2

C5

—

8

C6

—

6

C7

—

6

C8

—

5

C9

—

4

C10

C11

C12

C13

C14

C15

C16

C17

—

2

—

5

—

3

—

10

—

9

—

8

—

7

—

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

19

General

Table 11. Radar AFE External Components (continued)

Component Component

Value

Tolerance

Placement

Priority of

Placement Special notes

Priority of

larger cap. ¹smaller cap¹

C18

C19

10 μF

—

1

—

X7R type

220 nF

—

Sigma Delta ADC input capacitor. See Figure

9

C20

220 nF

—

Sigma Delta ADC input capacitor. See Figure

9

R1

R2

40.2 kΩ

300 Ω

0.1%

—

tempco = 25ppm/C

DAC Rl See Table 27

R3

300 Ω

—

Crystal

40MHz

—

Connected between XOSC_EXTAL/

XOSC_XTAL, ESR ≤ 30Ω

1. All Radar AFE external bypass capacitors should be placed as close as possible to the associated package pin. As shown

in Radar AFE External Components Configuration figure, most pins have two values of bypass capacitor. Greater than 0.1

μF is referred to as the larger cap. 0.1 μF is referred to as the smaller cap.

4.5 Electromagnetic Compatibility (EMC) specifications

EMC measurements to IC-level IEC standards are available from NXP on request.

4.6 Electrostatic discharge (ESD) characteristics

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This

test conforms to the AEC-Q100-002/-003/-011 standard.

NOTE

A device will be defined as a failure if after exposure to ESD

pulses the device no longer meets the device specification

requirements. Complete DC parametric and functional testing

shall be performed per applicable device specification at room

temperature followed by hot temperature, unless specified

otherwise in the device specification.

Table 12. ESD ratings

No.

Symbol

Parameter

Electrostatic discharge

(Human Body Model)

Conditions¹

Class

Max value²

Unit

1

V_ESD(HBM)

T_A= 25 °C

H1C

2000

V

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S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

20

NXP Semiconductors

I/O Parameters

Table 12. ESD ratings (continued)

No.

Symbol

Parameter

Conditions¹

Class

Max value²

Unit

conforming to AEC-

Q100-002

2

V_ESD(CDM)

Electrostatic discharge

(Charged Device Model)

T_A= 25 °C

C3A

500³

V

conforming to AEC-

Q100-011

750 (corners)

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. Data based on characterization results, not tested in production.

3. 500 V for non-AFE pins, 250 V for AFE pins.

5 I/O Parameters

5.1 I/O pad DC electrical characteristics

NMI, TCK, TMS, JCOMP are treated as GPIO.

Table 13. I/O pad DC electrical specifications

Symbol

Parameter

Value

Unit

Min

Max

Vih_hys

Vil_hys

Vih

CMOS Input Buffer High Voltage (with hysteresis

enabled)

0.65*V_{DD_HV_IO}V_{DD_HV_IO}+ 0.3

V

CMOS Input Buffer Low Voltage (with hysteresis

enabled)

-0.3

0.35*V_{DD_HV_IO}

CMOS Input Buffer High Voltage (with hysteresis

disabled)

0.55 * V_{DD_HV_IO}V_{DD_HV_IO}+ 0.3

Vil

CMOS Input Buffer Low Voltage (with hysteresis

disabled)

-0.3

0.40 * V_{DD_HV_IO}

Vhys

CMOS Input Buffer Hysteresis

0.1 * V_{DD_HV_IO}

2

—

V_{DD_HV_ADCREFx}

+ 0.3

V

Vih_TTL

TTL Input high level voltage (All SAR_ADC input pins)

Vil_TTL

Vhyst_TTL

Pull_Ioh

Pull_Iol

Iinact_d

Voh

TTL Input low level voltage (All SAR_ADC input pins)

TTL Input hysteresis voltage (All SAR_ADC input pins)

Weak Pullup Current¹

-0.3

0.56

V

0.3

—

10

55

µA

V

Weak Pulldown Current²

10

55

Digital Pad Input Leakage Current (weak pull inactive)

Output High Voltage³

-2.5

2.5

0.8 * V_{DD_HV_IO}

—

Vol

Output Low Voltage⁴

—

18

0.2 * V_{DD_HV_IO}

V

Ioh_f

Full drive Ioh⁵(ipp_sre[1:0] = 11)

Full drive Iol⁵(ipp_sre[1:0] = 11)

Half drive Ioh⁵(ipp_sre[1:0] = 10)

Half drive Iol⁵(ipp_sre[1:0] = 10)

70

120

35

mA

Iol_f

21

Ioh_h

Iol_h

9

10.5

60

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

21

I/O Parameters

1. Measured when pad = 0 V

2. Measured when pad = V_{DD_HV_IO}

3. Measured when pad is sourcing 2 mA

4. Measured when pad is sinking 2 mA

5. Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.

5.1.1 RGMII pad DC electrical characteristics

Table 14. RGMII pad DC electrical specifications

Symbol

Parameter

Value

Unit

Min

Max

Vih

CMOS Input Buffer High Voltage

CMOS Input Buffer Low Voltage

Weak Pullup Current¹

0.65 x V_{DD_HV_IO}

V_{DD_HV_IO}+ 0.3

V

Vil

-0.3

10

0.35 x V_{DD_HV_IO}

V

Pull_Ioh

Pull_Iol

Iinact_d

55

µA

Weak Pulldown Current²

10

Digital Pad Input Leakage Current (weak pull

inactive)

-2.5

2.5

Voh

Vol

Output High Voltage³

Output Low Voltage⁴

Full drive Ioh⁵

0.8 x V_{DD_HV_IO}

—

V

—

8

0.2 * V_{DD_HV_IO}

Ioh_f

Iol_f

26

24

mA

Full drive Iol⁶

8

1. Measured when pad = 0 V

2. Measured when pad = V_{DD_HV_IO}

3. Measured when pad is sourcing 2 mA

4. Measured when pad is sinking 2 mA

5. Ioh_f value is measured with 0.8*VDDE applied to the pad.

6. Iol_f is measured when 0.2*VDDE is applied to the pad.

5.2 I/O pad AC specifications

AC Parameters are specified over the full operating junction temperature range of -40°C

to +150°C and for the full operating range of the V_{DD_HV_IO}supply defined in Table 7.

Table 15. Functional Pad electrical characteristics

Symbol

Prop. Delay (ns)¹

Rise/Fall Edge (ns)²

Drive Load (pF)

SIUL2_MSCR[SRC

]

L>H/H>L

Min

2.5/2.5

6.4/5

Max

8.25/7.5

19.5/19.5

8/8

Min

Max

3/3

MSB,LSB

pad_sr_hv

(output)

0.7/0.6

2.5/2.0

0.4/0.3

1.0/0.8

6.5/3.0

50

200

25

11

12/12

3.5/3.5

6.5/6.5

25/21

2.2/2.5

2.9/3.5

11/8

10

12.5/11

35/31

50

200

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

22

NXP Semiconductors

I/O Parameters

Table 15. Functional Pad electrical characteristics (continued)

Symbol

Prop. Delay (ns)¹

Rise/Fall Edge (ns)²

Drive Load (pF)

SIUL2_MSCR[SRC

]

L>H/H>L

Min

8.3/9.6

13.5/15

13/13

Max

45/45

65/65

75/75

100/100

2/2

Min

4/3.5

Max

25/25

30/30

40/40

51/51

0.5/0.5

MSB,LSB

50

200

50

01³

6.3/6.2

6.8/6

00³

NA

21/22

11/11

200

0.5

pad_sr_hv

(input)⁴

1. As measured from 50% of core side input to Voh/Vol of the output

2. Measured from 20% - 80% of output voltage swing

3. Slew rate control modes

4. Input slope = 2ns

NOTE

Data based on characterization results, not tested in production.

Table 16. Functional Pad AC Specifications

Symbol

Parameter

Value

Typ

4.7

Unit

Min

Max

pad_sr_hv(Cp)

Parasitic Input Pin Capacitance

4.5

5.0

pF

5.3 Aurora LVDS driver electrical characteristics

NOTE

The Aurora interface is AC coupled, so there is no common-

mode voltage specification.

Table 17. Aurora LVDS driver electrical characteristics

Symbol

Parameter¹

Value

Typ

—

Unit

Min

—

Max

F_TXRX

Data rate

1.15

Gbps

Transmitter Specifications

V_diffout

Differential output voltage swing (terminated)

Rise/Fall time (10% - 90% of swing)

+/- 400

60

+/- 600

+/- 800

mV

ps

T_rise/T_fall

Receiver Specifications

V_diffin

Differential voltage

+/- 100

mV

Termination

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

23

I/O Parameters

Symbol

Table 17. Aurora LVDS driver electrical characteristics (continued)

Parameter¹

Value

Typ

Unit

Min

Max

101

1

R_{V_L}

C_P

Terminating Resistance (external)

Parasitic Capacitance (pad + bondwire + pin)

Parasitic Inductance

99

100

Ohms

pF

L_P

7

nH

STARTUP

T_{STRT_BIAS}

T_{STRT_TX}

Bias startup time

Transmitter startup time²

Receiver startup time²

Receiver o/p duty cycle

—

30

—

5

µs

%

T_{STRT_RX}

LVDS_RXOUT³

5

70

1. Conditions for these values are V_{DD_LV_IO_AURORA}= 1.19V to 1.32V, T_J= –40 / 150 °C

2. Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down

(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.

3. Receiver o/p duty cycle is measured with 1.25 Gbps, 50% duty cycle, max 1 ns rise/fall time, 100 mV voltage swing signal

applied at the receiver input.

5.4 Reset pad electrical characteristics

The device implements a dedicated bidirectional RESET_B pin.

V

DD_HV_IOx

V

DDMIN

RESET_B

V

IH

V

IL

device reset forced by RESET_B

device start-up phase

Figure 4. Start-up reset requirements

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

24

NXP Semiconductors

I/O Parameters

V_{RESET_B}

hw_rst

‘1’

V

DD_HV_IO

V

IH

V

IL

‘0’

filtered by

lowpass filter

unknown reset

state

filtered by

hysteresis

filtered by

lowpass filter

device under hardware reset

W

FRST

W

NFRST

Figure 5. Noise filtering on reset signal

Table 18. RESET_B electrical characteristics

Symbol

Parameter

Conditions¹

Value

Unit

Min

Typ

Max

V_IH

Input high level TTL (Schmitt Trigger)

—

2.0

—

V_{DD_HV_IOx}

0.4

+

V

V_IL

Input low level TTL (Schmitt Trigger)

Input hysteresis TTL (Schmitt Trigger)

Strong pull-down current

—

–0.4

300

0.2

—

0.56

—

V

2

V_HYS

—

mV

mA

I_{OL_R}

Device under power-on reset

V_{DD_HV_IO}= 1.2 V

V_OL= 0.35 x V_{DD_HV_IO}

Device under power-on reset

V_{DD_HV_IO}=3.0 V

V_OL= 0.35 x V_{DD_HV_IO}

—

15

—

mA

W_FRST

RESET_B input filtered pulse

—

500

—

ns

µA

W_NFRST

RESET_B input not filtered pulse

—

2400

30

|I_WPD

|

Weak pull-down current absolute value V_IN= V_{DD_HV_IOx}

100

1. V_{DD_HV_IOx}= 3.3 V -5%,+10%, T_J= –40 / 150°C, unless otherwise specified.

2. Data based on characterization results, not tested in production.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

25

Peripheral operating requirements and behaviours

6 Peripheral operating requirements and behaviours

6.1 Clocks and PLL Specifications

6.1.1 40 MHz Oscillator (XOSC) electrical characteristics

The device provides an oscillator/resonator driver.

NOTE

XTAL/EXTAL must not be directly used to drive external

circuits.

Table 19. XOSC electrical characteristics

Symbol

XOSC_fout

t_stab

Parameter

Conditions

Min

Typ

Max

Unit

MHz

ms

Oscillator frequency

Oscillator start-up time

40

2

t_jitcc

Cycle to cycle jitter (peak –

peak)

2.5¹

ps

Output Duty Cycle

Input Capacitance ²

45

3.0

75

50

4.0

100

55

5.0

125

%

pF

Cin

Extal and Xtal each

R_inLVDS

LVDS bypass mode input

termination³

Between Extal and Xtal

ohm

V_CMLVDS

LVDS Common Mode

Voltage

Vdda/2

0.60

0.70

0.80

V

1. The number is 3.5 ps when SD-ADC and/or DAC is not used in the device.

2. When using a 40 MHz crystal, the recommended load capacitance is 8 pF. Need quiet ground connection on the board

and external crystal/load capacitor placement as close to the Extal and Xtal pins as possible to allow good jitter

performance.

3. The termination resistance is only active when the AFE is powered (VDD_HV_RAW, VDD_HV_DAC and the AFE

regulators are powered up) and the XOSC is powered down (default case once device is out of reset) or the XOSC is

configured in differential bypass mode.

6.1.2 FMPLL electrical characteristics

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

26

NXP Semiconductors

Clocks and PLL Specifications

PLL_0_PHI0

IRCOSC

XOSC

PLL_0

PLL_0_PHI1

PLL_1_PHI0

PLL_1

Figure 6. PLL integration

Table 20. PLL0 electrical characteristics

Symbol

f_PLL0IN

Parameter

PLL0 input clock^{2, 3}

Conditions¹

Min

14

Typ

—

Max

44

Unit

MHz

%

—

_PLL0IN

PLL0 input clock duty cycle²

PLL0 VCO frequency

PLL0 output clock PHI0

PLL0 output clock PHI1

PLL0 lock time

—

40

—

60

f_PLL0VCO

f_PLL0PHI0

f_PLL0PHI1

t_PLL0LOCK

_PLL0LTJ

—

600

4.76

20

—

1250

625⁴

156

100

1

MHz

µs

—

PLL0 long term jitter f_PLL0IN= 8 MHz

(resonator)⁵

f_PLL0PHI0= 40 MHz, 1 μs

f_PLL0PHI0= 40 MHz, 13 μs

ns

1

ns

I_PLL0

PLL0 consumption

—

5

mA

1. V_{DD_LV_PLL0}=1.25 V 5%, T_J= -40 / 150 °C unless otherwise specified.

2. PLL0IN clock retrieved directly from either IRCOSC or external XOSC clock.

3. f_PLL0INfrequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure the reference clock to the PLL analog

loop is in the range 8 MHz-20 MHz

4. The maximum clock outputs are limited by the design clock frequency requirements as per recommended operating

conditions.

5. V_{DD_LV_PLL0}noise due to application in the range V_{DD_LV_PLL0}= 1.25 V 5%, with frequency below PLL bandwidth (40 KHz)

will be filtered.

Table 21. FMPLL1 electrical characteristics

Symbol

f_PLL1IN

Parameter

PLL1 input clock²

PLL1 input clock duty cycle²

PLL1 VCO frequency

PLL1 output clock PHI0

PLL1 lock time

Conditions¹

Min

38

Typ

—

Max

78

Unit

MHz

%

—

_PLL1IN

—

35

65

f_PLL1VCO

f_PLL1PHI0

t_PLL1LOCK

f_PLL1MOD

|δ_PLL1MOD

—

600

4.76

—

1250

625

100

250

2

MHz

µs

—

PLL1 modulation frequency

—

kHz

%

|

PLL1 modulation depth (when

enabled)

Center spread

Down spread

0.25

0.5

—

4

%

I_PLL1

PLL1 consumption

6

mA

1. V_{DD_LV_PLL0}= 1.25 V 5%, T_J= -40 / 150°C unless otherwise specified.

2. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

27

Clocks and PLL Specifications

6.1.3 16 MHz Internal RC Oscillator (IRCOSC) electrical specifications

Table 22. Internal RC Oscillator electrical specifications

Symbol

F_Target

Parameter

IRC target frequency

Conditions

Min

—

Typ

16

—

Max

—

24

8

Unit

MHz

%

—

F_untrimmed

δF_var

IRC frequency (untrimmed)

IRC trimmed frequency variation ¹

Startup time

9.6

-8

—

T_startup

—

5

µs

1. The typical user trim step size (δf_TRIM) is 0.3% of current frequency for application of positive trim and 0.26% of current

frequency for application of negative trim, based on characterization results.

6.1.4 320 MHz AFE PLL electrical characteristics

Table 23. 320 MHz AFE PLL parameters

Symbol

PLL_fout

Parameter

Output Frequency

Conditions

Min

Typ

320

Max

Unit

MHz

—

PLL_fin

t_cal

Input Frequency

Calibration Time ¹

—

40

MHz

µs

LW64 = 1

LW64 = 0

after calibration

—

150

500

75

t_lock

t_jitcck

—

Lock Time

—

48

—

50

µs

ps

%

Cycle to cycle jitter (peak – peak)

Output duty cycle

10

—

52

1. The LW64 bit sets the wait time before the PLL frequency is measured after each calibration step to allow for stabilization.

If LW64 is '0', wait time of 256 reference clock cycles is used. If LW64 is'1', wait time of 64 reference clock cycles is used.

6.1.5 LFAST PLL electrical characteristics

The specifications in the following table apply to the interprocessor bus LFAST interface.

Table 24. LFAST PLL electrical characteristics

Symbol

f_{RF_REF}

ERR_REF

DC_REF

f_VCO

Parameter

Condition

Min

10

–1

45

—

Typ

—

Max

26

1

Unit

MHz

%

PLL reference clock frequency

PLL reference clock frequency error

PLL reference clock duty cycle

PLL VCO frequency

—

640¹

55

—

%

MHz

μs

t_LOCK

PLL phase lock²

—

40

300

ΔPER_REF

Input reference clock jitter (peak to peak) Single period, f_{RF_REF}

10 MHz

=

—

ps

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

28

NXP Semiconductors

Analog modules

Table 24. LFAST PLL electrical characteristics

(continued)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Long term, f_{RF_REF}= 10 –500

MHz

—

500

ΔPER_EYE

Output Eye Jitter (peak to peak)³

Random Jitter (Rj)

—

84

80

101

96

ps

Deterministic Jitter (Dj)

Total Jitter @BER 10^-9

1.09

1.31

bits

per

second

I_{VDD_LV_LFASTPLL}

V_{DD_LV_LFASTPLL}Supply Current

Normal Mode

Peak

—

6

7

10

11

27

mA

μA

Power Down

0.5

1. The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO

frequency is 624 MHz.

2. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral

bridge clock that is connected to the PLL on the device.

3. Measured at the transmitter output across a 100 Ω termination resistor on a device evaluation board.

7 Analog modules

7.1 ADC electrical characteristics

The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-

Digital Converter.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

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29

Analog modules

Offset Error OSE Gain Error GE

4095

4094

4093

4092

4091

4090

(2)

1 LSB ideal =(VrefH-VrefL)/ 4096 =

3.3V/ 4096 = 0.806 mV

Total Unadjusted Error

TUE = +/- 6 LSB = +/- 4.84mV

code out₇

(1)

6

5

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer

curve

(5)

4

3

(4)

(3)

2

1

1 LSB (ideal)

0

1

2

3

4

5

6

7

4089 4090 4091 4092 4093 4094 4095

V_in(A)(LSB_ideal

)

Offset Error OSE

Figure 7. ADC characteristics and error definitions

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

30

NXP Semiconductors

Analog modules

7.1.1 Input equivalent circuit

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Sampling

Selection

Source

Filter

Current Limiter

R

S

F

L

SW1

AD

C

V

C

P1

C

S

A

F

P2

R

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance

Sampling Switch Impedance

S

F

L

R

C

R

C

SW1

AD

P

Pin Capacitance (two contributions, C and C

Sampling Capacitance

)

P1

P2

S

Figure 8. Input equivalent circuit

Table 25. ADC conversion characteristics

Symbol

Parameter

Conditions¹

Min

Typ

Max

Unit

f_CK

ADC Clock frequency (depends on

ADC configuration) (The duty cycle

depends on AD_CK²frequency.)

—

20

80

MHz

f_s

Sampling frequency

Sample time³

—

1.00 MHz

t_sample

80 MHz@ 200 ohm source

impedance

275

—

ns

t_sampleC

T_sampleS

T_sampleBG

T_sampleTS

t_conv

SAR selftest C-algorithm sample time

SAR selftest S-algorithm sample time

Bandgap sample time

—

300

1

—

3

—

5

ns

µs

—

1.87

3.18

650

—

µs

Temperature sensor sample time

Conversion time⁴

—

µs

80 MHz

ns

, 5

C_S

ADC input sampling capacitance

ADC input pin capacitance 1

ADC input pin capacitance 2

Internal resistance of analog source

Integral non-linearity

—

pF

5

C_P1

—

5

pF

5

C_P2

—

0.8

875

825

2

pF

5

R_SW1

V_REFrange = 3.0 to 3.6 V

—

Ω

5

R_AD

—

Ω

INL

DNL

OFS

GNE

–2

LSB

Differential non-linearity⁶

–1

1

Offset error

–4

4

Gain error

–4

4

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

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31

Analog modules

Symbol

Table 25. ADC conversion characteristics (continued)

Parameter

Conditions¹

Min

–6

Typ

—

Max

6

Unit

LSB

TUE_IS1WINJTotal unadjusted error for IS1WINJ

TUE_IS1WWINJTotal unadjusted error for IS1WWINJ

IS1WINJ (pad (single ADC channel)

–6

—

6

going to one

nA

Max leakage

150 °C

—

250

3⁸

ADC)

Max positive/negative injection

–3

mA

IS1WWINJ (double ADC channel)

(pad going to

two ADCs)

nA

mA

dB

Max leakage

Max positive/negative injection ⁷

—

300

3.6

—

|Vref_ad0 - Vref_ad1| < 150 mV

3.3 V reference voltage

@ 50 KHz

–3.6

67

SNR

THD

Signal-to-noise ratio

Total harmonic distortion

Signal-to-noise and distortion

Effective number of bits

65

—

dB

SINAD

ENOB

Fin < 50 KHz

6.02 x ENOB + 1.76

10.5

dB

Fin < 50 KHz

—

bits

1. V_{DD_HV_ADC}= 3.3 V -5%,+10%, T_J= –40 to +150°C, unless otherwise specified and analog input voltage from V_AGNDto

V_{DD_HV_ADCREFx}

.

2. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

3. During the sample time the input capacitance C_Scan be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_sample. After the end of the

sample time t_sample, changes of the analog input voltage have no effect on the conversion result. Values for the sample

clock t_sampledepend on programming.

4. This parameter does not include the sample time t_sample, but only the time for determining the digital result and the time to

load the result register with the conversion result.

5. SeeInput equivalent circuit figure.

6. No missing codes.

7. ADC specifications are met only if injection is within these specified limits

8. Max injection current for all ADC IOs is 10 mA

NOTE

The ADC performance specifications are not guaranteed if two

ADCs simultaneously sample the same shared channel. Aurora

interface along with SAR-ADC would degrade SAR-ADC

performance. General Purpose Input (GPI) functionality should

not be used on any of the SAR-ADC channels when SARADC

is functional.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

32

NXP Semiconductors

Analog modules

7.2 Sigma Delta ADC electrical characteristics

Figure 9. ADC input equivalent circuit

Table 26. Sigma Delta ADC Parameters

Symbol

SPS_SDA

L_SDA

Parameter

Sample Rate

Latency

Condition

Min

—

Typ

10

Max Unit

After Decimation Filtering

10

MS/S

µs

@ 10 MS/s, full step input to 50% output.

Decimation filter delay not included

—

0.1

RT_SDA

Recovery Time

After overload condition

—

0.5

—

µs

, 1

SNR_{SDA_MM_ON}

Signal-to-Noise Ratio Input Frequency Range and integration

Mismatch Shaper on bandwidth are from 20 KHz to 5 MHz (using

full-bandwidth decimation filter coefficients).

Production test frequencies 449 KHz and 4

MHz. Production test amplitude is -6 dBFS =

0.6 Vpp.

63

67

dBFS

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

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33

Analog modules

Symbol

Table 26. Sigma Delta ADC Parameters (continued)

Parameter

Condition

Min

Typ

Max Unit

Characterized under the following conditions:

• 0.6 Vpp (i.e. -6 dBFS) input signals

applied at the following frequencies one

at a time: 20.77 KHz, 317.7 KHz, 857.7

KHz, 1.411 MHz, 2.95 MHz, 3.897

MHz, and 4.997 MHz and the SNR in

dBFS is then calculated.

• SNR at 5 MHz will be reduced by 5 dB

due to decimation filter roll off.

• The SNR is specified to be 67 dBFS

typical for input frequencies between 20

KHz and 4 MHz. Mismatch shaper on.

1

SNR_{SDA_MM_OFF}

Signal-to-Noise Ratio Input Frequency Range and integration

Mismatch Shaper off bandwidth are from 20 KHz to 5 MHz. (using

full-bandwidth decimation filter coefficients).

Production test frequencies 449 KHz and 4

MHz. Production test amplitude is -6 dBFS =

0.6 Vpp.

65

67

—

dBFS

Characterized under the following conditions:

• 0.6 Vpp (i.e. -6dBFS) input signals

applied at the following frequencies one

at a time: 20.77 KHz, 317.7 KHz, 857.7

KHz, 1.411 MHz, 2.95 MHz, 3.897

MHz, and 4.997 MHz and the SNR in

dBFS is then calculated.

• SNR at 5 MHz will be reduced by 5 dB

due to decimation filter roll off.

• The SNR is specified to be 67 dBFS

typical for input frequencies between 20

KHz and 4 MHz. Mismatch shaper off.

1

SNDR_{SDA_MM_ON}Signal-to-Noise-and- Input Frequency Range and integration

Distortion Ratio bandwidth are from 20 KHz to 5 MHz. (using

62

64

Mismatch Shaper on full-bandwidth decimation filter coefficients).

Production test frequencies 449 KHz and 4

MHz. Production test amplitude is -6 dBFS =

0.6 Vpp.

Characterized under the following conditions:

• 0.6 Vpp (i.e. -6 dBFS) input signals

applied at the following frequencies one

at a time: 20.77 KHz, 317.7 KHz, 857.7

KHz, 1.411 MHz, 2.95 MHz, 3.897

MHz, and 4.997 MHz and the SNDR in

dBFS is then calculated.

• SNR at 5 MHz will be reduced by 5 dB

due to decimation filter roll off.

• The SNR is specified to be 64 dBFS

typical for input frequencies between 20

KHz and 4 MHz. Mismatch shaper on.

1

SNDR_{SDA_MM_OFF}Signal-to-Noise-and- Input Frequency Range and integration

Distortion Ratio bandwidth are from 20 KHz to 5 MHz. (using

60

62

Mismatch Shaper off full-bandwidth decimation filter coefficients)

Table continues on the next page...

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NXP Semiconductors

Analog modules

Max Unit

Table 26. Sigma Delta ADC Parameters (continued)

Symbol

Parameter

Condition

Min

Typ

Production test frequencies 449 KHz and 4

MHz. Production test amplitude is -6 dBFS =

0.6Vpp.

Characterized under the following conditions:

• 0.6 Vpp (i.e. -6 dBFS) input signals

applied at the following frequencies

applied one at a time: 20.77 KHz, 317.7

KHz, 857.7 KHz, 1.411 MHz, 2.95 MHz,

3.897 MHz, and 4.997 MHz and the

SNDR in dBFS is then calculated.

• SNR at 5 MHz will be reduced by 5 dB

due to decimation filter roll off.

• The SNR is specified to be 62 dBFS

typical for input frequencies between 20

KHz and 4 MHz. Mismatch shaper off.

IFDR_SDA

Interference Free

Dynamic Range

20 ms integration, ADC inputs tied together at 90

the package pin. One side of the AC coupling

capacitors associated with each input should

remain connected to the ADC input and the

other side of the capacitor should connected

to ground.

—

dBFS

dBc

IMD_{SDA_MM_ON}

Intermodulation

Input Frequency Range and integration

62

Distortion Mismatch bandwidth are from 20 KHz to 5 MHz (using

Shaper on

full-bandwidth decimation filter coefficients).

Characterized under the following conditions:

• Two distinct sets of signal pairs at the

specified frequencies and at an

amplitude of -8 dBFs (i.e. 0.23886

Vpeak = 0.47772 Vpp differential) are

applied one signal pair at a time.

• Signal pair #1 is f1 = 1 MHz and f2 =

1.1 MHz and signal pair #2 is f1 =

390.625 KHz and f2 = 546.875 KHz.

• All inter modulation products are

checked. Mismatch Shaper on.

IMD_{SDA_MM_OFF}

Intermodulation

Input Frequency Range and integration

55

—

dBc

Distortion Mismatch bandwidth are from 20 KHz to 5 MHz (using

Shaper off

full-bandwidth decimation filter coefficients).

Characterized under the following conditions:

• Two distinct sets of signal pairs at the

specified frequencies and at an

amplitude of -8 dBFs (i.e. 0.23886

Vpeak = 0.47772 Vpp differential) are

applied one signal pair at a time.

• Signal pair #1 is f1 = 1 MHz and f2 =

1.1 MHz and signal pair #2 is f1 =

390.625 KHz and f2 = 546.875 KHz.

• All inter modulation products are

checked. Mismatch Shaper off.

GM

OE

Gain Mismatching

Input Offset Error

(ADCx to ADCy)

—

-3.5

-25

—

3.5

25

%

mV

Table continues on the next page...

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

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35

Analog modules

Table 26. Sigma Delta ADC Parameters (continued)

Symbol

Parameter

Condition

Min

Typ

Max Unit

OEV

Offset Variation

t = 50 ms, T = constant, data averaged in 1

ms increments

-0.07

—

0.07

mV

V_cm

Common Mode

Voltage²

SDADC switched on

—

vdda/2 –

30 mV

—

V

xtalk

Crosstalk (from any Processing a full scale signal.

—

-40

dB

ADC to the other

ADCs)

Zin

Input Impedance

Maximum input impedance occurs for input

7.3

—

33.5

kΩ

signals at 20 KHz and minimum input

impedance occurs at input frequencies

greater than 1 MHz³

R_cm

Resistance from

each SDADC input to

V_cm(see Figure 9)

-

27.3

9.0

32.2

37.0

12.5

kΩ

R_SDADC

Resistance from

each SDADC input

pin to differential

amplifier input (see

Figure 9)

-

10.75

C_SDADC

SDADC integrator

capacitors (see

Figure 9)

-

0.636

2.0

0.684

3.9

0.732

4.9

pF

C_inparasitic

parasitic input

-

capacitance from

ADC input to ground

DT

AA

Analog Delay

Variation

(ADCx to ADCy)

—

2

1

—

3

ns

dB

Alias Suppression

ADC input frequency between 315 and 325

MHz

50

0

STFoob

ADC out of band

Signal Transfer

Function peaking

Out of band Signal Transfer function peaking

from 20 MHz to 40 MHz

PR

passband ripple

From 20 KHz to 4 MHz (default decimation

filter coefficients must be used)

-0.5

0.0

—

0.5

—

dB

OOBA⁴

Out Of Band

Attenuation

Default decimation filter coefficients must be

used

-4.5

-10

-20

-40

-60

5 MHz

6 MHz

7 MHz

10 MHz

15 MHz

1. Derate specification by 2 dBFS for T_jless than 0°C.

2. vdda is an internally regulated and trimmed 1.45V 10mV voltage.

3. The input structure of the ADC is an active RC integrator which has a frequency dependent input impedance as indicated

in ADC input equivalent circuit.

4. All attenuation values are relative to 0 dB in the ADC passband.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

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NXP Semiconductors

Analog modules

7.3 DAC electrical specifications

NOTE

• All data is measured in single ended mode. Differential

mode is guaranteed by design.

• Specifications guaranteed only if factory trims are not

overridden.

Table 27. DAC parameters

Symbol

N_BIT

Parameter

Condition

Min

Typ

Max

Unit

Bits

Base bits

PWM bits

—

12

—

Bits

4

(extra

lsb's)

SPS_DAC

Sample rate

Linearity¹

—

10

—

MSam

ples/s

DNL

V_out

I_out

-24

1.2

4.0

—

4

LSB

V

Output Voltage^{1, 2, 3}

Single-Ended, Rl = 300 Ω

1.35

4.5

Full-Scale Output Current

DAC full-scale adjust bits set to

01 or 10

mA

N_DAC

DAC output noise ^{1, 4}

Static Offset Error^{1, 2}

—

nV/

sqrt(Hz

)

@250 kHz

@100 kHz

@10 kHz

@1 kHz

20

30

65

170

SOE

Single-Ended

60

75

0

100

30

mV

Differential with the full-scale

adjust bits set to either 01 or 10

-30

TOE

t_DV

Transient Offset Error^{1, 2, 5}

After low-pass filter and

averaging

—

0.05

LSB

ns

Transient Time Delay Variation ^{1, 2, 6}

LSB step

MSB step

1

10

Oc

Output compliance

single-ended, only the DNL

0

—

1.35

V

specification is guaranteed. The

TOE and Tdv may be degraded.

tempco

PSRR

Temperature coefficient

—

–1

30

—

1.0

—

LSB/K

2

Power Supply Rejection Ratio⁷

Freq < 250 KHz

dB

1. DAC linearity, output swing, noise, TOE, and Tdv specifications are all based upon a 300 Ω DAC output load resistor and

assume that the full-scale adjust bits are set to either 01 or 10. These specifications will NOT be met for other DAC output

load resistor values.

2. Once all of the LVDs have cleared and the DAC is powered on, a one-time wait time of 300 ms is required before the DAC

output signal is valid.

3. The full-scale DAC output is trimmed to 1.30 V 10 mV with all DAC inputs set to 1 including both full-scale adjust bits.

4. Rl = 300 Ω, 10uF capacitor between Vdd_HV_DAC and DAC_C, ideal supply

5. Difference between ideal and real (Va+Vb/2), for all base and PWM LSBs

6. Falling edge to falling edge or rising edge to rising edge. Any transition DACn -> DACn + 1

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

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Memory modules

7. DAC PSRR is 30 dB minimum for DAC output levels of 1/3 of full-scale or less. DAC PSRR is 24 dB minimum with the

DAC output at full-scale.

8 Memory modules

8.1 Flash memory program and erase specifications

NOTE

All timing, voltage, and current numbers specified in this

section are defined for a single embedded flash memory within

an SoC, and represent average currents for given supplies and

operations.

Table 28 shows the estimated Program/Erase times.

Table 28. Flash memory program and erase specifications

Symbol

Characteristic¹

Typ²

Factory

Field Update

Unit

Programming^{3, 4}

Initial

Max

Initial

Max, Full

Temp

Typical

End of

Life⁵

Lifetime Max⁶

20°C ≤T_A-40°C ≤T_J-40°C ≤T_J≤ 1,000 ≤ 250,000

≤30°C ≤150°C ≤150°C cycles cycles

t_dwpgm

Doubleword (64 bits) program time 43

100 150 55 500

μs

t_ppgm

Page (256 bits) program time

73

200

800

300

108

396

500

μs

t_qppgm

Quad-page (1024 bits) program

time

268

1,200

2,000

t_16kers

16 KB Block erase time

16 KB Block program time

32 KB Block erase time

32 KB Block program time

64 KB Block erase time

64 KB Block program time

256 KB Block erase time

256 KB Block program time

168

34

290

45

320

50

250

40

1,000

1,200

1,600

4,000

ms

t_16kpgm

t_32kers

t_32kpgm

t_64kers

217

69

360

100

490

180

1,520

720

390

110

590

210

2,030

880

310

90

315

138

884

552

420

170

1,080

650

t_64kpgm

t_256kers

t_256kpgm

—

1. Program times are actual hardware programming times and do not include software overhead. Block program times

assume quad-page programming.

2. Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

3. Conditions: ≤ 150 cycles, nominal voltage.

4. Plant Programing times provide guidance for timeout limits used in the factory.

5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations.

6. Conditions: -40°C ≤ T_J≤ 150°C, full spec voltage.

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8.2 Flash memory Array Integrity and Margin Read specifications

Table 29. Flash memory Array Integrity and Margin Read specifications

Symbol

Characteristic

Min

Typical

Max¹

Units

2

t_ai16kseq

Array Integrity time for sequential sequence on 16 KB block.

—

512 x

Tperiod x

Nread

—

t_ai32kseq

Array Integrity time for sequential sequence on 32 KB block.

Array Integrity time for sequential sequence on 64 KB block.

Array Integrity time for sequential sequence on 256 KB block.

—

1024 x

Tperiod x

Nread

t_ai64kseq

2048 x

Tperiod x

Nread

8192 x

Tperiod x

Nread

tai256kseq

t_mr16kseq

t_mr32kseq

t_mr64kseq

t_mr256kseq

Margin Read time for sequential sequence on 16 KB block.

Margin Read time for sequential sequence on 32 KB block.

Margin Read time for sequential sequence on 64 KB block.

Margin Read time for sequential sequence on 256 KB block.

73.81

128.43

237.65

893.01

—

110.7

192.6

μs

356.5

1,339.5

1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The

equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and

Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires

6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the

address pipeline set to 2, Nread would equal 4 (or 6 - 2).)

2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the

equation, the results of the equation are also unit accurate.

8.3 Flash memory module life specifications

Table 30. Flash memory module life specifications

Symbol

Characteristic

Conditions

Min

Typical

Units

P/E

Array P/E

cycles

Number of program/erase cycles per block

for 16 KB, 32 KB and 64 KB blocks.¹

—

250,000

—

cycles

Number of program/erase cycles per block

for 256 KB blocks.²

1,000

250,000

P/E

cycles

Data

retention

Minimum data retention.

Blocks with 0 - 1,000 P/E 50

cycles.

—

Years

Blocks with 100,000 P/E

cycles.

20

Blocks with 250,000 P/E

cycles.

10

1. Program and erase supported across standard temperature specs.

2. Program and erase supported across standard temperature specs.

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8.4 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the

following figure. The spec window represents qualified limits. The extrapolated dotted

line demonstrates technology capability, however is beyond the qualification limits.

8.5 Flash memory AC timing specifications

Table 31. Flash memory AC timing specifications

Symbol

Characteristic

Min

Typical

Max

Units

t_psus

Time from setting the MCR-PSUS bit until MCR-DONE bit is set

to a 1.

—

9.4

11.5

μs

plus four

system

clock

plus four

system

clock

periods

t_esus

Time from setting the MCR-ESUS bit until MCR-DONE bit is set

to a 1.

—

16

20.8

μs

plus four

system

clock

plus four

system

clock

periods

Table continues on the next page...

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Table 31. Flash memory AC timing specifications (continued)

Symbol

Characteristic

Min

Typical

Max

Units

t_res

Time from clearing the MCR-ESUS or PSUS bit with EHV = 1

until DONE goes low.

—

100

ns

t_done

Time from 0 to 1 transition on the MCR-EHV bit initiating a

program/erase until the MCR-DONE bit is cleared.

—

5

ns

μs

t_dones

Time from 1 to 0 transition on the MCR-EHV bit aborting a

program/erase until the MCR-DONE bit is set to a 1.

16

20.8

plus four

system

clock

plus four

system

clock

periods

t_drcv

Time to recover once exiting low power mode.

16

—

45

μs

plus seven

system

clock

plus seven

system

clock

periods.

periods

t_aistart

Time from 0 to 1 transition of UT0-AIE initiating a Margin Read

or Array Integrity until the UT0-AID bit is cleared. This time also

applies to the resuming from a suspend or breakpoint by

clearing AISUS or clearing NAIBP

—

5

ns

t_aistop

Time from 1 to 0 transition of UT0-AIE initiating an Array

Integrity abort until the UT0-AID bit is set. This time also applies

to the UT0-AISUS to UT0-AID setting in the event of a Array

Integrity suspend request.

—

80

plus fifteen

system

clock

periods

t_mrstop

Time from 1 to 0 transition of UT0-AIE initiating a Margin Read

abort until the UT0-AID bit is set. This time also applies to the

UT0-AISUS to UT0-AID setting in the event of a Margin Read

suspend request.

10.36

—

20.42

μs

plus four

system

clock

plus four

system

clock

periods

8.6 Flash memory read wait-state and address-pipeline control

settings

The following table describes the recommended settings of the Flash Memory

Controller's PFCR1,2,3[RWSC] and PCRC1,2,3[APC] fields at various operating

frequencies, based on specified intrinsic flash memory access timed of the Flash memory.

Table 32. Flash read wait state and address pipeline control guidelines

Operating Frequency (fsys = SYS_CLK)

RWSC

APC

Flash read latency on

min-cache miss (# of

fcpu clock periods)

Flash read latency

on mini-cache hit (#

of fcpu clock

periods)

0 MHz < fsys <= 33 MHz

0

3

1

Table continues on the next page...

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Table 32. Flash read wait state and address pipeline control guidelines (continued)

Operating Frequency (fsys = SYS_CLK)

RWSC

APC

Flash read latency on

min-cache miss (# of

fcpu clock periods)

Flash read latency

on mini-cache hit (#

of fcpu clock

periods)

33 MHz < fsys <= 100 MHz

100 MHz < fsys <= 120 MHz

2

3

1

5

6

1

9 Communication modules

9.1 Ethernet switching specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

9.1.1 MII signal switching specifications

The following timing specs meet the requirements for MII style interfaces for a range of

transceiver devices.

• Measurements are with input transition of 1 ns and output load of 25 pF.

Table 33. MII signal switching specifications

Symbol

—

Description

Min.

—

Max.

25

Unit

MHz

RXCLK frequency

RXCLK pulse width high

MII1

35%

65%

RXCLK

period

RXCLK

period

ns

MII2

RXCLK pulse width low

35%

65%

MII3

MII4

—

RXD[3:0], RXDV, RXER to RXCLK setup

RXCLK to RXD[3:0], RXDV, RXER hold

TXCLK frequency

5

—

ns

—

25

MHz

MII5

TXCLK pulse width high

35%

65%

TXCLK

period

TXCLK

period

ns

MII6

TXCLK pulse width low

35%

65%

MII7

MII8

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

2

—

25

ns

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MII6

MII5

MII7

TXCLK (input)

TXD[n:0]

TXEN

MII8

Valid data

TXER

Figure 10. MII transmit signal timing diagram

MII2

MII1

RXCLK (input)

RXD[n:0]

RXDV

MII3

MII4

Valid data

RXER

Figure 11. MII receive signal timing diagram

9.1.2 RMII signal switching specifications

The following timing specs meet the requirements for RMII style interfaces for a range of

transceiver devices.

• Measurements are with input transition of 1 ns and output load of 25 pF.

Table 34. RMII signal switching specifications

Num

—

Description

Min.

—

Max.

50

Unit

EXTAL frequency (RMII input clock RMII_CLK)

RMII_CLK pulse width high

MHz

RMII1

35%

65%

RMII_CLK

period

RMII2

RMII_CLK pulse width low

35%

65%

RMII_CLK

period

RMII3

RMII4

RMII7

RXD[1:0], CRS_DV, RXER to RMII_CLK setup

RMII_CLK to RXD[1:0], CRS_DV, RXER hold

RMII_CLK to TXD[1:0], TXEN invalid

4

2

4

—

ns

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Table 34. RMII signal switching specifications

(continued)

Num

Description

RMII_CLK to TXD[1:0], TXEN valid

Min.

Max.

Unit

RMII8

—

15

ns

RMII2

RMII1

RMII7

RMII_CLK (input)

RMII8

Valid data

TXD[n:0]

TXER

Valid data

Figure 12. RMII transmit signal timing diagram

RMII2

RMII1

RMII_CLK (input)

RXD[n:0]

RMII3

RMII4

Valid data

CRS_DV

RXER

Figure 13. RMII receive signal timing diagram

9.1.3 RGMII signal switching specifications

The RGMII interface works at 3.3 V compatible levels as mentioned in RGMII pad DC

electrical characteristics.

The following timing specs meet the requirements for RGMII style interfaces for a range

of transceiver devices.

• Measurements are with input transition of 0.750 ns and output load of 10 pF.

Table 35. RGMII signal switching specifications

Symbol Description

Min

48

Typ

—

Max

52

Unit

%

Notes

—

Input Duty cycle (Clock from external PHY)

Clock cycle duration

Tcyc

7.2

-500

1

8.0

0

8.8

500

2.6

ns

1

2

TskewT Data to clock output skew at transmitter

TskewR Data to clock input skew at receiver

ps

1.8

ns

Table continues on the next page...

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Table 35. RGMII signal switching specifications

(continued)

Symbol Description

Min

45

Typ

50

Max

55

Unit

%

Notes

Duty_G Duty cycle for Gigabit

Duty_T Duty cycle for 10/100T

3

40

50

60

%

Tr/Tf

Rise/fall time (20–80%)

—

1.5

ns

1. For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns 40 ns and 40 ns 4 ns respectively.

2. For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an

additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100

the Max value is unspecified.

3. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as

long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed

transitioned between.

TXC (at transmitter)

TskewT

TXD[8:5]

TXD[7:4]

TXD[3:0]

TXD[n:0]

TXD[4]

TXEN

TXD[9]

TXERR

TX_CTL

TskewR

TXC (at receiver)

Figure 14. RGMII transmit signal timing diagram

RXC (at transmitter)

TskewT

RXD[8:5]

RXD[7:4]

RXD[n:0]

RXD[3:0]

RXD[4]

RXDV

RXD[9]

RXERR

RX_CTL

TskewR

RXC (at receiver)

Figure 15. RGMII receive signal timing diagram

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9.1.4 MII/RMII Serial Management channel timing (MDC/MDIO)

The MDC/MDIO interface works at 3.3V compatible levels as mentioned in CMOS input

(vih/vil/voh/vol/)values in I/O pad DC electrical characteristics .

Ethernet works with maximum frequency of MDC at 2.5 MHz. Output pads configured

with SRC=11. MDIO pin must have external pull-up. Measurements are with input

transition of 1.0 ns and output load of 50 pF.

Table 36. Ethernet MDIO timing table

Num

Description

Min.

Max.

2.5

Unit

MHz

ns

MDC00 MDC clock frequency

—

MDC10 MDC falling edge to MDIO

output invalid (minimum

propagation delay)

(-0.8 +

(ENET_MSCR[HOLDTIME]

+1)*(PBRIDGE_n_CLK period in

ns))

—

MDC11 MDC falling edge to MDIO

output valid (maximum

—

(13 + (ENET_MSCR[HOLDTIME]

+1)*(PBRIDGE_n_CLK period in

ns))

ns

propagation delay)

MDC12 MDIO (input) to MDC rising

edge setup

13

0

—

ns

MDC13 MDIO (input) to MDC rising

edge hold

—

MDC14 MDC pulse width high

MDC15 MDC pulse width low

40%

60%

MDC Period

MDC14

MDC15

MDC (output)

MDC10

MDC11

MDIO (output)

MDIO (input)

MDC12

MDC13

Figure 16. RMII/MII serial management channel timing diagram

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9.2 FlexRay timing parameters

This section provides the FlexRay interface timing characteristics for the input and output

signals. These numbers are recommended per the FlexRay Electrical Physical Layer

Specification, Version 3.0.1, and subject to change per the final timing analysis of the

device.

9.2.1 TxEN

TxEN

80 %

20 %

dCCTxEN

FALL

RISE

Figure 17. FlexRay TxEN signal

Table 37. TxEN output characteristics¹

Name

Description

Min

Max

Unit

ns

dCCTxEN_RISE25

dCCTxEN_FALL25

dCCTxEN₀₁

Rise time of TxEN signal at CC

Fall time of TxEN signal at CC

—

9

ns

Sum of delay between Clk to Q of the last FF and the final

output buffer, rising edge

25

ns

dCCTxEN₁₀

Sum of delay between Clk to Q of the last FF and the final

output buffer, falling edge

—

25

ns

1. All parameters specified for V_{DD_HV_IOx}= 3.3 V -5%, +10%, T_J= –40 °C / 150 °C, TxEN pin load maximum 25 pF.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

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PE_Clk

TxEN

dCCTxEN

10

01

Figure 18. FlexRay TxEN signal propagation delays

9.2.2 TxD

TxD

dCCTxD

50%

80 %

50 %

20 %

dCCTxD

RISE

FALL

Figure 19. FlexRay TxD signal

• Measurements are with output load of 25 pF and pad configured as SRE =11.

Table 38. TxD output characteristics

Name

Description¹

Min

Max

Unit

dCCT_xAsym

Asymmetry of sending CC @ 25 pF load

–2.45

2.45

ns

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Table 38. TxD output characteristics (continued)

Name

Description¹

Min

Max

Unit

(=dCCTxD_50%- 100 ns)

dCCTxD_RISE25+dCCTx Sum of Rise and Fall time of TxD signal at the output

D_FALL25

—

9

ns

dCCTxD₀₁

Sum of delay between Clk to Q of the last FF and the final

output buffer, rising edge

25

dCCTxD₁₀

Sum of delay between Clk to Q of the last FF and the final

output buffer, falling edge

1. All parameters specified for V_{DD_HV_IOx}= 3.3 V -5%, +10%, T_J= –40 °C / 150°C, TxD pin load maximum 25 pF

PE_Clk*

TxD

dCCTxD

10

dCCTxD

01

*FlexRay Protocol Engine Clock

Figure 20. FlexRay TxD signal propagation delays

9.2.3 RxD

Table 39. RxD input characteristic

Name

Description¹

Min

—

Max

7

Unit

C_CCRxD

uCCLogic_1

uCCLogic_0

dCCRxD₀₁

Input capacitance on RxD pin

Threshold for detecting logic high

Threshold for detecting logic low

pF

%

35

30

—

70

65

10

%

Sum of delay from actual input to the D

input of the first FF, rising edge

ns

dCCRxD₁₀

Sum of delay from actual input to the D

input of the first FF, falling edge

—

10

ns

1. All parameters specified for V_{DD_HV_IOx}= 3.3 V -5%, +10%, T_J= –40 / 150 °C

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9.2.4 Receiver asymmetry

Table 40. Receiver asymmetry

Name

Description

Min

–31.5

–30.5

Max

+44.0

+43.0

Unit

ns

dCCRxAsymAccept₁₅

dCCRxAsymAccept₂₅

Acceptance of asymmetry at receiving CC with 15 pF load (*)

Acceptance of asymmetry at receiving CC with 25 pF load (*)

ns

9.3 LVDS Fast Asynchronous Transmission (LFAST) electrical

characteristics

The following table provides output driver characteristics for LFAST I/Os.

Table 41. LFAST output buffer electrical characteristics

Symbol

Parameter

Conditions¹

Value

Typ

Unit

Min

Max

|Δ_{VO_L}

|

Absolute value for differential output —

voltage swing (terminated)

100

200

285

mV

V_{ICOM_L}

T_{tr_L}

Common mode voltage

—

1.08

0.2

1.2

—

1.32

1.5

V

Transition time output pin LVDS

configuration

ns

1. V_{DD_HV_IOx}= 3.3 V (–5%, +10%), T_J= –40 / 150 °C, unless otherwise specified.

NOTE

Fast IOs must be specified only as fast (and not as high

current). See GPIO DC electrical specification.

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9.3.1 LFAST interface timing diagrams

Figure 21. LFAST timing definition

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H

lfast_pwr_down

L

Tsu

Differential TX

Data Lines

pad_p/pad_n

Data Valid

Figure 22. Power-down exit time

V

IH

Differential TX

Data Lines

90%

10%

pad_p/pad_n

V

IL

Tfall

Trise

Figure 23. Rise/fall time

9.3.2 LFAST interface electrical characteristics

NOTE

While LFAST is operating and 'Ready' (nex_rdy_b) signal is

used by the debugger on PAD_132, the recommended SRE

settings are ‘00' and ‘01'. TCK should be used with low

frequency (preferably less than 10 MHz).

Table 42. LFAST electrical characteristics

Symbol

Parameter

Conditions¹

Value

Typ

Unit

Min

—

Max

Typ+0.1%

3

Data Rate

DATARATE

T_{STRT_BIAS}

Data rate

—

312/320

0.5

Mbps

µs

STARTUP

—

Bias startup time²

—

Table continues on the next page...

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Table 42. LFAST electrical characteristics

(continued)

Symbol

Parameter

Conditions¹

Value

Typ

0.2

Unit

Min

Max

T_{PD2NM_TX}

Transmitter startup time

(power down to normal

mode)³

—

2

µs

ns

T_{SM2NM_TX}

T_{PD2NM_RX}

T_{PD2SM_RX}

Transmitter startup time

(sleep mode to normal

mode)⁴

Receiver startup time⁵

(Power down to Normal

mode)

Receiver startup time⁴

(Power down to Sleep

mode)

—

0.2

20

0.5

40

50

TRANSMITTER

V_{OS_DRF}

Common mode voltage

—

1.08

100

—

1.32

285

V

|Δ_{VOD_DRF}

|

Differential output voltage

swing (terminated)

200

mV

T_{TR_DRF}

Rise/Fall time (10% - 90% of

swing)

—

0.26

—

1.5

ns

R_{OUT_DRF}

C_{OUT_DRF}

Terminating resistance

Capacitance⁶

67

—

198

5

Ω

—

pF

RECEIVER

V_{ICOM_DRF}

|D_{VI_DRF}

Common mode voltage

Differential input voltage

Input hysteresis

—

0.15⁷

100

25

—

1.6⁸

—

V

|

mV

Ω

V_{HYS_DRF}

R_{IN_DRF}

C_{IN_DRF}

L_{IN_DRF}

—

Terminating resistance

Capacitance⁹

Parasitic Inductance¹⁰

80

115

3.5

5

150

6

—

pF

nH

—

10

TRANSMISSION LINE CHARACTERISTICS (PCB Track)

Z₀

Transmission line

characteristic impedance

—

47.5

50

52.5

105

Ω

Z_DIFF

Transmission line differential

impedance

—

95

100

1. V_{DD_VH_IOx}= 3.3 V -5%,+10%, T_J= –40 / 150 °C, unless otherwise specified

2. Startup time is defined as the time taken by LFAST current reference block for settling bias current after its pwr_down

(power down) has been deasserted. LFAST functionality is guaranteed only after the startup time.

3. Startup time is defined as the time taken by LFAST transmitter for settling after its pwr_down (power down) has been

deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the

startup time.

4. Startup time is defined as the time taken by LFAST transmitter for settling after its pwr_down (power down) has been

deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the

startup time.

5. Startup time is defined as the time taken by LFAST receiver for settling after its pwr_down (power down) has been

deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the

startup time.

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6. Total lumped capacitance including silicon, package pin and bond wire. Application board simulation is needed to verify

LFAST template compliancy.

7. Absolute min = 0.15 V – (285 mV / 2) = 0 V

8. Absolute max = 1.6 V + (285 mV / 2) = 1.743 V

9. Total capacitance including silicon, package pin and bond wire

10. Total inductance including silicon, package pin and bond wire

9.4 Serial Peripheral Interface (SPI) timing specifications

The following table describes the SPI electrical characteristics.

MTEF=1 Mode timing values given below are only applicable when external SPI is in

classic mode. Slave mode timing values given below are applicable when device is in

MTFE=0.

• Measurements are with maximum output load of 50 pF, input transition of 1 ns and

pad configured as SRE = 11.

Table 43. SPI timing

No. Symbol

Parameter

Conditions

Master (MTFE = 0)

Master (MTFE = 1)

Slave (MTFE = 0)

Slave Receive Only mode¹

Master

Min

50

Max

Unit

1

t_SCK

SPI cycle time

—

ns

50

—

50

—

16

—

2

3

4

t_CSC

t_ASC

t_SDC

PCS to SCK delay

After SCK delay

SCK duty cycle

63.8²

68.8³

t_SCK/2 – 1

—

ns

Master

Master⁴

Slave⁵

t_SCK/2 + 1

—

Slave Receive only mode⁶

tSCK/2 –

0.750

tSCK/2 +

0.750

5

6

7

8

9

t_A

Slave access time

Slave SOUT disable time

PCSx to PCSS time

SS active to SOUT valid

—

13 ⁷

13 ⁸

15

2

25

—

ns

t_DIS

SS inactive to SOUT High-Z or invalid

t_PCSC

t_PASC

t_SUI

—

PCSS to PCSx time

Data setup time for inputs

Master (MTFE = 0)

Slave

Slave Receive Mode

Master (MTFE = 1, CPHA = 0)⁹

2

15-N x SPI

IPG clock

period¹⁰

Master (MTFE = 1, CPHA = 1)

Master (MTFE = 0)

Slave

15

–2

4

—

10

t_HI

Data hold time for inputs

ns

Slave Receive Mode

4

Table continues on the next page...

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Table 43. SPI timing (continued)

No. Symbol

Parameter

Conditions

Min

Max

Unit

Master (MTFE = 1, CPHA = 0)⁹

-2 + N x SPI

IPG clock

period ¹⁰

—

Master (MTFE = 1, CPHA = 1)

–2

—

7 ¹¹

23

11

12

t_SUO

Data valid (after SCK edge)

Data hold time for outputs

Master (MTFE = 0)

ns

Slave

Master (MTFE = 1, CPHA = 0)¹²

7 + SPI IPG

Clock Period

Master (MTFE = 1, CPHA = 1)

Master (MTFE = 0)

—

–4 ¹¹

3.8

7

t_HO

—

ns

Slave

Master (MTFE = 1, CPHA = 0) ¹²

-4 + SPI IPG

Clock Period

Master (MTFE = 1, CPHA = 1)

–4

—

1. Slave Receive Only mode can operate at a maximum frequency of 60 MHz. In this mode, the SPI can receive data on SIN,

but no valid data is transmitted on SOUT.

2. For SPI_CTARn[PCSSCK] - 'PCS to SCK Delay Prescaler' configuration is '3' (01h) and SPI_CTARn[CSSCK] - 'PCS to

SCK Delay Scaler' configuration is '2' (0000h).

3. For SPI_CTARn[PASC] - 'After SCK Delay Prescaler' configuration is '3' (01h) and SPI_CTARn[ASC] - 'After SCK Delay

Scaler' configuration is '2' (0000h).

4. The numbers are valid when SPI is configured for 50/50. Refer the Reference manual for the mapping of the duty cycle to

each configuration. A change in duty cycle changes the parameter here. For example, a configuration providing duty cycle

of 33/66 at SPI translates to min tSCK/3 - 1.5 ns and max tSCK/3 + 1.5 ns.

5. The slave mode parameters (t_SUI, t_HI, t_SUOand t_HO) assume 50% duty cycle on SCK input. Any change in SCK duty cycle

input must be taken care during the board design or by the master timing.

6. The slave receive only mode parameters (t_SUIand t_HI) assume 50% duty cycle on SCK input. Any change in SCK duty

cycle input must be taken care during the board design or by the master timing. However, there is additional restriction in

the slave receive only mode that the duty cycle at the slave input should not go below t_sdc(min) corresponding to the

t_sdc(min) for the slave receive mode.

7. In the master mode, this is governed by t_PCSSCK. Refer the SPI chapter in the Reference Manual for details. The minimum

spec is valid only for SPI_CTARn[PCSSCK]= '0b01' (PCS to SCK delay prescalar of 3) or higher.

8. In the master mode, this is governed by t_PASC. Refer the SPI chapter in the Reference Manual for details. The minimum

spec is valid only for SPI_CTARn[PASC]= '0b01' (after SCK delay prescalar of 3) or higher.

9. For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 4.

10. N = Configured sampling point value in MTFE=1 Mode.

11. Same value is applicable for PCS timing in continuous SCK mode.

12. SPI_MCR[SMPL_PT] should be set to 1.

NOTE

For numbers shown in the following figures, see Table 43.

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Communication modules

2

3

PCSx

1

4

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

10

9

Last Data

SIN

First Data

Data

12

11

First Data

Last Data

SOUT

Figure 24. SPI classic SPI timing — master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

10

SCK Output

(CPOL=1)

9

Data

First Data

Last Data

SIN

12

11

SOUT

Last Data

First Data

Figure 25. SPI classic SPI timing — master, CPHA = 1

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NXP Semiconductors

Communication modules

3

2

SS

1

4

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

5

11

12

Data

6

First Data

Last Data

SOUT

SIN

9

10

Data

Last Data

First Data

Figure 26. SPI classic SPI timing — slave, CPHA = 0

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

Data

SOUT

SIN

First Data

10

9

Last Data

First Data

Figure 27. SPI classic SPI timing — slave, CPHA = 1

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Communication modules

3

PCSx

4

1

2

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

9

10

SIN

First Data

12

Last Data

Data

11

SOUT

First Data

Data

Figure 28. SPI modified transfer format timing — master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

10

9

SIN

Last Data

First Data

Data

12

Data

11

First Data

Last Data

SOUT

Figure 29. SPI modified transfer format timing — master, CPHA = 1

8

7

PCSS

PCSx

Figure 30. SPI PCS strobe (PCSS) timing

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Communication modules

9.5 LINFlexD timing specifications

The maximum bit rate is 1.875 MBit/s.

9.6 I²C timing

Table 44. I²C SCL and SDA input timing specifications

Number

Symbol

Parameter

Value

Unit

Min

2

Max

1

2

3

4

5

6

I_tHD:STA

Start Condition hold time

Clock low time

-

Peripheral clock

I_t_LOW

8

I_tHD:DAT

I_tHIGH

Data hold time

2

Clock high time

4

I_tSU:DAT

I_tSU:STA

Data setup time

4

Start condition setup time (for repeated

start condition only)

2

7

I_tSU:STOP

Stop condition setup time

2

-

Table 45. I²C SCL and SDA output timing specifications

Number

Symbol

Parameter

Value

Unit

Min

6

Max

1

2

3

4

5

6

O_tHD:STA

O_t_LOW

Start condition hold time¹

Clock low time¹

Data hold time¹

Clock high time¹

Data setup time¹

-

10

7

O_tHD:DAT

O_t_HIGH

O_tSU:DAT

O_tSU:STA

Peripheral clock

10

2

Start condition setup time (for

repeated start condition only)¹

20

7

8

9

O_tSU:STOP

O_tr

Stop condition setup time¹

SCL/SDA rise time²

SCL/SDA fall time¹

10

-

99.6

ns

O_tf

-

1. Programming IBFD (I²C Bus Frequency Divider Register) with the maximum frequency results in the minimum output

timings listed. The I²C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.

The actual position is affected by the prescale and division values programmed in IBDR (I²C Bus Data I/O Register).

2. Serial data (SDA) and Serial clock (SCL) reaches peak level depending upon the external signal capacitance and pull up

resistor values as SDA and SCL are open-drain type outputs which are only actively driven low by the I²C module.

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Debug modules

Figure 31. I²C input/output timing

10 Debug modules

10.1 JTAG/CJTAG interface timing

The following table lists JTAGC/CJTAG electrical characteristics.

• Measurements are with input transition of 1 ns, output load of 50 pF and pads

configured with SRE=11.

Table 46. JTAG/CJTAG pin AC electrical characteristics ¹

#

Symbol

Characteristic

Min

36

50

40

—

5

Max

Unit

2

1

t_JCYC

TCK Cycle Time (JTAG)

TCK Cycle Time (CJTAG)

TCK Clock Pulse Width

TCK Rise and Fall Times (40% - 70%)

—

ns

2

3

t_JDC

60

3

%

ns

t_TCKRISE

4

t_TMSS, t_TDISTMS, TDI Data Setup Time

—

5

t_TMSH, t_TDIHTMS, TDI Data Hold Time

5

—

15⁴

6

t_TDOV

t_TDOI

TCK Low to TDO/TMS Data Valid ³

TCK Low to TDO/TMS Data Invalid³

TCK Low to TDO/TMS High Impedance³

JCOMP Assertion Time

—

0

7

—

8

t_TDOHZ

t_JCMPPW

t_JCMPS

t_BSDV

—

100

40

—

22

9

—

10

11

12

JCOMP Setup Time to TCK Low

TCK Falling Edge to Output Valid

—

600⁵

t_BSDVZ

TCK Falling Edge to Output Valid out of High

Impedance

600

13

14

t_BSDHZ

t_BSDST

TCK Falling Edge to Output High Impedance

Boundary Scan Input Valid to TCK Rising Edge

—

600

—

ns

15

Table continues on the next page...

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Debug modules

Table 46. JTAG/CJTAG pin AC electrical characteristics ¹(continued)

#

Symbol

Characteristic

Min

Max

Unit

15

t_BSDHT

TCK Rising Edge to Boundary Scan Input Invalid

15

—

ns

1. These specifications apply to JTAG boundary scan only.

2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.

Refer to pad specification for allowed transition frequency.

3. TMS timing is applicable only in CJTAG mode

4. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

5. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

TCK

2

3

2

1

3

Figure 32. JTAG test clock input timing

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Debug modules

TCK

4

5

TMS, TDI

6

8

7

TDO

Figure 33. JTAG test access port timing

TCK

10

JCOMP

9

Figure 34. JTAG JCOMP timing

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Debug modules

TCK

11

13

Output

Signals

12

Output

Signals

14

15

Input

Signals

Figure 35. JTAG boundary scan timing

10.2 Nexus Aurora debug port timing

Table 47. Nexus Aurora debug port timing

#

1

Symbol

t_REFCLK

t_MCYC

t_RCDC

J_RC

Characteristic

Min

625

—

Max

1250

400

55

Unit

MHz

ps

Reference clock frequency

Reference Clock rise/fall time

Reference Clock Duty Cycle

Reference Clock jitter

Reference Clock Stability

Bit Error Rate

1a

2

45

—

%

3

40

ps

4

t_STABILITY

BER

50

—

10^-12

PPM

—

5

6

t_EVTIPW

J_D

EVTI Pulse Width

4.0

—

t_TCYC

OUI

7

Transmit lane Deterministic Jitter

Transmit lane Total Jitter

0.17

0.35

8

J_T

—

Table continues on the next page...

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WKUP/NMI timing specifications

Table 47. Nexus Aurora debug port timing (continued)

#

9

Symbol

S_O

Characteristic

Min

—

Max

20

Unit

ps

Differential output skew

Lane to lane output skew

Aurora lane Unit Interval

10

11

S_MO

—

1000

800

ps

OUI

800

ps

1

2

CLOCK_REF

Zero Crossover

CLOCK_REF

-

+

8

Tx Data

-

Ideal Zero Crossover

Tx Data

+

Tx Data [n]

Zero Crossover

Tx Data [n+1]

Zero Crossover

Tx Data [m]

Zero Crossover

9

Figure 36. Nexus Aurora timings

11 WKUP/NMI timing specifications

Table 48. WKUP/NMI glitch filter

Symbol

W_FNMI

Parameter

Min

—

Typ

Max

20

Unit

ns

NMI pulse width that is rejected

NMI pulse width that is passed

—

W_NFNMI

400

—

ns

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External interrupt timing (IRQ pin)

12 External interrupt timing (IRQ pin)

Table 49. External interrupt timing

No.

1

Symbol

t_IPWL

Parameter

Conditions

Min

3

Max

—

Unit

t_CYC

IRQ pulse width low

IRQ pulse width high

IRQ edge to edge time¹

—

2

t_IPWH

3

—

3

t_ICYC

6

—

1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both

NOTE

tCYC is equivalent to TCK (prescaled filter clock period)

which is the IRC clock prescaled to the Interrupt Filter Clock

Prescaler (IFCP) value. TCK = T(IRC) x (IFCP + 1) where

T(IRC) is the internal oscillator period. Refer SIUL2 chapter of

the device reference manual for details.

IRQ

1

2

3

Figure 37. External interrupt timing

13 Temperature sensor electrical characteristics

The following table describes the temperature sensor electrical characteristics.

Table 50. Temperature sensor electrical characteristics

Symbol

—

Parameter

Temperature monitoring range

Sensitivity

Conditions

Min

-40

—

Typ

—

Max

150

—

Unit

^°C

T_SENS

T_ACC

5.18

—

mV/°C

^°C

Accuracy

T_J= -40 to 150°C

5

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Radar module

14 Radar module

14.1 MIPICSI2 D-PHY electrical and timing specifications

This section describes MIPICSI2¹D-PHY electrical specifications, compliant with

MIPICSI2 version 1.1, D-PHY specification Rev. 1.0 (for MIPI sensor port x4 lanes).

REXT

15 kΩ

(+/-1%)

Figure 38. MIPICSI2 circuit

Table 51. Calibrator specifications

Symbol

Parameters

Min

Typ

Max

Unit

R_EXT

External reference resistor, 1% accuracy (or better), for auto

calibration

-

15

-

kΩ

T_cal

Time from when PD signal goes low to when CALCOMPL goes high

-

2

2.5

μs

14.1.1 Electrical and timing information

Table 52. Electrical and timing information

Symbol

Parameters

Min

Typ

Max

Unit

HS Line Receiver DC Specifications

V_IDTH

Differential input high voltage threshold

-

-70

-

70

-

mV

V_IDTL

Differential input low voltage threshold

Single ended input high voltage

Single ended input low voltage

Input common mode voltage

V_IHHS

460

-

V_ILHS

-40

70

-

V_CMRXDC

V_TERM-EN

330

450

Single-ended threshold for HS termination

enable

Z_ID

Differential input impedance

80

-

125

550

ohm

mV

LP Line Receiver DC Specifications

V_ILLP

Input low voltage

-

Table continues on the next page...

be disclosed, reproduced or used for any purpose other than as needed to support the use of the products of NXP

Semiconductors.

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Table 52. Electrical and timing information (continued)

Symbol

V_IHLP

V_HYST

Parameters

Min

880

25

Typ

Max

Unit

mV

Input high voltage

Input hysteresis

-

14.1.2 D-PHY signaling levels

The signal levels are different for differential HS mode and single-ended LP mode. The

figure below shows both the HS and LP signal levels on the left and right sides,

respectively. The HS signaling levels are below the LP low-level input threshold such

that LP receiver always detects low on HS signals.

Figure 39. D-PHY signaling levels

14.1.3 D-PHY switching characteristics

Table 53. D-PHY switching characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HS Line Receiver AC Specifications

-

Maximum serial data rate

On DATAP/N inputs. 80

Ohm<= RL <= 125 Ohm

80

-

1000

Mbps

Table continues on the next page...

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Radar module

Table 53. D-PHY switching characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

100

Unit

ΔVCMRX(HF)

Common mode interference beyond

450 MHz

-

mVpp

ΔVCMRX(LF)

Common mode interference between

50 MHz and 450 MHz

-50

-

50

60

mVpp

pF

CCM

Common mode termination

LP Line Receiver AC Specification

e_SPIKE

T _MIN

V_INT

Input pulse rejection

-

300

Vps

ns

Minimum pulse response

20

-

Pk-to-Pk interference voltage

Interference frequency

200

-

mV

MHz

f_INT

450

14.1.4 Low-power receiver timing

Figure 40. Input Glitch Rejection of Low-Power Receivers

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14.1.5 Data to clock timing

Figure 41. Definition

Table 54. Data to clock timing specifications

Symbol

T_CLKP

Parameter

Min

Typ

Max

Unit

MHz

Clock Period

40

-

500

UI_INST

T_SETUP

T_HOLD

UI Instantaneuous

1

12.5

ns

Data to Clock Setup Time

Clock to Data Hold Time

0.15

-

UIINST

14.2 MIPICSI2 Disclaimer

The material contained herein is not a license, either expressly or impliedly, to any IPR

owned or controlled by any of the authors or developers of this material or MIPI®. The

material contained herein is provided on an “AS IS” basis and to the maximum extent

permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS,

and the authors and developers of this material and MIPI hereby disclaim all other

warranties and conditions, either express, implied or statutory, including, but not limited

to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a

particular purpose, of accuracy or completeness of responses, of results, of workmanlike

effort, of lack of viruses, and of lack of negligence.

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Radar module

All materials contained herein are protected by copyright laws, and may not be

reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise

exploited in any manner without the express prior written permission of MIPI Alliance.

MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, trade names,

and other intellectual property are the exclusive property of MIPI Alliance and cannot be

used without its express prior written permission.

ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET

ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR

NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL OR THE CONTENTS

OF THIS DOCUMENT. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF

THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR MIPI BE

LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE

GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY

INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES

WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE,

ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT,

SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER

OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF

SUCH DAMAGES.

Without limiting the generality of this Disclaimer stated above, the user of the contents of

this Document is further notified that MIPI: (a) does not evaluate, test or verify the

accuracy, soundness or credibility of the contents of this Document; (b) does not monitor

or enforce compliance with the contents of this Document; and (c) does not certify, test,

or in any manner investigate products or services or any claims of compliance with the

contents of this Document. The use or implementation of the contents of this Document

may involve or require the use of intellectual property rights ("IPR") including (but not

limited to) patents, patent applications, or copyrights owned by one or more parties,

whether or not Members of MIPI. MIPI does not make any search or investigation for

IPR, nor does MIPI require or request the disclosure of any IPR or claims of IPR as

respects the contents of this Document or otherwise.

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NXP Semiconductors

Thermal Specifications

15 Thermal Specifications

15.1 Thermal characteristics

Table 55. 257MAPBGA package thermal characteristics

Symbol

Parameter

Conditions

257MAPBGA

Unit

R_θJA

Thermal resistance, junction-to-ambient natural

convection ^{1, 2}

Single layer board - 1s

Four layer board - 2s2p³

41.8

22.3

29.8

17.7

7.6

°C/W

R_θJMA

Thermal resistance, junction-to-ambient forced

convection at 200 ft/min^{1, 3}

Single layer board - 1s

°C/W

Four layer board - 2s2p

R_θJB

R_θJC

Ψ_JT

Thermal resistance junction-to-board⁴

Thermal resistance junction-to-case⁵

Junction-to-package-top natural convection⁶

—

°C/W

5.2

0.2

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification

for the specified package. Board temperature is measured on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2.

15.1.1 General notes for specifications at maximum junction

temperature

An estimation of the chip junction temperature, T_J, can be obtained from this equation:

T_J= T_A+ (R_θJA× P_D)

T_J= T_BRD+ (R_θJB× P_D)

where:

• T_A= ambient temperature for the package (°C)

• R_θJA= junction to ambient thermal resistance (°C/W)

• R_θJB= junction to board thermal resistance (°C/W)

• T_θBRD= average board temperature just outside the package periphery (°C)

• P_D= power dissipation in the package (W)

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Thermal Specifications

The junction to ambient thermal resistance is an industry standard parameter that

provides a quick and easy estimation of thermal performance. However, junction to board

thermal resistance is more appropriate for tight enclosure spaces where board temperature

should be used as reference temperature. Using 2s2p board with natural convection

conditions, junction temperature is found to be less than 150°C . There are two

parameters in common usage: the value determined on a single layer board and the value

obtained on a board with two inner planes. For packages such as PBGA, these values can

significantly differ. For customer board design with different number of layers and

copper percentage content, these values must be appropriately interpolated in order to

evaluate junction temperature. In general, the value obtained on a single layer board is

appropriate for the tightly packed printed circuit board. The value obtained on the board

with the internal planes is usually appropriate if the board has low power dissipation and

the components are well separated.

When a heat sink is used, the thermal resistance is expressed in the following equation as

the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:

R_θJA= R_θJC+ R_θCA

where:

• R_θJA= junction to ambient thermal resistance (°C/W)

• R_θJC= junction to case thermal resistance (°C/W)

• R_θCA= case to ambient thermal resistance (°C/W)

R_θJCis device related and cannot be influenced by the user. The user controls the thermal

environment to change the case to ambient thermal resistance, R_θCA. For instance, the

user can change the size of the heat sink, the air flow around the device, the interface

material, the mounting arrangement on printed circuit board, or change the thermal

dissipation on the printed circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks

are not used, the Thermal Characterization Parameter (Ψ_JT) can be used to determine the

junction temperature with a measurement of the temperature at the top center of the

package case using this equation:

T_J= T_T+ (Ψ_JT× P_D)

where:

• T_T= thermocouple temperature on top of the package (°C)

• Ψ_JT= thermal characterization parameter (°C/W)

• P_D= power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a

40 gauge type T thermocouple epoxied to the top center of the package case. The

thermocouple should be positioned so that the thermocouple junction rests on the

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

72

NXP Semiconductors

Packaging

package. A small amount of epoxy is placed over the thermocouple junction and over

about 1 mm of wire extending from the junction. The thermocouple wire is placed flat

against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

15.1.2 References

Semiconductor Equipment and Materials International; 3081 Zanker Road; San Jose, CA

95134 USA; (408) 943-6900

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global

Engineering Documents at 800-854-7179 or 303-397-7956.

JEDEC specifications are available on the Web at http://www.jedec.org.

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA

Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San

Diego, 1998, pp. 47–54.

2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-

Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.

3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board

Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of

SemiTherm, San Diego, 1999, pp. 212–220.

16 Packaging

The S32R274 is offered in the following package types.

If you want the drawing for this package

Then use this document number

257-ball MAPBGA

98ASA00081D

NOTE

For detailed information regarding package drawings, refer to

www.nxp.com.

17 Reset sequence

This section describes different reset sequences and details the duration for which the

device remains in reset condition in each of those conditions.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

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73

Reset sequence

17.1 Reset sequence duration

Table 57 specifies the minimum and the maximum reset sequence duration for the five

different reset sequences described in Reset sequence description.

Table 57. RESET sequences

No. Symbol

Parameter

T_Reset

Typ Max¹

50²

Unit

Min

15

1

2

3

4

5

T_DRB

T_DR

Destructive Reset Sequence, BIST enabled

Destructive Reset Sequence, BIST disabled

ms

µs

ms

µs

400

15

2000

50

T_ERLBExternal Reset Sequence Long, BIST enabled

T_FRL

T_FRS

Functional Reset Sequence Long, BIST disabled

Functional Reset Sequence Short³

400

1

2000

500

1. The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET

by an external reset generator.

2. Max time is based on STCU BIST configuration execution time + max RESET time (TDR). For default STCU BIST

configuration execution time, refer to EB834. Contact your NXP sales representative for details.

3. BIST is not executed on short functional reset

17.2 Reset sequence description

The figures in this section show the internal states of the device during the five different

reset sequences. The doted lines in the figures indicate the starting point and the end point

for which the duration is specified in Table 57.

With the beginning of DRUN mode, the first instruction is fetched and executed. At this

point, application execution starts and the internal reset sequence is finished.

The SMPS self test is always triggered during Phase3 after a destructive reset so that

duration is included into Phase3 below.

In external regulation mode, the VREG_POR_B pin should be de-asserted only when all

the design supplies are in operating range. Deassertion of VREG_POR_B pin triggers the

start of reset sequence in internal as well as external regulation modes.

The following figures show the internal states of the device during the execution of the

reset sequence and the possible states of the RESET_B signal pin.

NOTE

RESET_B is a bidirectional pin. The voltage level on this pin

can either be driven low by an external reset generator or by the

device internal reset circuitry. A high level on this pin can only

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

74

NXP Semiconductors

Reset sequence

be generated by an external pullup resistor which is strong

enough to overdrive the weak internal pulldown resistor. The

rising edge on RESET_B in the following figures indicates the

time when the device stops driving it low. The reset sequence

durations given in Table 57 are applicable only if the internal

reset sequence is not prolonged by an external reset generator

keeping RESET_B asserted low beyond the last Phase3.

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE0

PHASE1,2

PHASE3

BIST

PHASE1,2

PHASE3

DRUN

Establish

IRC and

PWR

Flash

Init

Flash

Init

Device

Config

Self

Test

Setup

Device

config

Application

execution

MBIST

LBIST

T_{DRB, min}< T_RESET< T_{DRB, max}

Figure 42. Destructive reset sequence, BIST enabled

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE0

PHASE1,2

PHASE3

DRUN

Establish

IRC and

PWR

Flash

Init

Device

Config

Application

Execution

T_{DR, min}< T_RESET< T_{DR, max}

Figure 43. Destructive reset sequence, BIST disabled

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE1,2

PHASE3

BIST

PHASE1,2

PHASE3

DRUN

Flash

Init

Flash

Init

Device

Config

Self

Test

Setup

Device

config

Application

execution

MBIST

LBIST

T_{ERLB, min}< T_RESET< T_{ERLB, max}

Figure 44. External reset sequence long, BIST enabled

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

75

Power sequencing requirements

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE1,2

PHASE3

DRUN

Flash

Init

Device

config

Application

execution

T_{FRL, min}< T_RESET< T_{FRL, max}

Figure 45. Functional reset sequence long

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE3

DRUN

Application

Execution

T_{FRS, min}< T_RESET< T_{FRS, max}

Figure 46. Functional reset sequence short

The reset sequences shown in Figure 45 and Figure 46 are triggered by functional reset

events. RESET is driven low during these two reset sequences only if the corresponding

functional reset source (which triggered the reset sequence) was enabled to drive

RESET_B low for the duration of the internal reset sequence. See the RGM_FBRE

register in the device reference manual for more information.

18 Power sequencing requirements

The device does not require any specific power sequencing as far as user follows

recommendations in this section.

Either ramp V_{DD_HV_IO}and V_{DD_HV_PMU}together or ramp V _{DD_HV_IO}before

V_{DD_HV_PMU}such that the two supplies always maintain 100 mV or less difference, when

using internal regulation mode. V_{DD_LV_DPHY}and V_{DD_LV_CORE}are to be driven from

same source. V_{DD_HV_IO}, V_{DD_HV_IO_RGMII}, V_{DD_HV_IO_PWM}and V_{DD_HV_IO_LFAST}

supplies should be treated as a single supply from board perspective.

As mentioned in the previous section, it is expected that the external ASIC which powers

up the device in external regulation mode deasserts VREG_POR_B pin only when all the

power supplies to the design are in operating range.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

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NXP Semiconductors

Pinouts

It should be noted that LVD and HVD detectors on VDD supply are disabled by default

in external regulation mode for preventing a conflict with external regulator operation but

they can be enabled by software once design is powered up.

While designing the system, it is important to ensure that AFE supplies are powered up

before data is sent on its input pads.

19 Pinouts

19.1 Package pinouts and signal descriptions

For package pinouts and signal descriptions, refer to the Reference Manual.

20 Revision History

Table 58. Revision History

Revision

Date

Description

Rev 4

May, 2018

• Removed section "4.1 Introduction".

• Removed section "3.2 Format".

• In Fields, removed figure "Commercial product code structure".

• In Nexus Aurora debug port timing, added t_EVTIPWrow.

• In Ethernet switching specifications changed the following:

• Updated the figure RMII/MII serial management channel timing diagram.

• In Ethernet MDIO timing table changed MDC10 Min value and MDC11 Max value.

• Extensively updated Table 32.

• In Table 7, changed V_inxoscclkvihMax value from 1.2 to 1.23.

• In Table 25, added rows for the symbols t_sampleC, t_sampleS,t_sampleBG, and t_sampleTS

• In Table 6, changed V_INAmaximum value to 6.0.

.

• Added the following footnotes in Absolute maximum ratings :

• The maximum value limits of injection current and input voltage both must be

followed together for proper device operation.

• The maximum value of 10 mA applies to pulse injection only. DC current injection is

limited to a maximum of 5 mA.

• In Table 7, changed V_INAmaximum value to V_{DD_HV_ADCREFx}

• In Table 2 :

.

• Changed part from FS32R274KBK2MMM to FS32R274KSK2MMM and changed

configuration from "B" to "S"

• Changed part from FS32R274KBK2VMM to FS32R274KSK2VMM and changed

configuration from "B" to "S"

• Added "B or S" to Table 3

Rev 5

July 03,

2018

• In Table 6, Removed footnote on I_INJPAD.

April 30,

2019

• In Table 1, added information for 266 MHz frequency parts .

• In Table 2, added the rows for "FS32R274JSK2MMM", "FS32R264KBK0MMM",

"FS32R264KCK0MMM", "FS32R264JBK0MMM" and "FS32R264JCK0MMM".

• Added the feature changes for S32R264 with respect to S32R274 in Feature list.

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

NXP Semiconductors

77

Revision History

Revision

Table 58. Revision History

Date

Description

• In Table 4, added the row for 266MHz frequency performance.

• In Table 8, added the Conditions and Max value in I_{DD_CORE}for 266 MHz frequency.

• Added note "S32R264 devices support AFE PLL while S32R274 devices support SDPLL",

in Block diagram.

• In Operating conditions, changed the footnote from "Full performance means Core0

running @ 120 MHz, Core1/2 running @ 240 MHz, SPT running @ 200 MHz, rich set of

peripherals used" to "Full performance means full frequency".

S32R274/S32R264 Series Data Sheet, Rev. 5, 04/2019

78

NXP Semiconductors

How to Reach Us:

Information in this document is provided solely to enable system and software implementers to use

NXP products. There are no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits based on the information in this document. NXP reserves the right to

make changes without further notice to any products herein.

Home Page:

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particular purpose, nor does NXP assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets

and/or specifications can and do vary in different applications, and actual performance may vary over

time. All operating parameters, including “typicals,” must be validated for each customer application

by customerʼs technical experts. NXP does not convey any license under its patent rights nor the

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found at the following address: nxp.com/SalesTermsandConditions.

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vulnerabilities. Customers are responsible for the design and operation of their applications and

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NXP accepts no liability for any vulnerability that is discovered. Customers should implement

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and products.

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Document Number S32R274

Revision 5, 04/2019


型号：	S32R274
厂家：	NXP
描述：	Safety core: Power ArchitectureÂ® e200Z4 32-bit CPU with checker core
文件：	总79页 (文件大小：3163K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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