S83C562-6A68 [NXP]
Single-chip 8-bit microcontroller; 单芯片8位微控制器
| 型号： | S83C562-6A68 |
| 厂家： | 
NXP |
| 描述： | Single-chip 8-bit microcontroller |
| 文件： | 总20页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
80C562/83C562
Single-chip 8-bit microcontroller
Product specification
IC20 Data Handbook
1992 Jan 08
Philips
Semiconductors
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
Single-chip 8-bit microcontroller with 8-bit A/D, capture/compare timer, high-speed outputs, PWM
DESCRIPTION
FEATURES
PIN CONFIGURATION
The 80C562/83C562 (hereafter generically
referred to as 8XC562) Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
83C562/83C562 has the same instruction set
as the 80C51.
• 80C51 instruction set
9
1
61
• 8k × 8 ROM expandable externally to
64k bytes
10
26
60
44
• 256 × 8 RAM, expandable externally to
PLASTIC
LEADED
64k bytes
CHIP CARRIER
• Two standard 16-bit timer/counters
• An additional 16-bit timer/counter coupled
to four capture registers and three compare
registers
The 8XC562 contains a non-volatile 256 × 8
read-only program memory, a volatile 256 × 8
read/write data memory (83C562) (the
80C562 is ROMless), a volatile 256 × 8
read/write data memory, six 8-bit I/O ports,
two 16-bit timer/event counters (identical to
the timers of the 80C51), an additional 16-bit
timer coupled to capture and compare
latches, a 15-source, two-priority-level,
nested interrupt structure, an 8-input ADC,
two pulse width modulated outputs, standard
80C51 UART, a “watchdog” timer and on-chip
oscillator and timing circuits. For systems that
require extra capability, the 83C562 can be
expanded using standard TTL compatible
memories and logic.
27
43
• Capable of producing eight synchronized,
Pin Function
Pin Function
timed outputs
1
2
3
4
5
6
7
8
9
P5.0/ADC0
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
XTAL1
V
V
• An 8-bit ADC with eight multiplexed analog
DD
SS
STADC
PWM0
PWM1
EW
V
SS
NC
inputs
P2.0/A08
P2.1/A09
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
• Two 8-bit resolution, pulse width modulated
outputs
P4.0/CMSR0
P4.1/CMSR1
P4.2/CMSR2
P4.3/CMSR3
P4.4/CMSR4
P4.5/CMSR5
P4.6/CMT0
P4.7/CMT1
RST
P1.0/CT0I
P1.1/CT1I
P1.2/CT2I
P1.3/CT3I
P1.4/T2
• Five 8-bit I/O ports plus one 8-bit input port
shared with analog inputs
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
• Full-duplex UART compatible with the
standard 80C51
ALE
EA
• On-chip watchdog timer
• Three temperature ranges
– 0 to +70°C
The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 12MHz crystal, 58% of the
instructions are executed in 1µs and 40% in
2µs. Multiply and divide instructions require
4µs.
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
AVref–
AVref+
AV
AV
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
– –40 to +85°C
P1.5/RT2
P1.6
– –40 to +125°C
P1.7
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
SS
DD
P3.5/T1
P3.6/WR
P3.7/RD
NC
NC
XTAL2
SU00224
2
1992 Jan 08
853–1463 05128
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
ORDERING INFORMATION
PHILIPS PART
ORDER NUMBER
PART MARKING
TEMPERATURE
PHILIPS NORTH AMERICA
PART ORDER NUMBER
RANGE °C
Drawing
Number
Drawing
Number
AND PACKAGE
FREQ
MHz
ROMless
ROM
ROMless
ROM
EPROM
PCB80C562- PCB83C562-
0 to +70, Plastic
Leaded Chip Carrier
2
S80C562-4A68 S83C562-4A68 SOT188 S87C552-4A68
SOT188-3
16
16WP
16WP/xxx
0 to +70, Plastic
Leaded Chip Carrier
w/Window
2
S87C552-4K68
1473A
16
12
2
PCF80C562- PCF83C562- S80C562-2A68 S83C562-2A68 SOT188 S87C552-5A68
12WP 12WP/xxx
SOT188-3
–40 to +85, Plastic
Leaded Chip
Carrier
–40 to +85, Plastic
Leaded Chip Carrier
w/Window
2
S87C552-5K68
1473A
12
12
PCA80C562- PCA83C562- S80C562-6A68 S83C562-6A68 SOT188
–40 to +125, Plastic
Leaded Chip Carrier
12WP
12WP/xxx
NOTES:
1. 80C562 and 83C562 frequency range is 1.2MHz–12MHz or 1.2MHz–16MHz.
2. 87C552 frequency range is 3.5MHz–16MHz. For full specification, see the 87C552 data sheets.
3. xxx denotes the ROM code number.
LOGIC SYMBOL
V
V
SS
DD
XTAL1
XTAL2
EA
ALE
PSEN
LOW ORDER
ADDRESS AND
DATA BUS
AV
AV
SS
DD
AVref+
AVref–
STADC
PWM0
PWM1
CT0I
CT1I
CT2I
CT3I
T2
RT2
ADC0-7
HIGH ORDER
ADDRESS AND
DATA BUS
CMSR0-5
RxD
TxD
INT0
INT1
T0
T1
CMT0
CMT1
WR
RD
RST
EW
SU00225
3
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
BLOCK DIAGRAM
T0
T1
INT0
INT1
3
PWM0 PWM1
ADC0–7
AV
AV
REF
SS
–
+
V
V
SS
5
DD
3
3
3
AV
STADC
DD
XTAL1
T0, T1
PROGRAM
MEMORY
8k x 8 ROM
(83C562)
DATA
MEMORY
256 x 8 RAM
TWO 16-BIT
TIMER/EVENT
COUNTERS
DUAL
PWM
XTAL2
EA
CPU
ADC
ALE
80C51 CORE
EXCLUDING
PSEN
ROM/RAM
3
WR
RD
8-BIT INTERNAL BUS
3
0
16
AD0–7
T2
16-BIT
COMPARATORS
WITH
REGISTERS
FOUR
16-BIT
CAPTURE
T2
16-BIT
TIMER/
EVENT
16
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
COMPARATOR
OUTPUT
SELECTION
T3
8-BIT
PORT
2
WATCHDOG
TIMER
LATCHES
COUNTERS
A8–15
3
3
1
1
1
4
P0
P1
P2
P3
TxD
RxD
P5
P4
CT0I–CT3I
T2
RT2
CMSR0–CMSR5
CMT0, CMT1
RST EW
3
4
5
0
1
2
ALTERNATE FUNCTION OF PORT 0
ALTERNATE FUNCTION OF PORT 3
ALTERNATE FUNCTION OF PORT 4
ALTERNATE FUNCTION OF PORT 5
ALTERNATE FUNCTION OF PORT 1
ALTERNATE FUNCTION OF PORT 2
SU00226
4
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
PIN DESCRIPTION
MNEMONIC
PIN NO. TYPE
NAME AND FUNCTION
V
2
3
I
I
Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode.
DD
STADC
Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started
by software).
PWM0
PWM1
EW
4
O
O
Pulse Width Modulation: Output 0.
5
6
Pulse Width Modulation: Output 1.
I
Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
P0.0–P0.7
57–50
I/O
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memory. In this application it uses strong internal
pull-ups when emitting 1s.
P1.0–P1.7
16–23
16–23
16–19
20
I/O
I/O
I/O
I
Port 1: 8-bit I/O port. Alternate functions include:
(P1.0–P1.7): Quasi-bidirectional port pins.
CT0I–CT3I (P1.0–P1.3): Capture timer input signals for timer T2.
T2 (P1.4): T2 event input
21
I
RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
P2.0–P2.7
P3.0–P3.7
39–46
I/O
Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08–A15).
24–31
24
I/O
Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:
RxD(P3.0): Serial input port.
25
TxD (P3.1): Serial output port.
26
INT0 (P3.2): External interrupt.
27
INT1 (P3.3): External interrupt.
28
T0 (P3.4): Timer 0 external input.
29
T1 (P3.5): Timer 1 external input.
30
31
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
P4.0–P4.7
P5.0–P5.7
7–14
7–12
13, 14
I/O
O
O
Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
CMSR0–CMSR5 (P4.0–P4.5): Timer T2 compare and set/reset outputs on a match with timer T2.
CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
68–62,
1
I
Port 5: 8-bit input port.
ADC0–ADC7 (P5.0–P5.7): Alternate function: Eight input channels to ADC.
RST
15
35
I/O
I
Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows.
XTAL1
Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock
generator. Receives the external clock signal when an external oscillator is used.
XTAL2
34
O
Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open–circuit when an
external clock is used.
V
36, 37
47
I
Digital ground.
SS
PSEN
ALE
O
O
Program Store Enable: Active-low read strobe to external program memory.
48
Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is
activated every six oscillator periods. During an external data memory access, one ALE pulse is
skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external
pull-up.
EA
49
I
External Access: When EA is held at TTL level high, the CPU executes out of the internal program
ROM provided the program counter is less than 8192. When EA is held at TTL low level, the CPU
executes out of external program memory. EA is not allowed to float.
AV
AV
AV
AV
58
59
60
61
I
I
I
I
Analog to Digital Conversion Reference Resistor: Low-end.
Analog to Digital Conversion Reference Resistor: High-end.
Analog Ground
REF–
REF+
SS
Analog Power Supply
DD
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V +0.5V or V – 0.5V,
DD
SS
respectively.
5
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
RESET
A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To ensure a good power-on reset,
the RST pin must be high long enough to
allow the oscillator time to start up (normally
a few milliseconds) plus two machine cycles.
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
At power-on, the voltage on V and RST
must come up at the same time for a proper
start-up.
DD
POWER-DOWN MODE
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. the
control bits for the reduced power modes are
in the special function register PCON. Table 1
shows the state of the I/O ports during low
current operating modes.
IDLE MODE
In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
Table 1.
External Pin Status During Idle and Power-Down Modes
PROGRAM
MEMORY
PWM0/
MODE
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
PORT 4
Data
PWM1
High
High
High
High
Idle
Internal
1
1
0
0
1
1
0
0
Idle
External
Internal
Float
Data
Address
Data
Data
Data
Power-down
Power-down
Data
Data
Data
Data
External
Float
Data
Data
Data
Data
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
V
Voltage on any other pin to V
–0.5 to +6.5
5.0
SS
Input, output DC current on any single I/O pin
mA
W
Power dissipation (based on package heat transfer limitations, not device power consumption)
1.0
Storage temperature range
–65 to +150
°C
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
6
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
DC ELECTRICAL CHARACTERISTICS
V
SS
, AV = 0V
SS
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
DD
Supply voltage
PCB8XC562
PCF8XC562
PCA8XC562
4.0
4.0
4.5
6.0
6.0
5.5
V
V
V
I
I
I
Supply current operating:
PCB8XC562
See notes 1 and 2
DD
f
f
f
= 16MHz
= 12MHz
= 12MHz
45
34
30
mA
mA
mA
OSC
OSC
OSC
PCF8XC562
PCA8XC562
Idle mode:
See notes 1 and 3
ID
PCB8XC562
PCF8XC562
PCA8XC562
f
f
f
= 16MHz
= 12MHz
= 12MHz
10
8
7
mA
mA
mA
OSC
OSC
OSC
Power-down current:
See notes 1 and 4;
2V < V < V max
PD
PD
DD
PCB8XC562
PCF8XC562
PCA8XC562
50
50
100
µA
µA
µA
Inputs
V
V
V
V
Input low voltage, except EA
–0.5
–0.5
0.2V –0.1
V
V
IL
DD
Input low voltage to EA
0.2V –0.3
DD
IL1
IH
Input high voltage, except XTAL1, RST
Input high voltage, XTAL1, RST
0.2V +0.9
V
DD
V
DD
+0.5
+0.5
V
DD
0.7V
V
IH1
DD
I
Logical 0 input current, ports 1, 2, 3, 4
Logical 1-to-0 transition current, ports 1, 2, 3, 4
Input leakage current, port 0, EA, STADC, EW
V
= 0.45V
–50
µA
µA
µA
IL
TL
IN
I
See note 5
0.45V < V < V
DD
–650
10
+I
IL1
I
Outputs
6
V
V
V
Output low voltage, ports 1, 2, 3, 4
I
I
= 1.6mA
0.45
0.45
V
V
OL
OL
6
Output low voltage, port 0, ALE, PSEN, PWM0, PWM1
Output high voltage, ports 1, 2, 3, 4
= 3.2mA
OL1
OH
OL
V
DD
+ 5V+10%
–I = 60µA
2.4
V
V
V
OH
–I = 25µA
0.75V
OH
DD
DD
–I = 10µA
OH
0.9V
V
OH1
Output high voltage (port 0 in external bus mode, ALE,
PSEN, PWM0, PWM1)
7
V
DD
+ 5V+10%
–I = 400µA
2.4
V
V
V
OH
–I = 150µA
0.75V
OH
DD
DD
–I = 40µA
OH
0.9V
V
OH2
Output high voltage (RST)
–I = 400µA
–I = 120µA
OH
2.4
0.8V
V
V
OH
DD
R
C
Internal reset pull-down resistor
Pin capacitance
50
150
10
kΩ
RST
IO
Test freq = 1MHz,
pF
T
= 25°C
amb
7
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Analog Inputs
AV
Analog supply voltage:
PCB8XC562
DD
AV = V ±0.2V
AV = V ±0.2V
DD DD
AV = V ±0.2V
DD DD
4.0
4.0
4.5
6.0
6.0
5.5
V
V
V
DD
DD
PCF8XC562
PCA8XC562
AI
AI
Analog supply current: operating:
Port 5 = 0 to AV
1.2
mA
DD
DD
Idle mode:
ID
PCB8XC562
PCF8XC562
PCA8XC562
50
50
100
µA
µA
µA
AI
PD
Power-down mode:
PCB8XC562
2V < AV < AV max
PD DD
50
50
100
µA
µA
µA
PCF8XC562
PCA8XC562
AV
AV
Analog input voltage
Reference voltage:
AV –0.2
AV +0.2
V
IN
SS
DD
REF
AV
AV
AV –0.2
V
V
REF–
REF+
SS
AV +0.2
DD
R
C
Resistance between AV
and AV
REF–
5
25
15
kΩ
pF
REF
REF+
Analog input capacitance
Sampling time
IA
t
6t
CY
µs
ADS
ADC
t
Conversion time (including sampling time)
24t
µs
CY
8, 9, 10
DL
Differential non-linearity
±1
LSB
LSB
LSB
%
e
8, 11
IL
e
Integral non-linearity
±1
±1
8, 12
OS
Offset error
e
8, 13
G
Gain error
0.4
±1
e
M
CTC
Channel to channel matching
LSB
dB
14
C
Crosstalk between inputs of port 5
0–100kHz
–60
t
NOTES:
1. See Figures 8 through 12 for I test conditions.
DD
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V + 0.5V;
r
f
IL
SS
V
IH
= V – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = V ; STADC = V
.
DD
DD
SS
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V + 0.5V;
r
f
IL
SS
V
IH
= V – 0.5V; XTAL2 not connected; Port 0 = EW = V ; EA = RST = STADC = V
.
DD
DD
SS
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V
;
DD
EA = RST = STADC = XTAL1 = V
.
SS
5. Pins of ports 1, 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2V.
IN
6. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
7. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the
OH
DD
address bits are stabilizing.
8. Conditions: AV = 0V; AV = 5.0V, AV = 5.12V. ADC is monotonic with no missing codes.
REF+
REF–
DD
9. The differential non-linearity (DL ) is the difference between the actual step width and the ideal step width. (See Figure 1.)
e
10.The ADC is monotonic; there are no missing codes.
11. The integral non-linearity (IL ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
e
appropriate adjustment of gain and offset error. (See Figure 1.)
12.The offset error (OS ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
e
a straight line which fits the ideal transfer curve. (See Figure 1.)
13.The gain error (G ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
e
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)
14.This should be considered when both analog and digital signals are simultaneously input to port 5.
8
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
Offset
error
Gain
error
OS
e
G
e
255
254
253
252
251
250
(2)
7
(1)
Code
Out
6
5
(5)
4
3
(4)
(3)
2
1
1 LSB
(ideal)
0
1
2
3
4
5
6
7
250
251
252
253
254
)
255
256
AV (LSB
IN
ideal
Offset
error
OS
e
AV
– AV
REF–
REF+
256
1 LSB =
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DL ).
e
(4) Integral non-linearity (IL ).
e
(5) Center of a step of the actual transfer curve.
SU00227
Figure 1. ADC Conversion Characteristic
9
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
1, 2
AC ELECTRICAL CHARACTERISTICS
12MHz CLOCK
VARIABLE CLOCK
MIN MAX
16
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency
MIN
MAX
UNIT
MHz
ns
2
2
2
2
2
2
2
2
2
2
2
2
1.2
CLCL
t
t
t
t
t
t
t
t
t
t
t
ALE pulse width
127
28
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
–55
–35
ns
AVLL
LLAX
LLIV
CLCL
CLCL
48
t
ns
234
145
4t
3t
–100
ns
CLCL
43
t
–40
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
205
3t
CLCL
–45
ns
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
ns
CLCL
0
0
ns
59
312
10
t
–25
ns
CLCL
5t
CLCL
–105
ns
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3, 4
3
Address valid to ALE low
RD pulse width
43
t
6t
6t
–35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLL
CLCL
CLCL
CLCL
400
400
–100
–100
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
DW
4
WR pulse width
3
RD low to valid data in
Data hold after RD
252
5t
–165
CLCL
3
0
0
3
Data float after RD
97
2t
–70
CLCL
3
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data before WR
517
585
300
8t
–150
–165
CLCL
CLCL
3
9t
3, 4
3, 4
4
200
203
23
3t
–50
3t
+50
CLCL
CLCL
4t
–130
–60
CLCL
CLCL
CLCL
CLCL
t
4
433
33
7t
t
–150
–50
4
Data hold after WR
WHQX
RLAZ
WHLH
3
RD low to address float
RD or WR high to ALE high
0
0
3, 4
43
123
t
–40
t
+40
CLCL
CLCL
External Clock
3
t
t
t
t
5
5
5
5
High time
20
20
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
3
Low time
3
Rise time
20
20
20
20
3
Fall time
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
10
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A – Address
Q – Output data
R – RD signal
– Time
V – Valid
W – WR signal
t
X – No longer a valid logic level
Z – Float
C – Clock
D – Input data
H – Logic level high
Examples: t
= Time for address valid
to ALE low.
AVLL
I
– Instruction (program memory contents)
t
= Time for ALE low to
PSEN low.
LLPL
L – Logic level low, or ALE
P – PSEN
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 2. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPH
A0–A15 FROM PCH
SU00007
Figure 3. External Data Memory Read Cycle
11
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
t
t
LLAX
WHQX
t
AVLL
QVWX
t
DW
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
SU00213
Figure 4. External Data Memory Write Cycle
t
r
t
f
t
HIGH
V
0.8V
V
IH1
0.8V
V
V
IH1
0.8V
IH1
IH1
0.8V
t
LOW
t
CK
SU00228
SU00215
SU00216
Figure 5. External Clock Drive XTAL1
2.4V
2.0V
0.8V
2.0V
0.8V
Test Points
0.45V
NOTE:
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at 2.0V for a logic ‘1’ and 0.8V for a logic ‘0’.
Figure 6. AC Testing Input/Output
Float
2.4V
2.4V
2.0V
0.8V
2.0V
0.8V
0.45V
0.45V
NOTE:
The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400µA at the voltage test levels.
Figure 7. AC Testing Input, Float Waveform
12
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
50
40
30
(1)
I
mA
DD
20
10
0
(2)
(3)
(4)
(1) Maximum operating mode; V
= 6V
= 4V
DD
DD
(2) Maximum operating mode; V
NOTE:
0
4
8
12
16
(3) Maximum idle mode; V
(4) Maximum idle mode; V
= 6V
DD
DD
These values are valid only within the frequency
specifications of the device under test.
f (MHz)
= 4V
SU00229
Figure 8. Supply Current (I ) as a Function of Frequency at XTAL1 (f
)
DD
OSC
V
DD
I
DD
V
DD
V
V
DD
DD
P0
EA
RST
(NC)
XTAL2
XTAL1
EW
CLOCK SIGNAL
V
SS
STADC
SU00230
Figure 9. I Test Condition, Active Mode
DD
All other pins are disconnected
V
DD
I
DD
V
DD
RST
V
DD
STADC
P0
EW
EA
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
AV
SS
V
SS
AV
ref
SU00231
Figure 10. I Test Condition, Idle Mode
DD
All other pins are disconnected
13
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
V
–0.5
DD
0.5V
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00232
Figure 11. Clock Signal Waveform for I
Tests in Active and Idle Modes
DD
t
= t
= 10ns
CHCL
CLCH
V
DD
I
DD
V
DD
V
RST
DD
STADC
P0
EW
EA
(NC)
XTAL2
XTAL1
AV
SS
AV
ref
V
SS
SU00233
Figure 12.
I
Test Condition, Power Down Mode
DD
All other pins are disconnected. V = 2V to 5.5V
DD
14
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
SOT188-3
15
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
1473A
68-PIN CERQUAD J-BEND (K) PACKAGE
853-1473A 05854
16
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
NOTES
17
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
NOTES
18
1992 Jan 08
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
NOTES
19
1992 Jan 08
Philips Semiconductors Microcontroller Products
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1992
All rights reserved. Printed in U.S.A.
Telephone 800-234-7381
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