S83C751-2A28 [NXP]
80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count; 80C51的8位单片机系列2K / 64 OTP / ROM ， I2C ，低引脚数
| 型号： | S83C751-2A28 |
| 厂家： | 
NXP |
| 描述： | 80C51 8-bit microcontroller family 2K/64 OTP/ROM, I2C, low pin count |
| 文件： | 总24页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
83C751/87C751
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
Product specification
1998 May 01
Supersedes data of 1998 Jan 19
IC20 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
DESCRIPTION
PIN CONFIGURATIONS
The Philips 83C751/87C751 offers the advantages of the 80C51
architecture in a small package and at low cost.
24
23
V
CC
P3.4/A4
P3.3/A3
1
2
3
The 8XC751 Microcontroller is fabricated with Philips high-density
CMOS technology. Philips epitaxial substrate minimizes CMOS
latch-up sensitivity.
P3.5/A5
P3.2/A2/A10
22 P3.6/A6
21 P3.7/A7
4
5
P3.1/A1/A9
P3.0/A0/A8
The 8XC751 contains a 2k × 8 ROM (83C751) EPROM (87C751), a
64 × 8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a
five-source, fixed-priority level interrupt structure, a bidirectional
inter-integrated circuit (I C) serial bus interface, and an on-chip
oscillator.
PLASTIC
DUAL
IN-LINE
PACKAGE
AND
SHRINK
SMALL
OUTLINE
PACKAGE
20 P1.7/T0/D7
19 P1.6/INT1/D6
6
7
P0.2/V
PP
2
P0.1/SDA/OE–PGM
P0.0/SCL/ASEL
18
P1.5/INT0/D5
2
17 P1.4/D4
16 P1.3/D3
The on-board inter-integrated circuit (I C) bus interface allows the
8
2
8XC751 to operate as a master or slave device on the I C small
9
RST
X2
area network. This capability facilitates I/O and RAM expansion,
access to EEPROM, processor-to-processor communication, and
15
14
13
P1.2/D2
P1.1/D1
P1.0/D0
10
11
12
2
efficient interface to a wide variety of dedicated I C peripherals.
X1
V
SS
FEATURES
• 80C51 based architecture
4
1
26
2
• Inter-Integrated Circuit (I C) serial bus interface
5
25
PLASTIC
LEADED
CHIP
• Small package sizes
– 24-pin DIP (300 mil “skinny DIP”)
– 24-pin Shrink Small Outline Package
– 28-pin PLCC
CARRIER
11
19
12
18
Pin
1
2
3
4
5
6
7
8
Function
P3.4/A4
P3.3/A3
P3.2/A2/A10
P3.1/A1/A9
NC*
PinFunction
Pin
19
20
21
22
23
24
25
26
27
28
Function
P1.4/D4
P1.5/INT0/D5
NC*
• 87C751 available in one-time programmable plastic packages
• Wide oscillator frequency range
10
11
12
13
14
15
16
17
18
NC*
RST
X2
X1
NC*
• Low power consumption:
– Normal operation: less than 11mA @ 5V, 12MHz
– Idle mode
V
P1.6/INT1/D6
P1.7/T0/D7
P3.7/A7
P3.6/A6
P3.5/A5
SS
P3.0/A0/A8
P1.0/D0
P1.1/D1
P1.2/D2
P1.3/D3
P0.2/V
PP
P0.1/SDA/OE-PGM
P0.0//SCLASEL
9
– Power-down mode
V
CC
• 2k × 8 ROM (83C751)
2k × 8 EPROM (87C751)
* DO NOT CONNECT
SU00315
• 64 × 8 RAM
• 16-bit auto reloadable counter/timer
• Fixed-rate timer
• Boolean processor
• CMOS and TTL compatible
• Well suited for logic replacement, consumer and industrial
applications
• LED drive outputs
2
1998 May 01
853-0599 19326
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
ORDERING INFORMATION
°
TEMPERATURE RANGE C
AND PACKAGE
DRAWING
FREQUENCY
1
ROM
EPROM
NUMBER
S83C751–1N24 S87C751–1N24
S83C751–2N24 S87C751–2N24
S83C751–4N24 S87C751–4N24
S83C751–5N24 S87C751–5N24
S83C751–1A28 S87C751–1A28
S83C751–2A28 S87C751–2A28
S83C751–4A28 S87C751–4A28
S83C751–5A28 S87C751–5A28
OTP
OTP
OTP
OTP
OTP
OTP
OTP
OTP
OTP
OTP
0 to +70, Plastic Dual In-line Package
–40 to +85, Plastic Dual In-line Package
0 to +70, Plastic Dual In-line Package
–40 to +85, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
–40 to +85, Plastic Leaded Chip Carrier
0 to +70, Plastic Leaded Chip Carrier
–40 to +85, Plastic Leaded Chip Carrier
0 to +70, Shrink Small Outline Package
0 to +70, Shrink Small Outline Package
3.5 to 12MHz
3.5 to 12MHz
3.5 to 16MHz
3.5 to 16MHz
3.5 to 12MHz
3.5 to 12MHz
3.5 to 16MHz
3.5 to 16MHz
3.5 to 12MHz
3.5 to 16MHz
SOT222-1
SOT222-1
SOT222-1
SOT222-1
SOT261-3
SOT261-3
SOT261-3
SOT261-3
SOT340-1
SOT340-1
S83C751–1DB
S83C751–4DB
S87C751–1DB
S87C751–4DB
NOTE:
1. OTP = One Time Programmable EPROM.
3
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
BLOCK DIAGRAM
P0.0–P0.2
PORT 0
DRIVERS
V
V
CC
SS
2
I C
CONTROL
RAM ADDR
REGISTER
PORT 0
LATCH
ROM/
EPROM
RAM
STACK
POINTER
B
ACC
REGISTER
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
PCON I2CFG I2STA TCON
ALU
I2DAT I2CON
IE
TH0
RTH
TL0
RTL
PC
INCRE-
MENTER
PSW
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
PROGRAM
COUNTER
TIMING
AND
RST
DPTR
CONTROL
PORT 1
LATCH
PORT 3
LATCH
PD
OSCILLATOR
PORT 1
DRIVERS
PORT 3
DRIVERS
X1
X2
P1.0–P1.7
P3.0–P3.7
SU00316
4
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
PIN DESCRIPTIONS
PIN NO.
DIP/
MNEMONIC
LCC
TYPE
NAME AND FUNCTION
SSOP
12
V
V
14
28
I
I
Circuit Ground Potential
Supply voltage during normal, idle, and power-down operation.
SS
24
CC
P0.0–P0.2
8–6
9–7
I/O
Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance inputs. Port 0 also serves as the serial I C
2
interface. When this feature is activated by software, SCL and SDA are driven low in accordance
2
2
with the I C protocol. These pins are driven low if the port register bit is written with a 0 or if the I C
subsystem presents a 0. The state of the pin can always be read from the port register by the
program.
2
To comply with the I C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the
electrical characteristics listed in the tables that follow. While these differ from “standard TTL”
characteristics, they are close enough for the pins to still be used as general-purpose I/O in
2
non-I C applications. Port 0 also provides alternate functions for programming the EPROM
memory as follows:
6
7
7
8
N/A
I
V
(P0.2) – Programming voltage input. (See Note 1.)
PP
OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
8
9
I
ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
2
7
8
8
9
I/O
I/O
SDA (P0.1) – I C data.
2
SCL (P0.0) – I C clock.
P1.0–P1.7
13–20 15–20,
23, 24
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I ). Port 1 serves to output the addressed EPROM contents in the verify
IL
mode and accepts as inputs the value to program into the selected address during the program
mode. Port 1 also serves the special function features of the 80C51 family as listed below:
18
19
20
20
23
24
I
I
I
INT0 (P1.5): External interrupt.
INT1 (P1.6): External interrupt.
T0 (P1.7): Timer 0 external input.
P3.0–P3.7
5–1,
23–21 27–25
6, 4–1,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I ). Port 3 also functions as the address input for the EPROM memory location to
IL
be programmed (or verified). The 11-bit address is multiplexed into this port as specified by
P0.0/ASEL.
RST
9
11
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to V permits a power-on RESET using only an external capacitor to
SS
V
CC
. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
the device in the programming state allowing programming address, data and V to be applied for
PP
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
X1
11
10
13
12
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
1. When P0.2 is at or close to 0V it may affect the internal ROM operation. We recommend that P0.2 be tied to V via a small pullup
CC
(e.g., 2kΩ).
5
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
1, 2
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
°C
V
Storage temperature range
–65 to +150
–0.5 to +6.5
Voltage from V to V
CC
SS
Voltage from any pin to V (except V
)
–0.5 to V + 0.5
V
SS
PP
CC
Power dissipation
1.0
0 to +13.0
10
W
Voltage on V pin to V
V
PP
SS
Maximum I per I/O pin
mA
OL
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
DC ELECTRICAL CHARACTERISTICS
1
T
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10% for 87C751, V = 5V ±10% for 83C751, V = 0V
amb
CC CC SS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
V
V
V
Input low voltage, except SDA, SCL
Input high voltage, except X1, RST
Input high voltage, X1, RST
–0.5
0.2V –0.1
V
V
V
IL
DD
0.2V +0.9
V
CC
V
CC
+0.5
+0.5
IH
CC
0.7V
IH1
CC
SDA, SCL, P0.2
Input low voltage
Input high voltage
V
V
–0.5
0.3V
V
V
IL1
CC
0.7V
V
CC
+0.5
IH2
CC
2
V
V
Output low voltage, ports 1 and 3
Output low voltage, port 0.2
I
I
= 1.6mA
= 3.2mA
0.45
0.45
V
V
OL
OL
2
OL1
OL
V
OH
Output high voltage, ports 1 and 3
I
I
I
= –60µA
= –25µA
= –10µA
2.4
V
V
V
OH
OH
OH
0.75V
CC
CC
0.9V
2
Port 0.0 and 0.1 (I C) – Drivers
V
Output low voltage
Driver, receiver combined:
Capacitance
I
= 3mA
0.4
V
OL2
OL
(over V range)
CC
C
10
pF
I
I
Logical 0 input current, ports 1 and 3
Logical 1 to 0 transition current, ports 1 and 3
V
= 0.45V
–50
–650
–750
µA
µA
µA
IL
IN
3
V
IN
= 2V (0 to 70°C)
= 2V (–40 to +85°C)
TL
IN
V
I
Input leakage current, port 0
Internal pull-down resistor
0.45 < V < V
CC
±10
µA
LI
IN
R
C
25
175
kΩ
RST
IO
Test freq = 1MHz,
= 25°C
Pin capacitance
10
50
pF
T
amb
4
I
Power-down current
V
= 2 to V max
µA
PD
CC
CC
V
CC
= 0V
= 5V±10%
SS
V
V
V
program voltage (for 87C751 only)
12.5
13.0
50
V
PP
PP
T
amb
= 21°C to 27°C
I
I
Program current (for 87C751 only)
Supply current (see Figure 2)
V
PP
= 13.0V
mA
PP
CC
NOTES TO DC ELECTRICAL CHARACTERISTICS ON NEXT PAGE.
6
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
NOTES TO DC ELECTRICAL CHARACTERISTICS:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
2. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
10mA
26mA
67mA
(NOTE: This is 85°C spec.)
OL
Maximum I per 8-bit port:
Maximum total I for all outputs:
OL
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2V.
IN
4. Power-down I is measured with all output pins disconnected; port 0 = V ; X2, X1 n.c.; RST = V .
CC
CC
SS
5. Active I is measured with all output pins disconnected; X1 driven with t
, t
= 5ns, V = V + 0.5V, V = V – 0.5V; X2 n.c.;
CC
CLCH CHCL IL SS IH CC
RST = port 0 = V . I will be slightly higher if a crystal oscillator is used.
CC CC
6. Idle I is measured with all output pins disconnected; X1 driven with t
, t
= 5ns, V = V + 0.5V, V = V – 0.5V; X2 n.c.;
CC
CLCH CHCL IL SS IH CC
port 0 = V ; RST = V
.
CC
SS
AC ELECTRICAL CHARACTERISTICS
1, 2
T
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10% for 87C751, V = 5V ±10% for 83C751, V = 0V
amb
CC CC SS
12MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
PARAMETER
MIN
MAX
MIN
MAX
UNIT
Oscillator frequency:
3.5
3.5
12
16
MHz
MHz
CLCL
External Clock (Figure 1)
t
t
t
t
High time
Low time
Rise time
Fall time
20
20
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
20
20
20
20
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
2. Load capacitance for ports = 80pF.
7
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
C – Clock
D – Input data
H – Logic level high
L
–
Logic level low
Q – Output data
T
V
X
Z
–
–
–
–
Time
Valid
No longer a valid logic level
Float
t
V
–0.5
CLCX
CC
0.2 V + 0.9
CC
0.2 V – 0.1
CC
t
0.45V
CHCX
t
t
CLCH
CHCL
t
CLCL
SU00297
Figure 1. External Clock Drive
5
22
MAX ACTIVE I
CC
20
18
16
14
12
10
8
I
(mA)
CC
5
TYP ACTIVE I
CC
6
6
MAX IDLE I
TYP IDLE I
CC
4
2
6
CC
4MHz
8MHz
FREQ
12MHz
16MHz
SU00298
Figure 2. I vs. FREQ
CC
Maximum I values taken at V max and worst case temperature.
CC
CC
Typical I values taken at V = 5.0V and 25°C.
CC
CC
Notes 5 and 6 refer to DC Electrical Characteristics.
8
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
should be noted that stack depth is limited to 64 bytes, the amount
of available RAM. A reset loads the stack pointer with 07 (which is
pre-incremented on a PUSH instruction).
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
(FFH) 255
Special
Function
Registers
(80H) 128
(3FH) 63
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-up, the voltage on
Internal Data
RAM
(00H) 0
V
CC
and RST must come up at the same time for a proper start-up.
SU00299
Figure 3. Memory Map
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
Program Memory
On the 8XC751, program memory is 2048 bytes long and is not
externally expandable, so the 80C51 instructions MOVX, LJMP, and
LCALL are not implemented. The only fixed locations in program
memory are the addresses at which execution is taken up in
response to reset and interrupts, which are as follows:
Program Memory
Event
Reset
Address
000
External INT0
Counter/timer 0
External INT1
Timer I
003
00B
013
01B
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. the control
bits for the reduced power modes are in the special function register
PCON.
2
I C serial
023
Counter/Timer Subsystem
The 8XC751 has one counter/timer called timer/counter 0. Its
operation is similar to mode 2 operation on the 80C51, but is
extended to 16 bits with 16 bits of autoload. The controls for this
counter are centralized in a single register called TCON.
Table 1.
External Pin Status During Idle and
Power-Down Modes
2
A watchdog timer, called Timer I, is for use with the I C subsystem.
MODE
Port 0
Port 1
Port 2
2
In I C applications, this timer is dedicated to time-generation and
2
2
Idle
Power-down
Data
Data
Data
Data
Data
Data
bus monitoring of the I C. In non-I C applications, it is available for
use as a fixed time-base.
Counter Timer – Special Function Register
The counter/timer has only one mode of operation, so the TMOD
SFR is not used. There is also only one counter/timer, so there is no
need for the TL1 and TH1 SFRs found on the 80C51. These have
been replaced on the 83C751 by RTL and RTH, the counter/timer
reload registers. Table 3 shows the special function registers, their
locations, and reset values.
DIFFERENCES BETWEEN THE 8XC751 AND THE
80C51
Memory Organization
The central processing unit (CPU) manipulates operands in two
address spaces as shown in Figure 3. The part’s internal memory
space consists of 2k bytes of program memory, and 64 bytes of data
RAM overlapped with the 128-byte special function register area.
The differences from the 80C51 are in RAM size (64 bytes vs. 128
bytes), in external RAM access (not available on the 83C751), in
internal ROM size (2k bytes vs. 4k bytes), and in external program
memory expansion (not available on the 83C751). The 128-byte
special function register (SFR) space is accessed as on the 80C51
with some of the registers having been changed to reflect changes
in the 83C751 peripheral functions. The stack may be located
anywhere in internal RAM by loading the 8-bit stack pointer (SP). It
Interrupt Subsystem – Fixed Priority
The IP register and the 2-level interrupt system of the 80C51 are
eliminated. Simultaneous interrupt conditions are resolved by a
single-level, fixed priority as follows:
Highest priority:
Pin INT0
Counter/timer flag 0
Pin INT1
Timer I
Serial I C
2
Lowest priority:
9
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
2
been replaced by I2CON and I2DAT, and two additional I C registers
have been added (I2STA and I2CFG).
Special Function Register – Interrupt Subsystem
Because the interrupt structure is single level on the 83C751, there
is no need for the IP SFR, so it is not used.
I/O Port Latches (P0, P1, P3)
The port latches function the same as those on the 80C51. Since
there is no port 2 on the 83C751, the P2 latch is not used. Port 0 on
the 83C751 has only 3 bits, so only 3 bits of the P0 SFR have a
useful function.
Serial Communications
2
The 8XC751 contains an I C serial communications port instead of
2
the 80C51 UART. The I C serial port is a single bit hardware
interface with all of the hardware necessary to support multimaster
and slave operations. Also included are receiver digital filters and
timer (timer I) for communication watch-dog purposes. The I C
2
Special Function Register – I/O Port Latches
There is no Port2 on the 8XC751, so P2 is not used. Also, only 3
bits of P0 SFR have a useful function.
2
serial port is controlled through four special function registers; I C
2
2
2
control, I C data, I C status, and I C configuration.
Data Pointer (DPTR)
Special Function Register –
The data pointer (DPTR) consists of a high byte (DPH) and a low
byte (DPL). In the 80C51 this register allows the access of external
data memory using the MOVX instruction. Since the 83C751 does
not support MOVX or external memory accesses, this register is
generally used as a 16-bit offset pointer of the accumulator in a
MOVC instruction. DPTR may also be manipulated as two
independent 8-bit registers.
Serial Communications
The 83C751 contains many of the special function registers (SFR)
that are found on the 80C51. Due to the different peripheral features
on the 83C751, there are several additional SFRs and several that
have been changed.
Since the standard UART found on the 80C51 has been replaced by
2
the I C serial interface, the UART SFRs, SCON, and SBUF have
2
Table 2. I C Special Function Register Addresses
REGISTER ADDRESS
BIT ADDRESS
LSB
NAME
SYMBOL
I2CON
I2DAT
ADDRESS
MSB
9F
2
I C control
98
99
D8
F8
9E
–
9D
–
9C
–
9B
–
9A
–
99
–
98
–
2
I C data
–
2
I C configuration
I2CFG
I2STA
DF
FF
DE
FE
DD
FD
DC
FC
DB
FB
DA
FA
D9
F9
D8
F8
2
I C status
ROM CODE SUBMISSION
When submitting ROM code for the 80C751, the following must be specified:
1. 2k byte user ROM data
ADDRESS
CONTENT
BIT(S)
COMMENT
0000H to 07FFH
DATA
7:0
User ROM Data
10
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
Table 3.
8XC751 Special Function Registers
DIRECT
DESCRIPTION
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ADDRESS MSB
RESET
VALUE
SYMBOL
LSB
E0
ACC*
B*
Accumulator
B register
E0H
F0H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
E2
F2
E1
F1
00H
F0
00H
DPTR:
Data pointer
(2 bytes)
DPH
DPL
High byte
Low byte
83H
82H
00H
00H
DF
DE
DD
0
DC
DB
–
DA
–
D9
D8
2
2
SLAVEN MASTRQ
I CFG*#
I C configuration
D8H/RD
WR
TIRUN
TIRUN
CT1
CT1
CT0
CT0
0000xx00B
SLAVEN MASTRQ
CLRTI
–
–
9F
9E
9D
9C
9B
9A
99
98
–
2
2
MASTER
I CON*#
I C control
98H/RD
WR
RDAT
CXA
ATN
IDLE
DRDY
CDR
ARL
STR
STP
81H
80H
CARL
CSTR
CSTP
XSTR
XSTP
2
2
I DAT#
I C data
99H/RD
WR
RDAT
XDAT
0
0
0
0
0
0
0
X
X
X
X
X
X
X
FF
–
FE
FD
FC
FB
FA
F9
F8
2
2
MAKSTR
MAKSTP
I STA*#
I C status
F8H
ABH
80H
IDLE
XDATA XACTV
XSTR
XSTP x0100000B
AF
EA
AE
–
AD
–
AC
EI2
AB
AA
A9
A8
IE*#
Interrupt enable
Port 0
ET1
EX1
ET0
EX0
00H
82
–
81
80
P0*#
–
–
–
–
–
SDA
SCL
xxxxx111B
97
T0
B7
96
INT1
B6
95
INT0
B5
94
–
93
–
92
–
91
–
90
–
P1*
P3*
Port 1
Port 3
90H
B0H
FFH
FFH
B4
B3
B2
B1
B0
PCON#
Power control
87H
–
–
–
–
–
–
PD
IDL
xxxxxx00B
D7
CY
D6
AC
D5
F0
D4
D3
D2
D1
–
D0
P
PSW*
SP
Program status word
Stack pointer
D0H
81H
88H
RS1
RS0
OV
00H
07H
00H
8F
8E
8D
TF
8C
TR
8B
8A
89
88
TCON*#
Timer/counter control
GATE
C/T
IE0
IT0
IE1
IT1
TL#
Timer low byte
Timer high byte
Timer low reload
Timer high reload
8AH
8CH
8BH
8DH
00H
00H
00H
00H
TH#
RTL#
RTH#
*
#
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
11
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
I/O Port Structure
TCON Register
The 8XC751 has two 8-bit ports (ports 1 and 3) and one 3-bit port
(port 0). All three ports on the 8XC751 are bidirectional. Each
consists of a latch (special function register P0, P1, P3), an output
driver, and an input buffer. Three port 1 pins and two port 0 pins are
multifunctional. In addition to being port pins, these pins serve the
function of special features as follows:
MSB
LSB
GATE
C/T
TF
TR
IE0
IT0
IE1
IT1
GATE
1
–
Timer/counter is enabled only when INT0 pin is
high, and TR is 1.
0
1
0
1
0
–
–
–
–
–
Timer/counter is enabled when TR is 1.
Counter/timer operation from T0 pin.
Timer operation from internal clock.
Set on overflow of TH.
Cleared when processor vectors to interrupt routine
and by reset.
Timer/counter enabled.
Timer/counter disabled.
Edge detected in INT0.
INT0 is edge triggered.
Port PinAlternate Function
C/T
TF
2
P0.0
P0.1
P1.5
P1.6
P1.7
I C clock (SCL)
2
I C data (SDA)
INT0 (external interrupt 0 input)
INT1 (external interrupt 1 input)
T0 (timer 0 external input)
TR
1
0
1
1
0
1
1
0
–
–
–
–
–
–
–
–
IE0
IT0
Ports 1 and 3 are identical in structure to the same ports on the
80C51. The structure of port 0 on the 8XC751 is similar to that of the
80C51 but does not include address/data input and output circuitry.
As on the 80C51, ports 1 and 3 are quasi-bidirectional while port 0 is
bidirectional with no internal pullups.
INT0 is level sensitive.
Edge detected on INT1.
INT1 is edge triggered.
INT1 is level sensitive.
IE1
IT1
These flags are functionally identical to the corresponding 80C51
flags, except that there is only one timer on the 83C751 and the
flags are therefore combined into one register.
Timer/Counter
The 8XC751 has two timers: a 16-bit timer/counter and a 10-bit
fixed-rate timer. The 16-bit timer/counter’s operation is similar to
mode 2 operation on the 80C51, but is extended to 16 bits. The
timer/counter is clocked by either 1/12 the oscillator frequency or by
transitions on the T0 pin. The C/T pin in special function register
TCON selects between these two modes. When the TCON TR bit is
set, the timer/counter is enabled. Register pair TH and TL are
incremented by the clock source. When the register pair overflows,
the register pair is reloaded with the values in registers RTH and
RTL. The value in the reload registers is left unchanged. See the
83C751 counter/timer block diagram in Figure 4. The TF bit in
special function register TCON is set on counter overflow and, if the
interrupt is enabled, will generate an interrupt.
Note that the positions of the IE0/IT0 and IE1/IT1 bits are
transposed from the positions used in the standard 80C51 TCON
register.
2
Timer I is used to control the timing of the I C bus and also to detect
a “bus locked” condition, by causing an interrupt when nothing
2
happens on the I C bus for an inordinately long period of time while
a transmission is in progress. If the interrupt does not occur, the
2
program can attempt to correct the fault and allow the last I C
transmission to be repeated.
2
The I C watchdog timer, timer I, is also available as a
2
general-purpose fixed-rate timer when the I C interface is not being
used. A clock rate of 1/12 the oscillator frequency forms the input to
the timer. Timer I has a timeout interval of 1024 machine cycles
when used as a fixed-rate timer.
OSC
÷ 12
C/T = 0
C/T = 1
TL
TH
TF
Int.
T0 Pin
TR
Reload
Gate
RTL
RTH
INT0 Pin
SU00300
Figure 4. 83C751 Counter/Timer Block Diagram
12
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
2
2
I C Serial Interface
performance of the I C bus. See special function register I2CFG
description for prescale values (CT0, CT1).
2
The I C bus uses two wires (SDA and SCL) to transfer information
between devices connected to the bus. The main features of the bus
are:
The MAXIMUM SCL CHANGE time is important, but its exact span
is not critical. The complete 10 bits of timer I are used to count out
the maximum time. When I C operation is enabled, this counter is
2
• Bidirectional data transfer between masters and slaves
• Serial addressing of slaves (no added wiring)
• Acknowledgment after each transferred byte
• Multimaster bus
cleared by transitions on the SCL pin. The timer does not run
2
between I C frames (i.e., whenever reset or stop occurred more
recently than the last start). When this counter is running, it will carry
out after 1020 to 1023 machine cycles have elapsed since a change
2
on SCL. A carry out causes a hardware reset of the 83C751 I C
interface and generates an interrupt if the timer I interrupt is
enabled. In cases where the bus hangup is due to a lack of software
response by this 83C751, the reset releases SCL and allows I C
operation among other devices to continue.
• Arbitration between simultaneously transmitting masters without
corruption of serial data on bus
2
• The 82B715 extends communication distance to 100 feet (30M).
2
2
A large family of I C compatible ICs is available. See the I C section
of this manual for more details on the bus and available ICs.
2
I C Interrupts
2
2
If I C interrupts are enabled (EA and EI2 are both set to 1), an I C
interrupt will occur whenever the ATN flag is set by a start, stop,
arbitration loss, or data ready condition (refer to the description of
2
The 83C751 I C subsystem includes hardware to simplify the
2
software required to drive the I C bus. The hardware is a single bit
2
ATN following). In practice, it is not efficient to operate the I C
interface which in addition to including the necessary arbitration and
framing error checks, includes clock stretching and a bus timeout
timer. The interface is synchronized to software either through polled
loops or interrupts. Refer to the application note AN422, in
Section 4, entitled “Using the 8XC751 Microcontroller as an I C Bus
Master” for additional discussion of the 83C751 I C interface and
2
interface in this fashion because the I C interrupt service routine
would somehow have to distinguish between hundreds of possible
2
conditions. Also, since I C can operate at a fairly high rate, the
2
2
software may execute faster if the code simply waits for the I C
2
interface.
sample driver routines.
2
Typically, the I C interrupt should only be used to indicate a start
2
condition at an idle slave device, or a stop condition at an idle master
Six time spans are important in I C operation and are insured by
timer I:
2
device (if it is waiting to use the I C bus). This is accomplished by
2
enabling the I C interrupt only during the aforementioned conditions.
• The MINIMUM HIGH time for SCL when this device is the master.
2
I C Register I2CON
• The MINIMUM LOW time for SCL when this device is a master.
This is not very important for a single-bit hardware interface like
this one, because the SCL low time is stretched until the software
7
6
5
4
3
2
1
0
–
Read
Write
RDAT
ATN
DRDY
ARL
STR
STP
MASTER
2
responds to the I C flags. The software response time normally
meets or exceeds the MIN LO time. In cases where the software
responds within MIN HI + MIN LO) time, timer I will ensure that
the minimum time is met.
CXA
IDLE
CDR
CARL CSTR
CSTP
XSTR
XSTP
Reading I2CON
RDAT
• The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition.
The data from SDA is captured into “Receive DATa”
whenever a rising edge occurs on SCL. RDAT is also
available (with seven low-order zeros) in the I2DAT
2
• The MINIMUM SDA HIGH TO SDA LOW time between I C stop
and start conditions (4.7µs, see spec.).
register. The difference between reading it here and there
2
• The MINIMUM SDA LOW TO SCL LOW time in a start condition.
is that reading I2DAT clears DRDY, allowing the I C to
proceed on to another bit. Typically, the first seven bits of a
received byte are read from I2DAT, while the 8th is read
here. Then I2DAT can be written to send the Ack bit and
clear DRDY.
2
• The MAXIMUM SCL CHANGE time while an I C frame is in
progress. A frame is in progress between a start condition and the
following stop condition. This time span serves to detect a lack of
software response on this 8XC751 as well as external I C
2
ATN
“ATteNtion” is 1 when one or more of DRDY, ARL, STR, or
STP is 1. Thus, ATN comprises a single bit that can be
tested to release the I C service routine from a “wait loop.”
problems. SCL “stuck low” indicates a faulty master or slave. SCL
“stuck high” may mean a faulty device, or that noise induced onto
the I C bus caused all masters to withdraw from I C arbitration.
2
2
2
DRDY “Data ReaDY” (and thus ATN) is set when a rising edge
occurs on SCL, except at idle slave. DRDY is cleared by
writing CDR = 1, or by writing or reading the I2DAT
register. The following low period on SCL is stretched until
the program responds by clearing DRDY.
2
The first five of these times are 4.7µs (see I C specification) and are
covered by the low order three bits of timer I. Timer I is clocked by
the 8XC751 oscillator, which can vary in frequency from 0.5 to
16MHz. Timer I can be preloaded with one of four values to optimize
timing for different oscillator frequencies. At lower frequencies,
software response time is increased and will degrade maximum
13
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
Checking ATN and DRDY
Regarding Transmit Active
When a program detects ATN = 1, it should next check DRDY. If
DRDY = 1, then if it receives the last bit, it should capture the data
from RDAT (in I2DAT or I2CON). Next, if the next bit is to be sent, it
should be written to I2DAT. One way or another, it should clear
DRDY and then return to monitoring ATN. Note that if any of ARL,
STR, or STP is set, clearing DRDY will not release SCL to high, so
that the I C will not go on to the next bit. If a program detects
ATN = 1, and DRDY = 0, it should go on to examine ARL, STR, and
STP.
Transmit Active is set by writing the I2DAT register, or by writing
I2CON with XSTR = 1 or XSTP = 1. The I C interface will only drive
2
the SDA line low when Transmit Active is set, and the ARL bit will
only be set to 1 when Transmit Active is set. Transmit Active is
cleared by reading the I2DAT register, or by writing I2CON with
CXA = 1. Transmit Active is automatically cleared when ARL is 1.
2
2
IDLE
Writing 1 to “IDLE” causes a slave’s I C hardware to
ignore the I C until the next start condition (but if MASTRQ
2
is 1, then a stop condition will make the 83C751 into a
master).
ARL
“Arbitration Loss” is 1 when transmit Active was set, but
this 83C751 lost arbitration to another transmitter.
Transmit Active is cleared when ARL is 1. There are four
separate cases in which ARL is set.
CDR
Writing a 1 to “Clear Data Ready” clears DRDY. (Reading
or writing the I2DAT register also does this.)
CARL
CSTR
CSTP
Writing a 1 to “Clear Arbitration Loss” clears the ARL bit.
Writing a 1 to “Clear STaRt” clears the STR bit.
1. If the program sent a 1 or repeated start, but another
device sent a 0, or a stop, so that SDA is 0 at the
rising edge of SCL. (If the other device sent a stop, the
setting of ARL will be followed shortly by STP being
set.)
2. If the program sent a 1, but another device sent a
repeated start, and it drove SDA low before the
83C751 could drive SCL low. (This type of ARL is
always accompanied by STR = 1.)
3. In master mode, if the program sent a repeated start,
but another device sent a 1, and it drove SCL low
before this 83C751 could drive SDA low.
4. In master mode, if the program sent stop, but it could
not be sent because another device sent a 0.
Writing a 1 to “Clear SToP” clears the STP bit. Note that if
one or more of DRDY, ARL, STR, or STP is 1, the low time
of SCL is stretched until the service routine responds by
clearing them.
2
XSTR
Writing 1s to “Xmit repeated STaRt” and CDR tells the I C
hardware to send a repeated start condition. This should
only be at a master. Note that XSTR need not and should
not be used to send an “initial” (nonrepeated) start; it is
2
sent automatically by the I C hardware. Writing XSTR = 1
includes the effect of writing I2DAT with XDAT = 1; it sets
Transmit Active and releases SDA to high during the SCL
2
low time. After SCL goes high, the I C hardware waits for
2
the suitable minimum time and then drives SDA low to
make the start condition.
STR
STP
“STaRt” is set to a 1 when an I C start condition is
detected at a non-idle slave or at a master. (STR is not set
when an idle slave becomes active due to a start bit; the
slave has nothing useful to do until the rising edge of SCL
sets DRDY.)
2
XSTP
Writing 1s to “Xmit SToP” and CDR tells the I C hardware
to send a stop condition. This should only be done at a
master. If there are no more messages to initiate, the
service routine should clear the MASTRQ bit in I2CFG to 0
before writing XSTP with 1. Writing XSTP = 1 includes the
effect of writing I2DAT with XDAT = 0; it sets Transmit
Active and drives SDA low during the SCL low time. After
2
“SToP” is set to 1 when an I C stop condition is detected
at a non-idle slave or at a master. (STP is not set for a
stop condition at an idle slave.)
MASTER“MASTER” is 1 if this 83C751 is currently a master on the
2
SCL goes high, the I C hardware waits for the suitable
2
I C. MASTER is set when MASTRQ is 1 and the bus is
minimum time and then releases SDA to high to make the
stop condition.
not busy (i.e., if a start bit hasn’t been received since reset
or a “Timer I” time-out, or if a stop has been received since
the last start). MASTER is cleared when ARL is set, or
after the software writes MASTRQ = 0 and then XSTP = 1.
NOTE: Because of the manner in which register bit addressing is
implemented in the 80C51 family, the I2CON register should never be
altered by use of the SETB, CLR, CPL, MOV (bit), or JBC
instructions. This is due to the fact that read and write functions of this
register are different. Testing of I2CON bits via the JB and JNB
instructions is supported.
Writing I2CON
2
Typically, for each bit in an I C message, a service routine waits for
ATN = 1. Based on DRDY, ARL, STR, and STP, and on the current
bit position in the message, it may then write I2CON with one or
more of the following bits, or it may read or write the I2DAT register.
CXA
Writing a 1 to “Clear Xmit Active” clears the Transmit
Active state. (Reading the I2DAT register also does this.)
14
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
2
2
I C Register I2DAT
I C Register I2CFG
7
6
5
0
4
0
3
0
2
0
1
0
0
0
7
6
5
0
4
3
–
2
–
1
0
Read
Write
RDAT
0
Read
Write
SLAVEN
SLAVEN
MASTRQ
MASTRQ
TIRUN
CT1
CT0
XDAT
X
X
X
X
X
X
X
CLRTI
TIRUN
–
–
CT1
CT0
RDAT
XDAT
“Receive DATa” is captured from SDA every rising edge of
SCL. Reading I2DAT also clears DRDY and the Transmit
Active state.
SLAVEN Writing a 1 to “SLAVe ENable” enables the slave functions
2
of the I C subsystem. If SLAVEN and MASTRQ are 0, the
2
I C hardware is disabled. This bit is cleared to 0 by reset
2
and by an I C time-out.
“Xmit Data” sets the data for the next bit. Writing I2DAT
also clears DRDY and sets the Transmit Active state.
2
MASTRQ Writing a 1 to “MASTRQ” requests mastership of the I C.
If a frame from another master is in progress when this
bit is changed from 0 to 1, action is delayed until a stop
condition is detected. Then, or immediately if a frame is
not in progress, a start condition is sent and DRDY is set
Regarding Software Response Time
2
Because the 83C751 can run at 16MHz, and because the I C
interface is optimized for high-speed operation, it is quite likely that
2
2
an I C service routine will sometimes respond to DRDY (which is set
(thus making ATN 1 and generating an I C interrupt).
at a rising edge of SCL) and write I2DAT before SCL has gone low
again. If XDAT were applied directly to SDA, this situation would
produce an I C protocol violation. The programmer need not worry
When a master wishes to release mastership status of
2
the I C, it writes a 1 to XSTP in I2CON. MASTRQ is
2
2
cleared by reset and by an I C time-out.
about this possibility because XDAT is applied to SDA only when
SCL is low.
CLRTI
TIRUN
Writing a 1 to this bit clears the Timer I interrupt flag. This
bit position always reads as a 0.
2
Conversely, a program that includes an I C service routine may take
Writing a 1 to this bit lets Timer I run; a zero stops and
clears it. Together with SLAVEN, MASTRQ, and
MASTER, this bit determines operational modes as
shown in Table 4.
2
a long time to respond to DRDY. Typically, an I C routine operates
on a flag-polling basis during a message, with interrupts from other
peripheral functions enabled. If an interrupt occurs, it will delay the
2
response of the I C service routine. The programmer need not worry
CT1,0
These two bits are programmed as a function of the OSC
rate, to optimize the MIN HI and LO time of SCL when
2
about this very much either, because the I C hardware stretches the
SCL low time until the service routine responds. The only constraint
on the response is that it must not exceed the Timer I time-out,
which is at least 765 microseconds.
2
this 83C751 is a master on the I C. The time value
determined by these bits controls both of these
parameters, and also the timing for stop and start
conditions. These bits are cleared to 00 by reset.
Values to be used in the CT1 and CT0 bits are shown in Table 5. To
2
allow the I C bus to run at the maximum rate for a particular
oscillator frequency, compare the actual oscillator rate to the f
OSC
max column in the table. The value for CT1 and CT0 is found in the
first line of the table where f
actual frequency.
max is greater than or equal to the
OSC
The table also shows the osc/12 count for various settings of
CT1/CT0. This allows calculation of the actual minimum high and
low times for SCL as follows:
SCL min high/low time (in microseconds) = 12 * count / osc (in MHz)
For instance, at a 16MHz frequency, with CT1/CT0 set to 10, the
minimum SCL high and low times will be 5.25µs.
The table also shows the Timer I timeout period (given in machine
cycles) for each CT1/CT0 combination. The timeout period varies
because of the way in which minimum SCL high and low times are
2
measured. When the I C interface is operating, Timer I is preloaded
at every SCL transition with a value dependent upon CT1/CT0. The
preload value is chosen such that a minimum SCL high or low time
has elapsed when Timer I reaches a count of 008 (the actual value
preloaded into Timer I is 8 minus the osc/12 count).
15
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
Table 4.
Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER
SLAVEN,
MASTRQ,
MASTER
TIRUN
OPERATING MODE
2
2
All 0
0
1
0
1
The I C interface is disabled. Timer I is cleared and does not run. This is the state assumed after a reset. If an I C
2
application wants to ignore the I C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero.
2
2
All 0
The I C interface is disabled. Timer I operates as a free-running time base. Use this mode only in non-I C
applications.
2
Any or all 1
Any or all 1
The I C interface is enabled. The 3 low-order bits of Timer I run for min-time generation, but the hi-order bits do
2
2
not, so that there is no checking for I C being “hung.” This configuration can be used for very slow I C operation.
2
2
The I C interface is enabled. Timer I runs during frames on the I C, and is cleared by transitions on SCL, and by
2
Start and Stop conditions. This is the normal state for I C operation.
Table 5.
CT1, CT0 Values
CT1, CT0
OSC/12 COUNT
f
MAX
TIMEOUT PERIOD
1023 cycles
OSC
10
01
00
11
7
6
5
4
16.8MHz
14.4MHz
12.0MHz
9.6MHz
1022 cycles
1021 cycles
1020 cycles
2
I C Register I2STA
The interrupt enable register (IE) is used to individually enable or
disable the five sources. Bit EA in the interrupt enable register can
be used to globally enable or disable all interrupt sources. The
interrupt enable register is described below. All other interrupt details
are based on the 80C51 interrupt architecture.
READ ONLY
7
6
5
4
3
2
1
0
–
IDLE
XDATA
XACTV
MAKSTR
MAKSTP
XSTR
XSTP
MSB
LSB
2
Interrupt Enable Register
7
6
5
4
3
2
1
0
This register is read only and reflects the internal status of the I C
hardware. IDLE, XSTR, and XSTP reflect the status of the like
named bits in the I2CON register.
EA
X
X
EI2
ETI
EX1
ET0
EX0
Symbol Position Function
XDATA
The content of the transmitter buffer.
XACTV Transmitter active.
EA
IE.7
Disables all interrupts. If EA = 0, no interrupt
will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit
MAKSTR This bit is high while the hardware is effecting a start
condition.
MAKSTP This bit is high while the hardware is effecting a stop
condition.
–
–
IE.6
IE.5
IE.4
Reserved
Reserved
XSTR
This bit is active while the hardware is effecting a
repeated start condition.
2
XSTP
This bit is active while the hardware is effecting a
repeated stop condition.
EI2
Enables or disables the I C interrupt.
2
If EI2 = 0, the I C interrupt is disabled
ETI
IE.3
Enables or disables the Timer I overflow
interrupt. If ETI = 0, the Timer I interrupt is
disabled.
Interrupts
The interrupt structure is a five-source, one-level interrupt system.
Interrupt sources common to the 80C51 are the external interrupts
(INT0, INT1) and the timer/counter interrupt (ET0). The I C interrupt
(EI2) and Timer I interrupt (ETI) are the other two interrupt sources.
The interrupt sources are listed below in their order of polling
sequence priority.
2
EX1
ET0
IE.2
IE.1
Enables or disables external interrupt 1.
If EX1 = 0, external interrupt 1 is disabled.
Enables or disables the Timer 0 overflow
interrupt. If ET0 = 0, theTimer 0 interrupt is
disabled.
Upon interrupt or reset the program counter is loaded with specific
values for the appropriate interrupt service routine in program
memory. These values are:
EX0
IE.0
Enables or disables external interrupt 0.
If EX0 = 0, external interrupt 0 is disabled.
Program Memory
Event
Reset
Address
000
Priority
Highest
INT0
003
Counter/Timer 0
INT1
00B
013
Timer I
I C
01B
023
2
Lowest
16
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
repeated until a total of 25 programming pulses have occurred. At
the conclusion of the last pulse, the PGM/ signal should remain high.
87C751 PROGRAMMING CONSIDERATIONS
EPROM Characteristics
The V signal may now be driven to the V level, placing the
PP
OH
The 87C751 is programmed by using a modified Quick-Pulse
Programming algorithm similar to that used for devices such as the
87C451 and 87C51. It differs from these devices in that a serial data
stream is used to place the 87C751 in the programming mode.
87C751 in the verify mode. (Port 1 is now used as an output port).
After four machine cycles (48 clock periods), the contents of the
addressed location in the EPROM array will appear on Port 1.
The next programming cycle may now be initiated by placing the
address information at the inputs of the multiplexed buffers, driving
Figure 5 shows a block diagram of the programming configuration
for the 87C751. Port pin P0.2 is used as the programming voltage
the V pin to the V voltage level, providing the byte to be
PP
PP
supply input (V signal). Port pin P0.1 is used as the program
PP
programmed to Port1 and issuing the 26 programming pulses on the
PGM/ pin, bringing V back down to the V level and verifying the
(PGM/) signal. This pin is used for the 25 programming pulses.
PP
C
byte.
Port 3 is used as the address input for the byte to be programmed
and accepts both the high and low components of the eleven bit
address. Multiplexing of these address components is performed
using the ASEL input. The user should drive the ASEL input high
and then drive port 3 with the high order bits of the address. ASEL
should remain high for at least 13 clock cycles. ASEL may then be
driven low which latches the high order bits of the address internally.
the high address should remain on port 3 for at least two clock
cycles after ASEL is driven low. Port 3 may then be driven with the
low byte of the address. The low address will be internally stable 13
clock cycles later. The address will remain stable provided that the
low byte placed on port 3 is held stable and ASEL is kept low. Note:
ASEL needs to be pulsed high only to change the high byte of the
address.
Programming Modes
The 87C751 has four programming features incorporated within its
EPROM array. These include the USER EPROM for storage of the
application’s code, a 16-byte encryption key array and two security
bits. Programming and verification of these four elements are
selected by a combination of the serial data stream applied to the
RESET pin and the voltage levels applied to port pins P0.1 and
P0.2. The various combinations are shown in Table 6.
Encryption Key Table
The 87C751 includes a 16-byte EPROM array that is programmable
by the end user. The contents of this array can then be used to
encrypt the program memory contents during a program memory
verify operation. When a program memory verify operation is
performed, the contents of the program memory location is
XNOR’ed with one of the bytes in the 16-byte encryption table. The
resulting data pattern is then provided to port 1 as the verify data.
The encryption mechanism can be disable, in essence, by leaving
the bytes in the encryption table in their erased state (FFH) since
the XNOR product of a bit with a logical one will result in the original
bit. The encryption bytes are mapped with the code memory in
16-byte groups. the first byte in code memory will be encrypted with
the first byte in the encryption table; the second byte in code
memory will be encrypted with the second byte in the encryption
table and so forth up to and including the 16the byte. The encryption
repeats in 16-byte groups; the 17th byte in the code memory will be
encrypted with the first byte in the encryption table, and so forth.
Port 1 is used as a bidirectional data bus during programming and
verify operations. During programming mode, it accepts the byte to
be programmed. During verify mode, it provides the contents of the
EPROM location specified by the address which has been supplied
to Port 3.
The XTAL1 pin is the oscillator input and receives the master system
clock. This clock should be between 1.2 and 6MHz.
The RESET pin is used to accept the serial data stream that places
the 87C751 into various programming modes. This pattern consists
of a 10-bit code with the LSB sent first. Each bit is synchronized to
the clock input, X1.
Programming Operation
Figures 6 and 7 show the timing diagrams for the program/verify
cycle. RESET should initially be held high for at least two machine
Security Bits
cycles. P0.1 (PGM/) and P0.2 (V ) will be at V as a result of the
PP
OH
Two security bits, security bit 1 and security bit 2, are provided to
limit access to the USER EPROM and encryption key arrays.
Security bit 1 is the program inhibit bit, and once programmed
performs the following functions:
RESET operation. At this point, these pins function as normal
quasi-bidirectional I/O ports and the programming equipment may
pull these lines low. However, prior to sending the 10-bit code on the
RESET pin, the programming equipment should drive these pins
1. Additional programming of the USER EPROM is inhibited.
high (V ). The RESET pin may now be used as the serial data input
IH
2. Additional programming of the encryption key is inhibited.
3. Verification of the encryption key is inhibited.
for the data stream which places the 87C751 in the programming
mode. Data bits are sampled during the clock high time and thus
should only change during the time that the clock is low. Following
transmission of the last data bit, the RESET pin should be held low.
4. Verification of the USER EPROM and the security bit levels may
still be performed.
(If the encryption key array is being used, this security bit should be
programmed by the user to prevent unauthorized parties from
reprogramming the encryption key to all logical zero bits. Such
programming would provide data during a verify cycle that is the
logical complement of the USER EPROM contents).
Next the address information for the location to be programmed is
placed on port 3 and ASEL is used to perform the address
multiplexing, as previously described. At this time, port 1 functions
as an output.
A high voltage V level is then applied to the V input (P0.2).
PP
PP
Security bit 2, the verify inhibit bit, prevents verification of both the
USER EPROM array and the encryption key arrays. The security bit
levels may still be verified.
(This sets Port 1 as an input port). The data to be programmed into
the EPROM array is then placed on Port 1. This is followed by a
series of programming pulses applied to the PGM/ pin (P0.1). These
pulses are created by driving P0.1 low and then high. This pulse is
17
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
Programming and Verifying Security Bits
Erasure Characteristics
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 6. When
programming either security bit, it is not necessary to provide
address or data information to the 87C751 on ports 1 and 3.
Erasure of the EPROM begins to occur when the chip is exposed to
light with wavelengths shorter than approximately 4,000 angstroms.
Since sunlight and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room level fluorescent lighting)
could cause inadvertent erasure. For this and secondary effects,
it is recommended that an opaque label be placed over the
window. For elevated temperature or environments where solvents
are being used, apply Kapton tape Flourless part number 2345–5 or
equivalent.
Verification occurs in a similar manner using the RESET serial
stream shown in Table 6. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
The recommended erasure procedure is exposure to ultraviolet light
(at 2537 angstroms) to an integrated dose of at least 15W-s/cm .
Exposing the EPROM to an ultraviolet lamp of 12,000µW/cm rating
2
2
for 20 to 39 minutes, at a distance of about 1 inch, should be
sufficient.
Erasure leaves the array in an all 1s state.
Table 6. Implementing Program/Verify Modes
OPERATION
SERIAL CODE
P0.1 (PGM/)
P0.2 (V
)
PP
Program user EPROM
Verify user EPROM
Program key EPROM
Verify key EPROM
Program security bit 1
Program security bit 2
Verify security bits
296H
296H
292H
292H
29AH
298H
29AH
–*
V
PP
V
IH
V
IH
–*
V
PP
V
IH
V
IH
PP
PP
–*
–*
V
V
V
IH
V
IH
NOTE:
*
Pulsed from V to V and returned to V
.
IH
IL
IH
87C751
V
V
A0–A10
P3.0–P3.7
P0.0/ASEL
+5V
CC
ADDRESS STROBE
SS
PROGRAMMING
PULSES
P0.1
V
/V VOLTAGE
P0.2
PP IH
P1.0–P1.7
DATA BUS
SOURCE
CLK SOURCE
XTAL1
RESET
CONTROL
LOGIC
RESET
SU00317
Figure 5. Programming Configuration
XTAL1
MIN 2 MACHINE
CYCLES
TEN BIT SERIAL CODE
RESET
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
UNDEFINED
UNDEFINED
P0.2
P0.1
SU00302
Figure 6. Entry into Program/Verify Modes
18
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
EPROM PROGRAMMING AND VERIFICATION
T
amb
= 21°C to +27°C, V = 5V ±10%, V = 0V
CC SS
SYMBOL
PARAMETER
MIN
1.2
MAX
UNIT
1/t
Oscillator/clock frequency
6
MHz
CLCL
1
t
t
t
t
t
t
t
t
t
t
t
t
t
Address setup to P0.1 (PROG–) low
Address hold after P0.1 (PROG–) high
Data setup to P0.1 (PROG–) low
Data hold after P0.1 (PROG–) high
10µs + 24t
AVGL
CLCL
48t
38t
36t
GHAX
DVGL
GHDX
SHGL
GHSL
GLGH
CLCL
CLCL
CLCL
V
V
setup to P0.1 (PROG–) low
hold after P0.1 (PROG–)
10
10
90
µs
µs
µs
PP
PP
P0.1 (PROG–) width
low (V ) to data valid
110
2
V
PP
48t
AVQV
CC
CLCL
P0.1 (PROG–) high to P0.1 (PROG–) low
ASEL high time
10
µs
GHGL
13t
MASEL
HAHLD
HASET
ADSTA
CLCL
CLCL
Address hold time
2t
Address setup to ASEL
Low address to valid data
13t
CLCL
48t
CLCL
NOTES:
1. Address should be valid at least 24t
before the rising edge of P0.2 (V ).
CLCL
PP
2. For a pure verify mode, i.e., no program mode in between, t
is 14t
maximum.
AVQV
CLCL
12.75V
P0.2 (V
)
5V
5V
t
PP
t
SHGL
GHSL
25 PULSES
P0.1 (PGM)
P0.0 (ASEL)
t
t
GHGL
GLGH
t
MASEL
98µs MIN
10µs MIN
t
AVGL
t
t
HAHLD
HASET
HIGH ADDRESS
LOW ADDRESS
PORT 3
PORT 1
t
t
t
t
ADSTA
DVGL
GHDX
AVQV
INVALID DATA
VERIFY MODE
INVALID DATA
VERIFY MODE
VALID DATA
DATA TO BE PROGRAMMED
PROGRAM MODE
VALID DATA
SU00303
Figure 7. Program/Verify Cycle
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
19
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
20
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
PLCC28: plastic leaded chip carrer; 28 leads; pedestal
SOT261-3
21
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
22
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
NOTES
23
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I2C, low pin count
83C751/87C751
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 05-98
Document order number:
9397 750 03845
Philips
Semiconductors
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