SA1638BE-T [NXP]
IC TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQFP48, Cellular Telephone Circuit;
| 型号： | SA1638BE-T |
| 厂家： | 
NXP |
| 描述： | IC TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQFP48, Cellular Telephone Circuit |
| 文件： | 总26页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SA1638
Low voltage IF I/Q transceiver
Product specification
IC17 Data Handbook
1997 Sept 03
Philips
Semiconductors
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
DESCRIPTION
• High performance on-board integrated receive filters with
The SA1638 is a combined Rx and Tx IF I/Q circuit. The receive
path contains an IF amplifier, a pair of quadrature down-mixers, and
a pair of baseband filters and amplifiers. A second pair of mixers in
the transmit path transposes a quadrature baseband input up to the
IF frequency. An external VCO signal is divided down internally and
buffered to provide quadrature local oscillator signals for the mixers.
A further divider chain, reference divider and phase detector are
provided to avoid the need for an external IF synthesizer. Rx or Tx
path or the entire circuit may be powered down by logic inputs.
On-board voltage regulators are provided to allow direct connection
to a battery supply.
bandwidth tunable between 50-850 kHz
• Switchable alternative bandwidth setting available to allow
channel bandwidth flexibility in operation
• Designed for a widely used I and Q baseband GSM interface
• Control registers power up in a default state
• Optional DC offset trim capability to <200mV
• Only a standard reference input frequency required, choice of 13,
26, 39 or 52MHz
• Fully compatible with SA1620 GSM RF front-end (see Figure 9)
FEATURES
• Direct supply: 3.3V to 7.5V
APPLICATIONS
• Two DC regulators giving 3.0V output
• IF circuitry for GSM 900MHz hand-held units
• Low current consumption: 18mA for Rx or 22mA for Tx
• Input/output IF frequency from 70-400 MHz
• IF circuitry for PCN (DCS1800) hand-held units
• Quadrature up and down mixer stage
• Internal IF PLL for synthesizing the local oscillator signal
PIN CONFIGURATION
LQFP Package
48 47 46 45 44 43 42 41 40 39 38 37
36
35
V
I
CP
EE
VREG1
1
2
3
4
5
6
7
8
9
REF
VREGF2
VREG2
34 LO INX
33
32
LO IN
GNDREG2
PON
ADJ IN
31 CLK IN
30
29 LOCK
V
BATT
48–pin LQFP
CLK INX
AOUT
BOUT
STROBE
CLOCK
28
27
DCRES
RESD 10
26 DATA
25
RESA
RESB
11
12
V
DIG
EE
13 14 15 16 17 18 19 20 21 22 23 24
SR00524
Figure 1. SA1638 Pin Configuration
ORDERING INFORMATION
DESCRIPTION
48-Pin Thin Quad Flat Pack (LQFP)
TEMPERATURE RANGE
ORDER CODE
DWG #
-40 to +85°C
SA1638BE
SOT313-2
2
1997 Sept 03
853-1818 18351
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
BLOCK DIAGRAM
PONRx
BIAS RX
V.REG.1
V.REG.2
V
REF
PDTx
ITx IN
BIAS TX
ITx INX
QTx IN
TxIFOUT
TxIFOUTX
V
TxRx
CC
QTx INX
GND3
GND1
IRxOUT
IRxOUTX
RxIF IN
IF
RxIF INX
GND2
QRxOUT
AMP
QRxOUTX
LO IN
DCRES
AOUT
DC
2
LO INX
÷
BUFFERS
ADJUST
STATUS
ADJ IN
BOUT
REGISTER
DC
N
LOCK
CP
÷
REGISTER
I
REF
CHARGE
PUMP
PHASE
TEST
DETECTOR
REGISTER
PONPLL
V
CP
CP
CC
÷
13, 26
39, 52
SYNTH
SERIAL
INPUT
V
EE
REGISTER
SR00525
Figure 2. SA1638 Block Diagram
3
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
PIN DESCRIPTIONS
Pin No.
1
Pin Name
VREG1
Description
Output voltage of regulator 1
Feedback of regulator 2
Output voltage of regulator 2
Ground of regulator 2
2
VREGF2
VREG2
GNDREG2
PON
3
4
5
Power-on input for voltage regulators 1 and 2 (active high)
Input voltage for regulators 1 and 2
Programmable logic output (see Figure 9)
Programmable logic output (see Figure 9)
Reference current setting resistor for DC offset circuit
Additional external current defining resistor for filters
Principal external current defining resistor for filters
Principal external current defining resistor for filters
Power-on input for Rx (active high)
Reference voltage
6
V
BATT
7
AOUT
BOUT
DCRES
RESD
RESA
RESB
PONRx
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
V
REF
QRxOUT
QRxOUTX
IRxOUT
IRxOUTX
QTx IN
Differential receive baseband output
Differential receive baseband output
Differential receive baseband output
Differential receive baseband output
Differential transmit baseband input
Differential transmit baseband input
Differential transmit baseband input
Differential transmit baseband input
Power-on for transmitter (active low)
Digital circuit supply
QTx INX
ITx IN
ITx INX
PDTx
V
V
DIG
CC
DIG
Digital ground
EE
DATA
Serial bus data input
CLOCK
STROBE
LOCK
Serial bus clock input
Serial bus strobe input
Test control/synthesizer lock indicator
Differential reference divider input
Differential reference divider input
Used for test only. Do not connect
Differential LO input
CLK INX
CLK IN
ADJ IN
LO IN
LO INX
Differential LO input
I
Reference current setting for charge pump
Charge pump ground
REF
V
EE
CP
CP
Charge pump output
V
CC
CP
Charge pump circuit supply
POnPLL
GND3
Power-on input for synthesizer circuits (active high)
Ground (internal connection to GND1 and GND2)
Differential transmit IFoutput (open collector)
Differential transmit IFoutput (open collector)
Ground (internal connection to GND1 and GND3)
Differential receive IF input
TxIFOUTX
TxIFOUT
GND2
RxIF INX
RxIF IN
GND1
Differential receive IF input
Ground (internal connection to GND2 and GND3)
Transmit and receive circuits supply voltage (also feedback of Regulator 1)
Ground of regulator 1
V
CC
TxRx
GNDREG1
NOTE: There are no ESD protection diodes at Pins 41 and 42. Thus, open collector outputs may have increased DC voltage or higher AC
peak voltage.
4
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
ABSOLUTE MAXIMUM RATINGS
SYMBOL
XXX
PARAMETER
Supply voltages: V TxRx, V DIG, V CP
RATING
-0.3 to +6.0
-0.3 to +8.0
UNITS
V
V
CC
CC
CC
CC
V
BATT
Battery voltage
V
V
IN
Voltage applied to any other pin
-0.3 to (V
+0.3)
V
CCXXX
∆VG
Any GND pin to any other GND pin
0
V
P
Power dissipation, T = 25°C (still air)
300
150
mW
°C
D
A
T
Maximum operating junction temperature
Maximum power input/output
JMAX
P
MAX
+20
dBm
°C
T
STG
Storage temperature range
–65 to +150
NOTE:
1. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance, θ . 48-pin LQFP: θ = 67°C/W.
JA
JA
RECOMMENDED OPERATING CONDITIONS
SYMBOL
XXX
PARAMETER
RATING
2.7 to 5.5
2.9 to 5.5
3.3 to 7.5
-40 to +85
UNITS
V
Supply voltages: V TxRx, V DIG
V
V
CC
CC
CC
V
CC
CP
Charge pump supply voltage
V
BATT
Battery voltage
V
T
A
Operating ambient temperature range
°C
Voltage Regulators
T = 25°C, P = 3V, P RX = 0V, PDTX = 3V, P PLL = 0V, V
= 3.3V, I
1 = I
2 = 15mA, V
1 connected to V TxRx, V
2
REG
A
ON
ON
ON
BATT
OUT
OUT
REG
CC
connected to V
F2; V DIG = V CP = 3V; unless otherwise stated.
REG
CC CC
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
Min
2.85
3.3
–3σ
2.93
Typ
+3σ
Max
3.15
7.5
V
V
1,
REG
Nominal V
3.00
3.07
V
V
OUT
2
REG
V
BATT
Maximum output current for each
regulator
I 1, I
OUT
2
OUT
30
mA
1
I
Supply current for both regulators
Power-down supply current
I
= 0mA
4.3
7.7
5
9
5.7
7
15
mA
µA
µF
µF
%
BATT
LOAD
I
P
= 0V, I = 0mA
LOAD
10.3
BATT PD
2
ON
C
1
2
V
V
1 cap load
2 cap load
0.1
0.1
1000
500
0.4
5
REG
REG
2
C
REG
REG
LINEREG
LOADREG Load regulation
BW Bandwidth
Line regulation
DC, V
= 3.3V to 7.5V
–0.4
–5
–0.2
0.001
-0.17
0.2
BATT
I
= 15mA to 30mA
–0.37
0.03
%
LOAD
100
kHz
Feedthrough attenuation from P to
each regulator
ON
F
PON
≤ -40
dB
f ≤ 100kHz
f = 10MHz
f = 100MHz
f = 400MHz
≤ -61
≤ -32
≤ -37
≤ -48
Feedthrough attenuation from V
each regulator
to
BATT
F
REG
dB
t
Turn ON time
10
µs
ON
NOTES:
1. At T ≥ 150°C a thermal switch reduces the output current to avoid damage.
j
2. Recommended load capacitors: In every case C
1 = C 2 = 100nF to ground with series resistance ≤0.1Ω. Additional capacitor
REG REG
optional ≤1000µF with series resistance ≤5Ω. The low series resistance is very important to ensure regulator stability.
3. Standard deviations are based on the characterization results of 90 ICs.
5
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
DC ELECTRICAL CHARACTERISTICS
V
CC
TxRx=V DIG=V CP=PONRx=PONPLL= +3V; V DIG = V CP=GND1=GND2=GND3=PDTx = 0V; T = 25°C, unless otherwise stated.
CC CC EE EE A
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
MAX
MIN
–3σ
TYP
+3σ
Supply current
PONRx = PONPLL = PDTx = Hi
Rx and IF synthesizer active
14.4
17.4
16
17.6
21.6
20
PONRx = PDTx = Low;
PONPLL = Hi
I
mA
24
CC
Tx and IF synthesizer active
19.5
PONRx = PONPLL = Low;
PDTx = Hi
Power-down mode
Reference voltage
0.068
1.57
V
Generated internally
1.39
1.86
1.75
2.14
V
REF
V
REF
I
I
5
5
SINK
SOURCE
IV
µA
REF
At pins TxIFOUT and
TxIFOUTX
I
DC output current
1.5
2.0
2.7
mA
OUT
Digital inputs (P
)
ON
V
High level input voltage range
Low level input voltage range
2.0
0
V
V
V
IH
BATT
V
0.8
IL
Digital inputs (PDTx, P Rx, P PLL, P )
ON
ON
ON
V
High level input voltage range
Low level input voltage range
2.0
0
V
TxRx
V
V
IH
CC
V
0.8
IL
Digital inputs (Clock, Data, Strobe)
V
High level input voltage range
Low level input voltage range
2.0
0
V
Dig
V
V
IH
CC
V
0.8
IL
Digital outputs (LOCK, AOUT, BOUT)
V
CC
DIG–0.4
V
Output voltage HIGH
Output voltage LOW
I
= -2mA
= 2mA
O
V
V
OH
O
V
I
0.4
OL
AC ELECTRICAL CHARACTERISTICS
V
TxRx=V DIG=V CP=PONRx=PONPLL= +3V; V DIG = V CP=GND1=GND2=GND3=PDTx = 0V; LO = 100mV
, 800MHz;
CC
CC
CC
EE
EE
IN
PEAK
CLK = 100mV
, 52MHz; serial registers programmed with default values; T = 25°C unless otherwise stated. Test Circuit Figure 8.
IN
PEAK
A
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
MIN
–3σ
TYP
+3σ
MAX
IF Transmit Modulator
BW Input modulation bandwidth
200Ω source impedance
0.82
0.94
1.5
1.06
MHz
V
Common mode range for
baseband inputs
DC at pins ITxIN, ITxINx,
QTxIN, QTxINx
V
COM
1
2
V
IN
Peak input signal amplitude
Centered on V
0.75
V
COM
| ITxIn | = | ITxInX | =
| QTxIn | = | QTxInX |
1
Third harmonic distortion
-61
-57
-53
-40
dB
= 0.75V
fin = 20kHz
PEAK;
Between pins: ITxIn and
ITxInX or QTxIn and
QTxInX
R
C
Input resistance
112
kΩ
INTx
INTx
At ITxIn, ITxInX,
QTxIn, QTxInX
Input capacitance
10
pF
V
Output saturation limit
V
CC
TxRx-0.3
| ITxIn | = | ITxInX | =
| QTxIn | = | QTxInX |
I
RMS output current
0.6
+30
+35
0.73
0.82
+43
+50
0.91
1.08
mA
dB
dB
OUT
= 0.75V
PEAK
| ITxIn | = | ITxInX | =
| QTxIn | = | QTxInX |
1
S
LO suppression
LO
= 0.75V
; fin = 20k
PEAK
| ITxIn | = | ITxInX | =
| QTxIn | = | QTxInX |
1
SSB
Sideband suppression
= 0.75V
; fin = 20k
PEAK
6
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
AC ELECTRICAL CHARACTERISTICS (Continued)
LIMITS
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
MAX
MIN
–3σ
+3σ
IF Transmit Modulator (continued)
Noise density at 600kHz
-130
-133
-129
-131
5
-128
-129
|ITxIn| = |ITxInX| = |QTxIn| =
dBc/Hz
|QTxInX| = 0.75V
Noise density at 10MHz
PEAK
t
Turn ON time
Turn OFF time
PdTx = LO, transmit signal to 90%
PdTx = HI, transmit signal to 10%
µs
µs
ON
t
5
OFF
IF Receiver (R = 36kΩ between pins RESA and RESB)
RInRx Differential input impedance
ROutRx Output impedance
Output common mode voltage
f
IN
= 400MHz
5 || 0.6
1
kΩ || pF
kΩ
V
REF
V
f3dB
Low pass filter -3dB bandwidth
70
83
90
58
kHz
Low pass filter attenuation:
200kHz
6.5
30
8.9
38.1
10.7
45
70
>80
>80
12.5
51.9
400kHz
600kHz
6.5MHz
13.0MHz
dB
Differential output PD into GSM
baseband relative to 1200Ω
source EMF
VG
NF
Voltage gain
43
49.4
5.7
51
52.7
8.3
dB
dB
1200Ω source and external
matching resistor and inductor
8
Noise figure
7.0
Channel matching:
Gain
-1.5
-60
-0.26
0.0
1.5
60
dB
degrees
f
= 400.005MHz
IN
Phase
2
Output DC offset
Differential, DCRES=562kΩ
-25
10 (700)
2.0
mV
µA
V
I
Output drive current at each pin
Minimum differential output swing
Source (Sink)
OUT
V
OUT
Input 1dB compression point:
In band
200kHz
400kHz
600kHz
-59
-54
-55.3
-49.3
-53
-47
-47
-47
-50.7
-44.8
-47
-40
P
-1dB
1200Ω source EMF
dBV
POnRx = HI, to baseband signal
out
3
t
Turn ON time
2
2
µs
µs
ON
POnRx = LO, to no baseband
signal out
t
Turn OFF time
OFF
IF Synthesizer
Local oscillator input frequency
f
LO
140
800
100
MHz
Ω || pF
mV
9
range
Between pins LO and LO X, f
IN
IN
IN
Z
Differential input impedance
LO peak input voltage range
276 || 0.6
LOIN
LOIN
= 800MHz
Single-ended
Referred to 50Ω
V
50
64
Programmable divider:
Division range
Step size
511
52
1
f
Reference clock input frequency
Differential input impedance
V
CLKIN
= 100mV
PEAK
MHz
kΩ || pF
mV
CLKIN
Z
V
Between pins ClkIn and ClkInX
10 || 1.0
CLKIN
CLK peak input voltage range
Single-ended, referred to 50Ω
50
400
CLKIN
IN
Charge pump input reference
current
I
31.2
µA
REF
Charge pump output current:
c0...c2 = 000
0.425 0.487
0.85 0.979
0.045 0.062
0.5
1.0
0.071
0.513 0.575
I
=31.2µA,
REF
| I
|
mA
CP
c0...c2 = 111
Step size
1.021
0.08
1.15
0.105
V
CP
= V CP/2
CC
7
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
AC ELECTRICAL CHARACTERISTICS (Continued)
LIMITS
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
MIN
–3σ
+3σ
MAX
IF Synthesizer (cont.)
DICP
4
Relative output current variation
I
=31.2µA
=31.2µA,
0.1
1.3
2.5
±10
%
REF
ICP
I
REF
5
∆I
CP_M
Output current matching
±12
±15
%
nA
µs
V
CP
= V CP/2
CC
|I
|
Output leakage current
Turn ON time
V
CP
= 0.3V to V CP-0.3V
-0.02
0.1
15
0.22
CP_L
CC
POnPLL = HI, to full charge
pump current
t
ON
POnPLL = LO, to I CP,
CC
6
I
DIG <5% of operational
t
Turn OFF time
15
µs
CC
OFF
supply current
7
Serial Interface
f
Clock frequency
10
MHz
ns
CLOCK
Set-up time: DATA to CLOCK,
CLOCK to STROBE
t
30
SU
t
Hold time: CLOCK to DATA
Pulse width: CLOCK
30
30
30
ns
H
t
W
ns
Pulse width: STROBE
NOTES:
1. Parameter measured relative to modulation sideband amplitude.
2. After programming the DC offset register for minimum offset. DCRES = 562kΩ.
3. The turn on time relates only to the power up time of the circuit. The settling time of the integrated baseband filters has to be added (for
GSM–mode = 8µs with filter bandwidth setting resistor = 36kΩ).
DI
(I2 * I1)
|(I2 ) I1)|
OUT + 2 @
4. The relative output current variation is defined thus:
; with V = 0.3V, V = V CP – 0.3V (see Figure 3).
1
2
CC
IOUT
5. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on.
6. As soon as P PLL is set to LO, the phase detector is reset and no charge pumps pulses are generated.
ON
7. Guaranteed by design.
Eno
20log ǒ Ǔ
8. NF =
* VG
where, E is the output noise voltage measured in a 1Hz bandwidth, R = 1200Ω, VG = gain in dB.
no
ƪ
ƫ
Ǹ
4kTR
9. Minimium frequency is guaranteed by design.
address bits and 1 subaddress bit. Figure 2 shows the timing
diagram of the serial input. When the STROBE = L, the clock driver
is enabled and on the positive edges of the CLOCK the signal on
DATA input is clocked into a shift register. When the STROBE = H,
the clock is disabled and the data in the shift register remains stable.
Depending on the value of the subaddress bit the data is latched
into different working registers. Table 3 shows the contents of each
word.
CURRENT
I
2
I
1
VOLTAGE
V
1
V
2
Default States
Upon power up (V DIG is applied) a reset signal is generated,
CC
which sets all registers to a default state. The logic level at the
STROBE pin should be low during power up to guarantee a proper
reset. These default states are shown in Table 3.
I
2
I
1
SR00526
Reference Divider
The reference divider can be programmed to four different division
ratios (:13, :26, :39, :52), see registers r0, r1; default setting: divide
by 13.
Figure 3. Relative Output Current Variation
FUNCTIONAL DESCRIPTION
Serial Programming Input
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program the counter ratios, charge pump current, status- and
DC-offset register, mode select and test register. The programming
data is structured into two 21-bit words; each word includes 4 chip
Main Divider
The external VCO signal, applied to the LO and LO X inputs, is
IN IN
divided by two and then fed to the main divider (:N). The main
divider is a programmable 9 bit divider, the minimum division ratio is
8
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
divide by 64. The division ratio is binary coded and set in the
registers n0 to n8. The default setting is a divide by 400.
Status Register
The s0 and s1 status bits determine the values of the logic output
pins A and B . These outputs can be connected to the AGC
OUT
OUT
At the completion of a main divider cycle, a main divider output is
generated which will drive the phase detector.
control inputs A and B of the SA1620. (See Figure 9)
DC Offset Register
Phase Detector
Registers i0 to i3 and q0 to q3 control a correction to the output DC
offset of the I and Q channels of the receiver. The polarity of the DC
offset correction in the I and Q channels are determined by i0 and
q0, respectively. The other bits set the magnitude of the offset
correction. The step size of the two offset correction DACs is fixed
by an external resistor between the DCRES pin and ground. A
value of 120kΩ will give a step size of 200mV.
The phase detector is a D-type flip-flop phase and frequency
detector shown in Figure 5. The flip-flops are set by the negative
edges of the output signals of the dividers. The rising edge of the
signal L will reset the flip-flops after both flip-flops have been set.
Around zero phase error this has the effect of delaying the reset for
1 reference input cycle. This avoids non-linearity or deadband
around zero phase error. The flip-flops drive on-chip charge pumps.
A source current from the charge pump acts to increase the VCO
frequency; a sink current acts to decrease the VCO frequency.
Mode Select Register
t0:
switches the RX IF gain.
t0 = 0
t0 = 1
no attenuation
10dB attenuation
Current Setting
The charge pump current is defined by the current set between the
pin I
and V CP. The current value to be set there is 31.2µA.
EE
REF
The attenuation switch is included between the IF amplifier and the I
and Q mixers, thereby influencing the noise figure negligibly. The
purpose of this switch is to provide another AGC step which does
not influence the receiver noise figure. Please note that this gain
change will influence the DC offset of the I and Q mixers.
t1 = 0 test mode only, always to be set to 0.
This current can be set by an external resistor to be connected
between the pin I
setting resistor) can be calculated with the formula
and V CP. The typical value R
(current
REF
EE
EXT
V
CCCP * 1.4V
31.2mA
REXT
+
t2, t3 sets the mode of the level locked loop (LLL)
The current can be set to zero by connecting the pin I
to V CP.
CC
REF
The LLL is a circuit which processes the LO input signal in order to
provide an LO signal with a perfect 50% duty cycle, which
determines the precision of the 90° shift of the I and Q mixing
signals generated by the ÷2 divider. For an external tuning of the
90° phase shift of the I and Q mixing signals, a trimming resistor
Charge Pumps
The charge pumps at pin CP are driven by the phase dectector and
the current value is determined by the binary value of the charge
pumps register CN = c2, c1, c0, default 1mA. The active charge
pump current is typically:
may be connected (but is not required) between the ADJ pin and
IN
ground, and the LLL has to be put in one of the following modes:
|ICP| + (c0 ) 2c1 ) 4c2) @ 71mA ) 500mA
Table 2.
Mode Select Register
LLL Status
t2 t3
Lock Detect
The output LOCK is H when the phase detector indicates a lock
condition. This condition is defined as a phase difference of less
0
0
1
1
0
1
0
1
LLL on (no external tune, monitor performance, default)
LLL on (with medium external tune)
LLL off (tune externally)
than ±1 cycle on the reference input CLK , CLK X.
IN
IN
LLL on (with fine external tune)
Test Modes (Synthesizer, Transmit Mixer)
The LOCK output is selectable as a test output. Bits x0, x1 control
the selection, the default setting is normal lock output as described
in the Lock detect section. The selection of a Bit x0, x1 combination
has a twofold effect: First it routes a divider output signal to the
LOCK pin, second it disables mixer stages in the transmit path.
Setting x0,1 = 11 disables both transmit path mixers. This mode can
be used to prevent the transmitter from producing an IF output
signal even if the transmit part is powered on (PDTx = 0V). This can
be used to simplify the control timing while commanding the transmit
and receive simultaneously without the transmit part causing
interference.
t4
selects the bandwidth of the RC low pass filters at the I, Q
Rx mixer outputs
t4 = 0
t4 = 1
cutt-off frequency (-3dB) 110kHz
cutt-off frequency (-3dB) 792kHz
t5
selects the bandwidth of the integrated 5th-order gyrator
filters. The filters are tuneable over a range of 50kHz to
1MHz with external resistors. The -3dB bandwidth is
inversely proportional to the value of the external resistor.
With
t5, two external resistor values are selectable.
t5 = 0
the resistance between the pins RESA and
RESB determines the cutoff frequency. For
GSM a nominal bandwidth of 80kHz is chosen
when the external resistor is 36kΩ.
Table 1.
Test Modes
Transmit Mixer
Synthesizer Signal
at LOCK Pin
x0 x1
Q-mixer I-mixer
t5 = 1
a second resistor between the pins RESB and
RESD is connected in parallel to the first
external resistor, thus increasing the filter
bandwidth. The relative amplification is
decreased in this mode.
0
1
0
1
0
0
1
1
normal lock detect
on
off
on
off
on
on
off
off
CLK divided by reference
IN
divider ratio
LO ÷ 2 * (main divider ratio)
IN
main divider output, that goes to
the phase detector
9
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
The overall filter response in the receive section is the sum of the
filter responses of the passive RC low-pass filter and the active
gyrator filter.
P
Rx = H powers up the receiver part.
ON
PDTx = L powers up the transmitter part.
PLL = H powers up the synthesizer part. As it also powers up
P
ON
Power Down Modes
the first divide by 2 stage for generating the 0/90 degree phase
shifted signals for the transmit and receive mixers, it also has to be
There are 4 power-on pins in the SA1638: P , P Rx, PDTx,
ON
ON
P
ON
PLL.
set H if either the transmit part or the receive part is used. P PLL
ON
= L powers down the dividers, resets the phase detector and
P
= H powers up both voltage regulators V
1 and V
2. P
REG ON
ON
REG
disconnects the current setting pin I
. In P PLL = L mode, the
REF ON
should be set to L, if these internal voltage regulators are not to be
used.
values in the serial input registers are still kept and the part still can
be reprogrammed as long as V DIG is present.
CC
Table 3. Definition of SA1638 Serial Registers
First data word: (shown with default values)
Sub
Adr
Address SA1638
N-Divider
Ref ÷ Reg
Charge-Pump
Reg Test
LSB
MSB
a0
a1
a2
a3
sa
n0
n1
n2
n3
n4
n5
n6
n7
n8
r0
r1
c0
c1
c2
x0
x1
1
1
1
0
0
1
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
Address: 4 bits, a0...a3, fixed to 1110
Sub:Address: 1 bit, sa, fixed to 0 for first data word
N-Divider: 9 bits, n0...n8, values 64 (00100 0000) to 511 (111111111) allowed for IF-choice, default 400
Reference Divider Register: 2 bits, r0...r1, 00 = ÷13, 01 = ÷26, 10 = ÷39, 11 = ÷52. Default: 00
Charge-Pump Register: 3 bits, c0...c2, Binary current setting factor for charge pumps, values 000 = minimum current to 111 =
maximum current, default maximum charge pump current
Test Register: 2 bits, x0...x1, default 00, see Functional Description
Second data word: (shown with default values)
DC Offset Register
Q-Channel I-Channel
Sub
Adr
Status
Reg
Address SA1638
Mode Select Register
MSB
LSB
t5
a0
a1
a2
a3
sa
s0
s1
q0
q1
q2
q3
i0
i1
i2
i3
t0
t1
t2
t3
t4
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address: 4 bits, a0...a3, fixed to 1110
Sub:Address: 1 bit, sa, fixed to 1 for second data word
Status Register: 2 bits, s0 sets pin A ; s1 sets pin B
, see Functional Description
OUT
OUT
DC Offset Register: 4 bits per channel, i0...i3 and q0...q3, no correction as default
i0 and q0 switches offset polarity, 0 to lower voltage, 1 to higher voltage
il...i3 and q1...q3, 000 no correction to 111 max. correction enabled
Mode Select Register: 6 bits,
t0...t5,
000000 = normal GSM-Operation as default, see Functional Description
10
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
LSB
MSB
DATA
a
a
0
X
or t
X or t
0 4
1
1
5
t
H
t
t
SU
SU
50%
CLOCK
FIRST CLOCK
LAST CLOCK
FIRST CLOCK
t
SU
STROBE
CLOCK ENABLED
SHIFT IN DATA
CLOCK
DISABLED
STORE DATA
t
W
50%
CLOCK
SR00527
STROBE
Figure 4. Serial Input Timing Sequence
L
“1”
R
D
C
Q
REFERENCE
DIVIDER
CLK
IN
V
CP
CC
R
R
P
P-TYPE
CHARGE PUMP
C
P
“1”
X
D
C
MAIN
DIVIDER
LO
IN
÷2
N-TYPE
CHARGE PUMP
Q
N
V
SS
CLK
IN
L
R
X
P
N
I
CP
SR00528
Figure 5. Phase Detector Structure with Timing
11
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
PIN FUNCTIONS
PIN
PIN
PIN
PIN
DC V
EQUIVALENT CIRCUIT
DC V
EQUIVALENT CIRCUIT
No. MNEMONIC
No. MNEMONIC
5
6
BG
1.2
47
48
V
TxRx
3.0
2.5
CC
10
10
11
RES
0.05
D
A
—
+
1
t5
35k
GND
V
1
REG
0.0
47
RES
0.00
25k
11
40 43 46
48
1
2
1
REG
3.0
3.0
40
43 46
5
6
V
F2
REG
BG
2.5
1.2
3
4
V
2
REG
ON
3.0
0.0
REG
—
+
3
2
GND
2
35k
25k
12
RES
0.05
B
5
6
P
3.3
3.3
4
12
V
BATT
40
43 46
13
P
ON
Rx
3.0
7
13
7
A
OUT
3.0
14
V
REF
1.5
8
8
B
OUT
3.0
14
15
16
17
QRX
QRX
1.5
1.5
1.5
OUT
X
OUT
9
15, 17
16, 18
9
DC
1.6
RES
IRX
OUT
18
IRX X
OUT
1.5
SR00529
Figure 6. Pin Functions
12
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
PIN FUNCTIONS (continued)
PIN
PIN
PIN
PIN
DC V
EQUIVALENT CIRCUIT
DC V
1.6
EQUIVALENT CIRCUIT
No. MNEMONIC
No. MNEMONIC
19
20
21
22
QTX
1.5
1.5
1.5
1.5
IN
19, 20, 21, 22
QTX
ITX
X
IN
IN
35
I
REF
35
ITX
X
IN
36
37
V
CP
0.0
EE
23
PdTx
0.0
23
37
CP
24
25
26
V
DIG
3.0
3.0
CC
38
39
V
CP
3.0
3.0
CC
V
DIG
EE
P
ON
PLL
DATA
39
27
28
CLOCK
26, 27, 28
40
41
GND3
0.0
STROBE
41
42
TXIF
X
X
OUT
29
29
LOCK
42
TXIF
OUT
30
31
CLK
2.0
2.0
IN
30
31
43
44
GND2
0.0
1.5
CLK
X
IN
RxIF
X
IN
44
45
45
46
RxIF
1.5
0.0
IN
32
32
ADJ
2.0
IN
V
REF
GND1
33
34
LO
2.0
2.0
IN
47
48
V
TxRx
3.0
0.0
CC
33
34
LO
X
IN
GND
1
REG
SR00530
Figure 7. Pin Functions (cont.)
13
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
output power can be reduced to an appropriate level by choice of
an external resistor.
Overview of Dual GSM/PCN Architecture
The SA1620 RF front-end and SA1638 IF transceivers form a dual
conversion architecture which uses a common IF and standard I/Q
baseband interface for both transmit and receive paths. The time
division multiplex nature of the GSM system permits integration of
the transmit and receive functions together on the one RF and one
IF chips. This simplifies the distribution of local oscillator signals,
maximizes circuitry commonality, and reduces power consumption.
• DC offsets generated in the receive channel are independent of
the LNA AGC setting, and correctable by software to prevent
erosion of signal handling dynamic range by DC offsets.
• Minimal high-quality filter requirements. As a result of the
integration in the SA1638 of high quality channel selectivity filters,
only sufficient filtering is needed in the receive path to provide
blocking protection for the second mixers. This reduces receiver
cost and size.
The SA1620 and SA1638 allow considerable flexibility to optimize
the transceiver design for particular price/size/performance
requirements, through choice of appropriate RF and IF filters. The
IF may be chosen freely in the range 70–400 MHz. The same IF
can be used in the transmit and receive directions. Alternately,
different IFs can be used if the SA1638 synthesizer frequency is
switched between transmit and receive timeslots. The comparison
frequency of the SA1638 PLL is high in order to provide fast
switching time.
• Operation at a high IF allows RF image reject filter requirements
to be relaxed. For example, at a 400MHz IF, the natural gain
roll-off in the SA1620 LNAs and mixer suppresses the image
signal in the 1800MHz band by typically 28dB below the desired
900MHz band signal.
DC Offset Correction
With suitable choice of the IF, an identical SA1638 IF receiver
design can be used for both 900MHz GSM and 1800MHz PCN
(DCS1800) equipment.
DC offset correction is provided by two DACs each feeding into one
of the two Rx channels. The step size of both DACs is set by the
value of the external resistor between DCRES and ground. Thus
any original offset less than 1.5V magnitude in either channel can be
reduced to the specified level by selecting the appropriate DAC
setting via the serial interface.
General Benefits/Advantages
• 2.7V operation. Compatible with 3V digital technology and
portable applications. (Higher voltage operation also possible, if
desired.)
Integrated Receive Filters
The low-pass characteristics of the Rx channel are determined by
two low-pass responses. The first of these is a passive filter at the
output of the quadrature mixers and the second is the low-pass
filters which follow the post-mixer amplifiers. These specifications
refer only to the response of the default state, but this may be
switched by the control register to an alternative setting with a
nominal 3dB point of 792kHz.
• Excellent dynamic range. The availability of two LNAs in the
SA1620 allows flexibility in receiver dynamic design for portable
and mobile GSM spec. applications with appropriate filters. If for
a particular application a GaAs or discrete front-end is desired,
one of the LNAs can be left unpowered. Placing the AGC gain
switches at the front results in some attenuation most of the time,
further increasing typical dynamic performance beyond that
specified by GSM.
The corner frequency of the low pass filters can be adjusted over a
wide range by varying the value of the external resistor between
RESA and RESB. The range of feasible corner frequencies extends
at least between 50kHz and 500kHz.
• High power transmit output driver, delivering +7.5dBm output.
This is sufficient to drive a filter and power amplifier input, without
a driver amplifier. To avoid unnecessary current consumption, the
14
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VREG1
GNDREG1
100nF
2
VREGF2
3V
V
TxRx
CC
0–30mA
3
VREG2
GND1
RxIN
1.8pF
2.5kΩ
TC4–14
100nF
4
GNDREG2
RxIFIN
RxIFINX
GND2
0–30mA
1800Ω
33nH
51.4Ω
51.4Ω
P
ON
5
6
1.8pF
P
V
ON
1nF
2:1
V
BATT
BATT
TxOUT
100nF
17.4Ω
TC4–14
A
B
OUT
OUT
7
TxIFOUT
TxIFOUTX
GND3
A
B
OUT
OUT
294Ω
294Ω
8
2:1
9
2–3V
PLL
1nF
DCRES
112kΩ
1MΩ
P
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ON
RESD
RESA
RESB
P
PLL
ON
100nF
1nF
22kΩ
56kΩ
V
CCP
VCP
V
CCP
CP
10nF
P
Rx
ON
P
V
Rx
V
CP
ON
EE
VCO
800MHz
V
REF
I
REF
REF
4740Ω
4.7nF
10nF
10nF
17.4Ω
470pF
QRxOUT
LOINX
LOIN
LOIN
294Ω
294Ω
10kΩ
QRxOUTX
IRxOUT
IRxOUTX
QTxIN
ADJ
IN
Rx OUT
+
–
ADJ
IN
10kΩ
1nF
CLKIN
10nF
17.4Ω
294Ω
CLKIN
10kΩ
49.9Ω
294Ω
CLKINX
LOCK
10kΩ
10nF
I/Q
LOCK
QTxINX
ITxIN
GEN
2.7pF
STROBE
STROBE
DC - 1MHz
10pF
3-WIRE
SERIAL
BUS
CLOCK
DATA
ITxINX
PDTx
CLOCK
DATA
10pF
PD Tx
10pF
1nF
V
CC DIG
V
V
EE DIG
CC DIG
1nF
10nF
SR00531
Figure 8. SA1638 Test Circuit
15
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
SR00532
Figure 9. SA1620 / SA1638 System Block Diagram
16
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS
Regulator Dropout Voltage vs. Temperature and V
Regulator Supply Current vs. Temperature and V
BATT
BATT
5
4.5
4
7
6.5
6
7.5V
No Load
I
=30mA
3.5
3
LOAD
5.5
5
5.5V
2.5
2
3.3V
4.5
4
5.5V
7.5V
1.5
1
3.5
3
3.3V
0.5
0
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Regulator Load Regulation vs.
Temperature and V
Regulator Powerdown Supply Current vs.
Temperature and V
BATT
BATT
40
35
30
25
20
15
10
5
1
0.8
0.6
0.4
0.2
0
ILoad = 15mA to 30mA
7.5V
7.5V
5.5V
5.5V
3.3V
-0.2
-0.4
-0.6
-0.8
-1
3.3V
0
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
Regulator Output Voltage vs.
Regulator Line Regulation vs.
Temperature and V
Temperature and V
BATT
BATT
3.15
3.1
0.4
3.3V
5.5V
0.3
0.2
0.1
0
I
=15ma
LOAD
I
=15mA
5.5V
LOAD
7.5V
7.5V
3.05
3
3.3V
-0.1
-0.2
-0.3
-0.4
2.95
2.9
2.85
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
Figure 10. Typical Performance Characteristics
17
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Transmitter Output Second Harmonic Distortion
Transmitter Input Modulation Bandwidth vs.
-50
Temperature and V TxRx
CC
1100.0
1050.0
1000.0
950.0
900.0
850.0
800.0
Tx In = 1.5V
P-P
ITXIN=ITXINX=QTXIN=QTXINX=1.5Vpp
-55
-60
-65
-70
2.7V
5.5V
4.0V
3.0V
4V
2.7V
-50
-30
-10
10
30
50
70
90
3V
Temperature (°C)
5.5V
Transmitter Output Third Harmonic vs.
Temperature and V TxRx
CC
-50
-55
-60
-65
-70
-50
0
50
100
Temperature (°C)
TX =1.5V
IN
P-P
2.7V
3V
4V
Transmitter Output Fourth Harmonic Distortion
5.5V
-60
-65
-70
-75
-80
Tx In = 1.5V
P-P
-50
-30
-10
10
30
50
70
90
2.7V
Temperature (°C)
3V
4V
5.5V
Transmitter Output Fifth Harmonic Distortion
-60
-65
-70
-75
-80
Tx In = 1.5V
P-P
3V
4V
-50
0
50
100
Temperature (°C)
5.5V
-50
0
50
100
Temperature (°C)
Figure 11. Typical Performance Characteristics (continued)
18
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Transmitter RMS Output Current
vs. Temperature and V TxRx
Transmitter Output Saturation vs.
Temperature and VccTxRx
CC
-50
-52
-54
-56
-58
-60
-62
-64
-66
-68
-70
1.1
1.05
1
TXIFOUT=TXIFOUTX=VccTxRx–0.3V
2.7V
3.0V
4.0V
IF=400MHz
0.95
0.9
5.5V
4.0V
3.0V
2.7V
0.85
0.8
5.5V
0.75
0.7
0.65
0.6
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
Transmitter LO Suppression vs.
Temperature and VccTxRx
Transmitter DC Output Current vs.
Temperature and V TxRx
CC
2.5
-36.0
-38.0
-40.0
-42.0
-44.0
-46.0
-48.0
-50.0
2.4
2.3
2.2
2.1
2
5.5V
4.0V
3.0V
2.7V
5.5V
4.0V
3.0V
2.7V
1.9
1.8
1.7
1.6
1.5
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
Transmit Noise Floor vs Temperature and Supply Voltage
Transmitter Side Band Suppresion vs.
TxRx and Temperature
-126
V
CC
Baseband Input = 1.5V
P-P
differential, 30kHz
-35
-40
-45
-50
-55
-60
-65
-70
-127
-128
-129
-130
-131
-132
-133
-134
-135
-136
600kHz from Carrier
5.5V
4.0V
3.0V
5.5V
4V
3V
2.7V
2.7V
5.5V
4V
3V
2.7V
10MHz from Carrier
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Figure 12. Typical Performance Characteristics (continued)
19
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Transmitter Input Common Mode Range
Vs. Supply Voltage
Receiver 3dB Bandwidth vs. Temperature and V TxRx
CC
0
-20
-40
-60
-80
100.0
90.0
80.0
70.0
60.0
50.0
40.0
2.7V
3.0V
T = +25°C
4.0V
5.5V
5.5V
2.7V 3.0V
4.0V
0
1
2
3
4
5
6
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
COMMON MODE VOLTAGE
Temperature (°C)
Receiver NF vs Temperature and Supply Voltage
16
14
12
10
8
Receiver Gain vs. Temperature and V TxRx
CC
60.0
Relative to 1200Ω source resistance
5.5V
58.0
56.0
54.0
52.0
50.0
48.0
46.0
44.0
42.0
40.0
IF=400.005MHz, LO=400MHz
4.0V
3.0V
2.7V
2.7V
3V
5.5V
4V
6
4
2
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
0
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Receiver Gain match vs V TxRx and Temperature
CC
Receiver Channel Matching Phase Error
vs. Temperature and V TxRx
1
CC
5
0.8
0.6
0.4
0.2
0
4
3
2
5.5V
2.7V
1
5.5V
0
3.0V
4.0V
3.0V
4.0V
-0.2
-0.4
-0.6
-0.8
-1
-1
-2
-3
-4
-5
2.7V
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
Figure 13. Typical Performance Characteristics (continued)
20
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Receiver Corrected Output Offset Voltage
Receiver In–band 1dB Compression Point
vs. Temperature and V TxRx
CC
vs. Temperature and V TxRx
CC
200
150
100
50
-47.0
-49.0
-51.0
-53.0
-55.0
-57.0
-59.0
DCRes Resistor=100k
5.5V
4.0V
2.7V
3.0V
5.5V
0
3.0V
4.0V
-50
2.7V
-100
-150
-200
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
SA1638 Receiver QRXOUT Voltage
Reference Voltage
1.8
1.7
1.6
1.5
1.4
1.8
5.5V
5.5V
1.75
1.7
4V
1.65
4V
1.6
3V
3V
1.55
2.7V
2.7V
1.5
1.45
-50
0
50
100
-50
0
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
LO Maximum Frequency Div800
Receiver IP2 vs Temperature and Supply Voltage
IN
1100
1050
1000
950
5.00
4.00
3.00
2.00
1.00
0
V
= 100mV
LOIN PEAK
3V
3V
2.7V
5.5V
4V
4V
-1.00
-2.00
-3.00
-4.00
-5.00
2.7V
5.5V
900
-50
0
50
100
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
Temperature (°C)
Figure 14. Typical Performance Characteristics (continued)
21
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
CLK Maximum Frequency Div52
N Charge Pump
IN
Output Current 000
250
-495
-500
-505
-510
-515
-520
-525
2.7V
2.7V
3V
225
3V
4V
4V
200
175
150
V
= 100mV
PEAK
CLKIN
5.5V
50
5.5V
-50
0
50
100
-50
0
100
TEMPERATURE (°C)
TEMPERATURE (°C)
P Charge Pump
Output Current 111
N Charge Pump Relative
Output Variation
-1000
-1010
-1020
-1030
-1040
-1050
-1060
1.25
1
2.7V
5.5V
3V
0.75
0.5
0.25
0
4V
4V
5.5V
3V
2.7V
-50
0
50
100
-50
0
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Charge Pump Match
Current 111
Charge Pump Output Leakage Current
0.25
-20
-30
-40
-50
-60
2.7V
2.7V
3V
3V
0
-0.25
-0.5
4V
4V
5.5V
5.5V
-0.75
-50
0
50
100
-50
0
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Typical Performance Characteristics (continued)
22
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Transmitter Supply Current vs.
Receiver Supply Current vs.
Temperature and V TxRx
Temperature and V TxRx
CC
CC
26
24
22
20
18
16
14
12
10
20
19
18
17
16
15
14
13
12
11
10
5.5V
4.0V
5.5V
4.0V
3.0V
2.7V
3.0V
2.7V
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
Power Down Supply Current vs.
Receiver Uncorrected Output Offset
Voltage vs Temperature and V TxRx
Temperature and V TxRx
CC
CC
270
265
260
255
250
160
140
120
100
80
DCRES = 100kΩ
5.5V
4.0V
3.0V
2.7V
60
40
5.5V
245 4.0V
3.0V
20
2.7V
240
-50
0
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-30
-10
10
30
50
70
90
Temperature (°C)
TEMPERATURE (°C)
Receiver Output Offset Control Step
Receiver Output Offset Control Step Size vs
Temperature and V TxRx
Size vs Temperature and V TxRx
CC
CC
37
36
330
320
310
300
290
280
DCRES = 100kΩ
5.5V
4.0V
3.0V
DCRES = 1MΩ
5.5V
35
34
33
32
4.0V
3.0V
2.7V
2.7V
-50
-30
-10
10
30
50
70
90
-50
-30
-10
10
30
50
70
90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Typical Performance Characteristics (continued)
23
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
24
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
NOTES
25
1997 Sept 03
Philips Semiconductors
Product specification
Low voltage IF I/Q transceiver
SA1638
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 08-98
Document order number:
9397 750 06847
Philips
Semiconductors
相关型号：
©2020 ICPDF网 联系我们和版权申明