SAA3323 [NXP]
Drive processor for DCC systems; 对于DCC系统驱动处理器
| 型号： | SAA3323 |
| 厂家： | 
NXP |
| 描述： | Drive processor for DCC systems |
| 文件： | 总56页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA3323
Drive processor for DCC systems
May 1994
Preliminary specification
File under Integrated Circuits, IC01
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
FEATURES
• Operating supply voltage: 2.7 to 3.6 V
• Low power dissipation: 84 mW (typ)
• Single chip digital equalizer, tape formatting and error
correction
• 8-bit flash analog-to-digital converter (ADC) for low
symbol error rate
• Frequency and phase regulation of capstan servo
during playback
• Two switchable Infinite Impulse-Response (IIR) filter
• Choice of Dynamic Random Access Memory (DRAM)
and Static Random Access Memory (SRAM) types for
system Random Access Memory (RAM)
sections
• 10-tap Finite Impulse-Response (FIR) filter per main
data channel, with 8 bit coefficients, identical for all main
channels
• Scratch pad RAM for microcontroller in system RAM
• Integrated interface for Precision Adaptive Sub-band
Coding (PASC) data bus
• 10-tap FIR filter for the AUX channel
• Analog and digital eye outputs
• Three wire microcontroller ‘L3’ interface
• Protection against invalid auxiliary data
• Seamless joins between recordings.
• Interrupt line triggered by internal auxiliary envelope
processing e.g. label, counter, and others
• Robust programmable digital PLL clock extraction unit
• Low power SLEEP mode
GENERAL DESCRIPTION
• Slew rate limited Electromagnetic Compatibility (EMC)
The SAA3323 performs the drive processor function in the
DCC system. This function is built up of digital equalizer,
error correction and tape formatting functions. The digital
equalizer is intended for use with DCC read amplifiers
TDA1318 or TDA1380. The tape formatting and error
correction circuit is intended for use with PASC ICs
SAA2003 and SAA2013, and write amplifiers TDA1319 or
TDA1381.
friendly output
• Digital Compact Cassette (DCC) optimized error
correction
• Programmable symbol synchronization strategy for tape
input data
• Microcontroller control of capstan servo possible during
playback and recording
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
plastic
CODE
SAA3323H
80
80
TQFP80(1)
QFP80(1)
SOT315-1
SOT318-2
SAA3323GP
plastic
Note
1. When using reflow soldering it is recommended that the Dry Packing instructions in the “Quality Reference
Pocketbook” are followed. The pocketbook can be ordered using the code 9398 510 34011.
May 1994
2
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
BLOCK DIAGRAM
SAA3323
DIGITAL-
TO-ANALOG
CONVERTER
ANAEYE
RDSYNC
RDMUX
PHASE
LOCKED
LOOP
ANALOG
TO-DIGITAL
CONVERTER
ZERO
CROSSING
(1)
(2)
BIAS
V
FIR
IIR
ref(p)
V
ref(n)
AUXILIARY
ENVELOPE
DETECTION
TAPE
INPUT
BUFFER
EQUALIZER
MODULE
SBDIR
SBMCLK
SBEF
TAPE
OUTPUT
BUFFER
TCLOCK
WDATA
SUB-BAND
I S
INTERFACE
2
INTERNAL DATA BUS
SBDA
SBCL
SBWS
SPEED
URDA
RESET
SLEEP
CONTROL
INTERFACE
ERROR
CORRECTOR
RAM
INTERFACE
L3REF
L3DATA
8
11
6
MLB761
(1) FIR = Finite Impulse-Response.
(2) IIR = Infinite Impulse-Response.
Fig.1 Block diagram.
May 1994
3
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
PINNING
PIN
SYMBOL
DESCRIPTION
TYPE(1)
QFP80
TQFP80
SBWS
SBCL
SBDA
SBDIR
SBMCLK
URDA
L3MODE
L3CLK
L3DATA
L3INT
VDD1
1
79
80
1
word select for sub-band PASC interface
bit clock for sub-band PASC interface
data line for sub-band PASC interface
direction line for sub-band PASC interface
master clock for sub-band PASC interface
unreliable data
I/O (1 mA)
I/O (1 mA)
I/O (1 mA)
O (1 mA)
I
2
3
4
2
5
3
6
4
O (1 mA)
I
7
5
mode line for L3 interface
bit clock line for L3 interface
serial data line for L3 interface
L3 interrupt output
8
6
I
9
7
I/O (2 mA)
O (1 mA)
S
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
8
9
digital supply voltage
VSS1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
digital ground
S
L3REF
RESET
SLEEP
CLK24
AZCHK
MCLK
TEST3
ERCOSTAT
OEN
L3 bus timing reference
O (1 mA)
I
reset SAA3323
sleep mode selection of SAA3323
24.576 MHz clock input
I
I
channel 0 and channel 7 azimuth monitor
6.144 MHz clock output
O (1 mA)
O (1 mA)
O (1 mA)
O (1 mA)
O (2 mA)
O (2 mA)
S
TEST3 output; do not connect
ERCO status, for symbol error rate measurements
output enable for RAM
A10/RAS
VDD2
address SRAM; RAS DRAM
digital supply voltage
VSS2
digital ground
S
D7
data SRAM
I/O (4 mA)
I/O (4 mA)
I/O (4 mA)
I/O (4 mA)
I/O (4 mA)
I/O (4 mA)
I/O (4 mA)
S
D6
data SRAM
D5
data SRAM
D4
data SRAM
D3
data SRAM; data DRAM
data SRAM; data DRAM
data SRAM; data DRAM
digital supply voltage for RAM
digital ground for RAM
D2
D1
VDD7
VSS7
S
D0
data SRAM; data DRAM
address SRAM; address DRAM
address SRAM; address DRAM
address SRAM; address DRAM
address SRAM; address DRAM
I/O (4 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
A0
A1
A2
A3
May 1994
4
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
PIN
SYMBOL
DESCRIPTION
address SRAM; address DRAM
TYPE(1)
QFP80
TQFP80
A4
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
O (2 mA)
S
VSS3
digital ground
VDD3
digital supply voltage
S
A5
address SRAM; address DRAM
address SRAM; address DRAM
address SRAM; address DRAM
address SRAM; Port expander output 5
address SRAM; Port expander output 1
address SRAM; Port expander output 3
address SRAM; Port expander output 4
write enable for RAM
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
S
A6
A7
A12/PINO5
A14/PINO1
A16/PINO3
A15/PINO4
WEN
A13/PINO2
A8
address SRAM; Port expander output 2
address SRAM; address DRAM
digital supply voltage
VDD4
VSS4
digital ground
S
A9/CAS
A11
address SRAM; CAS for DRAM
address SRAM
O (2 mA)
O (2 mA)
SPEED
PINO2
WDATA
TCLOCK
VSS5
Pulse Width Modulation (PWM) capstan control output for deck Ot (1 mA)
Port expander output 2
Ot (1 mA)
serial output to write amplifier
3.072 MHz clock output for tape I/O
digital ground
O (1 mA)
O (1 mA)
S
VDD5
digital supply voltage
S
TEST2
RDMUX
Vref(p)
TEST mode select; do not connect
analog multiplexed input from read amplifier
ADC positive reference voltage
ADC negative reference voltage
substrate connection
Ipd
IA
IA
Vref(n)
IA
SUBSTR
BIAS
IA
bias current for ADC
IA
VSSA
analog ground
S
VDDA
analog supply voltage
S
ANAEYE
RDSYNC
VDD6
analog eye pattern output
synchronization output for read amplifier
digital supply voltage
OA
O (1 mA)
S
VSS6
digital ground
S
CHTST1
CHTST2
TEST0
TEST1
channel test pin 1
O (1 mA)
O (1 mA)
Ipd
channel test pin 2
TEST mode select; do not connect
TEST mode select; do not connect
Ipd
May 1994
5
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
PIN
SYMBOL
DESCRIPTION
TYPE(1)
QFP80
TQFP80
PINI
78
79
80
76
77
78
Port expander input
I
PINO1
SBEF
Port expander output 1
O (1 mA)
O (1 mA)
sub-band PASC error flag line
Note
1. I = input; IA = analog input; Ipd = input with pull-down resistance; I/O = bidirectional; O = output; OA = analog output;
Ot = 3-state output; S = supply.
SBDA
SBDIR
1
2
60 TEST2
V
59
58
DD5
SS5
V
SBMCLK
URDA
3
4
57 TCLOCK
56 WDATA
55 PINO2
54 SPEED
53 A11
L3MODE
5
L3CLK
L3DATA
L3INT
6
7
8
V
9
52 A9/CAS
V
DD1
V
10
51
50
SS4
DD4
SS1
SAA3323
V
L3REF 11
RESET 12
SLEEP 13
CLK24 14
49 A8
48 A13/PINO2
47
WEN
AZCHK 15
MCLK 16
46 A15/PINO4
45 A16/PINO3
44 A14/PINO1
43 A12/PINO5
42 A7
TEST3 17
ERCOSTAT 18
19
20
OEN
A10/RAS
41 A6
MLB762
Fig.2 Pin configuration (SOT315-1; TQFP80).
6
May 1994
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
V
SBWS
SBCL
1
2
3
4
5
6
7
8
9
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
ref(p)
RDMUX
TEST2
SBDA
V
SBDIR
DD5
V
SBMCLK
URDA
SS5
TCLOCK
WDATA
PINO2
SPEED
A11
L3MODE
L3CLK
L3DATA
L3INT 10
V
11
12
13
A9/CAS
DD1
V
V
SS1
SS4
SAA3323
V
L3REF
DD4
RESET 14
SLEEP 15
A8
A13/PINO2
CLK24 16
WEN
AZCHK 17
MCLK 18
A15/PINO4
A16/PINO3
A14/PINO1
TEST3 19
ERCOSTAT 20
A12/PINO5
21
A7
A6
OEN
22
A10/RAS
V
23
42 A5
DD2
V
V
24
SS2
41
DD3
MLB763
Fig.3 Pin configuration (SOT318-2; QFP80).
7
May 1994
RAM
41464
BUFFER
64K x 4
speed control
CAPSTAN
DRIVE
L
DAC
analog
output
TDA1305
sub-band
R
2
I S
SFC3
SAA2003
WRAMP
TDA1381
WRITE AMP.
baseband
STEREO
FILTER CODEC
2
I S
DRP
SAA2023
OR
L
FIXED
HEAD
TAPE
analog
input
ADC
SAA7366
SAA3323
DRIVE
PROCESSOR
2
R
filtered I S
RDAMP
TDA1380
READ AMP.
ADAS3
SAA2013
ADAPTIVE
ALLOCATION
DIGITAL
AUDIO I/O
TDA1315
MECHANICS
DRIVERS
IEC958
search data
analog CC
L output
detect
switch
analog CC
R output
AUDIO IN/OUT
PASC PROCESSOR
TAPE DRIVE PROCESSING
SYSTEM
MICROCONTROLLER
SYSTEM CONTROL
MBD620
Fig.4 DCC system block diagram.
ahdnbok,uflapegwidt
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
A simplified block diagram of the SAA3323 is shown in
Fig.1.
Table 1 Basic modes of TFE module.
MODE EXPLANATION
DPAP
audio and SYSINFO (main data) play;
AUX play
DCC drive processing
The SAA3323 provides the following functions for the DCC
drive processing.
DPAR
DRAR
audio and SYSINFO (main data) play;
AUX record
audio and SYSINFO (main data) record;
AUX record
PLAYBACK MODES
• Analog-to-digital conversion
• Tape channel equalization
TFE REGISTERS
• Tape channel data and clock recovery
• 10-to-8 demodulation
The TFE module has 8 writable and 5 readable registers
that are accessible via the L3 interface, one write register
(CMD) and four read registers (STATUS0 to STATUS3)
which are directly addressable, the other registers are
indirectly addressable via commands sent to the CMD
register. The registers are named as shown in Table 2.
• Data placement in system RAM
• C1 and C2 error correction decoding
• Interfacing to sub-band serial PASC interface
Table 2 TFE register names.
• Interfacing to microcontroller for SYSINFO and AUX
data
REGISTER NAME
READ/WRITE
• Capstan control for tape deck.
CMD
W
R
STATUS0
STATUS1
STATUS2
STATUS3
SET0
RECORD MODES
R
• Interfacing to sub-band serial PASC interface
• C1 and C2 error correction encoding
• Formatting for tape transfer
• 8-to-10 modulation
R
R
W
W
W
W
W
W
W
R
SET1
SET2
• Interfacing to microcontroller for SYSINFO and AUX
data
SET3(1)
SPDDTY
BYTCNT
RACCNT
SPEED
• Capstan control for tape deck, programmable by
microcontroller.
SEARCH MODE
• Detection and interpretation of AUX envelope
information
Note
1. The 4 LSBs of register ‘SET3’ set RAM type (RType)
and RAM timing (RTim). See Table 3.
• AUX envelope counting
• Search speed estimation.
For normal operation the 4 MSBs of register ‘SET3’
should be logic 0.
Tape Formatting and Error (TFE) correction module
The TFE module has 3 basic modes of operation as shown
in Table 1.
May 1994
9
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 3 RAM settings by register SET3.
Table 4 TFE data streams.
RAM
REGISTER SET3
DATA STREAM NAME
READ/WRITE
RTYPE 0
RTYPE 1
RTim 0
bit 0
bit 1
bit 2
bit 3
SYSINFO
R/W
R/W
R/W
AUXINFO
Scratch pad RAM
RTim 1
TFE ‘COMMANDS’
TFE DATA STREAMS
These are the commands that need to be sent to the TFE
in order to access the indirectly accessible registers and
the data streams, see Table 5.
The TFE module has three read/write data streams that
are accessible via the L3 interface and they are shown in
Table 4.
Table 5 TFE commands.
COMMAND BYTE
NAME
EXPLANATION
7
6
5
4
3
2
1
0
RDSPEED
LDSET0
0
0
0
0
0
0
0
0
0
0
Y
Y
0
0
Y
Y
0
0
0
0
0
0
0
0
0
0
Z
Z
0
0
Z
Z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
1
1
0
0
1
0
1
0
1
0
1
read SPEED register
load new TFE settings register 0
load new TFE settings register 1
load new TFE settings register 2
load new TFE settings register 3
load SPDDTY register
LDSET1
LDSET2
LDSET3
LDSPDDTY
LDBYTCNT
LDRACCNT
RDAUX
load BYTCNT register
load RACCNT register
read AUXILIARY information
read SYSINFO
RDSYS
RDDRAC
RDWDRAC
WRAUX
read RAM data bytes (8 bits) from quarter YZ
read RAM data words (12 bits) from quarter YZ
write AUXILIARY information
write SYSINFO
WRSYS
WRDRAC
WRWDRAC
write RAM data bytes (8 bits) to quarter YZ
write RAM data words (12 bits) to quarter YZ
Digital equalizer module
DIGITAL EQUALIZER REGISTERS
The digital equalizer module has 2 basic modes of
operation as shown in Table 6.
The digital equalizer module has 9 write only, 3 read only
and 1 read/write register(s) that are accessible via the
L3 interface, one write register (CMD) and 2 read registers
(STATUS0 and STATUS1) which are directly addressable,
the other registers are indirectly addressable via
commands sent to the CMD register. The registers are
named as shown in Table 7.
Table 6 Basic modes of equalizer module.
MODE
EXPLANATION
Play
main data and AUX channels are
equalized
Search
only AUX channel is processed; AUX
envelope information is processed
May 1994
10
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 7 Digital equalizer register names.
DATA STREAMS
The digital equalizer module has one write only and one
read only data stream that are accessible via the
L3 interface and they are shown in Table 8.
REGISTER NAME
READ/WRITE
CMD
W
R
STATUS0
STATUS1
COEFCNT
FCTRL
R
Table 8 Digital equalizer data streams.
W
W
W
W
W
R/W
R
DATA STREAM NAME
FIR coefficients to buffer bank
FIR coefficients from active bank
READ/WRITE
W
W
CHT1SEL
CHT2SEL
ANAEYE
AEC
DIGITAL EQUALIZER “COMMANDS”
These are the commands that need to be sent to the digital
equalizer in order to access the indirectly accessible
registers and the data streams.
SSPD
INTMASK
DEQ2SET
CLKSET
W
W
W
Table 9 Digital equalizer commands.
COMMAND BYTE
NAME
WRCOEF
EXPLANATION
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
0
0
1
write FIR coefficients to the digital equalizer buffer bank
read FIR coefficients from the digital equalizer active bank
load FIR coefficient counter
RDCOEF
LDCOEFCNT
LDFCTRL
LDT1SEL
LDT2SEL
LDTAEYE
LDAEC
load filter control register
load CHTST1 pin selection register
load CHTST2 pin selection register
load ANAEYE channel selection register
load AEC counter
RDAEC
read AEC counter
RDSSPD
read SEARCH speed register
LDINTMSK
LDDEQ3SET
LDCLKSET
load interrupt mask register
load digital equalizer settings register
load PLL clock extraction settings register
Table 10 Filter control register.
BIT
7
6
−
0
5
−
0
4
µCS(1)
0
3
2
1
0
Meaning
Default
−
SH1
1
SH0
0
Reserved
0
1
1
Note
1. µCS is a microcontroller controlled coefficient bank switch. This causes the filter coefficients to be activated at a time
that is safe for the digital equalizer, i.e. at the end of the FIR program and that the complete value of coefficient
number 9 has been received.
May 1994
11
--------
-
---------
--------
-
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
There are 2 banks of coefficients for both the aux and the
main data channels, namely the ‘buffer’, and the ‘active’
banks. The microcontroller writes only to the ‘buffer’
banks, and reads only from the ‘active’ banks.
Table 11 SH1 and SH2 (FIR output scaling).
SH
EFFECT ON FIR OUTPUT
1
0
The microcontroller can poll the digital equalizer status bit
BKSW to see when the switch occurs. BKSW starts life
LOW, goes HIGH as a result of the bank switching and
goes LOW as result of the complete value of a main data
coefficient being received by the digital equalizer.
0
0
0
1
FIR mod 256
FIR
mod 256
mod 256
mod 256
2
1
1
0
1
FIR
4
The microcontroller sets µCS HIGH before sending the
new set of aux or main data coefficients, the digital
equalizer resets it once the bank switch occurs.
FIR
8
The actual FIR coefficients that are used are a function of
the tape head, read amplifier and type of tape (i.e.
pre-recorded or own recorded) used, such information is
outside of the scope of this data sheet.
Transfer of FIR coefficients
For the main data channels (tracks 0 to 7) there are
10 coefficients (taps) each of 8 bits, where all of the data
channels make use of the same coefficients. The
addresses for the main data coefficients 0 to 9 are
0 to 9dec respectively.
Coefficient address counter (COEFCNT)
This 5 bit counter is used to point to the FIR coefficient to
be transferred to or from the digital equalizer.
There are ten coefficients (taps) each of 8 bits for the aux
channel (CHAUX). The addresses for the auxiliary
coefficients 0 to 9 are 16 to 25dec respectively.
Table 12 Coefficient address counter.
BIT
7
6
5
4
3
2
1
0
Meaning
Default
−
−
−
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
0
0
0
mode, the SLEEP pin should be taken LOW and the
SAA3323 reset.
Pin explanations and interfacing to other hardware
RESET
CLK24
This is an active HIGH input which resets the SAA3323
and brings it into its default mode, DPAP. This reset does
not affect the contents of the FIR filter coefficients in the
digital equalizer. This should be connected to the system
reset, which can be driven by the microcontroller. The
duration of the reset pulse should be at least 15 µs.
This is the 24.576 MHz clock input and should be
connected directly to the SAA2003 (pin CLK24).
Sub-band serial PASC interface connections
The timing for the sub-band serial PASC interface is given
in Figs 5 to 7.
SLEEP
This pin is an active HIGH input which puts the SAA3323
in a low power consumption SLEEP mode. This pin should
be connected to the DCC SLEEP signal, which can be
driven by the microcontroller. The CLK24 clock may be
stopped and the VREFP and VREFN inputs brought to
ground while the SAA3323 is in ‘sleep’ mode to further
reduce power consumption. When recovering from sleep
May 1994
12
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SBCL(in)
SBWS(in)
SBDA(in)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SBCL(in)
SBWS(in)
SBDA(in)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
bit number
V
V
IH
SBCL(in)
SBWS(in)
SBDA(in)
OH
V
V
IH
OH
V
V
IH
OH
MGB381
2 x t
40 ns
40 ns
MCLK
Fig.5 Sub-band serial PASC interface timing; DRAR mode.
May 1994
13
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SBCL(out)
SBWS(out)
SBDA(out)
SBEF(out)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SBCL(out)
SBWS(out)
SBDA(out)
SBEF(out)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
bit number
V
V
IH
IL
SBMCLK(in)
V
V
OH
OL
SBCL(out)
SBWS(out)
SBDA(out)
SBDA(out)
60 ns
V
V
OH
OL
V
V
OH
OL
7 ns
7 ns
V
V
OH
OL
MGB382
Fig.6 Sub-band serial PASC interface timing in play modes; DRPMAS = logic 1.
May 1994
14
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SBCL(in)
SBWS(in)
SBDA(out)
SBEF(out)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SBCL(in)
SBWS(in)
SBDA(out)
SBEF(out)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
bit number
V
V
IH
IL
SBCL(in)
SBWS(in)
SBDA(out)
SBDA(out)
V
V
IH
IL
2 x t
40 ns
40 ns
MCLK
t
V
V
OH
OL
(40 85) ns
MCLK
V
V
OH
OL
MGB383
t
(40 40) ns
MCLK
Fig.7 Sub-band serial PASC interface timing in play modes; DRPMAS = logic 0.
SBMCLK
SBCL
This is the sub-band master clock input for the sub-band
serial PASC interface. The frequency of this signal is
nominally 6.144 MHz. When the SAA3323 is used with
SAA2003 this pin is tied to ground, and the TFE settings
bit ‘DRPMAS’ set to logic 1.
This input/output pin is the bit clock line for the sub-band
serial PASC interface to the SAA2003. When used with
SAA2003 this pin is input only. It has a nominal frequency
of 768 kHz.
SBWS
SBDIR
This input/output pin is the word select line for the
sub-band serial PASC interface to the SAA2003. When
used with SAA2003 this pin is input only. It has a nominal
frequency of 12 kHz.
This output pin is the sub-band serial PASC bus direction
signal, it indicates the direction of transfer on the sub-band
serial PASC bus. This pin connects directly to the SBDIR
pin on the SAA2003. The transfer directions are shown in
Table 13.
SBDA
This input/output pin is the serial data line for the sub-band
serial PASC interface to the SAA2003.
Table 13 PASC bus transfer directions.
SBDIR
DIRECTION
SBEF
1
0
SAA3323 to SAA2003 transfer (audio play)
SAA2003 to SAA3323 transfer (audio record)
This active HIGH output pin is the error-per-byte line for
the sub-band serial PASC interface to the SAA2003.
May 1994
15
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
the URDA pin of the SAA2003. URDA goes active as a
result of a reset, a mode change from mode DRAR to
DPAP, or if the SAA3323 has had to re-synchronize with
the incoming data from tape.
URDA
This active HIGH output pin indicates that the main data
(audio), the SYSINFO and the AUXILIARY data are NOT
usable, regardless of the state of the corresponding
reliability flags. The state of this pin is reflected in the
URDA bit of STATUS byte 0, which can be read by the
microcontroller. This pin should be connected directly to
The position of the first sub-band serial PASC bytes in a
tape frame is shown in Figs 8 and 9.
0
1
SNUM
SBWS
L3REF
'FIRST BYTE"
SBDA
MGB384
byte 0
byte 1 byte 2
Fig.8 Position of first sub-band serial PASC bytes in a tape frame in DPAP/DPAR mode.
3
0
SNUM
SBWS
L3REF
'FIRST BYTE'
SBDA
MGB385
byte 0 byte 1 byte 2
Fig.9 Position of first sub-band serial PASC bytes in a tape frame in DRAR mode.
May 1994
16
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
RAM connections
OEN
The SAA3323 has been designed to operate with DRAMs
and SRAMs. Suitable DRAMs are 64K × 4-bit or
256K × 4-bit configurations operating in page mode, with
an access time of 80 to 100 ns. The timing for read, write
and refresh cycles for DRAMs is shown in Figs 10 to 12.
The timing for SRAMs is shown in Figs 13 to 19.
This output pin is the output enable (active LOW) for the
RAM, it connects directly to the output enable pin of the
RAM.
WEN
This output pin is the write enable (active LOW) for the
RAM, it connects directly to the write enable pin of the
RAM.
For fast SRAMs: (these values are subject to verification
during characterization in). The conditions (most critical at
the required VDD) are shown in Table 14.
A0 TO A8
Table 14 Fast SRAM conditions.
When SAA3323 is used with DRAM these output pins are
the multiplexed column and row address lines. When the
64K × 4-bit DRAM is used, pins A0 to A7 should be
connected to the DRAM address input pins, and pin A8
should be left unconnected. When using the 256K × 4-bit
DRAM the address pins A0 to A8 should be connected to
the address input pins of the DRAM.
CONDITION(1)
TIME
W ≤ 140 ns
su ≤ 72 ns
cy ≤ 200 ns
ACC ≤ 240 ns
Write pulse duration
Data set-up to rising WEN
Write cycle time
t
t
T
Read access time
t
When SAA3323 is used with SRAM these are the lower
address pins and should be connected directly to the
SRAM address pins.
Note
1. The SAA3323 should work in: RType = ‘01’;
RTim = ‘00’ mode.
A11
A9/CAS
This output pin is the an address pin for the SRAM and
when SRAM is used they should be connected directly to
the address pins of the SRAM. When DRAM is used this
pin should not be connected.
When SAA3323 is used with SRAM this output pin is
Address line 9, and should be connected directly to the
corresponding address pin on the SRAM. When SAA3323
is used with DRAM this output pin is the column address
strobe (active LOW), it connects directly to the column
address strobe pin of the DRAM.
A10 AND A12 TO A16
These output pins are the upper address pins for the
SRAM and when SRAM is used they should be connected
directly to the address pins of the SRAM. When DRAM is
used or when the small SRAM is used all or some of these
pins become available as Port expander outputs.
A10/RAS
When SAA3323 is used with SRAM this output pin is
Address line 10, and should be connected to the
corresponding address pin of the SRAM. When SAA3323
is used with DRAM this output pin is the row address
strobe (active LOW), it connects directly to the row
address strobe pin of the DRAM.
May 1994
17
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 15 Port expander outputs.
PIN
PORT EXPANDER
OUTPUT
PIN NAME
CONDITIONS
QFP80
TQFP80
A14/PINO1
A13/PINO2
A16/PINO3
A15/PINO4
A12/PINO5
46
50
47
48
45
44
48
45
46
43
PINO1
PINO2
PINO3
PINO4
PINO5
RType = 00
RType = 00
RType = 00 or RType = 01
RType = 00 or RType = 01
RType = 00
D0 TO D3
When SAA3323 is used with SRAM these I/O pins form the lower nibble of the data bus connection to the RAM, and
should be connected to the corresponding data I/O pins of the SRAM. When SAA3323 is used with DRAM these
input/output pins are the data lines for the RAM, they should be connected directly to the DRAM data I/O pins.
D4 TO D7
These input/output pins are the upper nibble of the data bus for use with SRAM, and when SRAM is being used they
should be connected directly to the corresponding SRAM I/O pins.
WEN
OEN
t
RAS
A10/RAS
t
t
t
CAS
RP
RCD
t
A9/CAS
ASC
t
t
t
CP
RAH
t
t
CAH
ASR
A0 to A8
D0 to D3
ROW ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
OFF
COLUMN ADDRESS
t
t
CAC
OEZ
NIBBLE 0 DATA
NIBBLE 1 DATA
NIBBLE 2 DATA
t
MGB386
RAC
Fig.10 DRAM read cycle timing.
May 1994
18
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
t
WCS
t
WCH
WEN
OEN
t
RAS
A10/RAS
A9/CAS
t
t
t
CAS
RP
RCD
t
ASC
t
t
CP
RAH
t
t
CAH
ASR
A0 to A8
D0 to D3
ROW ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
NIBBLE 1 DATA
COLUMN ADDRESS
NIBBLE 2 DATA
NIBBLE 0 DATA
MGB387
t
DH
t
DS
Fig.11 DRAM write cycle timing.
WEN
OEN
t
t
RP
RAS
A10/RAS
A9/CAS
t
RAH
t
ASR
A0 to A8
D0 to D3
ROW ADDRESS
MGB388
Fig.12 DRAM refresh cycle timing.
19
May 1994
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
WEN
OEN
A0 to A16
D0 to D7
ADDRESS
ADDRESS
OH
t
t
t
OHZ
AA
DATA
DATA
MGB389
t
OLZ
READ
READ
Fig.13 Fast SRAM read cycle timing.
t
t
WP
WP
WEN
OEN
t
AW
t
WC
A0 to A16
ADDRESS
ADDRESS
t
DHO1
t
t
t
DW2
OLZ
DATA
DW1
D0 to D7
DATA
t
DATA
MGB390
t
AA
t
t
DH2
DH1
OHZ
READ MODIFY WRITE
WRITE
Fig.14 Fast SRAM write cycle timing; RTim = “00”.
20
May 1994
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
t
t
WP
WP
WEN
OEN
t
AW
t
WC
A0 to A16
D0 to D7
ADDRESS
ADDRESS
t
t
DHO1
t
DAH
DAH
t
OLZ
t
t
DW1
DW2
DATA
t
DATA
DATA
MGB391
t
AA
t
t
OHZ
DDH
DDH
WRITE
READ MODIFY WRITE
Fig.15 Fast SRAM write cycle timing; RTim = “01”.
t
t
WP
WP
WEN
OEN
t
AW
t
WC
A0 to A16
ADDRESS
ADDRESS
t
DHO1
t
t
OLZ
t
DW1
DW2
D0 to D7
DATA
DATA
OHZ
DATA
t
MGB392
t
DH2
t
DH1
t
AA
t
WOA
WRITE
READ MODIFY WRITE
Fig.16 Fast SRAM write cycle timing; RTim = “10”.
21
May 1994
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
WEN
OEN
A0 to A16
D0 to D7
MGB393
WRITE
READ MODIFY WRITE
Fig.17 Fast SRAM write cycle timing; RTim = “11”.
WEN
OEN
A0 to A16
D0 to D7
ADDRESS
t
ADDRESS
OHZ
t
OLZ
DATA
DATA
MGB394
t
t
OH
AA
READ
READ
Fig.18 Slow SRAM read cycle timing.
22
May 1994
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
t
t
WP
WP
WEN
OEN
t
t
AW
WC
AW
WC
t
t
A0 to A16
D0 to D7
ADDRESS
ADDRESS
t
t
DW1
DW2
DATA
DATA
MGB395
t
t
DH
DH
WRITE
WRITE
Fig.19 Slow SRAM write cycle timing.
Table 16 Timing values for Figs 10 to 12.
Table 17 Timing values for Figs 13 to 17.
SYMBOL
VALUE (ns)
SYMBOL
VALUE (ns)
tRP
≥110
≥510
≥70
tWP
tAW
tWC
tDW
tDM
tAA
≥140
≥180
≥200
≥72
tRAS
tRCD
tCP
≥30
tCAS
tASR
tRAH
tASC
tCAM
tDS
≥100
≥100
≥25
≥25
≤240
≥250
tHC
≥30
Table 18 Timing values for Figs 18 and 19.
SYMBOL VALUE (ns)
≥100
≥25
tDH
≥100
≥30
tWP
tAW
tWC
tDW
tDM
tAA
≥225
≥260
≥300
≥140
≥25
tWCS
tWCH
tRAC
tCAC
≥100
≤160
≤80
≤280
May 1994
23
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Read/write connections
RDSYNC
This output line provides synchronization information for
the read Amplifier data transfers. The relationship between
TCLOCK, RDSYNC and the channel information carried
by the RDMUX line is given in Fig.20. This pin should be
connected directly to the RDSYNC pin of the read
amplifier. When the digital equalizer in SAA3323 is in
search mode this pin will be HIGH ensuring that only the
AUX channel is processed by the SAA3323.
TCLOCK
This output pin is the 3.072 MHz clock output for the read
and write amplifiers, it should be connected directly to the
WCLOCK pin of the write amplifier and to the RDCLK pin
of the read amplifier.
RDMUX
This input pin carries the time multiplexed analog tape
channel signals from the read amplifier.
WDATA
This output pin is the multiplexed data and control line for
the write amplifier. Figure 21 shows the manner in which
this information is multiplexed onto WDATA. The WDATA
pin should be connected directly to the WDATA pin of the
write amplifier.
Vref(n) AND Vref(p)
These are the lower and upper voltage reference inputs for
the ADC in the digital equalizer part of SAA3323.
BIAS
This pin defines a bias current for the ADC. It should be
connected to the analog supply voltage VDDA via a 47 kΩ
resistor.
TCLOCK
RDMUX
RDSYNC
MGB396
Fig.20 RDMUX, RDSYNC and TCLOCK timing.
TCLOCK
WDATA
SYNC
MGB397
Fig.21 WDATA and TCLOCK timing.
May 1994
24
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Tape deck capstan control connections
SPEED
This pin outputs a pulse width modulated signal that may
be used for controlling the tape capstan of the deck.
Operation of the SPEED control signal
Table 19 gives the sources that determine the duty factor
of the SPEED signal. Note that the 3-state SPEED output
may be put into high-impedance state by programming the
TFE setting by bit HiZSpd.
Table 19 SPEED signal duty factor.
SOURCE FOR
MODE
DPAP
µCSPD
SPEED DUTY
FACTOR
0
1
0
1
0
1
tape(1)
µC(2)
tape(1)
µC(2)
50%(3)
µC(2)
DPAP
DPAR
DPAR
DRAR
DRAR
Notes
1. “Tape” means that the duty factor has been calculated
from the played back main data tape signal. When
tape is the source for the duty factor of the SPEED
signal, the type of regulation can be chosen with the
TFE settings bits EnFReg and SeINBand.
2. “µC” means that the microcontroller programs the duty
factor via the SPDDTY register.
3. “50%” means that the duty factor is fixed at 50%.
May 1994
25
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
MEA717
100 %
91 %
duty
factor
speed
50 %
9 %
0
0
+ 2 blocks
+ 10.6 ms
+ 1.65 blocks
+ 8.8 ms
– 1.65 blocks
– 8.8 ms
– 2 blocks
– 10.6 ms
Fig.22 SPEED regulation duty factor as a function of phase characteristic.
If EnFReg is programmed ‘LOW’ then there is phase
If EnFReg is programmed ‘HIGH’ then the above
regulation of the capstan speed. The period of the pulse
width modulated SPEED signal is 41.66 µs. The SAA3323
performs a new calculation to determine the duty factor of
SPEED once every 21.33 ms, giving a sampling rate of
approximately 46.9 Hz. This calculation is basically a
phase comparison between the incoming Main Data tape
frame and an internally generated reference. The SPEED
duty factor as a function of phase characteristic is shown
in Fig.22. As shown the duty factor increases
monotonously from approximately 9% when the incoming
Main Data tape frame is 1.65 tape blocks (8.8 ms) too
early up to 91% when it is 1.65 tape blocks (8.8 ms) too
late. Outside of a ±2 tape blocks range the pulse width
characteristic overflows and repeats itself forming a
sawtooth pattern. The SAA3323 has an internal buffer of
±8.8 ms outside of which the phase information is invalid.
description is over-ridden with frequency information. If the
incoming main data bit rate deviation from the nominal
96000 bits/s rate is less than the Phase Only Threshold
(POT) then the control is as described above in the phase
control description. If the deviation is more than the
Frequency Only Threshold (FOT) then the SPEED
information is gated with the phase information resulting in
the SPEED signal being continuously HIGH or LOW while
the condition continues. If the deviation is between the
POT and the FOT then the frequency information is gated
with the Phase information for 50% of the time.
The deviation thresholds POT and FOT are programmable
via the TFE settings bit SeINBand.
Table 20 POT and FOT deviation thresholds.
POT
FOT
SeINBand
(DEVIATION FROM NOMINAL)
(DEVIATION FROM NOMINAL)
0
1
±6%
±3%
±9%
±4.5%
May 1994
26
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
If SLEEP is ‘HIGH’ then the state of the SPEED signal will
be the state that it was in just before the SAA3323 went
into sleep. Thus if SPEED was HIGH just before sleep it
will stay HIGH during sleep. The same applies if it was
LOW or if it was in ‘high-Z’ state. Note that a reset of the
SAA3323 will take the SPEED signals out of ‘high-Z’ state.
Table 21 Timing values for Fig.23.
SYMBOL
TIME(1)
tW1
td1
th2
td2
td5
tcL
tcH
tsu1
th1
td3
th3
td4
T + tsu (L3MODE) + th (L3MODE); tw1 ≥ 200 ns
T + tsu (L3MODE) + th (L3CLK); td1 ≥ 200 ns
T + tsu (L3CLK) + th (L3MODE); th2 ≥ 200 ns
T + tsu (L3CLK) + td (L3DATA); td2 ≤ 250 ns
0 ≤ td5 ≤ 50 ns
Microcontroller connections
L3REF
T + tsu (L3CLK) + th (L3CLK); tcL ≥ 200 ns
T + tsu (L3CLK) + th (L3CLK); tcH ≥ 200 ns
T + tsu (L3DATA) + th (L3CLK); tsu1 ≤ 200 ns
T + tsu (L3CLK) + th (L3DATA); th1 ≤ 35 ns
2 × T + tsu (L3MODE) + td (L3DATA); td3 ≤ 250 ns
T + th (L3CLK) + td (L3DATA); th3 ≥ 50 ns
2 × T + tsu (L3CLK) + td (L3DATA); td4 ≤ 410 ns
3 × T + tsu (L3CLK) + td (L3DATA); td4 ≤ 575 ns
This active LOW output pin indicates the start of a time
segment, it goes LOW for 5.2 µs once every 42.66 ms
approximately and can be used for generating interrups for
the microcontroller. If a re-synchronization occurs then the
time between the occurrences van vary. This pin can be
connected directly to the interrupt input of the
microcontroller.
(2)
td4
L3CLK
This input pin is the clock line for the microcontroller
interface.
Notes
1. T is the period of the master clock on the chip.
2. td4 is the delay time between the last bit of a byte and
first bit of the next byte, if no ‘halt’ is used.
L3DATA
This input/output pin is the serial data line for the
microcontroller interface.
L3MODE
This input determines the type of transfer that is occurring
between the microcontroller and the SAA3323. If L3MODE
is LOW then a device address can be sent by the
microcontroller. If L3MODE is HIGH then a data transfer
may be occurring.
L3INT
This pin carries interrupts from the digital equalizer
module. It can also be programmed to reflect the state of
the AENV, LABEL and VIRGIN signals.
May 1994
27
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
t
W1
L3MODE
t
t
h2
d1
L3CLK
t
t
d5
d5
L3DATA
DRP to
microcontroller
a.
L3MODE
t
t
cH
cL
t
h2
L3CLK
t
t
d1
h1
L3DATA
microcontroller
to DRP
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
t
su1
b.
L3MODE
L3CLK
t
t
cH
cL
t
h2
t
t
h1
d1
L3DATA
microcontroller
to DRP
0
c.
t
su1
L3MODE
L3CLK
t
t
cH
cL
t
h2
t
t
t
d5
h3
d1
t
L3DATA
DRP to
microcontroller
0
t
d2
MGB398
t
d3
d4
d.
a. Halt mode.
b. Addressing mode.
c. Data mode (transfer from microcontroller to SAA3323).
d. Data mode (transfer from SAA3323 to microcontroller).
Fig.23 L3 interface timing and typical transfers (1).
28
May 1994
L3MODE
L3CLK
L3DATA
TFE3 WCMD
TFE3 RSTAT
TFE3 WCMD
LDSET0
TFE3 WDAT
SET0 DATA
TFE3 WCMD
LDSET1
TFE3 WDAT
SET1 DATA
a.
L3MODE
L3CLK
L3DATA
STATUS0
DATA
STATUS1
DATA
STATUS2
DATA
STATUS3
DATA
b.
L3MODE
L3CLK
L3DATA
LDBYCYNT
TFE3 WDAT
D8HEX
TFE3 WCMD
RDSYS
TFE3 RDAT
SYSINFO(8)
SYSINFO(9)
c.
L3MODE
L3CLK
L3DATA
TFE3 WCMD
TFE3 RSTAT
LDBYCYNT
TFE3 WDAT
D8HEX
TFE3 WCMD
RDSYS
TFE3 RSTAT
STATUS0
DATA
TFE3 RDAT
SYSINFO(8)
MGB399
L3MODE
L3CLK
L3DATA
STATUS0
DATA
TFE3 RDAT
SYSINFO(9)
d.
a. Write settings bytes 0 and 1 to TFE3 part of SAA3323.
b. Read all 4 status bytes from TFE part of SAA3323.
c. Read 2 SYSINFO bytes starting at byte 8 (in high-speed transfer part of program).
d. Read 2 SYSINFO bytes starting at byte 8 (in low-speed transfer part of program).
ahdnbok,uflapegwidt
Fig.24 L3 interface timing and typical transfers (2).
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SAA3323 test pins
PINO1
This output pin is connected directly to the PINO1 bit of the
TFE settings 0 register. The microcontroller can set or
reset this pin.
TEST0 TO TEST3
These input pins are for test only, do not connect.
AZCHK
PINO2 TO PINO5
This output pin indicates the occurrence of a tape channel
sync symbol on tape channels TCH0 and TCH7, the
distance between the pulses for the TCH0 and TCH7
channels gives a measure of the azimuth error between
the tape and head alignment. Figure 25 shows the typical
timing for this signal.
Depending upon the type and the size of system RAM
used, some or all of these Port expander output pins may
be available, (please see Section “RAM connections”
“A10 and A12 to A16” on interfacing to the RAM pins).
Supply pins
ERCOSTAT
VDD1 TO VDD6
This output pin can be connected to a symbol error rate
measurement system.
These are the supply pins, all of these pins must be
connected. We recommend that each power supply pin
pair (i.e. VDD1 to VSS1, VDD2 to VSS2, etc.) be decoupled
using a 22 nF capacitor as close as is physically possible
to the pins of the SAA3323.
Port expansion pins
PINI
This input pin is connected directly to the PINI bit in the
status byte 1, it can be read by the microcontroller, and
may be used for any CMOS level compatible input signals.
VSS1 TO VSS6
These are the supply ground pins, all of which must be
connected.
Duration of the one tape block
5.3 ms
AZCHK
(8 periods MCLK)
1.3 µs
MEA705
This is a measure of the azimuth error.
Nominal Inter Frame Gap (IFG) lasts 660 µs.
Fig.25 AZCHK timing.
May 1994
30
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
internally to all the supply ground pins (VSS1 to VSS6),
however it should always be connected externally.
VDD7
This is the supply pin for the output buffers to the data lines
of the system RAM. It should always be connected
externally. Decouple this pin with a 22 nF capacitor to the
Auxiliary envelope detection
INTMASK
VSS7 pin.
INTMASK is a interrupt mask register. This register sets
the mode of operation for the interrupt interface, and is
writable only.
VSS7
This is the ground supply pin for the output buffers of the
data lines of the system RAM. This pin is connected
Table 22 Interrupt mask register.
BIT
7
BP1
0
6
BP0
0
5
Vup(1)
0
4
AEup(2)
0
3
AEdn(3)
0
2
Lup(4)
0
1
Ldn(5)
0
0
ECZ(6)
0
Meaning
Default
Notes
1. Vup ≡ rising edge of VIRGIN interrupt.
2. AEup ≡ rising edge of AUX envelope interrupt.
3. AEdn ≡ falling edge of AUX envelope interrupt.
4. Lup ≡ rising edge of LABEL interrupt.
5. Ldn ≡ falling edge of LABEL interrupt.
6. ECZ ≡ AUX envelope counter has just reached zero interrupt.
The AUX envelope information is only valid when the
digital equalizer is in search mode and when the tape
speed is between the values of
3 to 48 × nominal tape speed. The timing relationships
between the AUX channel input signal, AENV, LAB and
VIR are shown in Figs 26 to 28. The delays td1 and td2 are
between 0.25 and 0.5tAUX (AUX envelope periods). The
delays td3, td4, td5 and td6 are between 2 and 6tAUX
(AUX envelope periods).
BP1 AND BP0 (BYPASS)
If any of the bypass bits are HIGH then the interrupts are
not passed on to the microcontroller, instead the level of
the corresponding signal is available an the interrupt pin.
Table 23 BP1 and BP0.
BP
EFFECT OF BYPASS
1
0
When using the digital equalizer in search mode first
program the digital equalizer to search mode, then
program the INTMASK register.
0
0
1
1
0
1
0
1
no bypass
LAB on L3INT pin; note 1
AENV on L3INT pin; note 2
VIR on L3INT pin; note 3
MASK
If the BP1 and BP0 bits are LOW then the mask bits take
effect. Any combination of the mask bits may be HIGH,
enabling the corresponding interrupts. The interrupt pin
L3INT is active LOW when used for interrupts and active
HIGH when used for bypassing. So if it is not in bypass
mode and at least one of the interrupts has occurred it will
go LOW and stays LOW until DEQ status byte 0 has been
read. Extra interrupts that occur after the first interrupt and
before the DEQ status byte 0 is read are seen in the status
register. Extra interrupts that occur after the status byte
Notes
1. LAB = LABEL (HIGH if a LABEL condition is detected
in the envelope of the AUX channel).
2. AENV = envelope of the AUX channel (1 bit binary).
3. VIR = VIRGIN (indicated by the total [continuous]
absence of signal on the AUX channel).
May 1994
31
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
has been read will generate a new interrupt. Interrupts that are already noted in the digital equalizer Status 0 are cleared
by reading it.
Table 24 Digital equalizer STATUS0.
BIT
7
6
5
4
3
2
1
0
Meaning
BKSW(1)
TEST
Vup(2)
AEup(3)
AEdn(4)
Lup(5)
Ldn(6)
ECZ(7)
Notes
1. BKSW (filter bank switched) indicates that the last main data coefficients sent to the digital equalizer have been
activated.
2. Vup indicates whether an interrupt caused by the rising edge of VIRGIN has occurred.
3. AEup indicates whether an interrupt caused by the rising edge of AUX envelope has occurred.
4. AEdn indicates whether an interrupt caused by the falling edge of AUX envelope has occurred
5. Lup indicates whether an interrupt caused by the rising edge of LABEL has occurred.
6. Ldn indicates whether an interrupt caused by the falling edge of LABEL has occurred.
7. ECZ indicates that the AUX envelope counter has reached zero.
t
AUX
RDMUX
AENV
MGB400
t
t
d2
d1
Fig.26 AUX channel envelope to AENV delays.
t
AUX
AENV
(internal)
LAB
MGB401
t
t
d4
d3
Fig.27 AENV to LAB delays.
32
May 1994
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
t
AUX
AENV
(internal)
Vir
MGB402
t
t
d6
d5
Fig.28 AENV to VIR delays.
Table 25 Digital equalizer STATUS1.
BIT
7
6
5
4
3
2
1
0
Meaning
−
−
−
−
−
VIR(1)
AENV(2)
LAB(3)
Notes
1. VIR gives the state of the VIRGIN signal.
2. AENV represents the state of the AENV signal.
3. LAB gives the state of the LAB signal.
AUX envelope count (AECNT) register
This 16 bit register is used for loading the AUX envelope
counter and for reading the state of that counter, it is
therefore readable and writable as 2 bytes. Least
Significant Byte first.
Table 26 AECNT register.
AECNT
BIT
LEAST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Meaning
27
26
25
24
23
22
21
20 215 214 213 212 211 210 29
28
Search speed (SSPD) register
Search speed = 2SR
×
× normal speed
51.2
-----------
SV
Table 27 Search speed register.
BIT
7
6
5
4
3
2
1
0
Meaning
SVF(1)
SV4(2)
SV3(2)
SV2(2)
SV1(2)
SV0(2)
SR1(3)
SR0(3)
Notes
1. SVF speed validation flag, if HIGH then the search speed measurement is invalid.
2. SV4 to SV0 search speed value.
3. SR1 and SR0 search speed range.
May 1994
33
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
ANAEYE register
Table 28 ANAEYE register analog eye pattern selection register.
BIT
Meaning
7
−
0
6
−
0
5
−
0
4
AEN(1)
0
3
2
1
0
ACHN3(2) ACHN2(2) ACHN1(2) ACHN0(2)
Default
0
0
0
0
Notes
1. AEN analog eye pattern output enable. If this bit is LOW the Digital-to-Analog Converter (DAC) is switched off and
the output is HIGH.
2. ACHN3 to ACHN0 select channel for analog eye output.
Table 29 ACHN3 to ACHN0 channel selections for analog eye output.
ACHN
CHANNEL ON ANAEYE
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
AUX
T1sel register
Table 30 T1SEL register CHTST1 pin selection register.
BIT
Meaning
Default
7
6
5
4
3
2
1
0
−
T1F2
0
T1F1
0
T1F0
0
T1C3
0
T1C2
0
T1C1
0
T1C0
0
0
Table 31 T1C3 to T1C0 CHTST1 pin channel selections.
T1C
CHANNEL ON CHTST1
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
AUX
May 1994
34
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 32 T1F2 to T1F0 CHTST1 pin function selections.
T1F
FUNCTION OF CHTST1 PIN
2
1
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
off; logic 0
digital eye pattern
sliced data
bit clock
clock extraction frequency
The digital eye pattern is in 8 bits two’s complement notation, the sliced data and the bit clock give the current binary
state of the corresponding signals, and the clock extraction frequency output is in 8 bits offset binary format. The timing
diagrams for the digital eye pattern output and the clock extraction frequency output are shown in Fig.29.
T2sel register
Table 33 T2SEL register CHTST2 pin selection register.
BIT
7
6
5
4
3
2
1
0
Meaning
Default
−
T2F2
0
T2F1
0
T2F0
0
T2C3
0
T2C2
0
T2C1
0
T2C0
0
0
Table 34 T2C3 to T2C0 CHTST2 pin channel selections.
Table 35 T2F2 to T2F0 CHTST2 pin function selections.
T2C
T2F
CHANNEL ON
FUNCTION OF CHTST2 PIN
CHTST2
3
2
1
0
2
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
off; logic 0
digital eye pattern
sliced data
2
3
bit clock
4
clock extraction frequency
5
6
7
AUX
May 1994
35
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
RDSYNC
TCLOCK
MCLK
LSB
MSB
7
0
1
2
3
4
5
6
0
1
2
3
CHTST
MGB403
Fig.29 CHTST1 and CHTST2 output timing.
Table 36 DEQSET digital equalizer settings.
BIT
7
6
5
4
3
2
1
0
Meaning
Default
−
−
−
−
−
ACup(1)
0
DM1
0
DM0
0
0
0
0
0
0
Note
1. ACup is the AUX envelope counter direction is up. This setting caused the AUX envelope counter increment or to
decrement by 1 every rising edge of the AUX envelope signal AENV.
DM1 and DM0
Table 37 DM1 and DM0 digital equalizer mode of
operation.
DM
MODE OF OPERATION OF
DIGITAL EQUALIZER
1
0
0
1
1
0
0
1
0
1
normal(1)
search(2)
off(3)
off(3)
Notes
1. In normal mode the main data channels and the AUX
channel are processed (equalized), the AUX channel
envelope information is not processed.
2. In search mode only the AUX channel is processed by
the digital equalizer.
3. Off means that the digital equalizer is put to sleep (low
power), this can be used for example in portable
recording equipment. RDSYNC is HIGH if off mode.
Also note that the other digital equalizer registers are
not addressable while the digital equalizer is in off
mode.
May 1994
36
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
CLKSET
Table 38 CLKSET clock extraction settings.
BIT
7
LEAE(1)
1
6
FR1
0
5
FR0
0
4
GNOR
1
3
GE1
1
2
GE0
0
1
RD1
1
0
RD0
0
Meaning
Default
Note
1. LEAE (leakage enable): this setting enables a leakage function in the PLL clock extraction loop filter. This gives a
slightly improved performance with high SER tapes at the cost of a slight decrease in dynamic performance. For
home (static) applications program this bit to logic 1 and for portable applications to logic 0.
Table 39 FR1 and FR0 clock extraction frequency range
Table 40 GNOR gain in normal frequency range mode of
control.
clock extraction.
FR
GNOR
EFFECT ON GAIN IN NORMAL RANGE
gain 2; for portable (mobile) applications
gain 1; for home (static) applications
EFFECT ON PLL FREQUENCY
LOOP
0
1
1
0
0
0
1
1
0
1
0
1
range ±8%
range ±16%
range ±22%
range ±28%
Table 41 GE1 and GE0 gain in extended frequency
range mode of clock extraction.
GE
EFFECT ON PLL GAIN IN EXTENDED
RANGE
1
0
Note that in the (FR = 0) range the clock extraction stays
in its normal range only, hence it does not enter the
extended range.
0
0
1
1
0
1
0
1
gain 2
gain 3
Figure 30 shows the lock characteristic of the clock
extraction PLL.
gain 4
gain 5; do not use
MGB404
30
28% frequency loop range limitation
22% frequency loop range limitation
bit rate
deviation
(%)
(3)
20
16% frequency loop range limitation
8% frequency loop range limitation
(2)
(1)
10
0
10
2
3
4
(1) Gain 4.
(2) Gain 3.
(3) Gain 2.
10
10
f (Hz)
Fig.30 Clock extraction PLL lock characteristic.
37
May 1994
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
The 128 bytes in each tape frame contain SYSINFO. The
SYSINFO bytes can for convenience, be considered as
being grouped into 4 SYSINFO blocks with:
RD1 and RD0 return delay
This is the delay before returning to normal mode after
being in ‘extended range mode’ (i.e. the number of
consecutive channel clock bit periods where the bit clock
frequency falls within the normal range before the clock
extraction returns to normal frequency mode).
SYSBLK0 → SI0 to SI31, SYSBLK1 → SI31 to SI63, etc.
In modes DPAP and DRAR SYSINFO transfers may occur
in two ways:
1. 4 blocks of 36 bytes, one block being transferred to the
SAA3323 in each time segment.
Table 42 RD1 and RD0 return delay.
2. 1 block of 128 bytes being transferred in time
segment 1.
RD
DELAY IN BITS TO RETURN TO
NORMAL MODE
1
0
0
1
1
0
0
1
0
1
In mode DRAR SYSINFO must be transferred as 4 blocks
of 32 bytes, one block in each segment.
64
128
256
512
Figures 31 to 34 show the offsets between the SYSINFO
and AUX and the time segment counter, for the various
modes of operation of the SAA3323.
SYSINFO and AUX data offsets in the SAA3323
AUX data consists of 4 blocks of 36 bytes, one block being
transferred in each (n) time segment.
Table 43 Block offsets with respect to time segment.
MODE
DESCRIPTION
DPAP
SYSBLK = (SNUM + 3) MOD4; or read all 4 SYSINFO blocks when SNUM = logic 0; if AUX and
main were recorded simultaneously then AUXBLK = (SNUM + 1) MOD4; else read and interpret
1 AUX block in each time segment.
DRAR
DPAR
SYSBLK = SNUM; AUXBLK = (SNUM + 1) MOD4
SYSBLK = (SNUM + 3) MOD4; or read all 4 SYSINFO blocks when SNUM = logic 0
May 1994
38
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SNUM
0 1
2
3
1
3
0
2
0
1
3
1
2
0
2
3
1
3
0
2
0
1
3
1
2
0
2
3
1
3
0
2
0
1
3
1
2
0
2
3
AUX BLK
SYS BLK
SYS BLK
1
2
0
3
1
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
*
AUX, MAIN
DATA INPUT
FROM TAPE
0 1
2
3
0
1
2
3
0
1
2
3
0
1
2
MLB413
Fig.31 SYSINFO and AUX block delays in DPAP mode; audio and AUX simultaneously recorded.
SNUM
0 1
2
3
0
1
2
3
0
1
2
3
0
1
0
2
DEPENDS ON PHASE OF AUX WRT MAIN DATA CHANNELS
AUX BLK
SYS BLK
SYS BLK
3
0
1
2
3
0
1
2
3
0
1
2
3
1
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
*
AUX, MAIN
DATA INPUT
FROM TAPE
0 1
2
3
0
1
2
3
0
1
2
3
0
1
2
MLB414
Fig.32 SYSINFO and AUX block delays in DPAP mode; audio and AUX separately recorded.
39
May 1994
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SNUM
0
1
0
1
2
1
2
3
2
3
0
3
0
1
0
1
2
1
2
3
2
3
0
3
0
1
0
1
2
1
2
3
2
3
0
3
0
1
0
1
2
1
2
3
2
AUX BLK
SYS BLK
AUX, MAIN
DATA OUTPUT
TO TAPE
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
MBG405
Fig.33 SYSINFO and AUX block delays in DRAR mode.
SNUM
0 1
2
3
1
3
0
2
0
1
3
1
2
0
2
3
1
3
0
2
0
1
3
1
2
0
2
3
1
3
0
2
0
1
3
1
2
0
2
3
1
AUX BLK
SYS BLK
SYS BLK
1
2
0
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
*
MAIN DATA
INPUT
FROM TAPE
0 1
2
1
3
2
0
3
1
0
2
1
3
2
0
3
1
0
2
1
3
2
0
3
1
0
2
AUX OUTPUT
TO TAPE
0
1
1
MLB416
Fig.34 SYSINFO and AUX block delays in DPAR mode.
40
May 1994
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
the scratch pad RAM may be written and read in 8 bit or
12 bit units.
Scratch pad RAM
The SAA3323 provides the microcontroller with a scratch
pad RAM that the microcontroller can use for whatever it
likes. The size of the scratch pad depends upon the size
and type of RAM used with the SAA3323. The locations in
The RAM may be viewed as having up to 4 quarters, the
availability of these quarters for the scratch pad RAM is
given in Table 44.
Table 44 Availability of RAM quarters for the scratch pad RAM.
RTYPE
TYPE OF RAM USED
AVAILABLE RAM QUARTERS YZ(1)
1
0
0
0
0
1
1
1
0
0
1
0
1
1
DRAM 64K × 4
00
DRAM 256K × 4
00, 01, 10 and 11
SRAM 32K × 8 fast
SRAM 128K × 8 fast
SRAM (2×) 32K × 8 slow
SRAM 128K × 8 slow
00
00, 01, 10 and 11
00
00 and 10
Note
1. In RAM quarter YZ = 00, the scratch pad is arranged as 6 pages, where each page consists of 7 columns × 64 rows.
The pages are numbered 0 to 5, the columns 1 to 7 and the rows 0 to 63.
This gives a total of (6 × 7 × 64) 2688 locations.
In each of the RAM quarters YZ = 01, 10 and 11 the scratch pad is arranged as 6 pages where each page consists
of 8 columns × 448 rows. The pages are numbered 0 to 5, the columns 0 to 7 and the rows 0 to 447. This gives then
a total of (6 × 8 × 448) 21504 locations per RAM quarter YZ.
During communication with the scratch pad RAM, the
RAM quarter YZ is chosen when sending the RDDRAC,
RDWDRAC, WRDRAC or WRWDRAC commands to the
TFE module.
The 8 bit transfers are initiated by the WRDRAC and
RDDRAC commands, these transfers are each 1 byte per
memory location, therefore the byte counter will increment
after each byte transfer.
Use of the scratch pad RAM outside the specified ranges
is not allowed and it may upset the operation of the
SAA3323.
The 12 bit transfers are initiated by the WRDRAC and
RDDRAC commands, these transfers are each 2 bytes
per memory location. The first byte contains the 4 Most
Significant Bits (MSBs) of the memory location in its
4 Least Significant Bits (LSBs) positions. The other bit
positions being ‘don’t care’. The second byte contains the
8 LSBs of the memory location. The byte counter is
incremented after the transfer of the second byte.
As with SYSINFO and AUX transfers can occur at high
speed at all times except the second half of time
segment 0, that is when the status bit SLOWTFR is HIGH.
When SLOWTFR is HIGH the microcontroller must poll the
status bit RFBT to investigate when a transfer can occur.
The RACCNT and BYTCNT registers are used for
addressing the scratch pad.
Two addressing modes are available for the scratch pad,
namely random access and auto-increment. For random
access mode the address of each location is sent by the
microcontroller to the SAA3323 before each location
transfer. For auto-increment mode the address of the first
location is sent by the microcontroller before the first
location transfer, auto-incrementing of the row occurs then
for all transfers until the end of the column.
For RAM quarter YZ = 00 the mapping of the scratch pad
RAM address onto the RACCNT and BYTCNT registers is
shown in Table 45.
May 1994
41
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 45 Mapping of scratch pad RAM address for RAM quarter YZ = 00.
REGISTER
RACCNT
BYTCNT
BIT
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Value
P2
P1
P0
C2
C1
C0
1
1
R6
R5
R4
R3
R2
R1
R0
For The other three quarters of the RAM the mapping of the scratch pad RAM address onto the RACCNT and BYTCNT
registers is shown in Table 46.
Table 46 Mapping of scratch pad RAM address for RAM quarter YZ = 01, 10 and 11.
REGISTER
RACCNT
BYTCNT
BIT
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Value
P2
P1
P0
C2
C1
C0
R8
R7
R6
R5
R4
R3
R2
R1
R0
Mode changes
Mode change DRAR to DPAP
This mode change occurs at the first end of time
segment 0 after the TFE module receives the new setting.
Writing of Main and AUX data stops immediately after the
mode change.The time segment jumps back to logic 0,
URDA goes HIGH and stays HIGH for 5 time segments
(i.e. approximately 213.3 ms) after which it goes LOW, as
shown in Fig.37.
The possible mode changes for the TFE are shown in
Table 47.
Table 47 Mode changes.
NEW MODE
CURRENT
MODE
DPAP
DRAR
DPAR
DPAP
DRAR
DPAR
−
yes
−
yes
no
−
Mode change DPAR to DPAP
yes
yes
This mode change occurs at the first end of time
segment 0 after the TFE module receives the new setting.
The writing of AUX data to tape stops immediately after the
mode change. The first AUX read from tape can be
expected during the following time segment 0 or 1 (i.e.
approximately 128 to 170.67 ms after the mode change),
as shown in Fig.38.
no
TIMING FOR SAA3323 MODE CHANGES
Mode change DPAP to DRAR
This mode change occurs at the end of the time segment
in which the TFE module receives the new settings.
Writing of the first Main and AUX data to tape starts at the
start of the time segment 1 which occurs 2 ‘end of time
segment 3’ s after the mode change. The delay to writing
to tape is approximately 222 ms, as shown in Fig.35.
Mode change DPAP to search
This mode change occurs almost instantaneously,
program the digital equalizer module in SAA3323 to go to
search mode, then program the interrupt mask register to
select the required type of interrupt.
If ‘seamless appending’ is required the new settings
should be sent to the TFE module during time segment 2.
Mode change search to DPAP
Mode change DPAP to DPAR
This mode change occurs almost instantaneously,
program the interrupt mask register to disable interrupts
program the digital equalizer module of SAA3323 to go to
normal mode. A re-synchronization will most likely occur
when as result of the data being read from tape, thus
causing URDA to go HIGH.
This mode change occurs at the first end of time
segment 2 after the TFE module receives the new
settings. Output of AUX to tape begins at the start of the
following time segment 1, (i.e. approximately 85.3 ms after
the mode change), as shown in Fig.36.
May 1994
42
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
andbook, halfpage
handbook, halfpage
SNUM
0
1
2 3 0
1
2
3
0
1
2
SNUM
1
2
3
0
1
2
3
0
1
2
DPAP
DRAR
DRAR
≈ 222 ms
MODE
MODE
DPAP
DPAR
85.3 ms
DPAR
NEW MODE
NEW MODE
≈
AUXILIARY, MAIN
TAPE OUT
AUXILIARY
TAPE OUT
MEA707 - 2
MEA708 - 2
Fig.35 Mode change to DRAR.
Fig.36 Mode change to DPAR.
handbook, halfpage
handbook, halfpage
SNUM
MODE
1
2
3
0
1
2
3
0
1
2
SNUM
1
2
3
0
0
1
2
3
0
1
DPAR
DPAP
DPAP
MODE
DRAR
DPAP
DPAP
NEW MODE
NEW MODE
AUXILIARY
TAPE OUT
URDA
≈
213.3 ms
≈
128 ms
MEA709 - 1
AUXILIARY
TO
MICROCONTROLLER
≈
170.66 ms
MEA710 - 2
Fig.37 Mode change from DRAR.
Fig.38 Mode change from DPAR.
May 1994
43
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
3.6
UNIT
VDD
VI
2.7
V
V
input voltage
note 1
−0.5
−10
tbf
VDD + 0.5
+10
II
input current
mA
V
VO
IO
output voltage
tbf
output current
−20
−
+20
mA
mA
mA
mW
°C
°C
V
IDD
ISS
Ptot
Tstg
supply current
100
supply current
−100
−
−
total power dissipation
storage temperature
operating ambient temperature
electrostatic handling
electrostatic handling
500
−55
−40
−2000
−200
+150
+85
Tamb
Ves1
Ves2
note 2
note 3
+2000
+200
V
Notes
1. The input voltage must not exceed maximum supply voltage unless otherwise specified.
2. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
3. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
DC CHARACTERISTICS
VDD = 2.7 to 3.6 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
IDD
supply voltage
supply current
2.7
tbf
3.6
V
digital plus analog;
see Fig.39
−
28.1
−
mA
inputs with internal
−
−
100
µA
pull-down to VSS
;
all other inputs to VSS
or VDD
Inputs CLK24, L3CLK, L3MODE, PINI, SLEEP and SBMCLK
VIL
VIH
II
LOW level input voltage
HIGH level input voltage
input current
−
−
−
−
0.3VDD
−
V
0.7VDD
V
VI = 0 V to VDD
;
−10
+10
µA
Tamb = 25 °C
Inputs TEST0, TEST1 and TEST2
VIL
VIH
II
LOW level input voltage
HIGH level input voltage
input current
−
−
−
−
0.3VDD
−
V
0.7VDD
V
VI = VDD; Tamb = 25 °C 25
400
µA
May 1994
44
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input RESET
VtLH
VtHL
Vhys
positive-going threshold
negative-going threshold
−
−
−
0.8VDD
V
V
V
0.2VDD
−
−
hysteresis (VtLH to VtHL
)
−
0.3VDD
Outputs AZCHK, CHTST1, CHTST2, ERCOSTAT, L3INT, L3REF, MCLK, PINO3, RDSYNC, SBDIR, SBEF, URDA,
TCLOCK and WDATA
VOH
VOL
HIGH level output voltage
LOW level output voltage
IO = 1 mA
V
DD − 0.5
DD − 0.5
DD − 0.5
−
−
−
V
V
IO = −1 mA
−
0.4
Outputs A0 to A8, A9/CAS, A10/RAS, OEN and WEN
VOH
VOL
HIGH level output voltage
LOW level output voltage
IO = 2 mA
V
−
−
−
V
V
IO = −2 mA
−
0.4
Outputs SPEED and PINO2
VOH
VOL
IOZ
HIGH level output voltage
IO = 1 mA
V
−
−
−
−
V
LOW level output voltage
3-state leakage current
IO = −1 mA
−
0.4
+10
V
VI = 0 V to VDD
;
−10
µA
Tamb = 25 °C
Inputs/outputs SBCL, SBDA and SBWS
VOH
VOL
VIL
HIGH level output voltage
LOW level output voltage
LOW level input voltage
HIGH level input voltage
3-state leakage current
IO = 1 mA
V
DD − 0.5
−
−
−
−
−
−
V
IO = −1 mA
−
0.4
0.3VDD
−
V
outputs in 3-state
outputs in 3-state
−
V
VIH
IOZ
0.7VDD
−10
V
VI = 0 V to VDD
;
+10
µA
Tamb = 25 °C
Inputs/outputs A11 to A16 and L3DATA
VOH
VOL
VIL
HIGH level output voltage
LOW level output voltage
LOW level input voltage
HIGH level input voltage
3-state leakage current
IO = 2 mA
V
−
−
DD − 0.5
−
−
−
−
−
−
V
IO = −2 mA
0.4
0.3VDD
−
V
outputs in 3-state
outputs in 3-state
V
VIH
IOZ
0.7VDD
V
VI = 0 V to VDD
;
−10
+10
µA
Tamb = 25 °C
Inputs/outputs D0 to D7
VOH
VOL
VIL
HIGH level output voltage
IO = 4 mA
V
−
−
2
DD − 0.5
−
−
−
−
−
−
V
LOW level output voltage
LOW level input voltage
HIGH level input voltage
3-state leakage current
IO = −4 mA
0.4
0.8
−
V
outputs in 3-state
outputs in 3-state
V
VIH
IOZ
V
VI = 0 V to VDD
;
−10
+10
µA
Tamb = 25 °C
May 1994
45
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Average current consumption
MLB778
60
I
DD
(mA)
max
40
typ
min
20
0
2.0
2.5
3.0
3.5
4.0
V
(V)
DD
Fig.39 Average current consumption.
AC CHARACTERISTICS
VDD = 2.7 to 3.6 V; Tamb = −40 to +85 °C; CL = 10 pF on all outputs; see Fig.40; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock inputs
CI
input capacitance
−
−
10
pF
CLK24
fCLK24
t24L
clock frequency
24
12
12
24.576
25
−
MHz
ns
pulse width LOW
pulse width HIGH
−
−
t24H
−
ns
SBMCLK
fSBMCLK
tSCL
clock frequency
pulse width LOW
pulse width HIGH
6.144
12.5
−
MHz
ns
30
30
−
−
tSCH
−
ns
May 1994
46
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock output MCLK
CL
td
load capacitance
−
−
−
20
pF
delay time from SLEEP HIGH to
SLEEP active
20
−
ns
fMCLK
tMCL
tMCH
tpd
clock frequency
6.144
6.25
−
MHz
ns
MCLK pulse width LOW
MCLK pulse width HIGH
50
50
−
−
−
−
−
ns
propagation delay time from rising
edge of CLK24
65
ns
Inputs
CI
input capacitance
−
−
10
pF
L3CLK, L3MODE AND RESET
tsu
th
set-up time to rising edge of MCLK
35
0
−
−
−
−
ns
ns
hold time from rising edge of MCLK
PINI
tsu
set-up time to rising edge of MCLK
hold time from rising edge of MCLK
60
0
−
−
−
−
ns
ns
th
Outputs
CL
load capacitance
−
−
−
−
20
50
pF
ns
A0 TO A8
tpd
propagation delay time from falling
edge of CLK24
A9/CAS, A10/RAS AND OEN
tpd propagation delay time from falling
−
−
−
50
ns
ns
edge of CLK24
td
delay time from SLEEP HIGH to
SLEEP active
20
−
WEN
tpd
propagation delay time
from falling edge of CLK24
−
−
−
−
50
50
ns
ns
from falling edge of WEN to rising long write pulse
edge of CLK24
mode
td
delay time from SLEEP HIGH to
SLEEP active
−
20
−
ns
ns
ns
AZCHK, CHTST1, CHTST2, L3INT, PINO3, RDSYNC, SBEF AND WDATA
tpd
propagation delay time from rising
edge of MCLK
−
−
−
45
55
ERCOSTAT, L3REF, SBDIR, SPEED, PINO2, URDA AND TCLOK
tpd
propagation delay time from rising
edge of MCLK
−
May 1994
47
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Inputs/outputs
CI
input capacitance
load capacitance
−
−
−
−
10
20
pF
CL
pF
A11 TO A16
td
delay time from SLEEP HIGH to
SLEEP active
−
−
25
−
ns
ns
tpd
propagation delay time from falling
edge of CLK24
−
55
D0 TO D3
td
delay time from SLEEP HIGH to
SLEEP active
−
20
−
ns
tsu
th
set-up time to falling edge of CLK24
hold time from falling edge of CLK24
propagation delay time
5
−
−
−
−
ns
ns
15
tpd
from falling edge of CLK24
−
−
−
50
50
ns
ns
from rising edge of CLK24
early write mode −
D4 TO D7
td
delay time from SLEEP HIGH to
SLEEP active
−
25
−
ns
tsu
th
set-up time to falling edge of CLK24
hold time from falling edge of CLK24
propagation delay time
5
−
−
−
−
ns
ns
15
tpd
from falling edge of CLK24
−
−
−
50
50
ns
ns
from rising edge of CLK24
early write mode −
L3DATA
td
delay time from SLEEP HIGH to
SLEEP active
−
25
−
ns
tsu
th
set-up time to rising edge of MCLK
hold time from rising edge of MCLK
propagation delay time
35
−
−
−
−
ns
ns
0
tpd
from rising edge of MCLK
from L3MODE
−
−
−
−
50
45
ns
ns
SBCL AND SBWS
td
delay time from SLEEP HIGH to
−
25
−
ns
SLEEP active
tsu
th
set-up time to rising edge of MCLK
hold time from rising edge of MCLK
propagation delay time
40
0
−
−
−
−
ns
ns
tpd
from rising edge of SBMCLK
−
−
−
−
60
55
ns
ns
from rising edge of MCLK
(3-state control)
May 1994
48
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SBDA
td
delay time from SLEEP HIGH to
SLEEP active
−
25
−
ns
tsu
th
set-up time to rising edge of MCLK
hold time from rising edge of MCLK
35
0
−
−
−
−
ns
ns
ns
−
tpd
propagation delay time from rising
edge of MCLK
−
55
t
24H
CLK24
V
IH
IL
V
t
t
su1
h1
t
t
24L
V
V
IH
IL
IN1
t
d2
d1
V
V
OH
OL
OUT1
MCLK
IN2
t
t
pd
d4
t
MCL
V
V
OH
OL
t
MCH
t
t
h2
su2
V
V
IH
IL
t
d
V
V
OH
OL
OUT2
SBMCLK
OUT3
t
SCL
V
V
IH
IL
t
SCH
t
d5
V
V
OH
OL
MGB407
Fig.40 Timing for AC characteristics.
May 1994
49
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
ADC CHARACTERISTICS
VDD = 2.7 to 3.6 V; Tamb = −40 to +85 °C; CL = 10 pF on TCLOCK output; see Fig.41; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
bits
AC RDMUX ADC resolution
positive reference voltage
negative reference voltage
Vref(p) to Vref(n)
−
8
−
−
−
−
V
−
−
Vref(p)
Vref(n)
∆Vref
Zi
−
DD − 0.5
V
0
V
2.0
V
input impedance
Vref(p) to Vref(n)
ref(n) to VSS
700
−
1200
1500
−
Ω
V
650
−
Ω
CI
input capacitance (RDMUX)
input current
−
15
pF
µA
LSB
dB
II
−
−
90
DNL
differential non-linearity
−
−
±0.99
−
S/(THD+N) signal-to-total harmonic
distortion plus noise ratio
−20 dB (FS);
100 to 500 kHz
24
−
Timing
Tcy
td1
cycle time of CLK24
40
−
−
−
ns
ns
TCLOCK delay time from
rising edge of CLK24
CL = 10 pF
−
80
tsu
th
RDMUX set-up time to falling Zsource < 150 Ω
edge of CLK24
60
40
−
−
−
−
ns
ns
RDMUX hold time from falling
edge of CLK24
t
d1
CLK24
V
V
IH
IL
t
T
cy
d2
V
V
OH
OL
TCLOCK
CLK ADC
RDMUX
t
d3
t
h
t
su
SAMPLE(1)
t
d4
V
V
IH
IL
TESTBUS DATA SAMPLE(1-3)
DATA SAMPLE(1-2)
MGB408
Fig.41 ADC timing.
May 1994
50
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
DAC CHARACTERISTICS
VDD = 2.7 to 3.6 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
bits
DIGEYE/ANAEYE resolution
ANAEYE output voltage
−
−
6
−
Vo
ZL > 1 MΩ
(VDD − 1.1) −
V
to VDD
May 1994
51
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
PACKAGE OUTLINES
seating plane
S
0.1
S
14.3
13.7
80
61
B
1.45
1.05
(4x)
60
1
pin 1 index
0.5
14.3
13.7
12.1
11.9
0.25
0.13
20
41
40
21
0.25
0.13
1.45
1.05
0.5
0.15 M
A
(4x)
X
12.1
11.9
A
0.70
0.58
1.5
1.3
1.7
1.5
0.18
0.12
0.16
0.04
o
0.7
0.3
0 to 4
detail X
MBB947
Dimensions in mm.
Fig.42 Plastic thin quad flatpack; 80 leads; body 12 × 12 × 1.4 mm (SOT315-1; TQFP80).
May 1994
52
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
seating plane
S
S
0.10
18.2
17.6
B
80
65
64
1
1.0
0.6
pin 1 index
(4x)
0.8
20.1 24.2
19.9 23.6
0.45
0.30
41
24
25
40
0.45
0.30
1.2
0.8
0.20 M
A
(4x)
X
0.8
14.1
13.9
A
1.4
1.2
2.90
2.65
3.2
2.7
0.25
0.05
0.25
0.14
1.0
0.6
o
0 to 7
detail X
MSA394 - 1
Dimensions in mm.
Fig.43 Plastic quad flatpack; 80 leads (lead length 1.95 mm); body 14 × 20 × 2.7 mm; high stand-off
height (SOT318-2; QFP80).
May 1994
53
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
SOLDERING
Plastic quad flatpacks
BY WAVE
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
May 1994
54
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.
May 1994
55
Philips Semiconductors – a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)
Norway: Box 1, Manglerud 0612, OSLO,
BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367
Tel. (022)74 8000, Fax. (022)74 8341
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. (02)805 4455, Fax. (02)805 4466
Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,
Pakistan: Philips Electrical Industries of Pakistan Ltd.,
Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546.
Tel. (01)60 101-1236, Fax. (01)60 101-1211
Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474
Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,
Tel. (31)40 783 749, Fax. (31)40 788 399
Brazil: Rua do Rocio 220 - 5th floor, Suite 51,
CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Portugal: PHILIPS PORTUGUESA, S.A.,
Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. (01)14163160/4163333, Fax. (01)14163174/4163366.
Tel. (011)821-2327, Fax. (011)829-1849
Canada: INTEGRATED CIRCUITS:
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. (800)234-7381, Fax. (708)296-8556
DISCRETE SEMICONDUCTORS: 601 Milner Ave,
SCARBOROUGH, ONTARIO, M1B 1M8,
Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477
Tel. (65)350 2000, Fax. (65)251 6500
South Africa: S.A. PHILIPS Pty Ltd., Components Division,
195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. (011)470-5911, Fax. (011)470-5494.
Spain: Balmes 22, 08007 BARCELONA,
Tel. (03)301 6312, Fax. (03)301 42 43
Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,
Tel. (0)8-632 2000, Fax. (0)8-632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Chile: Av. Santa Maria 0760, SANTIAGO,
Tel. (02)773 816, Fax. (02)777 6730
Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,
77621 BOGOTA, Tel. (571)249 7624/(571)217 4609,
Fax. (571)217 4549
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. (032)88 2636, Fax. (031)57 1949
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. (01)488 2211, Fax. (01)481 77 30
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West
Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382.
Tel. (9)0-50261, Fax. (9)0-520971
France: 4 Rue du Port-aux-Vins, BP317,
92156 SURESNES Cedex,
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. (662)398-0141, Fax. (662)398-3319.
Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. (01)4099 6161, Fax. (01)4099 6427
Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H.,
P.O. Box 10 63 23, 20043 HAMBURG,
Tel. (040)3296-0, Fax. (040)3296 213.
Greece: No. 15, 25th March Street, GR 17778 TAVROS,
Tel. (0212)279 2770, Fax. (0212)269 3094
Tel. (01)4894 339/4894 911, Fax. (01)4814 240
United Kingdom: Philips Semiconductors Limited, P.O. Box 65,
Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. (071)436 41 44, Fax. (071)323 03 42
Hong Kong: PHILIPS HONG KONG Ltd., Components Div.,
6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T.,
Tel. (852)424 5121, Fax. (852)428 6729
India: Philips INDIA Ltd, Components Dept,
Shivsagar Estate, A Block ,
Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. (022)4938 541, Fax. (022)4938 722
Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,
P.O. Box 4252, JAKARTA 12950,
United States:INTEGRATED CIRCUITS:
811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. (800)234-7381, Fax. (708)296-8556
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,
P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300
Uruguay: Coronel Mora 433, MONTEVIDEO,
Tel. (021)5201 122, Fax. (021)5205 189
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
Tel. (01)640 000, Fax. (01)640 200
Italy: PHILIPS COMPONENTS S.r.l.,
Viale F. Testi, 327, 20162 MILANO,
Tel. (02)6752.3302, Fax. (02)6752 3300.
Japan: Philips Bldg 13-37, Kohnan2-chome, Minato-ku, TOKYO 108,
SCD31
© Philips Electronics N.V. 1994
Tel. (03)3740 5028, Fax. (03)3740 0580
Korea: (Republic of) Philips House, 260-199 Itaewon-dong,
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,
SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880
Mexico: Philips Components, 5900 Gateway East, Suite 200,
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556
Printed in The Netherlands
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB
Tel. (040)783749, Fax. (040)788399
513061/1500/01/pp56
Date of release: May 1994
9397 732 30011
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. (09)849-4160, Fax. (09)849-7811
Document order number:
Philips Semiconductors
相关型号：
©2020 ICPDF网 联系我们和版权申明