SAA5291PS/NNN [NXP]
IC 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP52, 0.600 INCH, PLASTIC, SDIP-52, Microcontroller;
| 型号： | SAA5291PS/NNN |
| 厂家： | 
NXP |
| 描述： | IC 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP52, 0.600 INCH, PLASTIC, SDIP-52, Microcontroller 微控制器 光电二极管 |
| 文件： | 总72页 (文件大小：498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA5x9x family
Economy teletext and TV
microcontrollers
1998 Dec 14
Preliminary specification
Supersedes data of 1997 Jul 07
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
CONTENTS
9.3
East/West selection
9.4
9.5
National option characters
The twist attribute
1
FEATURES
9.6
9.7
9.8
9.9
Language group identification
525-line operation
On-Screen Display characters
Control characters
Quadruple width display (SAA549x)
Page attributes
Display modes
On-Screen Display boxes
Screen colour
Redefinable colours (SAA549x)
Cursor
Other display features
Display timing
Horizontal timing
Vertical timing
1.1
1.2
1.3
1.4
1.5
1.6
General
Microcontroller
Teletext acquisition
Teletext Display
Additional features of SAA529xA devices
Additional features of SAA549x devices
9.10
9.11
9.12
9.13
9.14
9.15
9.16
9.17
9.18
9.19
9.20
9.21
9.22
9.23
2
GENERAL DESCRIPTION
Device masking history
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
2.1
3
4
5
6
PINNING INFORMATION
6.1
6.2
Pinning
Pin description
Display position
Clock generator
Reset signal
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
Microcontroller
80C51 features not supported
Additional features
10
CHARACTER SETS
10.1
10.2
10.3
10.4
10.5
10.6
10.7
Pan-European
Cyrillic
Greek/Turkish
Arabic/English/French
Thai
Microcontroller interfacing
8
TELETEXT DECODER
8.1
8.2
8.3
8.4
8.5
8.6
Data slicer
Acquisition timing
Teletext acquisition
Rolling headers and time
Error checking
Memory organisation of SAA5296/7,
SAA5296/7A and SAA5496/7
Inventory page
Memory organisation of SAA5290, SAA5290A,
SAA5291, SAA5291A and SAA5491
Packet 26 processing
Arabic/Hebrew
Iranian
11
12
13
LIMITING VALUES
CHARACTERISTICS
CHARACTERISTICS FOR THE I2C-BUS
INTERFACE
8.7
8.8
14
15
16
17
18
QUALITY AND RELIABILITY
APPLICATION INFORMATION
EMC GUIDELINES
8.9
8.10
8.11
VPS
Wide Screen Signalling (SAA529xA and
SAA549x only)
525-line world system teletext
Fastext detection
PACKAGE OUTLINES
SOLDERING
8.12
8.13
8.14
8.15
8.16
18.1
18.2
18.3
18.4
Introduction
Through-hole mount packages
Surface mount packages
Suitability of IC packages for wave, reflow and
dipping soldering methods
Page clearing
Full channel operation
Independent data services (SAA5290,
SAA5290A, SAA5291, SAA5291A and
SAA5491 only)
19
20
21
DEFINITIONS
9
THE DISPLAY
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
9.1
9.2
Introduction
Character matrix
1998 Dec 14
2
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
1
FEATURES
General
1.1
• Single chip microcontroller with integrated teletext
decoder
• Single +5 V power supply
• Automatic detection of FASTEXT transmission
• Single crystal oscillator for teletext decoder, display and
microcontroller
• Real-time packet 26 engine for processing accented
(and other) characters
• Teletext function can be powered-down independently
of microcontroller function for reduced power
consumption in standby
• Comprehensive Teletext language coverage
• Video signal quality detector.
• Pin compatibility throughout family.
1.4
Teletext Display
1.2
Microcontroller
• 525-line and 625-line display
• 80C51 microcontroller core
• 12 × 10 character matrix
• 16/32/64 kbyte mask programmed ROM
• 256/768/1280 bytes of microcontroller RAM
• Double height, width and size On-Screen Display (OSD)
• Definable border colour
• Eight 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analog signals
• Enhanced display features including meshing and
shadowing
• One 14-bit PWM for Voltage Synthesis Tuner control
• Four 8-bit Analog-to-Digital converters
• 260 characters in mask programmed ROM
• Automatic FRAME output control with manual override
• RGB push-pull output to standard decoder ICs
• 2 high current open-drain outputs for directly driving
LEDs etc.
• I2C-bus interface
• Stable display via slave synchronisation to horizontal
sync and vertical sync.
• External ROM and RAM capability on QFP80 package
version.
1.5
Additional features of SAA529xA devices
• Wide Screen Signalling (WSS) bit decoding (line 23).
1.3
Teletext acquisition
• 1 page and 10 page Teletext version
1.6
Additional features of SAA549x devices
• Acquisition of 525-line and 625-line World System
Teletext, with automatic selection
• Wide Screen Signalling bit decoding (line 23)
• Quad width OSD capability
• Acquisition and decoding of VPS data (PDC system A)
• Page clearing in under 64 µs (1 TV line)
• 32 additional OSD characters in mask programmed
ROM
• Separate storage of extension packets
(SAA5296/7, SAA5296/7A and SAA5496/7)
• 8 foreground and 8 background colours definable from a
palette of 64.
• Inventory of transmitted Teletext pages stored in the
Transmitted Page Table (TPT) and Subtitle Page Table
(SPT) (SAA5296/7, SAA5296/7A and SAA5496/7)
1998 Dec 14
3
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
2
GENERAL DESCRIPTION
The SAA529x, SAA529xA and SAA549x family of
microcontrollers are a derivative of the Philips’
industry-standard 80C51 microcontroller and are intended
for use as the central control mechanism in a television
receiver. They provide control functions for the television
system and include an integrated teletext function.
The teletext hardware has the capability of decoding and
displaying both 525-line and 625-line World System
Teletext. The same display hardware is used both for
Teletext and On-Screen Display, which means that the
display features give greater flexibility to differentiate the
TV set.
The family offers both 1 page and 10 page Teletext
capability, in a range of ROM sizes. Increasing display
capability is offered from the SAA5290 to the SAA5497.
2.1
Device masking history
A number of mask variants have been produced for the
ETT family of devices. The current mask variants available
are:
• SAA5x90 M5A
• SAA5x91 M1A
• SAA5x96 M5A
• SAA5x97 M1A.
There have been two design issues with the M1 mask,
which required resolving, these brought about the
introduction of the M1A mask:
• Spanish G3 arrows
• OSD twist effect.
The Spanish G3 arrows issue was only encountered on
the Pan-European device, it became apparent that an
up arrow and a right arrow were missing from the Spanish
character map.
The OSD twist effect was inherent on all devices, although
not visible on the Pan-European version. Essentially, OSD
characters had the ability to set and reset the serial
attribute “twist”. This effect is described in detail in
Application note “SPG/AN97004 Version 1.0”.
1998 Dec 14
4
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
3
ORDERING INFORMATION
PACKAGE
PROGRAM
MEMORY (ROM)
TYPE NUMBER(1)
NAME
DESCRIPTION
VERSION
SAA5290PS/nnn
SDIP52 plastic shrink dual in-line package; 52 leads
(600 mil)
SOT247-1 16 kbytes
SAA5291PS/nnn
SAA5296PS/nnn
SAA5296APS/nnn
SAA5491PS/nnn
SAA5496PS/nnn
SAA5491H/nnn
SDIP52 plastic shrink dual in-line package; 52 leads
(600 mil)
SOT247-1 32 kbytes
QFP80 plastic quad flat package; 80 leads (lead length SOT318-2 32 kbytes and external
1.95 mm); body 14 × 20 × 2.8 mm
SAA5297PS/nnn
SAA5297APS/nnn
SAA5497PS/nnn
SAA5297AH/nnn
SAA5497H/nnn
SDIP52 plastic shrink dual in-line package; 52 leads
(600 mil)
SOT247-1 64 kbytes
QFP80 plastic quad flat package; 80 leads (lead length SOT318-2 64 kbytes or external
1.95 mm); body 14 × 20 × 2.8 mm
Note
1. ‘nnn’ is a three-digit number uniquely referencing the microcontroller program mask and OSD mask.
4
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
4.5
TYP.
5.0
MAX.
5.5
UNIT
VDDA
supply voltages
V
VDDM
VDDT
fxtal
crystal frequency
−
12
−
−
MHz
°C
Tamb
IDDM
operating ambient temperature
microcontroller supply current
−20
−
+70
35
20
mA
SAA5290, SAA5290A, SAA5291, SAA5291A and SAA5491
IDDA
IDDT
analog supply current
teletext supply current
−
−
35
40
50
65
mA
mA
SAA5296, SAA5296A, SAA5297, SAA5297A, SAA5496 and SAA5497
IDDA
IDDT
analog supply current
teletext supply current
−
−
35
50
50
80
mA
mA
1998 Dec 14
5
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
5
BLOCK DIAGRAM
V
V
V
V
V
SSA SSD
BLACK
IREF
DDA
DDM
DDT
CVBS0,
CVBS1
TELETEXT
ACQUISITION
R, G, B,
VDS,
COR
DATA SLICER
DISPLAY
PAGE
RAM
VSYNC
HSYNC
FRAME
ACQUISITION
TIMING
DISPLAY
TIMING
SAA5x9x
XTALIN
XTALOUT
OSCGND
OSCILLATOR
512 × 8
AUX RAM
32K × 8
ROM
256 × 8
RAM
TEXT
INTERFACE
data
address
8051
MICRO-
RESET
CONTROLLER
2
I C-BUS
INTERFACE
int
TIMER/
CTRS
ADC
PWM
PORT 1
PORT 0
PORT 3
PORT 2
MGK462
P1.0 to P1.7
P0.0 to P0.7
P3.0 to P3.7
P2.0 to P2.7
Fig.1 Block diagram.
1998 Dec 14
6
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
6
PINNING INFORMATION
Pinning
6.1
handbook, halfpage
P2.0/TPWM
1
2
3
4
5
6
7
8
9
52 P1.5
P2.1/PWM0
P2.2/PWM1
P2.3/PWM2
P2.4/PWM3
P2.5/PWM4
P2.6/PWM5
P2.7/PWM6
P3.0/ADC0
51 P1.4
50 P1.7/SDA
49 P1.6/SCL
48 P1.3/T1
47 P1.2/INT0
46 P1.1/T0
45 P1.0/INT1
V
44
DDM
P3.1/ADC1 10
P3.2/ADC2 11
P3.3/ADC3 12
43 RESET
42 XTALOUT
41 XTALIN
40 OSCGND
V
13
SSD
SAA5x9x
V
P0.0 14
P0.1 15
P0.2 16
P0.3 17
P0.4 18
P0.5 19
P0.6 20
39
38
DDT
DDA
V
37 VSYNC
36 HSYNC
35 VDS
34
33
32
R
G
B
P0.7 21
V
22
31 RGBREF
SSA
CVBS0 23
CVBS1 24
30 P3.4/PWM7
29
28
COR
V
BLACK
IREF
25
26
SSD
27 FRAME
MGK461
Fig.2 Pin configuration (SDIP52).
7
1998 Dec 14
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
64 P1.1/T0
P2.6/PWM5
P2.7/PWM6
P3.0/ADC0
n.c.
1
2
3
4
5
6
7
8
9
63 P1.0/INT1
62
V
DDM
61 P1.3/T1
60 P1.2/INT0
59 RESET
58 XTALOUT
57 XTALIN
56 OSCGND
55 A8
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
P2.5/PWM4
P2.4/PWM3
RD 10
WR 11
54 A9
53 A10
V
12
SSD
SAA5x9x
52 A11
EA 13
P0.0 14
P0.1 15
P0.2 16
51
V
DDT
50 REF+
49
V
DDA
48 P3.6
PSEN 17
ALE 18
REF− 19
P0.3 20
P0.4 21
P3.7 22
n.c. 23
47 VSYNC
46 P3.5
45 HSYNC
44 P3.4/PWM7
43 VDS
42
41
R
G
P0.5 24
MGL157
Fig.3 Pin configuration (QFP80).
8
1998 Dec 14
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
6.2
Pin description
Table 1 SDIP52 and QFP80 packages
PIN
SYMBOL
DESCRIPTION
SDIP52
QFP80
P2.0/TPWM
P2.1/PWM0
P2.2/PWM1
P2.3/PWM2
P2.4/PWM3
P2.5/PWM4
P2.6/PWM5
P2.7/PWM6
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
P3.4/PWM7
P3.5
1
2
77
78
79
80
9
Port 2: 8-bit open-drain bidirectional port with alternative functions.
P2.0/TPWM is the output for the 14-bit high precision PWM.
P2.1/PWM0 to P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6.
3
4
5
6
8
7
1
8
2
9
3
Port 3: 8-bit open-drain bidirectional port with alternative functions.
P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility.
P3.4/PWM7 is the output for the 6-bit PWM7.
10
11
12
30
−
5
6
7
44
46
48
22
12
14
15
16
20
21
24
25
26
27
28
29
30
P3.6
−
P3.7
−
VSSD
13
14
15
16
17
18
19
20
21
22
23
24
25
Digital ground.
P0.0
Port 0: 8-bit open-drain bidirectional port.
P0.1
P0.5 and P0.6 have 10 mA current sinking capability for direct drive of LEDs.
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VSSA
Analog ground.
CVBS0
Composite video inputs; a positive-going 1 V (peak-to-peak) input is required,
connected via a 100 nF capacitor.
CVBS1
BLACK
Video black level storage input: this pin should be connected to VSSA via a
100 nF capacitor.
IREF
26
27
31
36
Reference current input for analog circuits, connected to VSSA via a 27 kΩ
resistor.
FRAME
De-interlace output synchronised with the VSYNC pulse to produce a
non-interlaced display by adjustment of the vertical deflection circuits.
VSSD
COR
28
29
37
38
Internally connected; this pin should be connected to digital ground.
Open-drain, active LOW output which allows selective contrast reduction of
the TV picture to enhance a mixed mode display.
1998 Dec 14
9
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
PIN
SYMBOL
DESCRIPTION
SDIP52
QFP80
RGBREF
31
32
33
34
35
36
39
40
41
42
43
45
DC input voltage to define the output HIGH level on the RGB pins.
Pixel rate output of the BLUE colour information.
B
G
Pixel rate output of the GREEN colour information.
Pixel rate output of the RED colour information.
R
VDS
HSYNC
Video/data switch push-pull output for dot rate fast blanking.
Schmitt trigger input for a TTL level version of the horizontal sync pulse; the
polarity of this pulse is programmable by register bit TXT1.H POLARITY.
VSYNC
37
47
Schmitt trigger input for a TTL level version of the vertical sync pulse;
the polarity of this pulse is programmable by register bit TXT1.V POLARITY.
VDDA
38
39
40
41
42
43
49
51
56
57
58
59
+5 V analog power supply.
+5 V teletext power supply.
Crystal oscillator ground.
VDDT
OSCGND
XTALIN
XTALOUT
RESET
12 MHz crystal oscillator input.
12 MHz crystal oscillator output.
For a recommended reset circuit refer to the application diagram shown in
Fig.29.
VDDM
44
45
46
47
48
49
50
51
52
62
63
64
60
61
65
66
67
68
+5 V microcontroller power supply.
P1.0/INT1
P1.1/T0
P1.2/INT0
P1.3/T1
P1.6/SCL
P1.7/SDA
P1.4
Port 1: 8-bit open-drain bidirectional port with alternate functions.
P1.0/INT1 is external interrupt 1 which can be triggered on the rising and
falling edge of the pulse.
P1.1/T0 is the counter/timer 0.
P1.2/INT0 is external interrupt 0.
P1.3/T1 is the counter/timer 1.
P1.6/SCL is the serial clock input for the I2C-bus.
P1.5
P1.7/SDA is the serial data port for the I2C-bus.
Positive reference voltage for software driven ADC.
Negative reference voltage for software driven ADC.
Read control signal to external Data Memory.
Write control signal to external Data Memory.
Enable signal for external Program Memory.
External latch enable signal; active HIGH.
REF+
REF−
RD
−
−
−
−
−
−
−
50
19
10
11
17
18
13
WR
PSEN
ALE
EA
Control signal used to select external (LOW) or internal (HIGH) Program
Memory.
AD0 to AD7
A8 to A15
−
−
69 to 76 Address lines A0 to A7 multiplexed with data lines D0 to D7.
55 to 52, Address lines A8 to A15.
35 to 32
1998 Dec 14
10
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
7
FUNCTIONAL DESCRIPTION
Microcontroller
7.3
Additional features
The following features are provided in addition to the
standard 80C51 features.
7.1
The functionality of the microcontroller used in this family
is described here with reference to the industry-standard
80C51 microcontroller. A full description of its functionality
can be found in the “80C51-Based 8-Bit Microcontrollers;
Data Handbook IC20”. Using the 80C51 as a reference,
the changes made to this family fall into two categories:
7.3.1
INTERRUPTS
The external INT1 interrupt is modified to generate an
interrupt on both the rising and falling edges of the INT1
pin, when EX1 bit is set. This facility allows for software
pulse width measurement for handling of a remote control.
• Features not supported by the SAA529x, SAA529xA or
SAA549x devices
7.3.2
BIT LEVEL I2C-BUS INTERFACE
• Features found on the SAA529x, SAA529xA or
SAA549x devices but not supported by the 80C51.
For reasons of compatibility with SAA5290 and
SAA5290A, the SAA5291, SAA5291A and SAA5491
contain a bit level serial I/O which supports the I2C-bus.
P1.6/SCL and P1.7/SDA are the serial I/O pins. These two
pins meet the I2C-bus specification “The I2C-bus and how
to use it (including specifications)” concerning the input
levels and output drive capability. Consequently, these two
pins have an open-drain output configuration. All the four
following modes of the I2C-bus are supported.
7.2
80C51 features not supported
7.2.1
INTERRUPT PRIORITY
The IP SFR is not implemented and all interrupts are
treated with the same priority level. The normal
prioritisation of interrupts is maintained within the level.
Table 2 Interrupts and vectors address
• Master transmitter
• Master receiver
• Slave transmitter
• Slave receiver.
INTERRUPT SOURCE
VECTOR ADDRESS
Reset
000H
003H
00BH
013H
01BH
02BH
053H
External INT0
Timer 0
Three SFRs support the function of the bit-level I2C-bus
hardware: S1INT, S1BIT and S1SCS and are enabled by
setting register bit TXT8.I2C SELECT to logic 0.
External INT1
Timer 1
Byte I2C-bus
Bit I2C-bus; note 1
7.3.3
BYTE LEVEL I2C-BUS INTERFACE
The byte level serial I/O supports the I2C-bus protocol.
P1.6/SCL and P1.7/SDA are the serial I/O pins. These two
pins meet the I2C-bus specification concerning the input
levels and output drive capability. Consequently, these two
pins have an open-drain output configuration.
Note
1. SAA5290, SAA5290A, SAA5291, SAA5291A and
SAA5491 only.
The byte level I2C-bus serial port is identical to the I2C-bus
serial port on the 8xC552. The operation of the subsystem
is described in detail in the 8xC552 data sheet found in
“80C51-Based 8-Bit Microcontrollers; Data Handbook
IC20”.
7.2.2
OFF-CHIP MEMORY
The SDIP52 version does not support the use of off-chip
program memory or off-chip data memory.
7.2.3
IDLE AND POWER-DOWN MODES
Four SFRs support the function of the byte level I2C-bus
hardware, they are S1CON, S1STA, S1DAT and S1ADR
and are enabled by setting register bit TXT8.I2C SELECT
to logic 1.
As Idle and Power-down modes are not supported, their
respective bits in PCON are not available.
7.2.4
UART FUNCTION
The 80C51 UART is not available. As a consequence the
SCON and SBUF SFRs are removed and the ES bit in the
IE SFR is unavailable.
7.3.4
LED SUPPORT
Port pins P0.5 and P0.6 have a 10 mA current sinking
capability to enable LEDs to be driven directly.
1998 Dec 14
11
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
7.3.5
6-BIT PWM DACS
Eight 6-bit DACs are available to allow direct control of analog parts of the television.
Each low resolution 6-bit DAC is controlled by its associated Special Function Register (PWM0 to PWM7). The PWM
outputs are alternative functions of Port 2 and Port 3.4. The PWE bit in the SFR for the port corresponding to the PWM
output should be set to logic 1 for correct operation of the PWM output, e.g. if PWM0 is to be used, P2.1 should be set
to logic 1 setting the port pin to high-impedance.
7.3.5.1
Pulse Width Modulator Registers (PWM0 to PWM7)
Table 3 Pulse Width Modulator Registers (see Table 10 for addresses)
7
6
5
4
3
2
1
0
PWE
−
PV5
PV4
PV3
PV2
PV1
PV0
Table 4 Description of PWMn bits (n = 0 to 7)
BIT
SYMBOL
DESCRIPTION
7
PWE
If PWE is set to a logic 1, the corresponding PWM is active and controls its assigned
port pin. If PWE is set to a logic 0, the port pin is controlled by the corresponding bit in
the port SFR.
6
5
4
3
2
1
0
−
Not used.
PV5
PV4
PV3
PV2
PV1
PV0
The output of the PWM is a pulse of period 21.33 µs with a pulse HIGH time determined
by the binary value of these 6-bits multiplied by 0.33 µs. PV5 is the most significant bit.
1998 Dec 14
12
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
The 7 least significant bits, TDACL.TD6 to TDACL.TD0
(LSB), extend certain pulses by a further 0.33 µs, e.g. if the
7 least significant bits are given the value 01H, then
1 in 128 cycles is extended. If the 7 least significant bits
are given the value 02H, then 2 in 128 cycles is extended,
and so forth.
7.3.6
14-BIT PWM DAC
One 14-bit DAC is available to allow direct control of
analog sections of the television. The 14-bit PWM is
controlled using Special Function Registers TDACL and
TDACH.
The output of the TPWM is a pulse of period 42.66 µs.
The 7 most significant bits, TDACH.TD13 (MSB) to
TDACH.TD8 and TDACL.TD7, alter the pulse width
between 0 and 42.33 µs, in much the same way as in the
6-bit PWMs.
The TPWM will not start to output a new value until after
writing a value to TDACH. Therefore, if the value is to be
changed, TDACL should be written to before TDACH.
7.3.6.1
TPWM High Byte Register (TDACH)
Table 5 TPWM High Byte Register (SFR address D3H)
7
6
5
4
3
2
1
0
PWE
−
TD13
TD12
TD11
TD10
TD9
TD8
Table 6 Description of TDACH bits
BIT
SYMBOL
DESCRIPTION
7
PWE
If PWE is set to a logic 1, the TPWM is active and controls port line P2.0. If PWE is set
to a logic 0, the port pin is controlled by the corresponding bit in the port SFR.
6
5
4
3
2
1
0
−
Not used.
TD13
TD12
TD11
TD10
TD9
These 6-bits along with bit TD7 in the TDACL register control the pulse width period.
TD13 is the most significant bit.
TD8
7.3.6.2
TPWM Low Byte Register (TDACL)
Table 7 TPWM Low Byte Register (SFR address D2H)
7
6
5
4
3
2
1
0
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
Table 8 Description of TDACL bits
BIT
SYMBOL
DESCRIPTION
7
TD7
This bit is used with bits TD13 to TD8 in the TDACH register to control the pulse width
period.
6 to 0
TD6 to TD0 These 7-bits extend certain pulses by a further 0.33 µs.
1998 Dec 14
13
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
The setting of the value SAD.SAD7 to SAD.SAD4 must be
performed at least 1 instruction cycle before the setting of
SAD.ST to ensure comparison is made using the correct
SAD.SAD7 to SAD.SAD4 value.
7.3.7
SOFTWARE ADC
Up to 4 successive approximation ADCs can be
implemented in software by making use of the on-chip 8-bit
DAC and multiplexed voltage comparator. The software
ADC uses 4 analog inputs which are multiplexed with
P3.0 to P3.3.
The output of the comparator is SAD.VHI, and is valid
after 1 instruction cycle following the setting of SAD.ST to
a logic 1.
Table 9 ADC input channel selection
CH1
CH0
INPUT PIN
0
0
1
1
0
1
0
1
P3.3/ADC3
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
handbook, halfpage
P3.0
P3.1
P3.2
P3.3
ST
C1
1D
VH1
MULTIPLEXER
CH1, CH0
8-BIT DAC
The control of the ADC is achieved using the Special
Function Registers SAD and SADB.
REF−
REF+
SAD7 to SAD0
SAD.CH1 and SAD.CH0 select one of the four inputs to
pass to the comparator. The other comparator input
comes from the DAC, whose value is set by SAD.SAD7
(MSB) to SAD.SAD4 and SADB.SAD3 to SADB.SAD0
(LSB).
MGL115
Fig.4 SAD block diagram.
1998 Dec 14
14
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7.4
Microcontroller interfacing
The 80C51 communicates with the peripheral functions using Special Function Registers (SFRs) which are addressed as RAM locations. The registers
in the teletext decoder appear as normal SFRs in the microcontroller memory map, but are written to using an internal serial bus. The SFR map is given
in Table 10.
7.4.1
SPECIAL FUNCTION REGISTER MAP
Table 10 Special Function Register map; note 1
DIRECT
ADDR.
(HEX)
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
(HEX)
SYMBOL
ACC(2)
B(2)
NAME
Accumulator
B register
7
6
5
4
3
2
1
0
E0
E7
−
E6
−
E5
−
E4
−
E3
−
E2
−
E1
−
E0
−
00
F0
F7
−
F6
−
F5
−
F4
−
F3
−
F2
−
F1
−
F0
−
00
DPTR
Data Pointer
(2 bytes)
83
82
A8
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
00
00
00
DPH
DPL
IE(2)(3)
High byte
Low byte
Interrupt
Enable
AF
EA
87
−
AE
ES1
86
−
AD
ES2
85
−
AC
AB
ET1
83
−
AA
EX1
82
−
A9
ET0
81
−
A8
EX0
80
−
(1)
−
P0(2)
Port 0
80
90
A0
B0
87
84
−
FF
FF
FF
FF
10
P1(2)
Port 1
97
−
96
−
95
−
94
−
93
−
92
−
91
−
90
−
P2(2)
Port 2
A7
−
A6
−
A5
−
A4
−
A3
−
A2
−
A1
−
A0
−
P3(2)(3)
PCON(3)
Port 3
B7
−
B6
−
B5
−
B4
−
B3
−
B2
−
B1
−
B0
−
(1)
Power Control
−
ARD
−
−
GF1
GF0
−
−
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DIRECT
ADDR.
(HEX)
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
(HEX)
SYMBOL
NAME
Program
7
6
5
4
3
2
1
0
PSW(2)
D0
D7
CY
D6
AC
D5
F0
D4
D3
D2
OV
D1
D0
P
00
Status Word
(1)
RS1
PV4
RS0
PV3
−
(1)
PWM0(3)
PWM1(3)
PWM2(3)
PWM3(3)
PWM4(3)
PWM5(3)
PWM6(3)
PWM7(3)
S1ADR(3)
Pulse Width
Modulator 0
D5
D6
D7
DC
DD
DE
DF
D4
DB
PWE
−
PV5
PV2
PV1
PV1
PV1
PV1
PV1
PV1
PV1
PV1
ADR0
PV0
40
40
40
40
40
40
40
40
00
(1)
Pulse Width
Modulator 1
PWE
PWE
PWE
PWE
PWE
PWE
PWE
ADR6
−
PV5
PV5
PV5
PV5
PV5
PV5
PV5
ADR4
PV4
PV4
PV4
PV4
PV4
PV4
PV4
ADR3
PV3
PV3
PV3
PV3
PV3
PV3
PV3
ADR2
PV2
PV2
PV2
PV2
PV2
PV2
PV2
ADR1
PV0
PV0
PV0
PV0
PV0
PV0
PV0
GC
(1)
Pulse Width
Modulator 2
−
(1)
Pulse Width
Modulator 3
−
(1)
Pulse Width
Modulator 4
−
(1)
Pulse Width
Modulator 5
−
(1)
Pulse Width
Modulator 6
−
(1)
Pulse Width
Modulator 7
−
Serial
I2C-bus
address
ADR5
S1CON
Serial
D8
D8
DF
CR2
DF
DE
ENSI
DE
DD
STA
DD
DC
STO
DC
DB
SI
DA
AA
D9
CR1
D9
D8
CR0
D8
(2)(3)(4)
I2C-bus
00
S1SCS
(2)(3)(5)
Serial
I2C-bus
DB
DA
SDI
SCI
CLH
DAT5
BB
RBF
DAT3
WBF
DAT2
STR
DAT1
ENS
DAT0
E0
00
S1DAT(3)(4) Serial
I2C-bus data
S1INT(3)(5) Serial
I2C-bus
DA
DA
DAT7
DAT6
DAT4
SI
−
−
−
−
−
−
−
7F
Interrupt
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DIRECT
ADDR.
(HEX)
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
(HEX)
SYMBOL
NAME
7
6
5
4
3
2
1
0
S1STA(3)(4) Serial
I2C-bus status
S1BIT(3)(5) Serial
I2C-bus data
D9
D9
E8
STAT4
STAT3
STAT2
STAT1
STAT0
0
0
0
F8
7F
00
SDO/SDI
−
−
−
−
−
−
−
SAD(2)(3)
Software
EF
VHI
9F
EE
CH1
9E
ED
CH0
9D
EC
ST
9C
−
EB
SAD7
9B
EA
SAD6
9A
E9
SAD5
99
E8
SAD4
98
ADC (MSB)
SADB(2)(3) Software
ADC (LSB)
98
00
−
−
−
SAD3
8B
SAD2
8A
SAD1
89
SAD0
88
SP
Stack Pointer
81
88
8F
8E
8D
8C
TR0
07
00
TCON(2)
TF1
TR1
TF0
IE1
IT1
IE0
IT0
Timer/counter
control
(1)
TDACH
TDACL
TH0
TPWM
High byte
D3
D2
8C
8D
8A
8B
89
PWE
TD7
−
TD13
TD5
TD12
TD4
TD11
TD3
TD10
TD2
TD9
TD1
TD8
TD0
40
00
00
00
00
00
00
TPWM
Low byte
TD6
TH06
TH16
TL06
TL16
C/T
Timer 0
High byte
TH07
TH17
TL07
TL17
GATE
TH05
TH15
TL05
TL15
M1
TH04
TH14
TL04
TL14
M0
TH03
TH13
TL03
TL13
GATE
TH02
TH12
TL02
TL12
C/T
TH01
TH11
TL01
TL11
M1
TH00
TH10
TL00
TL10
M0
TH1
Timer 1
High byte
TL0
Timer 0
Low byte
TL1
Timer 1
Low byte
TMOD
Timer/counter
mode
Timer 1
Timer 0
TXT0(3)(6) Teletext
Register 0
C0
X24 POSN DISPLAY
X24
AUTO
FRAME
DISABLE DISPLAY
DISABLE
FRAME
VPS ON
INV ON
00
HDR
STATUS
ROW
ROLL
ONLY
TXT1(3)(6) Teletext
Register 1
C1
EXT PKT
OFF
8−BIT
ACQ OFF
X26
OFF
FULL
FIELD
FIELD
H
V
00
POLARITY POLARITY POLARITY
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DIRECT
ADDR.
(HEX)
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
(HEX)
SYMBOL
NAME
7
6
5
4
3
2
1
0
(1)
TXT2(3)(6) Teletext
Register 2
TXT3(3)(6) Teletext
Register 3
TXT4(3)(6) Teletext
Register 4
C2
C3
C4
−
REQ3
REQ2
REQ1
REQ0
SC2
SC1
SC0
00
00
00
(1)
(1)
(1)
−
−
−
PRD4
PRD3
PRD2
PRD1
PRD0
OSD
BANK
ENABLE
QUAD
WIDTH
ENABLE
EAST/
WEST
DISABLE
DBL HT
B MESH
ENABLE
C MESH
ENABLE
TRANS
ENABLE
SHADOW
ENABLE
TXT5(3)(6) Teletext
Register 5
TXT6(3)(6) Teletext
Register 6
TXT7(3)(6) Teletext
Register 7
TXT8(3)(6) Teletext
Register 8
C5
C6
C7
C8
BKGND BKGND IN COR OUT
OUT
COR IN
COR IN
TEXT
OUT
TEXT IN
TEXT IN
PICTURE PICTURE
ON OUT ON IN
PICTURE PICTURE
03
03
00
00
BKGND BKGND IN COR OUT
OUT
TEXT
OUT
ON OUT
ON IN
STATUS
ROW TOP
CURSOR
ON
REVEAL
TOP/
BOTTOM
DOUBLE
HEIGHT
BOX ON
24
BOX ON
1-23
BOX ON
0
(1)
I2C
IDS
−
DISABLE
SPANISH RECEIVE RECEIVE
PKT26
WSS
WSS ON
CVBS0/
CVBS1
SELECT
ENABLE
D
D
TXT9(3)(6) Teletext
Register 9
TXT10(3)(6) Teletext
Register 10
TXT11(3)(6) Teletext
Register 11
TXT12(3)(6) Teletext
Register 12
C9
CA
CB
CC
CURSOR
FREEZE MEMORY.
CLEAR
A0
C5
D5
R4
C4
D4
R3
R2
R1
C1
R0
C0
D0
00
00
00
(1)
(1)
−
−
C3
D3
C2
D2
D7
D6
D1
625/525
SYNC
ROM
VER R4
ROM
VER R3
ROM
VER R2
ROM
VER R1
ROM VER
R0
TXT ON
VIDEO
SIGNAL
QUALITY
0XXXX
X00B
TXT13(2)(3) Teletext
B8
BF
BE
BD
BC
BB
BA
B9
B8
00
(6)
Register 13
VPS
PAGE
525
525 TEXT
625
TEXT
PKT
8/30
FASTEXT
TIB
RECEIVE CLEARIN DISPLAY
D
G
TXT14(3)(6) Teletext
Register 14
CD
−
−
−
PAGE3
PAGE2
PAGE1
PAGE0
00
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DIRECT
ADDR.
(HEX)
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
(HEX)
SYMBOL
NAME
7
6
5
4
3
2
1
0
TXT15(3)(6) Teletext
Register 15
TXT16(3)(6) Teletext
Register 16
TXT17(3)(6) Teletext
Register 17
WSS1(3)(6) WSS
Register 1
CE
CF
B9
BA
−
−
−
−
BLOCK3
BLOCK2
BLOCK1
BLOCK0
00
00
00
00
−
−
−
Y2
Y1
Y0
−
−
X1
X0
FORCE
ACQ 1
FORCE
ACQ 0
FORCE
625
FORCE
525
SCREEN
COL2
SCREEN
COL1
SCREEN
COL0
−
−
WSS0 to
WSS3
ERROR
WSS3
WSS2
WSS6
WSS10
G0 or
WSS1
WSS5
WSS9
WSS0
WSS4
WSS8
WSS2(3)(6) WSS
Register 2
BB
BC
BD
−
−
−
WSS4 to
WSS7
ERROR
WSS7
00
00
00
WSS3(3)(6) WSS
Register 3
WSS11 to
WSS13
ERROR
WSS13
CLUT
WSS12
B1 or −
WSS11
WSS8 to
WSS10
ERROR
CLUT(3)(6) CLUT
Register
CLUT
ENABLE ADDRESS
B0 or −
G1 or
ENTRY 3 ENTRY 2
R1 or
ENTRY 1
R0 or
ENTRY 0
Notes
1. These bits are inactive and must be written to logic 0 for future compatibility.
2. SFRs are bit addressable.
3. SFRs are modified or added to the 80C51 SFRs.
4. This register used for Byte Orientated I2C-bus, TXT8.I2C SELECT = 1.
5. This register used for Bit Orientated I2C-bus, TXT8.I2C SELECT = 0.
6. Although the Teletext, WSS and CLUT registers are reset internally by hardware, it is advisable that these registers are explicitly reset by the
software following initial power-up and returning from the standby condition.
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
7.4.2
SPECIAL FUNCTION REGISTERS
Table 11 SFRs bit description
REGISTER
FUNCTION
Interrupt Enable Register (IE)
EA
disable all interrupts (logic 0) or use individual interrupt enable bits (logic 1)
bit I2C-bus interrupt enable (logic 1)
byte I2C-bus interrupt enable (logic 1)
ES1
ES2
ET1
EX1
ET0
EX0
enable timer 1 overflow interrupt (logic 1)
enable external interrupt 1 (logic 1)
enable timer 0 overflow interrupt (logic 1)
enable external interrupt 0 (logic 1)
Power Control Register (PCON)
ARD
AUX-RAM disable bit. Disables the 512 bytes of internal AUX-RAM (logic 1);
all MOVX-instructions access the external data memory
GF1
GF0
general purpose flag 1
general purpose flag 0
Program Status Word (PSW)
CY
carry flag
AC
auxiliary carry flag
flag 0
F0
RS1,RS0
register bank select control bits
overflow flag
OV
P
parity flag
6-bit Pulse Width Modulator Control Registers (PWM0 to PWM7)
PWE
activate this PWM and take control of respective port pin (logic 1)
binary value sets high time of PWM output
PV5 to PV0
Serial Interface Slave Address Register (S1ADR); note 1
ADR6 to ADR0
GC
I2C-bus slave address to which the device will respond
enables response to the I2C-bus general call address
Serial Interface Control Register (S1CON); note 1
CR2 to CR0
ENSI
STA
clock rate bits
I2C-bus interface enable
start condition flag
stop condition flag
interrupt flag
STO
SI
AA
assert acknowledge flag
1998 Dec 14
20
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
REGISTER
FUNCTION
Serial Interface Data Register (S1DAT); note 1
DAT7 to DAT0
Serial Interface Status Register (S1STA) - READ only; note 1
STAT4 to STAT0
I2C-bus interface status
Serial Interface Data Register (S1BIT) - READ; note 2
SDI
I2C-bus data bit input
Serial Interface Data Register (S1BIT) - WRITE; note 2
SDO
I2C-bus data bit output
Serial Interface Interrupt Register (S1INT); note 2
SI
I2C-bus interrupt flag
Serial Interface Control Register (S1SCS) - READ; note 2
I2C-bus data
SDI
serial data input at SDA
serial clock input at SCL
clock LOW-to-HIGH transition flag
bus busy flag
SCI
CLH
BB
RBF
WBF
STR
ENS
read bit finished flag
write bit finished flag
clock stretching enable (logic 1)
enable serial I/O (logic 1)
Serial Interface Control Register (S1SCS) - WRITE; note 2
SDO
SCO
CLH
STR
ENS
serial data output at SDA
serial clock output at SCL
clock LOW-to-HIGH transition flag
clock stretching enable (logic 1)
enable serial I/O (logic 1)
Software ADC Control Register (SAD)
VHI
comparator output indicating that analog input voltage greater than DAC voltage (logic 1)
ADC input channel selection bits; see Table 11
CH1 and CH0
ST
initiate voltage comparison (logic 1); this bit is automatically reset to logic 0
4 MSBs of DAC input value
SAD7 to SAD4
1998 Dec 14
21
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
REGISTER
FUNCTION
Software ADC Control Register (SADB)
SAD3 to SAD0
4 LSBs of DAC input value
Timer/Counter Control Register (TCON)
TF1
TR1
TF0
TR0
IE1
Timer 1 overflow flag
Timer 1 run control bit
Timer 0 overflow flag
Timer 0 run control bit
interrupt 1 edge flag
interrupt 1 type control bit
interrupt 0 edge flag
interrupt 0 type control bit
IT1
IE0
IT0
14-bit PWM MSB Register (TDACH)
PWE
activate this 14-bit PWM and take over port pin (logic 1)
6 MSBs of 14-bit number to be output by the 14-bit PWM
TD13 to TD8
14-bit PWM LSB Register (TDACL)
TD7 to TD0
8 LSBs of 14-bit number to be output by the 14-bit PWM
Timer 0 High byte (TH0)
TH07 to TH00
8 MSBs of Timer 0 16-bit counter
Timer 1 High byte (TH1)
TH17 to TH10
8 MSBs of Timer 1 16-bit counter
Timer 0 Low byte (TL0)
TL07 to TL00
8 LSBs of Timer 0 16-bit counter
Timer 1 Low byte (TL1)
TL17 to TL10
8 LSBs of Timer 1 16-bit counter
Timer/Counter Mode Control Register (TMOD)
GATE
C/T
gating control
counter or timer selector
mode control bits
M1, M0
1998 Dec 14
22
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
REGISTER
FUNCTION
Teletext Register 0 (TXT0) - WRITE only
X24 POSN
store packet 24 in extension packet memory (logic 0) or page memory (logic 1)
display X24 from page memory (logic 0) or extension packet memory (logic 1)
FRAME output switched off automatically if any video displayed (logic 1)
disable writing of rolling headers and time into memory (logic 1)
DISPLAY X24
AUTO FRAME
DISABLE HDR
ROLL
DISPLAY STATUS
ROW ONLY
display row 24 only (logic 1)
DISABLE FRAME
FRAME output always LOW (logic 1)
VPS ON
enable capture of VPS data (logic 1)
INV ON(3)
enable capture of inventory page in block 8 (logic 1)
Teletext Register 1 (TXT1) - WRITE only
EXT PKT OFF(3)
8-BIT
disable decoding of extension packets (logic 1)
data in packets 0 to 24 written into memory without error checking (logic 1)
prevent teletext acquisition section writing to memory (logic 1)
ACQ OFF
X26 OFF
disable automatic processing of packet 26 data (logic 1)
FULL FIELD
FIELD POLARITY
H POLARITY
V POLARITY
decode teletext on VBI lines only (logic 0) or decode teletext on any line (logic 1)
VSYNC in first half of the line (logic 0) or second half of the line (logic 1) at start of even field
HSYNC input positive-going (logic 0) or negative-going (logic 1)
VSYNC input positive-going (logic 0) or negative-going (logic 1)
Teletext Register 2 (TXT2) - WRITE only
REQ3 to REQ0(3)
SC2 to SC0
selects which page is modified by TXT3 page request data
start column at which page request data written to TXT3, page request data is placed
Teletext Register 3 (TXT3) - WRITE only
PRD4 to PRD0 page request data
Teletext Register 4 (TXT4) - WRITE only
OSD BANK
ENABLE(4)
bank switching of OSD enabled (logic 1)
QUAD WIDTH
ENABLE(4)
enable quad width characters (logic 1)
EAST/ WEST
western languages selected (logic 0) or Eastern languages selected (logic 1)
disable display of double height teletext control codes (logic 1) in OSD boxes
DISABLE DBL
HGHT
B MESH ENABLE
C MESH ENABLE
TRANS ENABLE
enable meshing of area with black background (logic 1)
enable meshing of area with other background colours (logic 1)
set black background to transparent i.e. video is displayed (logic 1)
SHADOW ENABLE enable south-east shadowing (logic 1)
1998 Dec 14
23
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
REGISTER
FUNCTION
Teletext Register 5 (TXT5) - WRITE only
BKGND OUT
BKGND IN
COR OUT
COR IN
background colour displayed outside teletext boxes (logic 1)
background colour displayed inside teletext boxes (logic 1)
COR output active outside teletext boxes (logic 1)
COR output active inside teletext boxes (logic 1)
text displayed outside teletext boxes (logic 1)
TEXT OUT
TEXT IN
text displayed inside teletext boxes (logic 1)
PICTURE ON OUT video picture displayed outside teletext boxes (logic 1)
PICTURE ON IN video picture displayed inside teletext boxes (logic 1)
Teletext Register 6 (TXT6) - WRITE only
See TXT5
this register has the same meaning as TXT5 but is only invoked if either newsflash (C5) or
subtitle (C6) bit in row 25 of the basic page memory is set
Teletext Register 7 (TXT7) - WRITE only
STATUS ROW TOP display row 24 below (logic 0) or above (logic 1) teletext page
CURSOR ON
REVEAL
display cursor at location pointed to by TXT9 and TXT10 (logic 1)
display characters in areas with the conceal attribute set (logic 1)
display rows 0 to 11 (logic 0) or 12 to 23 (logic 1) when the double height bit is set
display each character as twice normal height (logic 1)
enable teletext boxes in memory row 24 (logic 1)
TOP/BOTTOM
DOUBLE HEIGHT
BOX ON 24
BOX ON 1-23
BOX ON 0
enable teletext boxes in memory rows 1 to 23 (logic 1)
enable teletext boxes in memory row 0 (logic 1)
Teletext Register 8 (TXT8)
I2C SELECT(2)
IDS ENABLE(2)
select bit I2C-bus (logic 0) or byte I2C-bus (logic 1)
capture teletext Independent Date Services (logic 1)
disable special treatment of Spanish packet 26 decoding
DISABLE
SPANISH(2)
PKT 26 RECEIVED set to logic 1 when packet 26 teletext data processed
WSS RECEIVED(5) set to logic 1 when wide screen signalling data received
WSS ON(5)
enable acquisition of wide screen signalling data
CVBS0/CVBS1
select CVBS0 (logic 0) or CVBS1 (logic 1) input to the device
Teletext Register 9 (TXT9) - WRITE only
CURSOR FREEZE locks current cursor position (logic 1)
CLEAR MEMORY
A0
write 20H into every location in teletext memory (logic 1)
TXT11 accesses the basic page memory, selected by TXT15 on the 10 page device, (logic 0)
or extension packet memory (logic 1)
R4 to R0
memory row to be accessed by TXT11
1998 Dec 14
24
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
REGISTER
FUNCTION
Teletext Register 10 (TXT10) - WRITE only
C5 to C0
memory column to be accessed by TXT11
Teletext Register 11 (TXT11)
D7 to D0
data byte written to, or read from teletext memory
Teletext Register 12 (TXT12) - READ only
625/525 SYNC
a 625-line CVBS signal (logic 0), or a 525-line CVBS signal (logic 1) is being input
ROM VER R4 to R0 mask programmable identification for character set
TXT ON
power has been applied to the teletext hardware (logic 1)
CVBS input can be locked on by the teletext decoder (logic 1)
VIDEO SIGNAL
QUALITY
Teletext Register 13 (TXT13)
VPS RECEIVED
PAGE CLEARING
525 DISPLAY
525 TEXT
set to logic 1 when VPS data is received
set when software requested page clear in progress
set to logic 1 when 525-line syncs are driving the display
set to logic 1 when 525-line teletext is received
625 TEXT
set to logic 1 when 625-line teletext is received
PKT 8/30
set to logic 1 when packet 8/30 is detected
FASTEXT
set to logic 1 when packet X27/0 is detected
TIB
text interface busy; logic 1 indicates that TXT registers 0 to 16 cannot currently be accessed
Teletext Register 14 (TXT 14) - WRITE only; note 3
PAGE3 to PAGE0 selects which page to display
Teletext Register 15 (TXT15) - WRITE only; note 3
BLOCK3 to BLOCK0 selects which memory block accessed by TXT9, 10 and 11
Teletext Register 16 (TXT16) - WRITE only
Y2 to Y0
X1 to X0
sets vertical position of display area
sets horizontal position of display area
Teletext Register 17 (TXT17) - Write only
FORCE ACQ0,1
FORCE 625
force acquisition mode
force display to 625-line mode
force display to 525-line mode
FORCE 525
SCREEN COL 2 to 0 defines colour displayed instead of TV picture and black background
1998 Dec 14
25
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
REGISTER
FUNCTION
Wide Screen Signalling Register 1 (WSS1) - READ only; note 5
WSS 0-3 ERROR
WSS3 to WSS0
error flag for bits WSS0 to WSS3
signalling bits to define aspect ratio (group 1)
Wide Screen Signalling Register 2 (WSS2) - READ only; note 5
WSS 4-7 ERROR
WSS7 to WSS4
error flag for bits WSS4 to WSS7
signalling bits to define enhanced services (group 2)
Wide Screen Signalling Register 3 (WSS3) - READ only; note 5
WSS11-13 ERROR error flag for bits WSS11 to WSS13
WSS13 to WSS11
WSS8-10 ERROR
WSS10 to WSS8
signalling bits to define reserved elements (group 4)
error flag for bits WSS8 to WSS10
signalling bits to define subtitles (group 3)
Colour Look-Up Table Register (CLUT) - WRITE only; note 4
CLUT ENABLE
CLUT ADDRESS
B1
enable the colour look-up table (logic 1)
load CLUT address (logic 1) or CLUT data (logic 0)
most significant BLUE component data
least significant BLUE component data
B0
G1 or ENTRY3
G0 or ENTRY2
R1 or ENTRY1
R0 or ENTRY0
most significant GREEN component data or most significant bit of CLUT address
least significant GREEN component data or CLUT address
most significant RED component data or CLUT address
least significant RED component data or least significant bit of CLUT address
Notes
1. Available on SAA5296, SAA5296A, SAA5297, SAA5297A, SAA5496, SAA5497 permanently and SAA5290,
SAA5290A, SAA5291, SAA5291A, SAA5491 when TXT8.I2C SELECT set to logic 1.
2. Available on SAA5290, SAA5290A, SAA5291, SAA5291A and SAA5491.
3. Available on SAA5296, SAA5296A, SAA5297, SAA5297A, SAA5496, SAA5497.
4. Available on SAA5491, SAA5496, SAA5497.
5. Available on SAA5290A, SAA5291A, SAA5296A, SAA5297A, SAA5491, SAA5496, SAA5497.
1998 Dec 14
26
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
When the HOLD bit is set to a logic 0 the teletext decoder
will not recognise any page as having the correct page
number and no pages will be captured. In addition to
providing the user requested hold function this bit should
be used to prevent the inadvertent capture of an unwanted
page when a new page request is being made. For
example, if the previous page request was for page 100
and this was being changed to page 234, it would be
possible to capture page 200 if this arrived after only the
requested magazine number had been changed.
8
TELETEXT DECODER
Data slicer
8.1
The data slicer extracts the digital teletext data from the
incoming analog waveform. This is performed by sampling
the CVBS waveform and processing the samples to
extract the teletext data and clock.
8.2
Acquisition timing
The acquisition timing is generated from a logic level
positive-going composite sync signal VCS. This signal is
generated by a sync separator circuit which adaptively
slices the sync pulses. The acquisition clocking and timing
are locked to the VCS signal using a digital
The E1 and E0 bits control the error checking which should
be carried out on packets 1 to 23 when the page being
requested is captured. This is described in more detail in
Section 8.5.
phase-locked-loop. The phase error in the acquisition
phase-locked-loop is detected by a signal quality circuit
which disables acquisition if poor signal quality is detected.
For the ten page device, each packet can only be written
into one place in the teletext RAM so if a page matches
more than one of the page requests the data is written into
the area of memory corresponding to the lowest numbered
matching page request.
8.3
Teletext acquisition
This family is capable of acquiring 625-line and 525-line
World System Teletext see “World System Teletext and
Data Broadcasting System”. Teletext pages are identified
by seven numbers: magazine (page hundreds), page tens,
page units, hours tens, hours units, minutes tens and
minutes units. The last four digits, hours and minutes, are
known as the subcode, and were originally intended to be
time related, hence their names. A page is requested by
writing a series of bytes into the TXT3 SFR which
At power-up each page request defaults to any page, hold
on and error check Mode 0.
Table 12 The contents of the Page request RAM
START
COLUMN
PRD4
PRD3 PRD2 PRD1 PRD0
0
DO CARE HOLD MAG2 MAG1 MAG0
Magazine
corresponds to the number of the page required.
1
2
3
DO CARE PT3
Page Tens
PT2
PU2
X
PT1
PU1
HT1
PT0
PU0
HT0
The bytes written into TXT3 are put into a small RAM with
an auto-incrementing address. The start address for the
RAM is set using the TXT2 SFR. Table 12 shows the
contents of the page request RAM.
DO CARE PU3
Page Units
DO CARE
Hours
X
TXT2.REQ0 to TXT2.REQ3 determine which of the
10 page requests is being modified for a 10 page teletext
decoder. If TXT2.REQ is given a value greater than 09H,
then data written into TXT3 is ignored.
Tens
4
5
6
7
DO CARE HU3
Hours
Units
HU2
MT2
MU2
X
HU1
MT1
MU1
E1
HU0
MT0
MU0
E0
Up to 10 pages of teletext can be acquired on the 10 page
device, when TXT1.EXT PKT OFF is set to logic 1, and up
to 9 pages can be acquired when this bit is set to logic 0.
DO CARE
Minutes
Tens
X
If the ‘DO CARE’ bit for part of the page number is set to a
logic 0 then that part of the page number is ignored when
the teletext decoder is deciding whether a page being
received off air should be stored or not. For example, if the
‘DO CARE’ bits for the 4 subcode digits are all set to
logic 0s then every subcode version of the page will be
captured.
DO CARE MU3
Minutes
Units
X
X
1998 Dec 14
27
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
The last 8 characters of the page header are used to
provide a time display and are always extracted from every
valid page header as it arrives and written into the display
block.
Table 13 Notation used in Table 12
MNEMONIC
DESCRIPTION
MAG
PT
Magazine
Page Tens
The TXT0.DISABLE HEADER ROLL bit prevents any data
being written into row 0 of the page memory except when
a page is acquired off air i.e. rolling headers and time are
not written into the memory. The TXT1.ACQ OFF bit
prevents any data being written into the memory by the
teletext acquisition section.
PU
HT
HU
MT
MU
E
Page Units
Hours Tens
Hours Units
Minutes Tens
Minutes Units
Error check mode
When a parallel magazine mode transmission is being
received only headers in the magazine of the page
requested are considered valid for the purposes of rolling
headers and time. Only one magazine is used even if don’t
care magazine is requested. When a serial magazine
mode transmission is being received all page headers are
considered to be valid.
8.4
Rolling headers and time
When a new page has been requested it is conventional
for the decoder to turn the header row of the display green
and to display each page header as it arrives until the
correct page has been found.
8.5
Error checking
When a page request is changed (i.e. when the TXT3 SFR
is written to) a flag (PBLF) is written into bit 5, column 9,
row 25 of the corresponding block of the page memory.
The state of the flag for each block is updated every TV
line, if it is set for the current display block, the acquisition
section writes all valid page headers which arrive into the
display block and automatically writes an alphanumeric
green character into column 7 of row 0 of the display block
every TV line.
Before teletext packets are written into the page memory
they are error checked. The error checking carried out
depends on the packet number, the byte number, the error
check mode bits in the page request data and the
TXT1.8 BIT bit.
If an uncorrectable error occurs in one of the Hamming
checked addressing and control bytes in the page header
or in the Hamming checked bytes in packet 8/30, bit 4 of
the byte written into the memory is set, to act as an error
flag to the software. If uncorrectable errors are detected in
any other Hamming checked data the byte is not written
into the memory.
When a requested page header is acquired for the first
time, rows 1 to 23 of the relevant memory block are
cleared to space, i.e. have 20H written into every column,
before the rest of the page arrives. Row 24 is also cleared
if the TXT0.X24 POSN bit is set. If the
TXT1.EXT PKT OFF bit is set the extension packets
corresponding to the page are also cleared.
1998 Dec 14
28
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
Packet X/0
'8-bit' bit = 0
0
1
2
3
4
4
5
5
6
6
7
7
8
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
'8-bit' bit = 1
0
1
2
3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Packet X/1-23
'8-bit' bit = 0, error check mode = 0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
'8-bit' bit = 0, error check mode = 1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
'8-bit' bit = 0, error check mode = 2
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
'8-bit' bit = 0, error check mode = 3
0
1 2 3 4 5 6 7 8
0
1 2 3 4 5 6 7 8
0
1
2
3
4
4
5
5
6
6
7
7
8
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
'8-bit' bit = 1
0
1 2 3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Packet X/24
'8-bit' bit = 0
0
1
2
3
4
4
5
5
6
6
7
7
8
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
'8-bit' bit = 1
0
1
2
3
3
3
Packet X/27/0
0
1
2
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Packet 8/30/0,1
0
1 2
Packet 8/30/2,3,4-15
0
1
2
3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
MGK465
8-bit
data
odd parity
checked
8/4 Hamming
checked
Fig.5 Error checking.
1998 Dec 14
29
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
The interrupted sequence (C9) bit is automatically dealt
with by the acquisition section so that rolling headers do
not contain discontinuities in the page number sequence.
8.6
Memory organisation of SAA5296/7,
SAA5296/7A and SAA5496/7
The teletext memory is divided into 10 blocks. Normally,
when the TXT1.EXT PKT OFF bit is logic 0, each of blocks
0 to 8 contains a teletext page arranged in the same way
as the basic page memory (see Fig.6) of the page device
and block 9 contains extension packets (see Fig.7).
The magazine serial (C11) bit indicates whether the
transmission is a serial or a parallel magazine
transmission. This affects the way the acquisition section
operates and is dealt with automatically.
The newsflash (C5), subtitle (C6), suppress header (C7),
inhibit display (C10) and language control (C12 to 14) bits
are dealt with automatically by the display section,
described below.
When the TXT1.EXT PKT OFF bit is logic 1, no extension
packets are captured and block 9 of the memory is used to
store another page.
The number of the memory block into which a page is
written corresponds to the page request number which
resulted in the capture of the page.
The update (C8) bit has no effect on the hardware. The
remaining 32 bytes of the page header are parity checked
and written into columns 8 to 39 of row 0. Bytes which
pass the parity check have the MSB set to a logic 0 and
are written into the page memory. Bytes with parity errors
are not written into the memory.
Packet 0, the page header, is split into 2 parts when it is
written into the text memory. The first 8 bytes of the header
contain control and addressing information. They are
Hamming decoded and written into columns 0 to 7 of
row 25 (see Table 15). Row 25 also contains the
magazine number of the acquired page and the PBLF flag
but the last 14 bytes are unused and may be used by the
software, if necessary. The Hamming error flags are set if
the on-board 8/4 Hamming checker detects that there has
been an uncorrectable (2 bit) error in the associated byte.
Table 14 Notation used in Table 15
MNEMONIC
DESCRIPTION
Magazine
MAG
PT
Page Tens
PU
Page Units
Hours Tens
Hours Units
Minutes Tens
Minutes Units
It is possible for the page to still be acquired if some of the
page address information contains uncorrectable errors if
that part of the page request was a ‘don’t care’. There is no
error flag for the magazine number as an uncorrectable
error in this information prevents the page being acquired.
HT
HU
MT
MU
Table 15 The data in row 25 of the basic page memory
COL
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
0
0
0
0
0
−
0
0
0
0
0
0
0
0
0
0
−
0
Hamming error
Hamming error
Hamming error
Hamming error
Hamming error
Hamming error
Hamming error
Hamming error
FOUND
PU3
PT3
MU3
C4
PU2
PT2
MU2
MT2
HU2
C5
PU1
PT1
MU1
MT1
HU1
HT1
C8
PU0
PT0
MU0
MT0
HU0
HT0
C7
1
0
2
0
3
0
4
0
HU3
C6
5
0
6
0
C10
C14
0
C9
7
0
0
C13
MAG2
0
C12
MAG1
0
C11
MAG0
0
8
9
PBLF
−
0
0
10 to 23
unused
−
−
−
−
1998 Dec 14
30
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
Basic Page Blocks (0 to 8/9)
0
6
7
8
39
Row 0 OSD only
Packet X/0
Packet X/1
Packet X/2
Packet X/3
Packet X/4
Packet X/5
Packet X/6
Packet X/7
Packet X/8
Packet X/9
Packet X/10
Packet X/11
Packet X/12
Packet X/13
Packet X/14
Packet X/15
Packet X/16
Packet X/17
Packet X/18
Packet X/19
Packet X/20
Packet X/21
Packet X/22
Packet X/23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(1)
Packet X/24
(2)
25
Control Data
VPS Data
MGK466
0
9
23
(1) If ‘X24 Posn’ bit = 1.
(2) VPS data block 9, unused in blocks 0 to 8.
Fig.6 Packet storage locations.
1998 Dec 14
31
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
Extension Packet Block (9)
(1)
Row
0
1
2
Packet X/24 for page in block 0
Packet X/27/0 for page in block 0
Packet 8/30/0.1
Packet 8/30/2.3
3
(1)
Packet X/24 for page in block 1
4
Packet X/27/0 for page in block 1
5
6
(1)
Packet X/24 for page in block 2
Packet X/27/0 for page in block 2
7
(1)
8
Packet X/24 for page in block 3
Packet X/27/0 for page in block 3
9
(1)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Packet X/24 for page in block 4
Packet X/27/0 for page in block 4
(1)
Packet X/24 for page in block 5
Packet X/27/0 for page in block 5
(1)
Packet X/24 for page in block 6
Packet X/27/0 for page in block 6
(1)
Packet X/24 for page in block 7
Packet X/27/0 for page in block 7
(1)
Packet X/24 for page in block 8
Packet X/27/0 for page in block 8
Packet 8/30/4-15
VPS Data
23
MGD163
0
9
(1) If ‘X24 Position’ bit = 0.
Fig.7 Extension packet storage locations.
1998 Dec 14
32
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
The bit for a particular page in the TPT is set when a page
header is received for that page. The bit in the SPT is set
when a page header for the page is received which has the
‘subtitle’ page header control bit (C6) set.
8.7
Inventory page
If the TXT0.INV ON bit is a logic 1, memory block 8 is used
as an inventory page.The inventory page consists of two
tables: the Transmitted Page Table (TPT) and the Subtitle
Page Table (SPT).
Before the inventory page is enabled the software must
ensure that page request 8 is put on hold.
In each table, every possible combination of the page tens
and units digit, 00H to FFH, is represented by a byte.
Each bit of these bytes corresponds to a magazine number
so each page number, from 100 to 8FF, is represented by
a bit in the table.
Bytes in the table
column
0
8
16
24
32
39
row n
n + 1
n + 6
n + 7
Bytes in each byte
bit
7
0
6xx
5xx
4xx
3xx
2xx
1xx
8xx
7xx
MGD160
Fig.8 Table organisation.
1998 Dec 14
33
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
0
39
Row 0
1
2
Transmitted
Pages
Table
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Subtitle
Pages
Table
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
MGD165
0
23
Fig.9 Inventory page organisation.
1998 Dec 14
34
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
8.8
Memory organisation of SAA5290, SAA5290A, SAA5291, SAA5291A and SAA5491
Teletext packets each contain 40 bytes of data and one packet is stored in each row of the text memory, the row used
being dependent on the packet number.
Packet 0, the page header, is split into 2 parts when it is written into the text memory. The first 8 bytes of the header
contain control and addressing information. They are Hamming decoded and written into columns 0 to 7 of row 25.
Basic Page Block
0
6
7
8
39
Row 0 OSD only
aw/ag
Packet X/0
Packet X/1
Packet X/2
Packet X/3
Packet X/4
Packet X/5
Packet X/6
Packet X/7
Packet X/8
Packet X/9
Packet X/10
Packet X/11
Packet X/12
Packet X/13
Packet X/14
Packet X/15
Packet X/16
Packet X/17
Packet X/18
Packet X/19
Packet X/20
Packet X/21
Packet X/22
Packet X/23
Packet X/24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(1)
23
25
Control Data
VPS Data
0
9
Extension Packet Memory
(2)
Row 0
Packet X/24
1
2
Packet X/27/0
Packet 8/30
MGK467
(1) If X24 Position bit = 1.
(2) If X24 Position bit = 0.
Fig.10 Packet storage locations.
1998 Dec 14
35
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
The TXT8.Pkt 26 received bit is set by the hardware
whenever a character is written into the page memory by
the packet 26 decoding hardware. The flag can be reset by
writing a logic 0 into the SFR bit.
8.9
Packet 26 processing
One of the uses of packet 26 is to transmit characters
which are not in the basic teletext character set. The family
automatically decodes packet 26 data and, if a character
corresponding to that being transmitted is available in the
character set, automatically writes the appropriate
character code into the correct location in the teletext
memory. This is not a full implementation of the packet 26
specification allowed for in level 2 teletext, and so is often
referred to as level 1.5.
8.10 VPS
When the TXT0. VPS ON bit is set, any VPS data present
on line 16, field 0 of the CVBS signal at the input of the
teletext decoder is error checked and stored in row 25,
block 0 for SAA5291, SAA5291A, SAA5491 and row 25,
block 9 for SAA5296/7, SAA5296/7A, SAA5496/7 of the
basic page memory. The device automatically detects
whether teletext or VPS is being transmitted on this line
and decodes the data appropriately.
By convention, the packets 26 for a page are transmitted
before the normal packets. To prevent the default
character data overwriting the packet 26 data the device
incorporates a mechanism which prevents packet 26 data
from being overwritten. On the SAA5291,SAA5291A and
SAA5491 devices this mechanism is disabled when the
Spanish national option is detected as the Spanish
transmission system sends even parity (i.e. incorrect)
characters in the basic page locations corresponding to
the characters sent via packet 26 and these will not
overwrite the packet 26 characters anyway. The special
treatment of Spanish national option is prevented if
TXT12.ROM VER R4 is logic 0 or if the TXT8.DISABLE
SPANISH is set.
Each VPS byte in the memory consists of 4 bi-phase
decoded data bits (bits 0 to 3), a bi-phase error flag (bit 4)
and three 0s (bits 5 to 7).
The TXT13.VPS Received bit is set by the hardware
whenever VPS data is acquired. The flag can be reset by
writing a logic 0 into the SFR bit. Full details of the VPS
system can be found in “Specification of the Domestic
Video Programme Delivery Control System (PDC); EBU
Tech. 3262-E”.
Packet 26 data is processed regardless of the
TXT1.EXT PKT OFF bit, but setting theTXT1.X26 OFF
disables packet 26 processing.
Table 16 VPS data storage
COLUMN
ROW
0 TO 9
10 TO 11 12 TO 13 14 TO 15 16 TO 17 18 TO 19 20 TO 21 22 TO 23
Row 25 Teletext page header data
VPS
VPS
VPS
VPS
VPS
VPS
VPS
byte 11
byte 12
byte 13
byte 14
byte 15
byte 4
byte 5
1998 Dec 14
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
The first 8 data bytes of packet X/1/24 are used to extend
the Fastext prompt row to 40 characters. These characters
are written into whichever part of the memory the
packet 24 is being written into (determined by the ‘X24
Posn’ bit).
8.11 Wide Screen Signalling (SAA529xA and
SAA549x only)
The Wide Screen Signalling data transmitted on line 23
gives information on the aspect ratio and display position
of the transmitted picture, the position of subtitles and on
the camera/film mode. Some additional bits are reserved
for future use. A total of 14 data bits are transmitted.
Packets X/0/27/0 contain 5 Fastext page links and the link
control byte and are captured, Hamming checked and
stored by in the same way as are packets X/27/0 in
625-line text. Packets X/1/27/0 are not captured.
All of the available data bits transmitted by the Wide
Screen Signalling signal are captured by the appropriate
device in the family and stored in SFRs WSS1, WSS2 and
WSS3. The bits are stored as groups of related bits and an
error flag is provided for each group to indicate when a
transmission error has been detected in one or more of the
bits in the group.
Because there are only 2 magazine bits in 525-line text,
packets with the magazine bits all set to a logic 0 are
referred to as being in magazine 4. Therefore, the
broadcast service data packet is packet 4/30, rather than
packet 8/30. As in 625 line text, the first 20 bytes of packet
4/30 contain encoded data which is decoded in the same
way as that in packet 8/30. The last 12 bytes of the packet
contains half of the parity encoded status message.
Packet 4/0/30 contains the first half of the message and
packet 4/1/30 contains the second half. The last 4 bytes of
the message are not written into memory. The first
20 bytes of the each version of the packet are the same so
they are stored whenever either version of the packet is
acquired.
Wide screen signalling data is only acquired when the
TXT8.WSS ON bit is set.
The TXT8.WSS RECEIVED bit is set by the hardware
whenever wide screen signalling data is acquired. The flag
can be reset by writing a logic 0 into the SFR bit.
8.12 525-line world system teletext
As well as the 625-line teletext format described
previously, the family can acquire teletext in the 525-line
WST (World System Teletext) format.
In 525-line text each packet 26 only contains ten 24/18
Hamming encoded data triplets, rather than the 13 found
in 625-line text. The tabulation bit is used as an extra bit
(the MSB) of the designation code, allowing 32 packet 26s
to be transmitted for each page. The last byte of each
packet 26 is ignored.
The 525-line format is similar to the 625-line format but the
data rate is lower and there are less data bytes per packet
(32 rather than 40). There are still 40 characters per
display row so extra packets are sent each of which
contains the last 8 characters for four rows. These packets
can be identified by looking at the ‘tabulation bit’ (T), which
replaces one of the magazine bits in 525-line teletext.
When an ordinary packet with T = 1 is received, the
decoder puts the data into the four rows starting with that
corresponding to the packet number, but with the 2 LSBs
set to logic 0. For example, a packet 9 with T = 1 (packet
X/1/9) contains data for rows 8, 9, 10 and 11. The error
checking carried out on data from packets with T = 1
depends on the setting of the TXT1. 8 BIT bit and the error
checking control bits in the page request data and is the
same as that applied to the data written into the same
memory location in the 625-line format.
The device automatically detects whether 525 or 625-line
teletext is being received by checking whether teletext
packets are being recognised, and switching to the other
system if they are not.
The TXT13.625 TXT bit is set if the device has decided,
using the algorithm above, that 625-line text is being
received. The TXT13.525 Text bit is set if the device has
decided that 525-line text is being received. If the device
has not decided which type of text is being received then
neither flag is set.
The ‘FORCE ACQ0’ and ‘FORCE ACQ1’ bits in TXT17
can be used to override the automatic detection and
selection mechanism; see Table 17.
The rolling time display (the last 8 characters in row 0) is
taken from any packets X/1/1, 2 or 3 received. In parallel
magazine mode only packets in the correct magazine are
used for rolling time. Packet number X/1/0 is ignored.
The tabulation bit is also used with extension packets.
1998 Dec 14
37
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
Table 17 Acquisition selection table
FORCE ACQ1
FORCE ACQ0
TIMING
TELETEXT STANDARD
0
0
1
1
0
1
0
1
automatic
525-line
625-line
625-line
automatic
525-line
625-line
525-line
0
6
7
8
39
Row 0 OSD only aw/ag
Packet X/0/0
Packet X/0/1
Packet X/0/2
Packet X/0/3
Packet X/0/4
Packet X/0/5
Packet X/0/6
Packet X/0/7
Packet X/0/8
Packet X/0/9
Packet X/0/10
Packet X/0/11
Packet X/0/12
Packet X/0/13
Packet X/0/14
Packet X/0/15
Packet X/0/16
Packet X/0/17
Packet X/0/18
Packet X/0/19
Packet X/0/20
Packet X/0/21
Packet X/0/22
Packet X/0/23
Packet X/0/24
Rolling time
Packet X/1/1
1
2
3
4
Packet X/1/4
Packet X/1/8
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Packet X/1/12
Packet X/1/16
Packet X/1/20
(1)
(1)
Packet X/1 /24
25
Control Data
MGK468
0
9
23
(1) If X24 Position bit = 1.
Fig.11 Ordinary packet storage locations, 525-line.
1998 Dec 14
38
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
This allows the device to be used with teletext
8.13 Fastext detection
transmissions occupying the entire TV channel and with
data extracted from different TV broadcast standards (e.g.:
MAC packet teletext).
When a packet 27, designation code 0 is detected,
whether or not it is acquired, the TXT13.FASTEXT bit is
set. If the device is receiving 525-line teletext, a packet
X/0/27/0 is required to set the flag. The flag can be reset
by writing a logic 0 into the SFR bit.
8.16 Independent data services (SAA5290,
SAA5290A, SAA5291, SAA5291A and SAA5491
only)
When a packet 8/30 is detected, or a packet 4/30 when the
device is receiving a 525-line transmission, the TXT13.Pkt
8/30 is set. The flag can be reset by writing a logic 0 into
the SFR bit.
When the TXT8.IDS ENABLE bit is set, SAA5291 and
SAA5290 become a receiver for teletext ‘Independent
Data Services’. These services use teletext packet
numbers 30 and 31 to transmit data from a central
database to a large number of distributed receivers.
8.14 Page clearing
When a page header is acquired for the first time after a
new page request or a page header is acquired with the
erase (C4) bit set the page memory is ‘cleared’ to spaces
before the rest of the page arrives.
Unlike normal teletext data, IDS data is not organised into
pages but into ‘data channels’.
There are 16 data channels, identified by the magazine
number and the LSB of the packet number (actually, the
second byte of the magazine and packet number group).
Data channel 0 is the familiar packet 8/30, used to transmit
broadcast related information.
When this occurs, the space code (20H) is written into
every location of rows 1 to 23 of the basic page memory,
row 1 of the extension packet memory and the row where
teletext packet 24 is written. This last row is either row 24
of the basic page memory, if the TXT0.X24 POSN bit is
set, or row 0 of the extension packet memory, if the bit is
not set. Page clearing takes place before the end of the TV
line in which the header arrived which initiated the page
clear. This means that the 1 field gap between the page
header and the rest of the page which is necessary for
many teletext decoders is not required.
The data channel to be captured by the device is selected
by writing to column 0 of the page request RAM.
Only IDS packets from the selected data channel are
captured and rows 0 to 23 of the basic page memory are
used to store the last 24 packets acquired. The first IDS
packet acquired after theTXT8.IDS ENABLE bit is set is
written into row 0, the next into row 1 and so on until 24
packets have been acquired. The internal packet counter
then rolls over and the 25th packet is written into row 0.
The hardware never initiates a page clear in IDS mode but
if the software initiates one the packet counter is reset to 0
after the memory is cleared.
The software can also initiate a page clear, by setting the
TXT9.CLEAR MEMORY bit. When it does so, every
location in the memory is cleared. The CLEAR MEMORY
bit is not latched so the software does not have to reset it
after it has been set.
Only one page can be cleared in a TV line so if the
software requests a page clear it will be carried out on the
next TV line on which the hardware does not force the
page to be cleared. A flag, TXT13.PAGE CLEARING, is
provided to indicate that a software requested page clear
is being carried out. The flag is set when a logic 1 is written
into the TXT9.CLEAR MEMORY bit and is reset when the
page clear has been completed.
The data bytes in the IDS packers are not error checked in
any way.
The software must keep track of which of the IDS packets
in the memory it has processed and detect newly arrived
packets. It can do this by writing a value which cannot be
produced by the 8/4 Hamming checker (such as FFH) into
column 0 of each row and detecting when it is over written.
The 24 packet buffer is sufficient to ensure that the device
will not be overwhelmed by IDS data sent in the vertical
blanking interval, but it may not be able to cope with full
channel IDS data.
At power-on and reset the whole of the page memory is
cleared and theTXT13.PAGE CLEARING bit will be set.
8.15 Full channel operation
IDS data is dealt with in the same way for both the
525 and 625-line teletext standards.
If the TXT1.FULL FIELD bit is set the device will acquire
data transmitted on any TV line, not just during the vertical
blanking interval.
1998 Dec 14
39
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
Table 18 Page request RAM for IDS data
COL
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0
X
X
X
X
X
X
X
X
Data Ch 3 Data Ch 2 Data Ch 1 Data Ch 0
1 to 7
X
X
X
X
9
THE DISPLAY
Introduction
9.4
National option characters
The meanings of some character codes between 20H and
7FH depend on the C12 to C14 language control bits from
the teletext page header.
9.1
The capabilities of the display are based on the
requirements of level 1 teletext, with some enhancements
for use with locally generated on screen displays.
The interpretation of the C12 to C14 language control bits
is dependent on the East/West bit.
The display consists of 25 rows each of 40 characters,
with the characters displayed being those from
rows 0 to 24 of the basic page memory. If the
9.5
The twist attribute
TXT7.STATUS ROW TOP bit is set row 24 is displayed at
the top of the screen, followed by row 0, but normally
memory rows are displayed in numerical order.
In many of the character sets, the ‘twist’ serial attribute
(code 1BH) can be used to switch to an alternate basic
character code table, e.g. to change from the Hebrew
alphabet to the Arabic alphabet on an Arab/Hebrew
device. For some national option languages the alternate
code table is the default, and a twist control character will
switch to the first code table.
The teletext memory stores 8 bit character codes which
correspond to a number of displayable characters and
control characters, which are normally displayed as
spaces. The character set of the device is described in
more detail below.
The display hardware on the devices allows one language
to invoke the alternate code table by default when the
East/West register bit is a logic 0 and another when the bit
is a logic 1. In all of the character sets defined so far, the
language which invokes the alternate code table is the
same for either setting of the East/West bit.
9.2
Character matrix
Each character is defined by a matrix 12 pixels wide and
10 pixels high. When displayed, each pixel is 1⁄12 µs wide
and 1 TV line, in each field, high.
9.6
Language group identification
9.3
East/West selection
The devices have a readable register TXT12 which
contains a 5 bit identification code TXT12.ROM VER R4 to
TXT12.ROM VER R0 which is intended for use in
identifying which character set the device is using.
In common with their predecessors, these devices store
teletext pages as a series of 8 bit character codes which
are interpreted as either control codes (to change colour,
invoke flashing etc.) or displayable characters. When the
control characters are excluded, this gives an addressable
set of 212 characters at any given time.
More characters than this were required to give the
language coverage required from the first version of the
device, so the TXT4.East/West bit was introduced to allow
the meanings of character codes D0H to FFH to be
changed, depending on where in Europe the device was to
be used.
This bit is still used with the other language variants,
although the name East/West may not make much sense.
1998 Dec 14
40
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
character and independently of the foreground colour.
The background colour is changed from the position of the
background colour control character.
9.7
525-line operation
When used with 525-line display syncs, the devices modify
their displays such that the bottom line is omitted from
each character cell. The character sets have been
designed to be readable under these circumstances and
anyone designing OSD symbols is advised to consider this
mode of operation.
Displayable characters between a ‘flash’ (08H) and a
‘steady’ (09H) control character will flash on and off.
Displayable characters between a ‘conceal display’ (18H)
character and an alphanumerics or graphics control
character are displayed as spaces, unless the
TXT7.REVEAL bit is set.
9.8
On-Screen Display characters
Character codes 80H to 9FH are not addressed by the
teletext decoding hardware. An editor is available to allow
these characters to be redefined by the customer.
The ‘contiguous graphics’ (19H) and ‘separated graphics’
(1AH) characters control the way in which mosaic shapes
are displayed. The difference between the two is shown in
Fig.12.
The alternative character shapes in columns 8a and 9a
(SAA549x only) can be displayed when the ‘graphics’
serial attribute is set. This increases the number of
customer definable characters to 64.
Control characters encountered between a ‘hold graphics’
(1EH) control character and a ‘release graphics’ (1FH)
control character are displayed as the last character
displayed in graphics mode, rather than as spaces. From
the hold graphics character until the first character
displayed in graphics mode the held character is a space.
To ensure compatibility with devices only having 32 OSD
characters, the additional OSD characters are only
accessible when the TXT4.OSD BANK ENABLE bit is set.
If this bit is not set, the characters in columns 8 and 9 will
be displayed in both alphanumeric and graphics modes.
The ‘start box’ (0BH) and ‘end box’ (0AH) characters are
used to define teletext boxes. Two start box characters are
required to begin a teletext box, with the box starting
between the 2 characters. The box ends after an end box
character has been encountered. The display can be set
up so that different display modes are invoked inside and
outside teletext boxes e.g. text inside boxes but TV
outside. This is described in Section 9.13.
9.9
Control characters
Character codes 00H to 1FH, B0H to B7H and
BCH to BFH are interpreted as control characters which
can be used to change the colour of the characters, the
background colour, the size of characters, and various
other features. All control characters are normally
displayed as spaces.
The ‘normal size’ (0CH), ‘double height’ (0DH), ‘double
width’ (0EH) and ‘double size’ (0FH) control characters are
used to change the size of the characters displayed. If any
double height (or double size) characters are displayed on
a row the whole of the next row is displayed as spaces.
Double height display is not possible on either row 23 or
row 24.
The alphanumerical colour control characters
(00H to 07H) are used to change colour of the characters
displayed.
The graphics control characters (10H to 17H) change the
colour of the characters and switch the display into a mode
where the codes in columns 2, 3, 6 and 7 of the character
table (see the character table above) are displayed as the
block mosaic characters in columns 2a, 3a, 6a and 7a.
The display of mosaics is switched off using one of the
alphanumerics colour control characters.
The character in the position occupied by the right hand
half of a double width (or double size) character is ignored,
unless it is a control character in which case it takes effect
on the next character displayed. This allows double width
to be used to produce a display in which blank spaces do
not appear when character attributes are changed.
The ‘new background’ character (1DH) the background
colour of the display, sets the background colour equal to
the current foreground colour. The ‘black background’
character (1CH) changes the background colour to black
independently of the current foreground colour. The
background colour control characters in the upper half of
the code table (B0H to B7H) are additions to the normal
teletext control characters which allow the background
colour to be changed to any colour with a single control
The size implying OSD (BCH to BFH) control characters
are not standard teletext control characters and have been
included in this device to allow OSD messages to be
generated with the minimum disruption to the teletext page
stored in the memory. These characters are described in
full later in this document.
1998 Dec 14
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
This is because if two consecutive size implying OSD
control characters are used, the first starts the OSD box
and the second finishes the OSD box, and therefore no
OSD box is defined.
handbook, halfp
Quadruple width characters must not start in columns 37,
38 or 39 of the display since the whole of the character
cannot be displayed.
9.11 Page attributes
Row 25 of the basic page memory contains control data
from the page header of the page stored in the memory.
The bits which affect the display are the newsflash (C5),
subtitle (C6), suppress header (C7), inhibit display (C10)
and language control (C12 to 14) bits.
mosaics character 7FH
contiguous
mosaics character 7FH
separated
MGL117
If either the newsflash or the subtitle bit is set a different
SFR is used to define the display mode, as described in
Section 9.13.
Fig.12 Contiguous and separated mosaics.
The suppress header bit causes the header row (row 0) to
be displayed as if every character was a space and the
inhibit display bit has this effect on every display row.
9.10 Quadruple width display (SAA549x)
The language control bits cause certain character codes to
be interpreted differently, as described above.
Two successive double width control characters will
invoke quadruple width display. Quad width display is
terminated by another size control character.
9.12 Display modes
Any combination of two of the four controls which invoke
double width display (double width, double size, double
width OSD and double size OSD) can invoke quad width
display. If a double size control character is part of the
sequence, characters will be displayed in quad width and
double height.
The device signals the TVs display circuits to display the
R, G and B outputs of the device, rather than the video
picture, by outputting a logic 1 on the VDS output. The way
in which this signal is switched is controlled by the bits in
the TXT5 and TXT6 SFRs. There are 3 control functions:
text on, background on and picture on. Separate sets of
bits are used inside and outside teletext boxes so that
different display modes can be invoked. Also, different
SFRs are used depending on whether the newsflash (C5)
or subtitle (C6) bits in row 25 of the basic page memory are
set (SFR TXT6) or not (SFR TXT5). This allows the
software to set up the type of display required on
To ensure that broadcast teletext pages can be displayed
correctly, quadruple width will only be displayed if the
TXT4.QUAD WIDTH ENABLE bit is set. If this bit is not set,
two successive double width characters will invoke double
width display.
If quadruple width characters are to be used within OSD
boxes (see later section) then the first of the width
characters must be either ‘double width’ (OEH) or ‘double
size’ (OFH).
newsflash and subtitle pages (e.g. text inside boxes, TV
picture outside) this will be invoked without any further
software intervention when such a page is acquired.
1998 Dec 14
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
When teletext box control characters are present in the
page memory, whichever is relevant of the ‘Boxes On
Row 0’, ‘Boxes On Row 1 to 23’ and ‘Boxes On Row 24’
SFR bits in TXT17 must be set if the display mode is to
change in the box. These bits are present to allow boxes
in certain areas of the screen to be disabled so that teletext
boxes can be used for the display of OSD messages
without the danger of subtitles in boxes, which may also be
in the page memory, being displayed. The use of teletext
boxes for OSD messages has been superseded in this
device by the OSD box concept, described later, but these
bits remain to allow teletext boxes to be used, if required.
The readability of text can also be enhanced using
‘meshing’. Meshing causes the VDS signal to switch so
that when the text background colour should be displayed
every other pixel is displayed from the video picture. Text
foreground pixels are always displayed.
The TXT4.BMESH bit enables meshing on areas of the
screen within the text display area with black as the
background colour. The TXT4.CMESH bit has the same
effect on areas with other background colours. Meshing
can only be invoked in areas displayed in text mode i.e.
where the TXT5.TEXT IN and TXT5.BKGND IN bits are
both set to logic 1s, and in OSD boxes. Meshed text can
also be shadowed. Meshing is illustrated in Fig.13.
The COR bits in the TXT5 and TXT6 SFRs control when
the COR output of the device is activated (i.e. pulled
down). This output is intended to act on the TV’s display
circuits to reduce the contrast of the video display when it
is active. The result of contrast reduction is to improve the
readability of the text in a mixed text and video display.
The TXT4.TRANS bit causes areas of black background
colour to become transparent i.e. video is displayed
instead of black background. Black background
transparency can also only be invoked in areas displayed
in text mode i.e. where the TXT5.TEXT IN and
TXT5.BKGND IN bits are both set to a logic 1, and in OSD
boxes.
The bits in the TXT5 and TXT6 SFRs allow the display to
be set up so that, for example, the areas inside teletext
boxes will be contrast reduced when a subtitle is being
displayed but that the rest of the screen will be displayed
as normal video.
The operation of transparency mode on SAA5290M4A
devices and earlier, has subtly changed to align the
architecture with that of 10 page ETT text devices.
Setting the shadow TXT4.SHADOW ENABLE bit will add
a ‘south east’ shadow to the text, significantly enhancing
its readability in mix mode. Shadowing is illustrated in
Fig.13.
Previously, transparency mode only functioned inside
OSD boxes, this has been modified to include text mode
as well for the SAA5290M5/M5A and SAA5290AM5/M5A
devices.
Table 19 Display control bits
PICTURE ON
TEXT ON
BACKGROUND ON
EFFECT
text mode, black screen
text mode, background always black
text mode
0
0
0
1
1
1
0
1
1
0
1
1
X
0
1
X
0
1
TV mode
mixed text and TV mode
text mode, TV picture outside text area
1998 Dec 14
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Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
normal mix mode
SE shadowing
handbook, halfpage
meshing
meshing and shadowing
TV picture
black
text foreground colour
text background colour
MGL118
Fig.13 Meshing and shadowing.
Table 20 Enhanced display mode selection
SHADOW TRANS BMESH CMESH
DISPLAY
normal, unshadowed, unmeshed text
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
X
X
0
0
1
0
1
0
1
1
text with coloured backgrounds meshed, black background solid
text with coloured backgrounds solid, black background meshed
text with all backgrounds meshed
text with coloured backgrounds solid, black background transparent
text with coloured backgrounds meshed, black background transparent
shadowed text with coloured backgrounds meshed, black background
solid
1
0
1
0
shadowed text with coloured backgrounds solid, black background
meshed
1
1
0
1
1
1
0
shadowed text with all backgrounds meshed
X
shadowed text with coloured backgrounds solid, black background
transparent
1
1
X
1
shadowed text with coloured backgrounds meshed, black background
transparent
1998 Dec 14
44
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
Screen colour is displayed from 10.5 to 62.5 µs after the
active edge of the Hsync input and on TV lines 23 to 310
inclusive, for a 625-line display, and lines 17 to 260
inclusive for a 525-line display.
9.13 On-Screen Display boxes
The size implying OSD control characters (BCH to BFH)
are intended to allow OSD messages to be displayed with
the minimum disruption to the teletext page stored in the
page memory. OSD boxes are not the same as teletext
boxes created using the teletext boxing control characters
(0AH and 0BH).
When the screen colour has been redefined, no TV picture
is displayed so the FRAME de-interlace output can be
activated, if the SFR bits controlling FRAME are set up to
allow this.
When one of these characters occurs the display size
changes appropriately (to normal size for BCH, double
height for BDH, double width for BEH and double size for
BFH) and an OSD box starts from the next character
position (‘set after’). The OSD box ends either at the end
of the row of text or at the next size implying OSD
character. When an OSD box is ended using another size
implying OSD character the box ends at the position of the
control character (‘set at’). This arrangement allows
displays to be created without blank spaces at the ends of
the OSD boxes.
Table 21 Screen colours
SCREEN
COL 2
SCREEN
COL 1
SCREEN
COL 0
SCREEN
COLOUR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
transparent
red
green
yellow
blue
To prevent control characters from the teletext page
affecting the display of the OSD message the flash,
teletext box, conceal, separated graphics, twist and hold
graphics functions are all reset at the start of an OSD box,
as they are at the start of the row. In order to allow the most
commonly used display attributes to be set up before the
box starts the foreground colour, background colour and
mosaics on/off attributes are not reset.
magenta
cyan
white
9.15 Redefinable colours (SAA549x)
The CLUT SFR can be used to load a colour look-up table
(CLUT) which allows the 8 foreground colours and
8 background colours to be redefined. Each entry has
6 bits, 2 for each colour component, giving a total palette
of 64 colours from which to choose.
The text within an OSD box is always displayed in text
mode i.e. as if the Text On and Bkgnd On bits are both set
to a logic 1. The type of display produced inside an OSD
box is, therefore, dependent on the states of the
TXT4.SHADOW ENABLE, TXT4.TRANS ENABLE,
TXT4.BMESH ENABLE and TXT4.CMESH ENABLE
register bits, as described previously. OSD boxes can only
be displayed in TV mode i.e. when the Picture On SFR bit
is a logic 1 and the Text On SFR bit is a logic 0, both inside
and outside text boxes and for both normal and
newsflash/subtitle pages.
When the CLUT.CLUT ENABLE bit is a logic 0 the CLUT
is disabled and the device will display the normal, full
intensity, teletext colours.
The meaning of the least significant 6 bits of the CLUT
SFR depends on the setting of the CLUT.CLUT
ADDRESS bit when the register is written to. If the
CLUT.CLUT ADDRESS bit is a logic 1, the 4 LSBs of the
SFR contain the address of the entry in the CLUT which
will be modified by subsequent writes to the CLUT SFR. If
the CLUT.CLUT ADDRESS bit is a logic 0, the 6 LSBs of
the SFR define a colour which will be written into the CLUT
at the address defined by a previous write to the CLUT
SFR. An entry is written into the CLUT whenever the CLUT
SFR is written to, unless the CLUT.CLUT ADDRESS bit is
set.
The display of OSD boxes is not affected by the C7,
suppress header, and C10, inhibit display, control bits
stored in row 25 of the page memory.
9.14 Screen colour
The register bits TXT17.SCREEN COL2 to COL0 can be
used to define a colour to be displayed in place of TV
picture and the black background colour. If the bits are all
set to logic 0s, the screen colour is defined as ‘transparent’
and the TV picture and background colour are displayed
as normal.
Table 22 shows which CLUT entry corresponds to which
full intensity colour. The contents of the CLUT are not reset
at power-up and should be defined by the software before
the CLUT is enabled.
1998 Dec 14
45
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
This feature can be used for either a user controlled
‘enlarge’ facility or to provide very large characters for
OSD.
Table 22 CLUT Address
CLUT ADDRESS FULL INTENSITY EQUIVALENT
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
black foreground
red foreground
The display of rows 0 to 23 can be disabled by setting the
TXT0.DISLAY STATUS ROW ONLY bit.
green Foreground
yellow foreground
blue foreground
The Fastext prompt row (packet 24) can be displayed from
the extension packet memory by setting the
TXT0.DISPLAY X/24 bit. When this bit is set the data
displayed on display row 24 is taken from row 0 in the
extension packet memory.
magenta foreground
cyan foreground
white foreground
black background
red background
When the display from extension packet block option is
enabled, the display will revert to row 24 of the basic page
memory if bit 3 of the link control byte in packet 27 is set.
green background
yellow background
blue background
magenta background
cyan background
white background
9.18 Display timing
The display synchronises to the device’s Hsync and Vsync
inputs. A typical configuration is shown in Fig.14.
The Hsync and Vsync signals are derived from the signals
driving the deflection coils of the TV. The CVBS input is
only used to extract teletext from. Locking the display to
the signals from the scan circuits allows the device give a
stable display under almost all signal conditions.
9.16 Cursor
The polarity of the input signals which the device is
expecting can be set using the TXT1.H polarity and
TXT1.V polarity bits. If the polarity bit is a logic 0, a positive
going signal is expected and if it is a logic 1, a negative
going signal is expected.
If the TXT7.CURSOR ON bit is set, a cursor is displayed.
The cursor operates by reversing the background and
foreground colours in the character position pointed to by
the active row and column bits in the TXT9 and TXT10
SFRs.
Setting the TXT9.CURSOR FREEZE bit, causes the
cursor to stay in its current position, no matter what
happens to the active row and column positions. This
means that the software can read data from the memory
(e.g. TOP table information) without affecting the position
of the cursor.
9.19 Horizontal timing
Every time an Hsync pulse is received the display
resynchronizes to its leading edge. To get maximum
display stability, the Hsync input must have fast edges,
free of noise to ensure that there is no uncertainty in the
timing of the signal to which the display synchronisation
circuits must lock.
9.17 Other display features
The display area starts 17.2 µs into the line and lasts for
40 µs. The display area will be in the centre of the screen
if the Hsync pulse is aligned with line flyback signal.
Therefore, it is better to derive Hsync directly from the line
flyback or from an output of the line output transformer
than from, say, slicing the sandcastle signal as this would
introduce delays which would shift the display to the right.
Setting the TXT7.DOUBLE HEIGHT bit causes the normal
height of all display characters to be doubled and the
whole of the display area to be occupied by half of the
display rows. Characters normally displayed double height
will be displayed quadruple height when this bit is set.
Rows 12 to 24 can be enlarged, rather then rows 0 to 11,
by setting the TXT7.TOP/BOTTOM bit.
1998 Dec 14
46
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
Setting the TXT0.DISABLE FRAME bit forces the FRAME
output to a logic 0. Setting the TXT0.AUTO FRAME bit
causes the FRAME output to be active when just text is
being displayed but to be forced to a logic 0 when any
video is being displayed. This allows the de-interlacing
function to take place with virtually no software
intervention.
9.20 Vertical timing
The vertical display timing also resynchronizes to every
sync pulse received. This means that the device can
produce a stable display on both 625 and 525-line
screens. Display starts on the 41st line of each field and
continues for 250 lines, or until the end of the field.
Normally, television displays are interlaced, i.e. only every
other TV line is displayed on each field. It is normal to
de-interlace teletext displays to prevent the displayed
characters flickering up and down. In many TV designs this
is achieved by modulating the vertical deflection current in
such a way that odd fields are shifted up and even fields
are shifted down on the screen so that lines 1 and 314,
2 and 315 etc. are overlaid. The FRAME output is
provided to facilitate this.
Some TV architectures do not use the FRAME output but
accomplish the de-interlacing function in the vertical
deflection IC, under software control, by delaying the start
of the scan for one field by half a line, so that lines in this
field are moved up by one TV line. In such TVs, Vsync may
occur in the first half of the line at the start of an odd field
and in the second half of the line at the start of an even
field. In order to obtain correct de-interlacing in these
circumstances, the TXT1.FIELD POLARITY must be set
to reverse the assumptions made by the vertical timing
circuits on the timing of Vsync in each field. The start of the
display may be delayed by a line. The ‘Field Polarity’ bit
does not affect the FRAME output.
The odd/even field decision is made on the timing between
the active edge of Hsync and the active edge of the Vsync
pulses. The active edge is programmed using the TXT1
register H polarity and V polarity bits.
The timing windows are designed to prevent the FRAME
output oscillating from odd to even, these are detailed
below:
handbook, halfpage
CVBS
RGB
VIDEO
• If H to V is 0 to 16 µs then output is even (FRAME = 0)
DECODING
CRT
TUNER/IF
• If H to V is 16 to 32 µs then output is based on previous
field (i.e. previous value of FRAME)
DISPLAY
HSYNC, VSYNC
SYNC
CIRCUITS
• If H to V is 32 to 48 µs then output is odd (FRAME = 1)
RGB, VDS
• If H to V is 48 to 64 µs then output is based on previous
field (i.e. previous value of FRAME).
SAA5x9x
FRAME
MGK464
The algorithm used to derive Frame is such that a
consistent output will be obtained no matter where the
Vsync signal is relative to the Hsync signal, even if Vsync
occurs at the start and mid points of a line.
Fig.14 Timing configuration.
1998 Dec 14
47
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
9.21 Display position
The position of the display relative to the Hsync and Vsync
inputs can be varied over a limited range to allow for
optimum TV set-up.
The horizontal position is controlled by the X0 and X1 bits
in TXT16. Table 23 gives the time from the active edge of
the Hsync to the start of the display area for each setting
of X0 and X1.
Table 23 Display horizontal position
Hsync TO DISPLAY
X1
X0
(µs)
0
0
1
1
0
1
0
1
17.2
16.2
15.2
14.2
The line on which the display area starts depends on
whether the display is 625-line or 525-line and on the
setting of the Y0 to Y2 bits in TXT16. Table 24 gives the
first display line for each setting of Y0 to Y2, for both
625 and 525-line display.
On the other field, the display starts on the equivalent line.
Table 24 Display vertical position
FIRST LINE FOR DISPLAY
Y2
Y1
Y0
625-LINE
525-LINE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
42
44
46
48
34
36
38
40
28
30
32
34
20
22
24
26
1998 Dec 14
48
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
64 µs
23
lines
52 µs
∆Y
10.5
µs
∆X
40 µs
25
250
lines
287
lines lines
312
TEXT DISPLAY AREA
rows
40 characters
TV PICTURE AREA
FIELD SCANNING AREA
MGL122
Fig.15 625-line display format.
63.55 µs
52 µs
17
lines
∆Y
10.5
µs
∆X
40 µs
25
rows
225
lines
243
lines lines
263
TEXT DISPLAY AREA
40 characters
TV PICTURE AREA
FIELD SCANNING AREA
MGL123
Fig.16 525-line display format.
49
1998 Dec 14
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
9.22 Clock generator
9.23 Reset signal
The oscillator circuit is a single-stage inverting amplifier in
a Pierce oscillator configuration. The circuitry between
XTALIN and XTALOUT is basically an inverter biased to
the transfer point. A crystal must be used as the feedback
element to complete the oscillator circuitry. It is operated in
parallel resonance. XTALIN is the high gain amplifier input
and XTALOUT is the output. To drive the device externally
XTALIN is driven from an external source and XTALOUT
is left open-circuit.
The externally applied RESET signal (active HIGH) is
used to initialize the microcontroller core, in addition to the
teletext decoder. However, the teletext decoder
incorporates a separate internal reset function which is
activated on the rising edge of the analog supply pin, VDDA
.
The purpose of this internal reset circuit is to initialize the
teletext decoder when returning from the “text standby
mode”.
To ensure correct device operation for both “text standby”
and “power-on” modes, it is recommended that the internal
reset signal is active for between 10 to 15 ms. The RESET
signal should only be applied after the power supplies
(VDDM, VDDA and VDDT) and the external crystal oscillator
have stabilized.
handbook, halfpage
OSCGND
(1)
C1
XTALIN
(1)
C2
XTALOUT
MLC110
(1) The values of C1 and C2 depend on the crystal specification:
C1 = C2 = 2CL.
Fig.17 Oscillator circuit.
handbook, halfpage
OSCGND
not connected
XTALIN
external clock
XTALOUT
not connected
MLC111
Fig.18 Oscillator circuit driven from external source.
1998 Dec 14
50
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
10 CHARACTER SETS
The two Pan-European character sets are shown in Figs 20 and 21. The character sets for Cyrillic, Greek/Turkish,
Arabic/English/French, Thai, Arabic/Hebrew and Iranian are available on request.
A detailed description of the ETT family character sets can be found in the application note “SPG/AN97009, version 1.1”.
10.1 Pan-European
MGL133
Fig.19 Pan-European geographical coverage.
1998 Dec 14
51
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E/W = 0
1
E/W = 1
1 1
B
I
T
S
b
7
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
b
0
0
0
0
1
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
6
b
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
1
5
b
b
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
4
b
b
b
2 1
3
0
column
r
0
1
2
2a
3
3a
4
5
6
6a
7
7a
8
9
A
B
C
D
E
F
D
E
F
o
w
alpha -
numerics
black
back-
ground
black
graphics
black
nat
opt
nat
opt
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
OSD
OSD
OSD
OSD
alpha -
numerics
red
back
ground
red
graphics
red
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
alpha -
numerics
green
back-
ground
green
graphics
green
2
3
OSD
OSD
alpha -
numerics
yellow
back-
ground
yellow
graphics
yellow
nat
opt
OSD
OSD
OSD
OSD
alpha -
numerics
blue
back-
ground
blue
graphics
blue
nat
opt
4
alpha -
numerics
magenta
back-
ground
magenta
graphics
magenta
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
OSD
5
alpha -
numerics
cyan
back-
ground
cyan
graphics
cyan
6
back-
ground
white
alpha -
numerics
white
graphics
white
7
conceal
display
8
flash
contiguous
graphics
9
steady
separated
graphics
A
B
C
D
E
F
end box
start box
nat
opt
nat
opt
OSD
OSD
OSD
OSD
normal
size
OSD
black
back -
ground
nat
opt
nat
opt
normal
height
new
back -
ground
double
height
OSD
double
height
nat
opt
nat
opt
OSD
OSD
OSD
OSD
OSD
OSD
double
width
OSD
double
width
hold
graphics
nat
opt
nat
opt
double
size
OSD
double
size
release
graphics
nat
opt
MGR468
nat
opt
character dependent on the language of page, refer to National Option characters
customer definable On-Screen Display character
OSD
ahdnbok,uflapegwidt
Fig.20 Pan-European basic character set.
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
LANGUAGE
CHARACTER
5D 5E 5F
23
5B
5C
60
7B
7C
7D
7E
E/W C12 C13 C14
24
40
(1)
ENGLISH
GERMAN
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
(1)
(1)
SWEDISH
(1)
ITALIAN
(1)
(1)
FRENCH
0
0
1
1
0
1
1
0
SPANISH
TURKISH
ENGLISH
(1)
(2)
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
(1)
POLISH
(1)
GERMAN
(1)
ESTONIAN
(2)
GERMAN
(2)
GERMAN
(1)
SERBO-CROAT
(1)
CZECH
(1)
1
1
1
1
RUMANIAN
MGL125
(1) Languages in bold typeface conform to the EBU document SP492 or where superseded ETSI document pr ETS 300 706 with respect to
C12/C13/C14 definition.
(2) Languages in italic typeface are included for backward compatibility with previous generation of Philips teletext decoders.
Fig.21 National option characters.
1998 Dec 14
53
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
10.2 Cyrillic
MGL128
Fig.22 Cyrillic geographical coverage.
10.3 Greek/Turkish
MGL129
Fig.23 Greek/Turkish geographical coverage.
54
1998 Dec 14
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
10.4 Arabic/English/French
MGL131
Fig.24 Arabic/English/French geographical coverage.
10.5 Thai
MGL132
Fig.25 Thai geographical coverage.
55
1998 Dec 14
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
10.6 Arabic/Hebrew
b
MGL130
Fig.26 Arabic/Hebrew geographical coverage.
10.7 Iranian
MGR467
Fig.27 Iranian geographical coverage.
56
1998 Dec 14
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
supply voltage (all supplies)
CONDITIONS
MIN.
−0.3
MAX.
+6.5
UNIT
VDD
VI
V
V
V
input voltage (any input)
note 1
note 1
−0.3
−0.3
−
VDD + 0.5
VDD + 0.5
±10
VO
output voltage (any output)
output current (each output)
DC input or output diode current
operating ambient temperature
storage temperature
IO
mA
mA
°C
IIOK
Tamb
Tstg
−
±20
−20
−55
+70
+125
°C
Note
1. This value has an absolute maximum of 6.5 V independent of VDD
.
12 CHARACTERISTICS
VDD = 5 V ±10%; VSS = 0 V; Tamb = −20 to +70 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN.
TYP.
MAX.
UNIT
Supplies
VDDX
IDDM
IDDA
IDDT
supply voltage
4.5
−
5.0
20
35
40
5.5
35
50
65
V
microcontroller supply current
analog supply current
mA
mA
mA
−
teletext supply current
SAA5290, SAA5290A,
SAA5291, SAA5291A,
SAA5491
−
IDDT
teletext supply current
SAA5296/7, SAA5296/7A,
SAA5496/7
−
50
80
mA
Digital inputs
RESET, EA
VIL
VIH
ILI
LOW-level input voltage
−0.3
−
−
−
−
0.2VDD − 0.1
V
HIGH-level input voltage
input leakage current
input capacitance
0.7VDD
−10
−
VDD + 0.3
V
VI = 0 to VDD
+10
4
µA
pF
CI
HSYNC AND VSYNC
Vthf
Vthr
VHYS
CI
switching threshold falling
0.2VDD
−
−
V
switching threshold rising
hysteresis voltage
−
−
−
−
0.8VDD
V
0.33VDD
−
V
input capacitance
−
4
pF
1998 Dec 14
57
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital outputs
R, G AND B; note 1
VOL
VOH
ZO
CL
IO
LOW-level output voltage
HIGH-level output voltage
output impedance
IOL = 2 mA
0
V
−
−
−
−
−
0.2
V
IOH = −2 mA
RGBREF − 0.3 VRGBREF VRGBREF + 0.4 V
−
−
−
−
150
50
Ω
load capacitance
pF
mA
ns
DC output current
−4
tr
output rise time
between 10 and 90%;
CL = 50 pF
20
tf
output fall time
between 90 and 10%;
CL = 50 pF
−
−
20
ns
VDS
VOL
VOH
CL
LOW-level output voltage
HIGH-level output voltage
load capacitance
IOL = 1.6 mA
0
V
−
−
−
−
−
−
0.2
V
IOH = −1.6 mA
DD − 0.3
VDD + 0.4
V
50
20
pF
ns
tr
output rise time
between 10 and 90%;
CL = 50 pF
tf
output fall time
between 90 and 10%;
CL = 50 pF
−
−
−
−
−
−
20
ns
ns
V
R, G, B AND VDS
tskew skew delay between any two
pins
20
COR (OPEN-DRAIN OUTPUT)
VOH
HIGH-level pull-up output
VDD
voltage
VOL
IOL
CL
LOW-level output voltage
LOW-level output current
load capacitance
IOL = 2 mA
0
−
−
−
−
−
0.5
2
V
mA
pF
25
FRAME, RD, WR, ALE, PSEN, AD0 TO AD7, A8 TO A15
VOH
VOL
IOL
HIGH-level output voltage
LOW-level output voltage
LOW-level output current
load capacitance
IOL = 8 mA
0
−
−
−
−
0.5
VDD
+8
V
IOL = −8 mA
V
DD − 0.5
V
−8
mA
pF
CL
−
100
1998 Dec 14
58
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
SYMBOL
Digital input/outputs
P0.0 TO P0.4, P0.7, P1.0 TO P1.5, P2.0 TO P2.7 AND P3.0 TO P3.4
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIL
VIH
CI
LOW-level input voltage
HIGH-level input voltage
input capacitance
−0.3
−
−
−
−
−
0.2VDD − 0.1
V
0.2VDD + 0.9
VDD + 0.3
V
−
0
−
4
pF
V
VOL
CL
LOW-level output voltage
load capacitance
IOL = 3.2 mA
0.45
50
pF
P0.5 AND P0.6
VIL
VIH
CI
LOW-level input voltage
−0.3
−
−
−
−
−
0.2VDD − 0.1
V
HIGH-level input voltage
input capacitance
0.2VDD + 0.9
VDD + 0.3
V
−
0
−
4
pF
V
VOL
CL
LOW-level output voltage
load capacitance
IOL = 10 mA
0.45
50
pF
P1.6 AND P1.7
VIL
VIH
CI
LOW-level input voltage
−0.3
3.0
−
−
−
−
−
−
−
+1.5
VDD + 0.3
5
V
HIGH-level input voltage
input capacitance
V
pF
V
VOL
CL
tf
LOW-level output voltage
load capacitance
IOL = 3 mA
0
0.5
−
400
pF
ns
output fall time
between 3 and 1 V
−
200
Analog inputs
CVBS0 AND CVBS1
Vsync
sync voltage amplitude
0.1
0.7
0.3
1.0
0.6
1.4
V
V
Vvid(p-p)
video input voltage amplitude
(peak-to-peak value)
Zsource
VIH
ZI
source impedance
HIGH level input voltage
input impedance
−
−
250
Ω
3.0
2.5
−
−
VDD + 0.3
V
5.0
−
−
kΩ
pF
CI
input capacitance
10
IREF
Rgnd
resistor to ground
−
27
−
kΩ
RGBREF; note 1
VI
II
input voltage
DC input current
−0.3
−
−
VDD
12
V
−
mA
1998 Dec 14
59
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
REF+, REF−
VIH
ZI
HIGH level input voltage
input impedance
3.0
2.5
−
−
VDD + 0.3
V
5.0
−
kΩ
pF
CI
input capacitance
−
10
ADC0, ADC1 and ADC2
VIL
LOW-level input voltage
−0.3
−
VDD
V
Analog input/output
BLACK
CBLACK
VBLACK
storage capacitor to ground
−
100
−
nF
V
black level voltage for nominal
sync amplitude
1.8
2.15
2.5
ILI
input leakage current
−10
−
+10
µA
Crystal oscillator
OSCIN
VIL
VIH
CI
LOW-level input voltage
−0.3
−
−
−
0.2VDD − 0.1
VDD + 0.3
10
V
HIGH-level input voltage
input capacitance
0.7VDD
V
−
pF
OSCOUT
CO
output capacitance
−
−
10
pF
CRYSTAL SPECIFICATION; note 2
fxtal
CL
C1
C0
Rr
nominal frequency
load capacitance
series capacitance
parallel capacitance
resonance resistance
temperature range
adjustment tolerance
drift
−
12
32
18.5
4.9
35
+25
−
−
MHz
pF
fF
−
−
T
amb = 25 °C
amb = 25 °C
−
−
T
−
−
pF
Ω
Tamb = 25 °C
−
−
Txtal
Xj
−20
−
+70
°C
Tamb = 25 °C
±50 × 10-6
±30 × 10-6
Xd
−
−
Notes
1. All RGB current is sourced from the RGBREF pin. The maximum effective series resistance between RGBREF and
the R, G and B pins is 150 Ω.
2. Crystal order number 4322 143 05561.
1998 Dec 14
60
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
13 CHARACTERISTICS FOR THE I2C-BUS INTERFACE
SYMBOL
PARAMETER
INPUT
OUTPUT
I2C-BUS SPECIFICATION
SCL timing
tHD;STA
tLOW
tHIGH
trC
START condition hold time
SCL LOW time
≥4.0 µs
note 1
note 1
≥4.0 µs; note 2 ≥4.0 µs
note 3 ≤1.0 µs
≤0.3 µs; note 4 ≤0.3 µs
≥4.0 µs
≥4.7 µs
≥4.0 µs
≤1.0 µs
≤0.3 µs
≥4.7 µs
SCL HIGH time
SCL rise time
tfC
SCL fall time
SDA timing
tSU;DAT1
tHD;DAT
tSU;STA
tSU;STO
tBUF
data set-up time
≥250 ns
≥0 ns
note 1
note 1
note 1
note 1
note 1
note 3
≥250 ns
≥0 ns
data hold time
repeated START set-up time
STOP condition set-up time
bus free time
≥4.7 µs
≥4.0 µs
≥4.7 µs
≤1.0 µs
≤0.3 µs
≥4.7 µs
≥4.0 µs
≥4.7 µs
≤1.0 µs
trD
SDA rise time
tfD
SDA fall time
≤0.3 µs; note 4 ≤0.3 µs
Notes
1. This parameter is determined by the user software. It must comply with the I2C-bus specification.
2. This value gives the auto-clock pulse length which meets the I2C-bus specification for the special crystal frequency.
Alternatively, the SCL pulse must be timed by software.
3. The rise time is determined by the external bus line capacitance and pull-up resistor. It must be less than 1 µs.
4. The maximum capacitance on bus lines SDA and SCL is 400 pF.
1998 Dec 14
61
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repeated START condition
START or repeated START condition
START condition
t
STOP condition
SU;STA
t
rD
0.7V
DD
SDA
(input / output)
0.3V
DD
t
BUF
t
t
t
fC
rC
fD
t
SU;STO
0.7V
DD
SCL
(input / output)
0.3V
DD
t
SU;DAT3
t
t
t
t
t
HD;DAT
HD;STA
LOW
HIGH
SU;DAT1
t
MLC104
SU;DAT2
Fig.28 I2C-bus interface timing.
ahdnbok,uflapegwidt
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
14 QUALITY AND RELIABILITY
This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated
Circuits SNW-FQ-611-Part E”; “Quality Reference Handbook, order number 9398 510 63011”. The principal
requirements are shown in Table 25 to 28.
Table 25 Acceptance tests per lot; note 1
TEST
Mechanical
Electrical
REQUIREMENTS
REQUIREMENTS
cumulative target: <80 ppm
cumulative target: <80 ppm
Table 26 Processability tests (by package family); note 2
TEST
solderability
mechanical
<7% LTPD
<15% LTPD
solder heat resistance <15% LTPD
Table 27 Reliability tests (by process family); note 3
TEST
CONDITIONS
REQUIREMENTS
operational life
humidity life
168 hours at Tj = 150 °C
<1000 FPM at Tj = 70 °C
temperature, humidity, bias 1000 hours, 85 °C, 85% RH
<2000 FPM
(or equivalent test)
temperature cycling
performance
Tstg(min) to Tstg(max)
<2000 FPM
Table 28 Reliability tests (by device type)
TEST
CONDITIONS
REQUIREMENTS
ESD and latch-up
ESD Human body model 100 pF, 1.5 kΩ
ESD Machine model 200 pF, 0 Ω
latch-up
2000 V
200 V
100 mA, 1.5 × VDD (absolute maximum)
Notes to Tables 25, 26 and 27
1. ppm = fraction of defective devices, in parts per million.
2. LTPD = Lot Tolerance Percent Defective.
3. FPM = fraction of devices failing at test condition, in failures per million.
1998 Dec 14
63
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a
V
V
40 V
DD
DD
V
A0
A1
A2
DD
RC
PH2369
V
tune
EEPROM
PCF8582E
SCL
SDA
V
V
DD
DD
V
SS
47 µF
100 nF
V
DD
V
V
SS
SS
V
V
SS
SS
V
SS
V
DD
P2.0/TPWM
P2.1/PWM0
P2.2/PWM1
P2.3/PWM2
P2.4/PWM3
P2.5/PWM4
P2.6/PWM5
P2.7/PWM6
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
P1.5
52
1
P1.4
51
brightness
contrast
2
P1.7/SDA
3
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
TV
control
signals
P1.6/SCL
saturation
hue
4
P1.3/T1
5
P1.2/INT0
P1.1/T0
volume (L)
volume (R)
6
7
P1.0/INT1
8
V
V
V
SS
DD
DDM
IR
RECEIVER
9
V
afc
RESET
reset pulse
12MHz
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
XTALOUT
XTALIN
V
DD
V
DD
22 pF
V
OSCGND
SSD
47 µF
100 nF
V
V
SAA5x9x
V
SS
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
DD
DDT
V
V
SS
DDA
VSYNC
HSYNC
VDS
field flyback
line flyback
R
V
SS
G
V
DD
B
1 kΩ
V
to TV's
display
circuits
SSA
RGBREF
P3.4/PWM7
COR
V
SS
CVBS0
CVBS1
BLACK
IREF
V
DD
100 nF
100 nF
V
29
28
27
SS
V
SSD
CVBS (IF)
V
SS
FRAME
CVBS (SCART)
27 kΩ
100 nF
MGK463
V
SS
Fig.29 Application diagram.
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
A ferrite bead or inductor with resistive characteristics at
high frequency may be utilized in the supply line close to
the decoupling capacitor to provide a high impedance.
To prevent pollution by conduction onto signal lines (which
then may radiate), signals connected to the +5 V supply
via a pull-up resistor should not be connected to the IC
side of the ferrite component.
16 EMC GUIDELINES
Optimization of circuit return paths and minimization of
common mode noise will be assisted by using a
double-sided PCB with a low induction ground plane.
On a single-sided PCB a local ground plane under the
whole IC should be present, as shown in Fig.30. This
should be connected by the widest possible connection
back to the PCB ground connection and bulk electrolytic
decoupling capacitor. It should preferably not connect to
other grounds on the way and no wire links should be
present in this connection. The use of wire links increases
ground bounce by introducing inductance into the ground.
OSCGND should connected only to the crystal load
capacitors and not the local or circuit GND.
Keep physical connection distances to associated active
devices short.
Route output traces with close proximity mutually coupled
ground return paths.
The supply pins can be decoupled at the pin to the ground
plane under the IC. This is easily accomplished using
surface mount capacitors, which are more effective than
leaded components at high frequency. Using a device
socket will unfortunately add to the area and inductance of
the external bypass loop.
GND +5 V
electrolytic decoupling capacitor (2.2 µF)
wire links
other
GND
connections
SM decoupling capacitors (22 to 100 nF)
V
V
V
DDT
DDA
DDM
under-IC GND plane
under-IC GND plane
GND connection
note: no wire links
IC (SAA5290)
V
V
SSA
SSD
MGL127
Fig.30 Power supply and GND connections for SOT247-1.
1998 Dec 14
65
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
17 PACKAGE OUTLINES
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
D
M
E
A
2
A
L
A
1
c
e
(e )
1
w M
Z
b
1
M
H
b
52
27
pin 1 index
E
1
26
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
47.9
47.1
14.0
13.7
3.2
2.8
15.80
15.24
17.15
15.90
mm
5.08
0.51
4.0
1.778
15.24
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
90-01-22
95-03-11
SOT247-1
1998 Dec 14
66
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT318-2
y
X
A
64
65
41
40
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
w M
p
θ
pin 1 index
L
p
b
L
80
25
detail X
1
24
w M
Z
v
M
M
D
A
B
b
p
e
D
B
H
v
D
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.90
0.05 2.65
0.45 0.25 20.1 14.1
0.30 0.14 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.0
0.6
1.2
0.8
mm
3.2
0.25
0.8
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT318-2
1998 Dec 14
67
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
18 SOLDERING
18.1 Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
18.3.2 WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
18.2 Through-hole mount packages
18.2.1 SOLDERING BY DIPPING OR BY SOLDER WAVE
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
18.2.2 MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
300 and 400 °C, contact may be up to 5 seconds.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
18.3 Surface mount packages
18.3.1 REFLOW SOLDERING
18.3.3 MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1998 Dec 14
68
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
18.4 Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
WAVE
REFLOW(1) DIPPING
suitable(2)
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(3)
MOUNTING
PACKAGE
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
−
suitable
Surface mount
BGA, SQFP
suitable
suitable
suitable
suitable
suitable
−
−
−
−
−
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(4)(5)
not recommended(6)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1998 Dec 14
69
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
19 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
20 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Dec 14
70
Philips Semiconductors
Preliminary specification
Economy teletext and TV microcontrollers
SAA5x9x family
NOTES
1998 Dec 14
71
Philips Semiconductors – a worldwide company
Argentina: see South America
Middle East: see Italy
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Fax. +43 160 101 1210
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
Norway: Box 1, Manglerud 0612, OSLO,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belgium: see The Netherlands
Brazil: see South America
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Portugal: see Spain
Romania: see Italy
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Colombia: see South America
Czech Republic: see Austria
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Slovakia: see Austria
Slovenia: see Italy
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Spain: Balmes 22, 08007 BARCELONA,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/00/02/pp72
Date of release: 1998 Dec 14
Document order number: 9397 750 04246
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