SAA5553PS_技术文档

INTEGRATED CIRCUITS

DATA SHEET

SAA55xx

Standard TV microcontrollers with

On-Screen Display (OSD)

Preliminary speciﬁcation

1999 Oct 27

File under Integrated Circuits, IC02

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

CONTENTS

17.2

17.3

17.4

Memory mapping

Addressing memory

Page clearing

1

2

3

4

5

6

FEATURES

GENERAL DESCRIPTION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAM

18

DATA CAPTURE

18.1

18.2

18.3

18.4

Data Capture Features

Broadcast service data detection

VPS acquisition

WSS acquisition

PINNING INFORMATION

19

DISPLAY

6.1

6.2

Pinning

Pin description

19.1

19.2

19.3

19.4

19.5

19.6

19.7

19.8

Display features

Display mode

Display feature descriptions

Character and attribute coding

Screen and global controls

Screen colour

Text display control

Display positioning

Character set

Display synchronization

Video/data switch (fast blanking) polarity

Video/data switch adjustment

RGB brightness control

Contrast reduction

7

MICROCONTROLLER

Microcontroller features

MEMORY ORGANISATION

7.1

8

8.1

8.2

8.3

8.4

8.5

8.6

Security bits - program and verify

RAM organisation

Data memory

SFR memory

Character set feature bits

External (auxiliary) memory

19.9

19.10

19.11

19.12

19.13

19.14

9

POWER-ON RESET

10

REDUCED POWER MODES

20

MEMORY MAPPED REGISTERS

LIMITING VALUES

10.1

10.2

10.3

Idle mode

Power-down mode

Standby mode

21

22

CHARACTERISTICS

11

I/O FACILITY

22.1

23

I²C-bus characteristics

11.1

11.2

11.3

11.4

I/O ports

Port type

Port alternate functions

LED support

QUALITY AND RELIABILITY

23.1

23.2

23.3

Group A

Group B

Group C

12

INTERRUPT SYSTEM

24

25

APPLICATION INFORMATION

12.1

12.2

12.3

12.4

Interrupt enable structure

Interrupt enable priority

Interrupt vector address

Level/edge interrupt

ELECTROMAGNETIC COMPATIBILITY

(EMC) GUIDELINES

26

PACKAGE OUTLINE

SOLDERING

13

TIMER/COUNTER

27

14

WATCHDOG TIMER

27.1

Introduction to soldering through-hole mount

packages

Soldering by dipping or by solder wave

Manual soldering

Suitability of through-hole mount IC packages

for dipping and wave soldering methods

14.1

15

Watchdog Timer operation

PULSE WIDTH MODULATORS

27.2

27.3

27.4

15.1

15.2

15.3

PWM control

Tuning Pulse Width Modulator (TPWM)

Software ADC (SAD)

I²C-BUS SERIAL I/O

I²C-bus port selection

MEMORY INTERFACE

Memory structure

28

29

30

DEFINITIONS

16

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I²C COMPONENTS

16.1

17

17.1

1999 Oct 27

2

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

1

FEATURES

• Single-chip microcontroller with integrated On-Screen

Display (OSD)

• Versions available with integrated data capture

• One Time Programmable (OTP) memory for both

program Read Only Memory (ROM) and character sets

2

GENERAL DESCRIPTION

• Single power supply: 3.0 to 3.6 V

The SAA55xx standard family of microcontrollers are a

derivative of the Philips industry-standard 80C51

microcontroller, and are intended for use as the central

control mechanism in a television receiver. They provide

control functions for the television system, OSD, and some

versions include an integrated data capture and display

function.

• 5 V tolerant digital inputs and I/O

• 29 I/O lines via individual addressable controls

• Programmable I/O for push-pull, open-drain and

quasi-bidirectional

• Two port lines with 8 mA sink (at <0.4 V) capability, for

direct drive of Light Emitting Diode (LED)

The data capture hardware has the capability of decoding

and displaying both 525 and 625-line World System

Teletext (WST), Video Programming System (VPS) and

Wide Screen Signalling (WSS) information. The same

display hardware is used both for Teletext and OSD, which

means that the display features available give greater

flexibility to differentiate the TV set.

• Single crystal oscillator for microcontroller, OSD and

data capture

• Power reduction modes: Idle and Power-down

• Byte level I²C-bus with dual port I/O

• Pin compatibility throughout family

• Operating temperature: −20 to +70 °C.

The SAA55xx standard family offers a range of

functionality from non-text, 16-kbyte program ROM and

256-byte Random Access Memory (RAM), to a 10-page

text version, 64-kbyte program ROM and 1.2-kbyte RAM.

3

QUICK REFERENCE DATA

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Supply

V_DDX

I_DDP

any supply voltage (V_DDto V_SS

periphery supply current

core supply current

)

3.0

3.3

3.6

V

1

−

mA

MHz

°C

I_DDC

−

15

18

I_DDC(id)

I_DDC(pd)

I_DDC(stb)

I_DDA

Idle mode core supply current

−

4.6

0.76

5.11

45

6

Power-down mode core supply current

Standby mode core supply current

analog supply current

−

1

−

6.50

48

−

I_DDA(id)

I_DDA(pd)

I_DDA(stb)

f_xtal

Idle mode analog supply current

Power-down mode analog supply current

Standby mode analog supply current

crystal frequency

−

0.87

0.45

0.95

12

1.0

0.7

1.20

−

T_amb

operating ambient temperature

storage temperature

−20

−55

−

+70

+125

T_stg

−

°C

1999 Oct 27

3

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

4

ORDERING INFORMATION

PACKAGE⁽²⁾

TEXT

RAM

TYPE NUMBER⁽¹⁾

ROM

PAGES

NAME

DESCRIPTION

VERSION

SAA5500PS/nnnn

SAA5501PS/nnnn

SAA5502PS/nnnn

SAA5503PS/nnnn

SAA5520PS/nnnn

SAA5521PS/nnnn

SAA5522PS/nnnn

SAA5523PS/nnnn

SAA5551PS/nnnn

SAA5552PS/nnnn

SAA5553PS/nnnn

SDIP52 plastic shrink dual in-line package; SOT247-1 16-kbyte

256-byte

512-byte

256-byte

512-byte

256-byte

512-byte

750-byte

1-kbyte

−

52 leads (600 mil)

32-kbyte

48-kbyte

64-kbyte

16-kbyte

32-kbyte

48-kbyte

64-kbyte

32-kbyte

48-kbyte

64-kbyte

−

1

750-byte

1-kbyte

10

1.2-kbyte

Notes

1. ‘nnnn’ is a four digit number uniquely referencing the microcontroller program mask.

2. For details of the LQFP100 package, please contact your local regional office for availability.

1999 Oct 27

4

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

5

BLOCK DIAGRAM

handbook, full pagewidth

TV CONTROL

AND

2

I C-bus, general I/O

INTERFACE

ROM

(16 TO 64-KBYTE)

MICROPROCESSOR

(80C51)

SRAM

(256-BYTE)

DRAM

MEMORY

(3 TO 12-KBYTE)

INTERFACE

R

G

DATA

CAPTURE

DISPLAY

CVBS

B

VDS

DATA

CAPTURE

TIMING

VSYNC

HSYNC

DISPLAY

TIMING

GSA029

Fig.1 Block diagram (top level architecture).

1999 Oct 27

5

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

6

PINNING INFORMATION

Pinning

6.1

handbook, halfpage

P2.0/TPWM

1

2

3

4

5

6

7

8

9

52 P1.5/SDA1

51 P1.4/SCL1

50 P1.7/SDA0

49 P1.6/SCL0

48 P1.3/T1

P2.1/PWM0

P2.2/PWM1

P2.3/PWM2

P2.4/PWM3

P2.5/PWM4

P2.6/PWM5

P2.7/PWM6

P3.0/ADC0

47 P1.2/INT0

46 P1.1/T0

45 P1.0/INT1

44

V

DDP

P3.1/ADC1 10

P3.2/ADC2 11

P3.3/ADC3 12

43 RESET

42 XTALOUT

41 XTALIN

40 OSCGND

V

13

SSC

SAA55xx

P0.0 14

P0.1 15

P0.2 16

P0.3 17

P0.4 18

P0.5 19

P0.6 20

P0.7 21

39

38

V

DDC

SSP

37 VSYNC

36 HSYNC

35 VDS

34

33

32

31

R

G

B

V

22

SSA

DDA

CVBS0 23

CVBS1 24

30 P3.4/PWM7

29 COR

SYNC_FILTER 25

IREF 26

28 VPE

27 FRAME

MBK951

Fig.2 SDIP52 pin configuration.

6

1999 Oct 27

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

handbook, full pagewidth

P2.7/PWM6

P3.0/ADC0

n.c.

1

2

3

4

5

6

7

8

9

V

75

DDP

74 n.c.

73 RESET

P3.1/ADC1

P3.2/ADC2

P3.3/ADC3

n.c.

72

71

XTALOUT

70 XTALIN

OSCGND

n.c.

69

68

67

n.c.

n.c. 10

66 n.c.

V

11

n.c.

V

65

64

63

SSC

V

12

SSP

P0.5 13

n.c. 14

n.c. 15

P0.0 16

P0.1 17

P0.2 18

n.c. 19

n.c. 20

n.c. 21

P0.3 22

n.c. 23

P0.4 24

P3.7 25

SAA55xx

DDC

62 VPE_2

n.c.

V

61

60

59

SSP

P3.6

58 n.c.

n.c.

57

56

55 VSYNC

54 P3.5

HSYNC

VDS

53

52

51 n.c.

GSA001

Fig.3 LQFP100 pin configuration.

7

1999 Oct 27

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

6.2

Pin description

Table 1 SDIP52 and LQFP100 packages

SYMBOL

TYPE

DESCRIPTION

SDIP52

LQFP100

P2.0/TPWM

P2.1/PWM0

P2.2/PWM1

P2.3/PWM2

P2.4/PWM3

P2.5/PWM4

P2.6/PWM5

P2.7/PWM6

P3.0/ADC0

P3.1/ADC1

P3.2/ADC2

P3.3/ADC3

P3.4/PWM7

P3.5

1

2

100

93

94

95

96

97

98

1

I/O

−

Port 2. 8-bit programmable bidirectional port with

alternative functions.

3

P2.0/TPWM is the output for the 14-bit high precision

PWM and P2.1/PWM0 to P2.7/PWM6 are the outputs

for the 6-bit PWMs 0 to 6.

4

5

6

7

8

9

2

Port 3. 8-bit programmable bidirectional port with

alternative functions.

10

11

12

30

−

4

5

P3.0/ADC0 to P3.3/ADC3 are the inputs for the

software ADC facility and P3.4/PWM7 is the output for

the 6-bit PWM7. P3.5 to P3.7 have no alternative

functions and are only available with the LQFP100

package.

6

44

54

59

25

11

16

17

18

22

24

13

28

29

30

31

32

P3.6

−

P3.7

−

V_SSC

13

14

15

16

17

18

19

20

21

22

23

24

core ground

P0.0

I/O

−

Port 0. 8-bit programmable bidirectional port.

P0.1

P0.5 and P0.6 have 8 mA current sinking capability for

direct drive of LEDs.

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

V_SSA

analog ground

CVBS0

I

Composite video input. A positive-going 1 V

(peak-to-peak) input is required; connected via a

100 nF capacitor.

CVBS1

I

SYNC_FILTER

IREF

25

26

27

34

35

41

I

CVBS sync ﬁlter input. This pin should be connected to

V_SSAvia a 100 nF capacitor.

Reference current input for analog circuits, connected

to V_SSAvia a 24 kΩ resistor.

FRAME

O

De-interlace output synchronized with the VSYNC

pulse to produce a non-interlaced display by

adjustment of the vertical deﬂection circuits.

VPE

28

42

I

OTP programming voltage

1999 Oct 27

8

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

SYMBOL

TYPE

DESCRIPTION

SDIP52

LQFP100

COR

29

43

O

Open-drain, active LOW output which allows selective

contrast reduction of the TV picture to enhance a

mixed mode display.

V_DDA

B

31

32

33

34

35

45

46

47

48

52

−

+3.3 V analog power supply

O

Pixel rate output of the BLUE colour information.

Pixel rate output of the GREEN colour information.

Pixel rate output of the RED colour information.

G

R

VDS

Video/data switch push-pull output for dot rate fast

blanking.

HSYNC

VSYNC

36

37

53

55

I

Schmitt triggered input for a TTL-level version of the

horizontal sync pulse; the polarity of this pulse is

programmable by register bit TXT1.H POLARITY.

Schmitt triggered input for a TTL-level version of the

vertical sync pulse; the polarity of this pulse is

programmable by register bit TXT1.V POLARITY.

V_SSP

38

39

40

41

42

43

12, 60

63

−

I

periphery ground

V_DDC

+3.3 V core power supply

crystal oscillator ground

12 MHz crystal oscillator input

12 MHz crystal oscillator output

OSCGND

XTALIN

XTALOUT

RESET

69

70

71

O

I

73

If the reset input is HIGH for at least 2 machine cycles

(24 oscillator periods) while the oscillator is running,

the device is reset; this pin should be connected to

V_DDPvia a capacitor.

V_DDP

44

45

46

47

48

49

50

51

52

75

76

78

79

80

81

82

83

84

−

+3.3 V periphery power supply

P1.0/INT1

P1.1/T0

I/O

Port 1. 8-bit programmable bidirectional port with

alternative functions.

P1.2/INT0

P1.3/T1

P1.0/INT1 is external interrupt 1 which can be

triggered on the rising and falling edge of the pulse.

P1.1/T0 is the counter/Timer 0. P1.2/INT0 is external

interrupt 0. P1.3/T1 is the counter/Timer 1. P1.6/SCL0

is the serial clock input for the I²C-bus and P1.7/SDA0

is the serial data port for the I²C-bus. P1.4/SCL1 is the

serial clock input for the I²C-bus. P1.5/SDA1 is the

serial data port for the I²C-bus.

P1.6/SCL0

P1.7/SDA0

P1.4/SCL1

P1.5/SDA1

VPE_2

n.c.

−

62

I

OTP programming voltage

not connected

3, 7 to 10,14, 15,

19 to 21, 23, 26, 27, 33,

36 to 40, 49 to 51,

−

56 to 58, 61, 64 to 68,

72, 74, 77, 85 to 92, 99

1999 Oct 27

9

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

7

MICROCONTROLLER

8

MEMORY ORGANIZATION

The functionality of the microcontroller used on this device

is described here with reference to the industry standard

80C51 microcontroller. A full description of its functionality

can be found in “Handbook IC20, 80C51-Based 8-bit

Microcontrollers”.

The device has the capability of a maximum of 64-kbyte

Program ROM and 1.2-kbyte Data RAM internally.

8.1

Security bits - program and verify

SAA55xx devices have a set of security bits allied with

each section of the device, i.e. Program ROM, Character

ROM and Packet 26 ROM. The security bits are used to

prevent the ROM from being overwritten once

programmed, and also the contents being verified once

programmed. The security bits are one-time

7.1

Microcontroller features

• 80C51 microcontroller core standard instruction set and

timing

• 1 µs machine cycle

programmable and cannot be erased.

• Maximum 64K × 8-bit Program ROM

• Maximum of 1.2K × 8-bit Auxiliary RAM

The SAA55xx memory and security bits are structured as

shown in Fig.4. The SAA55xx security bits are set as

shown in Fig.5 for production programmed devices and

are set as shown in Fig.6 for production blank devices.

• Interrupt Controller for individual enable/disable with two

level priority

• Two 16-bit Timer/Counter registers

• Watchdog Timer

8.2

RAM organisation

The internal Data RAM is organised into two areas, Data

memory and Special Function Registers (SFRs) as shown

in Fig.7.

• Auxiliary RAM page pointer

• 16-bit Data pointer

• Idle and Power-down modes

• 29 general I/O lines

8.3

Data memory

• Eight 6-bit Pulse Width Modulator (PWM) outputs for

control of TV analog signals

The Data memory is 256 × 8-bit and occupies the address

range 00H to FFH when using indirect addressing and

00H to 7FH when using direct addressing. The SFRs

occupy the address range 80H to FFH and are accessible

using direct addressing only.

• One 14-bit PWM for Voltage Synthesis Tuner (VST)

control

• 8-bit Analog-to-Digital Converter (ADC) with

4 multiplexed inputs

The lower 128 bytes of Data memory are mapped as

shown in Fig.8.

• 2 high current outputs for directly driving LEDs

• I²C-bus byte level bus interface with dual ports.

The lowest 24 bytes are grouped into 4 banks of

8 registers, the next 16 bytes above the register banks

form a block of bit addressable memory space.

The upper 128 bytes are not allocated for any special area

or functions.

1999 Oct 27

10

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

handbook, full pagewidth

MEMORY

SECURITY BITS INTERACTION

USER ROM PROGRAMMING

PROGRAM ROM

VERIFY

(ENABLE/DISABLE)

USER ROM

(64K x 8-BIT)

CHARACTER ROM

USER ROM PROGRAMMING

(ENABLE/DISABLE)

VERIFY

(ENABLE/DISABLE)

USER ROM

(9K x 12-BIT)

PACKET 26 ROM

USER ROM PROGRAMMING

(ENABLE/DISABLE)

VERIFY

(ENABLE/DISABLE)

USER ROM

(4K x 8-BIT)

GSA030

Fig.4 Memory and security bit structures.

_{handbook, full pagewidth}MEMORY

SECURITY BITS SET

USER ROM PROGRAMMING

(ENABLE/DISABLE)

VERIFY

(ENABLE/DISABLE)

PROGRAM ROM

DISABLED

ENABLED

CHARACTER ROM

PACKET 26 ROM

DISABLED

ENABLED

MBK954

Fig.5 Security bits for production devices.

11

1999 Oct 27

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

_{handbook, full pagewidth}MEMORY

SECURITY BITS SET

USER ROM PROGRAMMING

(ENABLE/DISABLE)

VERIFY

(ENABLE/DISABLE)

PROGRAM ROM

CHARACTER ROM

PACKET 26 ROM

ENABLED

MBK955

Fig.6 Security bits for production blank devices.

handbook, halfpage

SPECIAL

FUNCTION

REGISTERS

DATA

MEMORY

FFH

accessible

by indirect

addressing

only

accessible

by direct

addressing

only

upper 128 bytes

80H

7FH

accessible

by direct

and indirect

addressing

lower 128 bytes

00H

MBK956

Fig.7 Internal Data memory.

12

1999 Oct 27

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

handbook, halfpage

7FH

30H

2FH

bit-addressable space

(bit addresses 00H to 7FH)

20H

1FH

R7

R0

R7

18H

17H

R0

R7

10H

0FH

4 banks of 8 registers

(R0 to R7)

R0

R7

08H

07H

R0

0

MGM677

Fig.8 Lower 128 bytes of internal RAM.

1999 Oct 27

13

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

Table 3 SFR bit description

BIT

FUNCTION

Accumulator (ACC)

ACC7 to ACC0

accumulator value

B register value

B Register (B)

B7 to B0

Data Pointer High byte (DPH)

DPH7 to DPH0

data pointer high byte, used with DPL to address auxiliary memory

data pointer low byte, used with DPH to address auxiliary memory

Data Pointer Low byte (DPL)

DPL7 to DPL0

Interrupt Enable Register (IE)

EA

disable all interrupts (logic 0), or use individual interrupt enable bits (logic 1)

enable BUSY interrupt

enable I²C-bus interrupt

EBUSY

ES2

ET1

EX1

ET0

EX0

enable Timer 1 interrupt

enable external interrupt 1

enable Timer 0 interrupt

enable external interrupt 0

Interrupt Priority Register (IP)

PBUSY

PES2

PCC

PT1

priority EBUSY interrupt

priority ES2 interrupt

priority ECC interrupt

priority Timer 1 interrupt

priority external interrupt 1

priority Timer 0 interrupt

priority external interrupt 0

PX1

PT0

PX0

Port 0 (P0)

P07 to P00

Port 1 (P1)

P17 to P10

Port 2 (P2)

P27 to P20

Port 3 (P3)

P37 to P30

Port 0 I/O register connected to external pins

Port 1 I/O register connected to external pins

Port 2 I/O register connected to external pins

Port 3 I/O register connected to external pins; P37 to P35 are only available with

the LQFP100 package

1999 Oct 27

17

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

BIT

FUNCTION

Port 0 Conﬁguration A (P0CFGA) and Port 0 Conﬁguration B (P0CFGB)

P0CFGA<7:0> and P0CFGB<7:0> These two registers are used to conﬁgure Port 0 pins. For example, the

conﬁguration of Port 0 pin 3 is controlled by setting bit 3 in both P0CFGA and

P0CFGB. P0CFGB<x>/P0CFGA<x>:

00 = P0.x in open-drain configuration

01 = P0.x in quasi-bidirectional configuration

10 = P0.x in high-impedance configuration

11 = P0.x in push-pull configuration

Port 1 Conﬁguration A (P1CFGA) and Port 1 Conﬁguration B (P1CFGB)

P1CFGA<7:0> and P1CFGB<7:0> These two registers are used to conﬁgure Port 1 pins. For example, the

conﬁguration of Port 1 pin 3 is controlled by setting bit 3 in both P1CFGA and

P1CFGB. P1CFGB<x>/P1CFGA<x>:

00 = P1.x in open-drain configuration

01 = P1.x in quasi-bidirectional configuration

10 = P1.x in high-impedance configuration

11 = P1.x in push-pull configuration

Port 2 Conﬁguration A (P2CFGA) and Port 2 Conﬁguration B (P2CFGB)

P2CFGA<7:0> and P2CFGB<7:0> These two registers are used to conﬁgure Port 2 pins. For example, the

conﬁguration of Port 2 pin 3 is controlled by setting bit 3 in both P2CFGA and

P2CFGB. P2CFGB<x>/P2CFGA<x>:

00 = P2.x in open-drain configuration

01 = P2.x in quasi-bidirectional configuration

10 = P2.x in high-impedance configuration

11 = P2.x in push-pull configuration

Port 3 Conﬁguration A (P3CFGA) and Port 3 Conﬁguration B (P3CFGB)

P3CFGA<7:0> and P3CFGB<7:0> These two registers are used to conﬁgure Port 3 pins. For example, the

conﬁguration of Port 3 pin 3 is controlled by setting bit 3 in both P3CFGA and

P3CFGB. P3CFGB<x>/P3CFGA<x>:

00 = P3.x in open-drain configuration

01 = P3.x in quasi-bidirectional configuration

10 = P3.x in high-impedance configuration

11 = P3.x in push-pull configuration

1999 Oct 27

18

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

BIT

FUNCTION

Power Control Register (PCON)

ARD

auxiliary RAM disable bit, all MOVX instructions access the external data

memory

RFI

WLE

GF1

GF0

PD

disable ALE during internal access to reduce radio frequency interference

Watchdog Timer enable

general purpose ﬂag 1

general purpose ﬂag 0

Power-down mode activation bit

Idle mode activation bit

IDL

Program Status Word (PSW)

C

carry bit

AC

auxiliary carry bit

F0

ﬂag 0

RS1 to RS0

register bank selector bits RS<1:0>:

00 = Bank 0 (00H to 07H)

01 = Bank 1 (08H to 0FH)

10 = Bank 2 (10H to 17H)

11 = Bank 3 (18H to 1FH)

overﬂow ﬂag

OV

P

parity bit

Pulse Width Modulator 0 Control Register (PWM0)

PW0E

activate this PWM and take control of respective port pin (logic 1)

pulse width modulator high time

PW0V5 to PW0V0

Pulse Width Modulator 1 Control Register (PWM1)

PW1E

activate this PWM (logic 1)

pulse width modulator high time

PW1V5 to PW1V0

Pulse Width Modulator 2 Control Register (PWM2)

PW2E

activate this PWM (logic 1)

pulse width modulator high time

PW2V5 to PW2V0

Pulse Width Modulator 3 Control Register (PWM3)

PW3E

activate this PWM (logic 1)

pulse width modulator high time

PW3V5 to PW3V0

Pulse Width Modulator 4 Control Register (PWM4)

PW4E

activate this PWM (logic 1)

pulse width modulator high time

PW4V5 to PW4V0

1999 Oct 27

19

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

BIT

FUNCTION

Pulse Width Modulator 5 Control Register (PWM5)

PW5E

activate this PWM (logic 1)

pulse width modulator high time

PW5V5 to PW5V0

Pulse Width Modulator 6 Control Register (PWM6)

PW6E

activate this PWM (logic 1)

pulse width modulator high time

PW6V5 to PW6V0

Pulse Width Modulator 7 Control Register (PWM7)

PW7E

activate this PWM (logic 1)

PW7V5 to PW7V0

pulse width modulator high time

standby activation bit

ROM Bank (ROMBK)

STANDBY

I²C-bus Slave Address Register (S1ADR)

ADR6 to ADR0

GC

I²C-bus slave address to which the device will respond

enable I²C-bus general call address (logic 1)

I²C-bus Control Register (S1CON)

CR2 to CR0

clock rate bits; CR<2:0>:

000 = 100 kHz bit rate

001 = 3.75 kHz bit rate

010 = 150 kHz bit rate

011 = 200 kHz bit rate

100 = 25 kHz bit rate

101 = 1.875 kHz bit rate

110 = 37.5 kHz bit rate

111 = 50 kHz bit rate

ENSI

STA

enable I²C-bus interface (logic 1)

START ﬂag. When this bit is set in slave mode, the hardware checks the I²C-bus

and generates a START condition if the bus is free or after the bus becomes free.

If the device operates in master mode it will generate a repeated START

condition.

STO

STOP ﬂag. If this bit is set in a master mode a STOP condition is generated. A

STOP condition detected on the I²C-bus clears this bit. This bit may also be set

in slave mode in order to recover from an error condition. In this case no STOP

condition is generated to the I²C-bus, but the hardware releases the SDA and

SCL lines and switches to the not selected receiver mode. The STOP ﬂag is

cleared by the hardware.

1999 Oct 27

20

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

BIT

FUNCTION

SI

Serial Interrupt ﬂag. This ﬂag is set and an interrupt request is generated, after

any of the following events occur:

• A START condition is generated in master mode

• The own slave address has been received during AA = 1

• The general call address has been received while S1ADR.GC and AA = 1

• A data byte has been received or transmitted in master mode (even if arbitration

is lost)

• A data byte has been received or transmitted as selected slave

• A STOP or START condition is received as selected slave receiver or

transmitter. While the SI ﬂag is set, SCL remains LOW and the serial transfer is

suspended. SI must be reset by software.

AA

Assert Acknowledge ﬂag. When this bit is set, an acknowledge is returned

after any one of the following conditions:

• Own slave address is received

• General call address is received (S1ADR.GC = 1)

• A data byte is received, while the device is programmed to be a master receiver

• A data byte is received, while the device is selected slave receiver.

When the bit is reset, no acknowledge is returned. Consequently, no interrupt is

requested when the own address or general call address is received.

I²C-bus Data Register (S1DAT)

DAT7 to DAT0

I²C-bus data

I²C-bus Status Register (S1STA)

STAT4 to STAT0

I²C-bus interface status

Software ADC Register (SAD)

VHI

analog input voltage greater than DAC voltage (logic 1)

CH1 to CH0

ADC input channel select bits; CH<1:0>:

00 = ADC3

01 = ADC0

10 = ADC1

11 = ADC2

ST⁽¹⁾

initiate voltage comparison between ADC input channel and SAD value

4 MSBs of DAC input word

SAD7 to SAD4

Software ADC Control Register (SADB)

DC_COMP

enable DC comparator mode (logic 1)

SAD3 to SAD0

4 LSBs of SAD value

stack pointer value

Stack Pointer (SP)

SP7 to SP0

1999 Oct 27

21

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

BIT

FUNCTION

Timer/Counter Control Register (TCON)

TF1

Timer 1 overﬂow ﬂag. Set by hardware on timer/counter overﬂow. Cleared by

hardware when processor vectors to interrupt routine.

TR1

TF0

Timer 1 run control bit. Set/cleared by software to turn timer/counter on/off.

Timer 0 overﬂow ﬂag. Set by hardware on timer/counter overﬂow. Cleared by

hardware when processor vectors to interrupt routine.

TR0

IE1

Timer 0 run control bit. Set/cleared by software to turn timer/counter on/off.

Interrupt 1 Edge ﬂag. Both edges generate ﬂag. Set by hardware when external

interrupt edge detected. Cleared by hardware when interrupt processed.

IT1

IE0

IT0

Interrupt 1 type control bit. Set/cleared by software to specify edge/LOW level

triggered external interrupts.

Interrupt 0 Edge l ﬂag. Set by hardware when external interrupt edge detected.

Cleared by hardware when interrupt processed.

Interrupt 0 type ﬂag. Set/cleared by software to specify falling edge/LOW level

triggered external interrupts.

14-bit PWM MSB Register (TDACH)

TPWE

activate this 14-bit PWM (logic 1)

TD13 to TD8

6 MSBs of 14-bit number to be output by the 14-bit PWM

14-bit PWM LSB Register (TDACL)

TD7 to TD0

8 LSBs of 14-bit number to be output by the 14-bit PWM

8 MSBs of Timer 0 16-bit counter

Timer 0 High byte (TH0)

TH07 to TH00

Timer 1 High byte (TH1)

TH17 to TH10

8 MSBs of Timer 1 16-bit counter

Timer 0 Low byte (TL0)

TL07 to TL00

8 LSBs of Timer 0 16-bit counter

Timer 1 Low byte (TL1)

TL17 to TL10

8 LSBs of Timer 1 16-bit counter

Timer/Counter Mode Control (TMOD)

GATE

C/T

gating control Timer/Counter 1

Counter/Timer 1 selector

M1 to M0

mode control bits timer/counter 1; M<1:0>:

00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler

01 = 16-bit time interval or event counter

10 = 8-bit time interval or event counter with automatic reload upon overflow;

reload value stored in TH1

11 = stopped

GATE

C/T

Gating control Timer/Counter 0

Counter/Timer 0 selector

1999 Oct 27

22

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

BIT

FUNCTION

mode control bits timer/counter 0; M<1:0>:

M1 to M0

00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler

01 = 16-bit time interval or event counter

10 = 8-bit time interval or event counter with automatic reload upon overflow;

reload value stored in TH0

11 = one 8-bit time interval or event counter and one 8-bit time interval counter

Text Register 0 (TXT0)

X24 POSN

store packet 24 in extension packet memory (logic 0) or page memory (logic 1)

display X24 from page memory (logic 0) or extension packet memory (logic 1)

FRAME output switched off automatically if any video displayed (logic 1)

disable writing of rolling headers and time into memory (logic 1)

display row 24 only (logic 1)

DISPLAY X24

AUTO FRAME

DISABLE HEADER ROLL

DISPLAY STATUS ROW ONLY

DISABLE FRAME

VPS ON

FRAME output always LOW (logic 1)

enable capture of VPS data (logic 1)

INV ON

enable capture of inventory page in block 8 (logic 1)

Text Register 1 (TXT1)

EXT PKT OFF

8-BIT

disable acquisition of extension packets (logic 1)

disable checking of packets 0 to 24 written into memory (logic 1)

disable writing of data into Display memory (logic 1)

disable automatic processing of X/26 data (logic 1)

acquire data on any TV line (logic 1)

ACQ OFF

X26 OFF

FULL FIELD

FIELD POLARITY

H POLARITY

V POLARITY

VSYNC pulse in second half of line during even ﬁeld (logic 1)

HSYNC reference edge is negative going (logic 1)

VSYNC reference edge is negative going (logic 1)

Text Register 2 (TXT2)

ACQ BANK

select acquisition Bank 1 (logic 1)

page request

REQ3 to REQ0

SC2 to SC0

start column of page request

Text Register 3 (TXT3)

PRD4 to PRD0

page request data

Text Register 4 (TXT4)

OSD BANK ENABLE

alternate OSD location available via graphic attribute, additional 32 locations

(logic 1)

QUAD WIDTH ENABLE

EAST/WEST

enable display of quadruple width characters (logic 1)

eastern language selection of character codes A0H to FFH (logic 1)

disable normal decoding of double height characters (logic 1)

enable meshing of black background (logic 1)

DISABLE DOUBLE HEIGHT

B MESH ENABLE

C MESH ENABLE

TRANS ENABLE

enable meshing of coloured background (logic 1)

display black background as video (logic 1)

SHADOW ENABLE

display shadow/fringe (default SE black) (logic 1)

1999 Oct 27

23

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

BIT

FUNCTION

Text Register 5 (TXT5)

BKGND OUT

BKGND IN

background colour displayed outside teletext boxes (logic 1)

background colour displayed inside teletext boxes (logic 1)

COR active outside teletext and OSD boxes (logic 1)

COR active inside teletext and OSD boxes (logic 1)

text displayed outside teletext boxes (logic 1)

COR OUT

COR IN

TEXT OUT

TEXT IN

text displayed inside teletext boxes (logic 1)

PICTURE ON OUT

PICTURE ON IN

video displayed outside teletext boxes (logic 1)

video displayed inside teletext boxes (logic 1)

Text Register 6 (TXT6)

BKGND OUT

BKGND IN

background colour displayed outside teletext boxes (logic 1)

background colour displayed inside teletext boxes (logic 1)

COR active outside teletext and OSD boxes (logic 1)

COR active inside teletext and OSD boxes (logic 1)

text displayed outside teletext boxes (logic 1)

COR OUT

COR IN

TEXT OUT

TEXT IN

text displayed inside teletext boxes (logic 1)

PICTURE ON OUT

PICTURE ON IN

video displayed outside teletext boxes (logic 1)

video displayed inside teletext boxes (logic 1)

Text Register 7 (TXT7)

STATUS ROW TOP

display memory row 24 information above teletext page (on display row 0)

(logic 1)

CURSOR ON

REVEAL

display cursor at position given by TXT9 and TXT10 (logic 1)

display characters in area with conceal attribute set (logic 1)

display memory rows 12 to 23 when DOUBLE HEIGHT height bit is set (logic 1)

display each character as twice normal height (logic 1)

BOTTOM/TOP

DOUBLE HEIGHT

BOX ON 24

enable display of teletext boxes in memory row 24 (logic 1)

enable display of teletext boxes in memory row 1 to 23 (logic 1)

enable display of teletext boxes in memory row 0 (logic 1)

BOX ON 1 to 23

BOX ON 0

Text Register 8 (TXT8)

FLICKER STOP ON

DISABLE SPANISH

PKT 26 RECEIVED⁽²⁾

WSS RECEIVED⁽²⁾

WSS ON

disable ‘Flicker Stopper’ circuitry (logic 1)

disable special treatment of Spanish packet 26 characters (logic 1)

packet 26 data has been processed (logic 1)

WSS data has been processed (logic 1)

enable acquisition of WSS data (logic 1)

CVBS1/CVBS0

select CVBS1 as source for device (logic 1)

1999 Oct 27

24

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

BIT

FUNCTION

Text Register 9 (TXT9)

CURSOR FREEZE

CLEAR MEMORY⁽¹⁾

A0

lock cursor at current position (logic 1)

clear memory block pointed to by TXT15 (logic 1)

access extension packet memory (logic 1)

current memory row value

R4 to R0⁽³⁾

Text Register 10 (TXT10)

C5 to C0⁽⁴⁾

current memory column value

Text Register 11 (TXT11)

D7 to D0

data value written or read from memory location deﬁned by TXT9, TXT10 and

TXT15

Text Register 12 (TXT12)

625/525 SYNC

525-line CVBS signal is being received (logic 1)

Spanish character set present (logic 1)

SPANISH

ROM VER3 to ROM VER0

VIDEO SIGNAL QUALITY

mask programmable identiﬁcation for character set

acquisition can be synchronized to CVBS (logic 1)

Text Register 13 (TXT13)

VPS RECEIVED

PAGE CLEARING

525 DISPLAY

525 TEXT

VPS data (logic 1)

software or power-on page clear in progress (logic 1)

525-line synchronisation for display (logic 1)

525-line WST being received (logic 1)

625-line WST being received (logic 1)

packet 8/30/x(625) or packet 4/30/x(525) data detected (logic 1)

packet x/27 data detected (logic 1)

625 TEXT

PKT 8/30

FASTEXT

Text Register 14 (TXT14)

PAGE3 to PAGE0

current display page

Text Register 15 (TXT15)

BLOCK3 to BLOCK0

current micro block to be accessed by TXT9, TXT10 and TXT11

Text Register 17 (TXT17)

FORCE ACQ1 to FORCE ACQ0

FORCE ACQ<1:0>:

00 = automatic selection

01 = force 525 timing, force 525 teletext standard

10 = force 625 timing, force 625 teletext standard

11 = force 625 timing, force 525 teletext standard

FORCE DISP<1:0>:

FORCE DISP1 to FORCE DISP0

00 = automatic selection

01 = force display to 525 mode (9 lines per row)

10 = force display to 625 mode (10 lines per row)

11 = not valid (default to 625 mode)

1999 Oct 27

25

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

BIT

FUNCTION

SCREEN COL2 to SCREEN COL0 Deﬁnes colour to be displayed instead of TV picture and black background; these

bits are equivalent to the RGB components. SCREEN COL<2:0>:

000 = transparent

001 = CLUT entry 9

010 = CLUT entry 10

011 = CLUT entry 11

100 = CLUT entry 12

101 = CLUT entry 13

110 = CLUT entry 14

111 = CLUT entry 15

Text Register 18 (TXT18)

NOT3 to NOT0

BS1 to BS0

national option table selection, maximum of 31 when used with EAST/WEST bit

basic character set selection

Text Register 19 (TXT19)

TEN

enable twist character set (logic 1)

TC2 to TC0

TS1 to TS0

language control bits (C12, C13 and C14) that has twisted character set

twist character set selection

Text Register 20 (TXT20)

OSD LANG ENABLE

enable use of OSD LAN<2:0> to deﬁne language option for display, instead of

C12, C13 and C14

OSD LAN2 to OSD LAN0

alternative C12, C13 and C14 bits for use with OSD menus

Text Register 21 (TXT21)

I²C PORT 1

I²C PORT 0

enable I²C-bus Port 1 selection (P1.5/SDA1 and P1.4/SCL1) (logic 1)

enable I²C-bus Port 0 selection (P1.7/SDA0 and P1.6/SCL0) (logic 1)

Text Register 22 (TXT22)

GPF7 to GPF6

GPF5

reserved

standard device (logic 0)

10 pages available (logic 1)

GPF4

GPF3

PWM0, PWM1, PWM2 and PWM3 outputs routed to Port 2.1 to Port 2.4

respectively (logic 1)

GPF2

GPF1

GPF0

reserved

text acquisition available (logic 1)

reserved

Watchdog Timer (WDT)

WDV7 to WDV0

Watchdog Timer period

1999 Oct 27

26

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

BIT

FUNCTION

Watchdog Timer Key (WDTKEY)

WKEY7 to WKEY0⁽⁵⁾

Watchdog Timer Key

Wide Screen Signalling 1 (WSS1)

WSS<3:0> ERROR

WSS3 to WSS0

error in WSS<3:0> (logic 1)

signalling bits to deﬁne aspect ratio (group 1)

Wide Screen Signalling 2 (WSS2)

WSS<7:4> ERROR

error in WSS<7:4> (logic 1)

WSS7 to WSS4

signalling bits to deﬁne enhanced services (group 2)

Wide Screen Signalling 3 (WSS3)

WSS<13:11> ERROR

WSS13 to WSS11

error in WSS<13:11> (logic 1)

signalling bits to deﬁne reserved elements (group 4)

error in WSS<10:8> (logic 1)

WSS<10:8> ERROR

WSS10 to WSS8

signalling bits to deﬁne subtitles (group 3)

XRAMP

XRAMP7 to XRAMP0

internal RAM access upper byte address

Notes

1. This flag is set by software and reset by hardware.

2. This flag is set by hardware and must be reset by software.

3. Valid range TXT mode 0 to 24.

4. Valid range TXT mode 0 to 39.

5. Must be set to 55H to disable Watchdog Timer when active.

1999 Oct 27

27

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

8.5

Character set feature bits

Features available on the SAA55xx devices are reflected in a specific area of the character ROM. These sections of the

character ROM are mapped to two Special Function Registers: TXT22 and TXT12. Character ROM address 09FEH is

mapped to SFR TXT22 as shown in Table 4. Character ROM address 09FFH is mapped to SFR TXT12 as shown in

Table 6.

Table 4 Character ROM - TXT22 mapping

U = used; X = reserved

MAPPED ITEMS

11

10

9

8

7

6

5

4

3

2

1

0

Character ROM

address 09FEH

X

U

X

U

X

Mapped to TXT22

−

7

6

5

4

3

2

1

0

Table 5 Description of Character ROM address 09FEH bits

BIT NUMBER

FUNCTION

0

1

reserved; normally set to logic 1

1 = Text Acquisition available

0 = Text Acquisition not available

reserved

2

3

1 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 2.1 to Port 2.4 respectively

0 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 3.0 to Port 3.3 respectively

4

1 = 10 page available

0 = 6 page available

5

0 = standard device

6 to 11

reserved; normally set to logic 1

Table 6 Character ROM - TXT12 mapping

U = used; X = reserved

MAPPED ITEMS

11

10

9

8

7

6

5

4

3

2

1

0

Character ROM

address 09FFH

X

U

X

Mapped to TXT12

−

6

5

4

3

2

Table 7 Description of Character ROM address 09FFH bits

BIT NUMBER

FUNCTION

4

1 = Spanish character set present

0 = no Spanish character set present

reserved; normally set to logic 1

0 to 3, 5 to 11

1999 Oct 27

28

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

8.6

External (auxiliary) memory

8.6.1

AUXILIARY RAM PAGE SELECTION

The normal 80C51 external memory area has been

mapped internally to the device, this means that the MOVX

instruction accesses memory internal to the device.

The Auxiliary RAM page pointer is used to select one of

the 256 pages within the Auxiliary RAM, not all pages are

allocated, refer to Fig.10 for further detail. A page consists

of 256 consecutive bytes.

handbook, halfpage

7FFFH

FFFFH

4800H

47FFH

DISPLAY RAM

FOR

TEXT PAGES

8C00H

(2)

87FFH

DISPLAY REGISTERS

2000H

1FFFH

500H

87F0H

871FH

CLUT

4FFH

(1)

DATA RAM

0000H

8700H

GSA031

lower 32 kbytes

upper 32 kbytes

(1) Amount of Data RAM depends on the device.

(2) Amount of Display RAM depends on the device.

Fig.9 Auxiliary RAM allocation.

1999 Oct 27

29

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

handbook, full pagewidth

FFH

FFFFH

SFR XRAMP = FFH

00H

FFH

FF00H

FEFFH

SFR XRAMP = FEH

00H

FE00H

MOVX @ Ri,A

MOVX A, @ Ri

MOVX @ DPTR,A

MOVX A, @ DPTR

01FFH

FFH

SFR XRAMP = 01H

SFR XRAMP = 00H

00H

FFH

0100H

00FFH

00H

0000H

MBK958

Fig.10 Indirect addressing of Auxiliary RAM.

9

POWER-ON RESET

An automatic reset can be obtained when V_DDis turned on

by connecting the RESET pin to V_DDPthrough a

10 µF capacitor, providing the V_DDrise time does not

exceed 1 ms, and the oscillator start-up time does not

exceed 10 ms.

To ensure correct initialisation, the RESET pin must be

held high long enough for the oscillator to settle following

power-up, usually a few ms. Once the oscillator is stable,

a further 24 clocks are required to generate the reset (two

machine cycles of the microcontroller). Once the above

reset condition has been detected an internal reset signal

is triggered which remains active for 2048 clock cycles.

1999 Oct 27

30

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

10 REDUCED POWER MODES

• The third method of terminating Idle mode is with an

external hardware reset. Since the oscillator is running,

the hardware reset need only be active for two machine

cycles (24 clocks at 12 MHz) to complete the reset

operation. Reset defines all SFRs and Display memory

to an initialized state, but maintains all other RAM

values. Code execution commences with the Program

Counter set to ‘0000’.

There are two power saving modes, Idle and Power-down,

incorporated into the 10 page devices. There is an

additional Standby mode incorporated into the 1 page

devices. When utilizing any mode, power to the device

(V_DDP, V_DDCand V_DDA) should be maintained, since power

saving is achieved by clock gating on a section by section

basis.

10.2 Power-down mode

10.1 Idle mode

In Power-down mode the crystal oscillator is stopped.

The contents of all SFRs and Data memory are

During Idle mode, Acquisition, Display and the Central

Processing Unit (CPU) sections of the device are disabled.

The following functions remain active:

maintained, However, the contents of the Auxiliary/Display

memory are lost. The port pins maintain the values defined

by their associated SFRs. Since the output values on RGB

and VDS are maintained the display output must be made

inactive before entering Power-down mode.

• Memory interface

• I²C-bus interface

• Timer/Counters

The Power-down mode is activated by setting the PD bit in

the PCON register. It is advised to disable the Watchdog

Timer prior to entering power-down.

• Watchdog Timer

• Pulse Width Modulators.

To enter Idle mode the IDL bit in the PCON register must

be set. The Watchdog Timer must be disabled prior to

entering the Idle mode to prevent the device being reset.

Once in Idle mode, the crystal oscillator continues to run,

but the internal clock to the CPU, Acquisition and Display

are gated out. However, the clocks to the Memory

interface, I²C-bus interface, Timer/Counters, Watchdog

Timer and Pulse Width Modulators are maintained.

The CPU state is frozen along with the status of all SFRs,

internal RAM contents are maintained, as are the device

output pin values.

There are three methods of exiting power-down:

• An external interrupt provides the first mechanism for

waking from power-down. Since the clock is stopped,

external interrupts needs to be set level sensitive prior to

entering power-down. The interrupt is serviced, and

following the instruction RETI, the next instruction to be

executed will be the one after the instruction that put the

device into Power-down mode.

• A second method of exiting power-down is via an

interrupt generated by the SAD DC Compare circuit.

When the device is configured in this mode, detection of

a certain analog threshold at the input to the SAD may

be used to trigger wake-up of the device i.e. TV Front

Panel Key-press. As above, the interrupt is serviced,

and following the instruction RETI, the next instruction to

be executed will be the one following the instruction that

put the device into power-down.

Since the output values on Red Green Blue (RGB) and the

Video Data Switch (VDS) are maintained the display

output must be disabled before entering this mode.

There are three methods to recover from Idle mode:

• Assertion of an enabled interrupt will cause the IDL bit to

be cleared by hardware, thus terminating Idle mode.

The interrupt is serviced, and following the instruction

RETI, the next instruction to be executed will be the one

after the instruction that put the device into Idle mode.

• The third method of terminating the Power-down mode

is with an external hardware reset. Reset defines all

SFRs and Display memory, but maintains all other RAM

values. Code execution commences with the Program

Counter set to ‘0000’.

• A second method of exiting the Idle mode is via an

interrupt generated by the SAD DC Compare circuit.

When the device is configured in this mode, detection of

an analog threshold at the input to the SAD may be used

to trigger wake-up of the device i.e. TV Front Panel

Key-press. As above, the interrupt is serviced, and

following the instruction RETI, the next instruction to be

executed will be the one following the instruction that put

the device into Idle mode.

1999 Oct 27

31

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

10.3 Standby mode

11.2.1 OPEN-DRAIN

This mode is only available on 1 page devices. When

Standby mode is entered both Acquisition and Display

sections are disabled. The following functions remain

active:

The open-drain configuration can be used for bidirectional

operation of a port. It requires an external pull-up resistor,

the pull-up voltage has a maximum value of 5.5 V, to allow

connection of the device into a 5 V environment.

The I²C-bus ports (P1.4,P1.5, P1.6 and P1.7) can only be

configured as open-drain.

• 80C51 core

• Memory interface

• I²C-bus interface

• Timer/Counters

• Watchdog Timer

• Software ADC

11.2.2 QUASI-BIDIRECTIONAL

The quasi-bidirectional configuration is a combination of

open-drain and push-pull. It requires an external pull-up

resistor to V_DDP(nominally 3.3 V). When a signal transition

from LOW-to-HIGH is output from the device, the pad is

put into push-pull configuration for one clock cycle

(166 ns) after which the pad goes into open-drain

configuration. This configuration is used to speed up the

edges of signal transitions. This is the default mode of

operation of the pads after reset.

• Pulse Width Modulators.

To enter Standby mode, the STANDBY control bit in the

ROMBK SFR (bit 7) must be set. It can be used in

conjunction with either Idle or Power-down modes to

switch between power saving modes. This mode enables

the 80C51 core to decode either IR remote commands or

receive I²C-bus commands without the device being fully

powered.

11.2.3 HIGH-IMPEDANCE

The high-impedance configuration can be used for input

only operation of the port. When using this configuration

the two output transistors are turned off.

The Standby state is maintained upon exit from either the

Idle mode or Power-down mode. No wake-up from

Standby is necessary as the 80C51 core remains

operational.

11.2.4 PUSH-PULL

Since the output values on RGB and VDS are maintained

the display output must be disabled before entering this

mode.

The push-pull configuration can be used for output only.

In this mode the signal is driven to either 0 V or V_DDP

which is nominally 3.3 V.

,

11.3 Port alternate functions

11 I/O FACILITY

11.1 I/O ports

Ports 1, 2 and 3 are shared with alternative functions to

enable control of external devices and circuitry.

The alternative functions are enabled by setting the

appropriate SFR and also writing a logic 1 to the port bit

that the function occupies.

The SAA55xx devices have 29 I/O lines, each is

individually addressable, or form three parallel 8-bit

addressable ports which are Port 0, Port 1 and Port 2.

Port 3 has 5-bit parallel I/O only.

11.4 LED support

11.2 Port type

Port pins P0.5 and P0.6 have a 8 mA current sinking

capability to enable LEDs in series with current limiting

resistors to be driven directly, without the need for

additional buffering circuitry.

All individual ports can be programmed to function in one

of four I/O configurations: open-drain, quasi-bidirectional,

high-impedance and push-pull. The I/O configuration is

selected using two associated Port Configuration

Registers: PnCFGA and PnCFGB (where n = port number

0, 1, 2 or 3); see Table 3.

1999 Oct 27

32

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

12 INTERRUPT SYSTEM

If requests of the same priority level are received

simultaneously, an internal polling sequence determines

which request is serviced. Thus, within each priority level

there is a second priority structure determined by the

polling sequence as defined in Table 8.

The device has six interrupt sources, each of which can be

enabled or disabled. When enabled each interrupt can be

assigned one of two priority levels. There are four

interrupts that are common to the 80C51, two of these are

external interrupts (EX0 and EX1) and the other two are

timer interrupts (ET0 and ET1). In addition to the

conventional 80C51 interrupts, one application specific

interrupt is incorporated internal to the device which has

following functionality:

Table 8 Interrupt priority (within same level)

PRIORITY

WITHIN LEVEL

INTERRUPT

VECTOR

SOURCE

EX0

ET0

highest

0003H

000BH

0013H

001BH

002BH

0033H

• Display Busy interrupt (EBUSY). An interrupt is

generated when the display enters either a Horizontal or

Vertical Blanking Period. i.e. Indicates when the

microcontroller can update the Display RAM without

causing undesired effects on the screen. This interrupt

can be configured in one of two modes using the

Memory Mapped Register (MMR) Configuration

(address 87FFH, bit TXT/V):

−

EX1

−

ET1

−

ES2

EBUSY

lowest

12.3 Interrupt vector address

– Text Display Busy. An interrupt is generated on each

active horizontal display line when the Horizontal

Blanking Period is entered

The processor acknowledges an interrupt request by

executing a hardware generated LCALL to the appropriate

servicing routine. The interrupt vector addresses for each

source are shown in Table 8.

– Vertical Display Busy. An interrupt is generated on

each vertical display field when the Vertical Blanking

Period is entered.

12.4 Level/edge interrupt

The external interrupt can be programmed to be either

level-activated or transition-activated by setting or clearing

the IT0/IT1 bits in the Timer Control SFR (TCON).

12.1 Interrupt enable structure

Each of the individual interrupts can be enabled or

disabled by setting or clearing the relevant bit in the

Interrupt Enable Register (IE). All interrupt sources can

also be globally disabled by clearing the EA bit (IE.7).

Table 9 External interrupt activation

ITx

0

LEVEL

EDGE

12.2 Interrupt enable priority

active LOW −

Each interrupt source can be assigned one of two priority

levels. The interrupt priorities are defined by the Interrupt

Priority Register (IP). A low priority interrupt can be

interrupted by a high priority interrupt, but not by another

low priority interrupt. A high priority interrupt can not be

interrupted by any other interrupt source. If two requests of

different priority levels are received simultaneously, the

request with the highest priority level is serviced.

1

−

INT0 = negative edge

INTI = positive and negative edge

The external interrupt INT1 differs from the standard

80C51 interrupt in that it is activated on both edges when

in edge sensitive mode. This is to allow software pulse

width measurement for handling remote control inputs.

1999 Oct 27

33

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

handbook, full pagewidth

H1

L1

highest priority level 1

EX0

highest priority level 0

H2

L2

ET0

EX1

H3

L3

H4

L4

ET1

H5

L5

ES2

lowest priority level 1

lowest priority level 0

H6

L6

EBUSY

GSA033

interrupt

source

enable

global

enable

priority

control

<

>

<

>

SFR IE 0:6

SFR IE.7

SFR IP 0:6

Fig.11 Interrupt structure.

1999 Oct 27

34

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

13 TIMER/COUNTER

The 8-bit timer is incremented every ‘t’ seconds where:

Two 16-bit timers/counters are incorporated Timer 0 and

Timer 1. Both can be configured to operate as either timers

or event counters.

1

t = 12 × 2048 ×

= 12 × 2048 ×

= 2.048 ms

--------

f_osc

---------------------

12 × 10⁶

In Timer mode, the register is incremented on every

machine cycle. It is therefore counting machine cycles.

Since the machine cycle consists of twelve oscillator

periods, the count rate is ¹⁄₁₂f_osc= 1 MHz.

14.1 Watchdog Timer operation

The Watchdog operation is activated when the WLE bit in

the Power Control SFR (PCON) is set. The Watchdog can

be disabled by software by loading the value 55H into the

Watchdog Key SFR (WDTKEY). This must be performed

before entering Idle or Power-down mode to prevent

exiting the mode prematurely.

In Counter mode, the register is incremented in response

to a negative transition at its corresponding external pin T0

or T1. Since the pins T0 and T1 are sampled once per

machine cycle, it takes two machine cycles to recognise a

transition, this gives a maximum count rate of

¹⁄₂₄f_osc= 0.5 MHz.

Once activated the Watchdog Timer SFR (WDT) must be

reloaded before the timer overflows. The WLE bit must be

set to enable loading of the WDT SFR, once loaded the

WLE bit is reset by hardware, this is to prevent erroneous

software from loading the WDT SFR.

There are six Special Function Registers used to control

the timers/counters. These are: TCON, TMOD, TL0, TH0,

TL1 and TH1.

The value loaded into the WDT defines the Watchdog

Interval (WI).

The timer/counter function is selected by control bits C/T in

the Timer Mode SFR (TMOD). These two Timer/Counters

have four operating modes, which are selected by bit-pairs

(M1 and M0) in TMOD. Detail of the modes of operation is

given in “Handbook IC20, 80C51-Based 8-bit

Microcontrollers”.

WI = (256 – WDT) × t = (256 – WDT) × 2.048 ms

The range of intervals is from WDT = 00H which gives

524 ms to WDT = FFH which gives 2.048 ms.

TL0 and TH0 are the actual Timer/Counter registers for

Timer 0. TL0 is the low byte and TH0 is the high byte.

TL1 and TH1 are the actual Timer/Counter registers for

Timer 1. TL1 is the low byte and TH1 is the high byte.

15 PULSE WIDTH MODULATORS

The device has eight 6-bit Pulse Width Modulated (PWM)

outputs for analog control of e.g. volume, balance, bass,

treble, brightness, contrast, hue and saturation. The PWM

outputs generate pulse patterns with a repetition rate of

21.33 µs, with the high time equal to the PWM SFR value

multiplied by 0.33 µs. The analog value is determined by

the ratio of the high time to the repetition time, a DC

voltage proportional to the PWM setting is obtained by

means of an external integration network (low-pass filter).

14 WATCHDOG TIMER

The Watchdog Timer is a counter that once in an overflow

state forces the microcontroller into a reset condition.

The purpose of the Watchdog Timer is to reset the

microcontroller if it enters an erroneous processor state

(possibly caused by electrical noise or RFI) within a

reasonable period of time. When enabled, the Watchdog

circuitry will generate a system reset if the user program

fails to reload the Watchdog Timer within a specified length

of time known as the Watchdog Interval (WI).

15.1 PWM control

The relevant PWM is enabled by setting the PWM enable

bit PWxE in the PWMx Control Register (where x = 0 to 7).

The high time is defined by the value PWxV<5:0>.

The Watchdog Timer consists of an 8-bit counter with an

11-bit prescaler. The prescaler is fed with a signal whose

frequency is ¹⁄₁₂f_osc(1 MHz for 12 MHz oscillator).

1999 Oct 27

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Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

15.2 Tuning Pulse Width Modulator (TPWM)

The resolution of the DAC voltage with a nominal value is

3.3

⁄₂₅₆≈ 13 mV. The external analog voltage has a lower

The device has a single 14-bit PWM that can be used for

Voltage Synthesis Tuning. The method of operation is

similar to the normal PWM except the repetition period is

42.66 µs.

value equivalent to V_SSAand an upper value equivalent to

_DDP− V_tn, where V_tnis the threshold voltage for an N type

V

Metal Oxide Semiconductor transistor. The reason for this

is that the input pins for the analog signals (P3.0 to P3.3)

are 5 V tolerant for normal port operations, i.e. when not

used as analog input. To protect the analog multiplexer

and comparator circuitry from the 5 V, a series transistor is

used to limit the voltage. This limiting introduces a voltage

drop equivalent to V_tn(≈0.6 V) on the input voltage.

Therefore, for an input voltage in the range V_DDPto

15.2.1 TPWM CONTROL

Two SFRs are used to control the TPWM, they are TDACL

and TDACH. The TPWM is enabled by setting the

TPWE bit in the TDACH SFR. The most significant bits

TD<13:7> alter the high period between 0 and 42.33 µs.

The 7 least significant bits TD<6:0> extend certain pulses

by a further 0.33 µs, e.g. if TD<6:0> = 01H then

V_DDP− V_tnthe SAD returns the same comparison value.

1 in 128 periods will be extended by 0.33 µs, if

15.3.3 SAD DC COMPARATOR MODE

TD<6:0> = 02H then 2 in 128 periods will be extended.

The SAD module incorporates a DC Comparator mode

which is selected using the DC_COMP control bit in the

SADB SFR. This mode enables the microcontroller to

detect a threshold crossing at the input to the selected

analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or

P3.3/ADC3) of the Software ADC. A level sensitive

interrupt is generated when the analog input voltage level

at the pin falls below the analog output level of the SAD

DAC.

The TPWM will not start to output a new value until TDACH

has been written to. Therefore, if the value is to be

changed, TDACL should be written before TDACH.

15.3 Software ADC (SAD)

Four successive approximation Analog-to-Digital

Converters can be implemented in software by making use

of the on-board 8-bit Digital-to-Analog Converter and

Analog Comparator.

This mode is intended to provide the device with a

wake-up mechanism from Power-down or Idle mode when

a key-press on the front panel of the TV is detected.

15.3.1 SAD CONTROL

The control of the required analog input is done using the

channel select bits CH<1:0> in the SAD SFR, this selects

the required analog input to be passed to one of the inputs

of the comparator. The second comparator input is

generated by the DAC whose value is set by the bits

SAD<7:0> in the SAD and SADB SFRs. A comparison

between the two inputs is made when the start compare

bit ST in the SAD SFR is set, this must be at least one

instruction cycle after the SAD<7:0> value has been set.

The result of the comparison is given on VHI one

instruction cycle after the setting of ST.

The following software sequence should be used when

utilizing this mode for Power-down or Idle:

1. Disable INT1 using the IE SFR.

2. Set INT1 to level sensitive using the TCON SFR.

3. Set the DAC digital input level to the desired threshold

level using SAD/SADB SFRs and select the required

input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or

P3.3/ADC3) using CH<1:0> in the SAD SFR.

4. Enter DC Compare mode by setting the DC_COMP

enable bit in the SADB SFR.

5. Enable INT1 using the IE SFR.

15.3.2 SAD INPUT VOLTAGE

6. Enter Power-down or Idle mode. Upon wake-up the

SAD should be restored to its conventional operating

mode by disabling the DC_COMP control bit.

The external analog voltage that is used for comparison

with the internally generated DAC voltage does not have

the same voltage range. The DAC has a lower reference

level of V_SSAand an upper reference level of V_SSP

.

1999 Oct 27

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Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

V

handbook, halfpage

DDP

ADC0

ADC1

ADC2

ADC3

MUX

4 : 1

<

>

CH 1:0

VHI

<

SAD 3:0

8-BIT

DAC

<

>

SADB 3:0

MBK960

Fig.12 SAD block diagram.

1999 Oct 27

37

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

16 I²C-BUS SERIAL I/O

17.1 Memory structure

The I²C-bus consists of a serial data (SDA) line and a

serial clock (SCL) line. The definition of the I²C-bus

protocol can be found in the document “The I²C-bus and

how to use it (including specification)”. This document may

be ordered using the code 9398 393 40011.

The memory is partitioned into two distinct areas, the

dedicated Auxiliary RAM area, and the Display RAM area.

The Display RAM area when not being used for Data

Capture or display, can be used as an extension to the

auxiliary RAM area.

The device operates in four modes:

• Master transmitter

• Master receiver

17.1.1 AUXILIARY RAM

The Auxiliary RAM is not initialised at power-up.

The contents of the Auxiliary RAM are maintained during

Idle mode, but are lost if Power-down mode is entered.

• Slave transmitter

• Slave receiver.

17.1.2 DISPLAY RAM

The microcontroller peripheral is controlled by the Serial

Control SFR (S1CON) and its status is indicated by the

Status SFR (S1STA). Information is transmitted/received

to/from the I²C-bus using the Data SFR (S1DAT) and the

Slave Address SFR (S1ADR) is used to configure the

slave address of the peripheral.

The Display RAM is initialised on power-up to a value

of 20H throughout. The contents of the Display RAM are

maintained when entering Idle mode. If Idle mode is exited

using an interrupt then the contents are unchanged, if Idle

mode is exited using a reset then the contents are

initialised to 20H.

The byte level I²C-bus serial port is identical to the I²C-bus

serial port on the P8xCE558, except for the clock rate

selection bits CR<2:0> in S1CON. The operation of the

subsystem is described in detail in the “P8xCE558 data

sheet”.

17.2 Memory mapping

The dedicated Auxiliary RAM area occupies a maximum of

8 kbytes, with an address range from 0000H to 1FFFH.

The Display RAM occupies a maximum of 10 kbytes with

an address range from 2000H to 47FFH for TXT mode

(see Fig.13).

16.1 I²C-bus port selection

Two I²C-bus ports are available SCL0/SDA0 and

SCL1/SDA1. The selection of the port is done using

TXT21.I²C PORT 0 and TXT21.I²C PORT 1. When the

port is enabled, any information transmitted from the

device goes onto the enabled port. Any information

transmitted to the device can only be acted on if the port is

enabled.

17.3 Addressing memory

The memory can be addressed by the microcontroller in

two ways, either directly using a MOVX command, or via

Special Function Registers depending on what address is

required.

The Display memory in the range 2000H to 47FFH can

either be directly accessed using the MOVX, or via the

Special Function Registers.

If both ports are enabled then data transmitted from the

device is seen on both ports, however data transmitted to

the device on one port can not be seen on the other port.

17.3.1 TXT DISPLAY MEMORY SFR ACCESS

17 MEMORY INTERFACE

The Display memory when in TXT mode (see Fig.14) is

configured as 40 columns wide by 25 rows and occupies

1K × 8 bits of memory. There can be a maximum of

10 display pages. Using TXT15.BLOCK<3:0>, the

required display page can be selected to be written to.

The row and column within that block is selected using

TXT9.R<4:0> and TXT10.C<5:0>. The data at the

selected position can be read or written using

TXT11.D<7:0>.

The memory interface controls access to the embedded

Dynamic Random Access Memory (DRAM), refreshing of

the DRAM and page clearing. The DRAM is shared

between Data Capture, display and microcontroller

sections. The Data Capture section uses the DRAM to

store acquired information that has been requested.

The display reads from the DRAM information and

converts it into RGB values. The microcontroller uses the

DRAM as embedded auxiliary RAM.

1999 Oct 27

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Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

Whenever a read or write is performed on TXT11, the row

values stored in TXT9 and column value stored in TXT10

are automatically incremented. For rows 0 to 24 the

column value is incremented up to a maximum of 39, at

which point it resets to ‘0’ and increments the row counter

value. When row 25 column 23 is reached the values of

the row and column are both reset to zero.

When this occurs, the space code (20H) is written into

every location of rows 1 to 23 of the basic page memory,

the appropriate packet 27 row of the extension packet

memory and the row where teletext packet 24 is written.

This last row is either row 24 of the basic page memory, if

the TXT0.X24 POSN bit is set, or row 0 of the extension

packet memory, if the bit is not set. Page clearing takes

place before the end of the TV line in which the header

arrived which initiated the page clear.

Writing values outside of the valid range for TXT9 or

TXT10 will cause undetermined operation of the

auto-incrementing function for accesses to TXT11.

This means that the 1 field gap between the page header

and the rest of the page which is necessary for many

teletext decoders is not required.

17.3.2 TXT DISPLAY MEMORY MOVX ACCESS

It is important for the generation of OSD displays, that use

this mode of access, to understand the mapping of the

MOVX address onto the display row and column value.

This mapping of row and column onto address is shown in

Table 10. The values shown are added onto a base

address for the required memory block (see Fig.13) to give

a 16-bit address.

17.4.2 SOFTWARE PAGE CLEAR

The software can also initiate a page clear, by setting the

TXT9.CLEAR MEMORY bit. When it does so, every

location in the memory block pointed to by

TXT15.BLOCK<3:0> is cleared to a space code (20H).

The CLEAR MEMORY bit is not latched so the software

does not have to reset it after it has been set.

17.4 Page clearing

Only one page can be cleared in a TV line so if the

software requests a page clear it will be carried out on the

next TV line on which the Data Capture hardware does not

force the page to be cleared. A flag, TXT13.PAGE

CLEARING, is provided to indicate that a software

requested page clear is being carried out. The flag is set

when a logic 1 is written into the TXT9.CLEAR MEMORY

bit and is reset when the page clear has been completed.

Page clearing is performed on request from either the Data

Capture block, or the microcontroller under the control of

the embedded software.

At power-on and reset the whole of the page memory is

cleared. The TXT13.PAGE CLEARING bit will be set while

this takes place.

17.4.1 DATA CAPTURE PAGE CLEAR

If TXT0.INV ON bit = 1 and a page clear is initiated on

Block 8 all locations are cleared to 00H.

When a page header is acquired for the first time after a

new page request or a page header is acquired with the

erase (C4) bit set the page memory is ‘cleared’ to spaces

before the rest of the page arrives.

Table 10 Column and row to MOVX address (lower 10 bits of address)

ROW

COL. 0

.....

COL. 23

.....

COL. 31 COL. 32

.....

COL. 39

Row 0

Row 1

:

000H

020H

:

.....

:

017H

037H

:

.....

:

01FH

03FH

:

3F8H

3F0H

:

.....

:

3FFH

3F7H

:

Row 23

Row 24

Row 25

2E0H

300H

320H

.....

3F7H

317H

337H

.....

2FFH

31FH

.....

340H

338H

.....

347H

33FH

:

1999 Oct 27

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Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

lower 32 kbytes

7FFFH

handbook, halfpage

TXT BLOCK 8

TXT BLOCK 7

TXT BLOCK 6

TXT BLOCK 5

TXT BLOCK 4

TXT BLOCK 3

TXT BLOCK 2

TXT BLOCK 1

TXT BLOCK 9

TXT BLOCK 0

4400H

4000H

3C00H

3800H

3400H

3000H

2C00H

2800H

2400H

2000H

AUXILIARY

0000H

GSA034

Fig.13 DRAM memory mapping.

1999 Oct 27

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Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

Column

handbook, full pagewidth

0

10

20

30

39

Row 0

1

C

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

control data

non-displayable data

(byte 10 reserved)

0

9 10

23

<

>

<

>

active position TXT9.R 4:0 = 01H, TXT10.C 5:0 = 0AH, TXT11 = 43H

MBK962

Fig.14 TXT memory map.

1999 Oct 27

41

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

18 DATA CAPTURE

• Data Capture for Wide Screen Signalling (WSS) bit

decoding

The Data Capture section takes in the analog Composite

Video and Blanking Signal (CVBS), and from this extracts

the required data, which is then decoded and stored in

memory.

• Automatic selection between 525 WST/625 WST

• Automatic selection between 625 WST/VPS on line 16

of Vertical Blanking Interval (VBI)

• Real-time capture and decoding for WST Teletext in

hardware, to enable optimized microprocessor

throughput

The extraction of the data is performed in the digital

domain. The first stage is to convert the analog CVBS

signal into a digital form. This is done using an ADC

sampling at 12 MHz. The data and clock recovery is then

performed by a Multi-Rate Video Input Processor

(MulVIP). From the recovered data and clock the following

data types are extracted: WST Teletext (625/525), VPS

and WSS. The extracted data is stored in either memory

(DRAM) via the Memory interface or in SFR locations.

• Up to 10 pages stored on-chip

• Inventory of transmitted Teletext pages stored in the

Transmitted Page Table (TPT) and Subtitle Page Table

(SPT)

• Automatic detection of FASTEXT transmission

• Real-time packet 26 engine in hardware for processing

18.1 Data Capture features

accented, G2 and G3 characters

• Signal quality detector for WST/VPS data types

• Comprehensive Teletext language coverage

• Two CVBS inputs

• Video Signal Quality detector

• Data Capture for 625-line WST

• Data Capture for 525-line WST

• Full Field and Vertical Blanking Interval (VBI) data

capture of WST data.

• Data Capture for VPS data (Programme Delivery

Control (PDC) system A)

CVBS0 CVBS1

handbook, full pagewidth

CVBS

SWITCH

CVBS

SYNC

SEPARATOR

ADC

SYNC_FILTER

<

>

data 7:0

VCS

DATA SLICER

ACQUISITION

TIMING

AND

CLOCK RECOVERY

TTC

TTD

ACQUISITION

FOR

WST/VPS/WSS

GSA032

output data to memory interface and SFRs

Fig.15 Data capture block diagram.

42

1999 Oct 27

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

18.1.1 CVBS SWITCH

18.1.6.1 Making a page request

The CVBS switch is used to select the required analog

input depending on the value of TXT8.CVBS1/CVBS0.

A page is requested by writing a series of bytes into the

TXT3.PRD<4:0> SFR which corresponds to the number of

the page required. The bytes written into TXT3 are stored

in a RAM with an auto-incrementing address. The start

address for the RAM is set using the TXT2.SC<2:0> to

define which part of the page request is being written, and

TXT2.REQ<3:0> is used to define which of the 10 page

requests is being modified. If TXT2.REQ<3:0> is greater

than 09H, then data being written to TXT3 is ignored.

Table 12 shows the contents of the page request RAM.

18.1.2 ANALOG-TO-DIGITAL CONVERTER

The output of the CVBS switch is passed to a

differential-to-single-ended converter, although in this

device it is used in single-ended configuration with a

reference. The analog output of the differential amplifier is

converted into a digital representation by a full flash ADC

with a sampling rate of 12 MHz.

Up to 10 pages of teletext can be acquired on the 10 page

device, when TXT1.EXT PKT OFF is set to logic 1, and up

to 9 pages can be acquired when this bit is set to logic 0.

For a 20 page device the 10 page acquisition channels are

banked, the bank being selected using TXT2.ACQ BANK.

18.1.3 MULTI-RATE VIDEO INPUT PROCESSOR

The multi-rate video input processor is a Digital Signal

Processor designed to extract the data and recover the

clock from a digitised CVBS signal.

If the ‘DO CARE’ bit for part of the page number is set to

logic 0 then that part of the page number is ignored when

the teletext decoder is deciding whether a page being

received off air should be stored or not. For example, if the

‘DO CARE’ bits for the four subcode digits are all set to

logic 0 then every subcode version of the page will be

captured.

18.1.4 DATA STANDARDS

The data and clock standards that can be recovered are

shown in Table 11.

Table 11 Data slicing standards

CLOCK RATE

DATA STANDARD

(MHz)

Table 12 The contents of the Page request RAM

625 WST

525 WST

VPS

6.9375

5.7272

5.0

START

COLUMN

PRD4

PRD3 PRD2 PRD1 PRD0

0

DO CARE HOLD MAG2 MAG1 MAG0

Magazine

WSS

5.0

1

2

3

4

DO CARE PT3

Page Tens

PT2

PU2

X

PT1

PU1

HT1

HU1

PT0

PU0

HT0

HU0

18.1.5 DATA CAPTURE TIMING

DO CARE PU3

Page Units

The Data Capture timing section uses the synchronisation

information extracted from the CVBS signal to generate

the required horizontal and vertical reference timings.

DO CARE

Hour Tens

X

The timing section automatically recognises and selects

the appropriate timings for either 625 (50 Hz)

synchronisation or 525 (60 Hz) synchronisation. A flag

TXT12.VIDEO SIGNAL QUALITY is set when the timing

section is locked correctly to the incoming CVBS signal.

When TXT12.VIDEO SIGNAL QUALITY is set another

flag TXT12.525/625 SYNC can be used to identify the

standard.

DO CARE HU3

Hours

Units

HU2

5

6

7

DO CARE

Minutes

Tens

X

MT2

MU2

X

MT1

MU1

E1

MT0

MU0

E0

DO CARE MU3

Minutes

Units

18.1.6 ACQUISITION

X

The acquisition sections extracts the relevant information

from the serial stream of data from the MulVIP and stores

it in memory.

1999 Oct 27

43

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

When the HOLD bit is set to a logic 0 the teletext decoder

will not recognise any page as having the correct page

number and no pages will be captured. In addition to

providing the user requested hold function this bit should

be used to prevent the inadvertent capture of an unwanted

page when a new page request is being made.

For example, if the previous page request was for

page 100 and this was being changed to page 234, it

would be possible to capture page 200 if this arrived after

only the requested magazine number had been changed.

When a requested page header is acquired for the first

time, rows 1 to 23 of the relevant memory block are

cleared to space, i.e. have 20H written into every column,

before the rest of the page arrives. Row 24 is also cleared

if the TXT0.X24 POSN bit is set. If the

TXT1.EXT PKT OFF bit is set the extension packets

corresponding to the page are also cleared.

The last 8 characters of the page header are used to

provide a time display and are always extracted from every

valid page header as it arrives and written into the display

block.

The E1 and E0 bits control the error checking which should

be carried out on packets 1 to 23 when the page being

requested is captured. This is described in more detail in

Section 18.1.6.3.

The TXT0.DISABLE HEADER ROLL bit prevents any data

being written into row 0 of the page memory except when

a page is acquired off air i.e. rolling headers and time are

not written into the memory. The TXT1.ACQ OFF bit

prevents any data being written into the memory by the

teletext acquisition section.

For a multi-page device, each packet can only be written

into one place in the teletext RAM so if a page matches

more than one of the page requests the data is written into

the area of memory corresponding to the lowest numbered

matching page request.

When a parallel magazine mode transmission is being

received only headers in the magazine of the page

requested are considered valid for the purposes of rolling

headers and time. Only one magazine is used even if don’t

care magazine is requested. When a serial magazine

mode transmission is being received all page headers are

considered to be valid.

At power-up each page request defaults to any page, hold

on and error check Mode 0.

18.1.6.2 Rolling headers and time

When a new page has been requested it is conventional

for the decoder to turn the header row of the display green

and to display each page header as it arrives until the

correct page has been found.

18.1.6.3 Error checking

Before teletext packets are written into the page memory

they are error checked. The error checking carried out

depends on the packet number, the byte number, the error

check mode bits in the page request data and the

TXT1.8-BIT bit.

When a page request is changed (i.e. when the TXT3 SFR

is written to) a flag (PBLF) is written into bit 5, column 9,

row 25 of the corresponding block of the page memory.

The state of the flag for each block is updated every TV

line, if it is set for the current display block, the acquisition

section writes all valid page headers which arrive into the

display block and automatically writes an alphanumeric

green character into column 7 of row 0 of the display block

every TV line.

If an uncorrectable error occurs in one of the Hamming

checked addressing and control bytes in the page header

or in the Hamming checked bytes in packet 8/30, bit 4 of

the byte written into the memory is set, to act as an error

flag to the software. If uncorrectable errors are detected in

any other Hamming checked data the byte is not written

into the memory.

1999 Oct 27

44

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

Packet X/0

handbook, full pagewidth

'8-bit' bit = 0

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 1

0

1

2

3

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Packet X/1-23

'8-bit' bit = 0, error check mode = 0

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 0, error check mode = 1

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 0, error check mode = 2

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 0, error check mode = 3

0

1 2 3 4 5 6 7 8

0

1 2 3 4 5 6 7 8

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 1

0

1 2 3

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Packet X/24

'8-bit' bit = 0

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

'8-bit' bit = 1

0

1

2

3

Packet X/27/0

0

1

2

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Packet 8/30/0,1

0

1 2

Packet 8/30/2,3,4-15

0

1

2

3

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

MGK465

8-bit

data

odd parity

checked

8/4 Hamming

checked

Fig.16 Error checking.

45

1999 Oct 27

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

Basic Page Blocks (0 to 8/9)

handbook, full pagewidth

0

6

7

8

39

Row 0 OSD only

Packet X/0

Packet X/1

Packet X/2

Packet X/3

Packet X/4

Packet X/5

Packet X/6

Packet X/7

Packet X/8

Packet X/9

Packet X/10

Packet X/11

Packet X/12

Packet X/13

Packet X/14

Packet X/15

Packet X/16

Packet X/17

Packet X/18

Packet X/19

Packet X/20

Packet X/21

Packet X/22

Packet X/23

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

(1)

Packet X/24

(2)

25

Control Data

VPS Data

GSA003

(3)

0

9

10

23

(1) If ‘X24 POSN’ bit = 1.

(2) VPS data block 9, unused in blocks 0 to 8.

(3) Byte 10 reserved.

Fig.17 Packet storage locations.

1999 Oct 27

46

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

18.1.6.4 Teletext memory organisation

Packet 0, the page header, is split into two parts when it is

written into the text memory. The first 8 bytes of the header

contain control and addressing information. They are

Hamming decoded and written into columns 0 to 7 of

row 25. Row 25 also contains the magazine number of the

acquired page and the PLBF flag but the last 14 bytes are

unused and may be used by the software, if necessary.

The teletext memory is divided into 2 banks of 10 blocks.

Normally, when the TXT1.EXT PKT OFF bit is logic 0,

each of blocks 0 to 8 contains a teletext page arranged in

the same way as the basic page memory of the page

device and block 9 contains extension packets. When the

TXT1.EXT PKT OFF bit is logic 1, no extension packets

are captured and block 9 of the memory is used to store

another page. The number of the memory block into which

a page is written corresponds to the page request number

which resulted in the capture of the page.

Extension Packet Block (9)

(1)

handbook, full pagewidth

Row

0

1

2

Packet X/24 for page in block 0

Packet X/27/0 for page in block 0

Packet 8/30/0.1

Packet 8/30/2.3

3

(1)

Packet X/24 for page in block 1

4

Packet X/27/0 for page in block 1

5

6

(1)

Packet X/24 for page in block 2

Packet X/27/0 for page in block 2

7

(1)

8

Packet X/24 for page in block 3

Packet X/27/0 for page in block 3

9

(1)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Packet X/24 for page in block 4

Packet X/27/0 for page in block 4

(1)

Packet X/24 for page in block 5

Packet X/27/0 for page in block 5

(1)

Packet X/24 for page in block 6

Packet X/27/0 for page in block 6

(1)

Packet X/24 for page in block 7

Packet X/27/0 for page in block 7

(1)

Packet X/24 for page in block 8

Packet X/27/0 for page in block 8

Packet 8/30/4-15

VPS Data

(2)

GSA002

0

9 10

23

(1) If ‘X24 POSN’ bit = 0.

(2) Byte 10 reserved.

Fig.18 Extension packet storage locations.

1999 Oct 27

47

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

18.1.6.5 Row 25 data contents

The magazine serial (C11) bit indicates whether the

transmission is a serial or a parallel magazine

transmission. This affects the way the acquisition section

operates and is dealt with automatically.

The Hamming error flags are set if the on-board 8/4

Hamming checker detects that there has been an

uncorrectable (2-bit) error in the associated byte. It is

possible for the page to still be acquired if some of the

page address information contains uncorrectable errors if

that part of the page request was a ‘don’t care’. There is no

error flag for the magazine number as an uncorrectable

error in this information prevents the page being acquired.

The newsflash (C5), subtitle (C6), suppress header (C7),

inhibit display (C10) and language control (C12 to 14) bits

are dealt with automatically by the display section.

The update (C8) bit has no effect on the hardware.

The remaining 32 bytes of the page header are parity

checked and written into columns 8 to 39 of row 0. Bytes

which pass the parity check have the MSB set to a logic 0

and are written into page memory. Bytes with parity errors

are not written into the memory.

The interrupt sequence (C9) bit is automatically dealt with

by the acquisition section so that rolling headers do not

contain a discontinuity in the page number sequence.

Table 13 The data in row 25 of the basic page memory

COL

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

PU3

BIT 2

PU2

BIT 1

PU1

BIT 0

PU0

0

−

0

−

0

Hamming error

FOUND

1

0

PT3

MU3

C4

HU3

C6

C10

C14

0

PT2

MU2

MT2

HU2

C5

PT1

MU1

MT1

HU1

HT1

C8

PT0

MU0

MT0

HU0

HT0

C7

2

0

3

0

4

0

5

0

6

0

C9

7

0

C13

MAG2

0

C12

MAG1

0

C11

MAG0

0

8

9

PBLF

−

0

10 to 23

unused

−

1999 Oct 27

48

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

18.1.6.6 Inventory page

The bit for a particular page in the TPT is set when a page

header is received for that page. The bit in the SPT is set

when a page header for the page is received which has the

‘subtitle’ page header control bit (C6) set. The bit for a

particular page in the TPT is set when a page header is

received for that page. The bit in the SPT is set when a

page header for the page is received which has the

‘subtitle’ page header control bit (C6) set.

If the TXT0.INV ON bit is a logic 1, memory block 8 is used

as an inventory page.The inventory page consists of two

tables: the Transmitted Page Table (TPT) and the Subtitle

Page Table (SPT).

In each table, every possible combination of the page tens

and units digit, 00H to FFH, is represented by a byte.

Each bit of these bytes corresponds to a magazine number

so each page number, from 100H to 8FFH, is represented

by a bit in the table.

Bytes in the table

handbook, full pagewidth

column

0

8

16

24

32

39

row n

n + 1

n + 6

n + 7

bits in each byte

bit

7

0

6xx

5xx

4xx

3xx

2xx

1xx

8xx

7xx

MGD160

Fig.19 Transmitted/subtitle page organisation.

1999 Oct 27

49

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

0

39

handbook, full pagewidth

Row 0

1

2

Transmitted

Pages

Table

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Subtitle

Pages

Table

Unused

MGD165

0

23

Fig.20 Inventory page organisation.

1999 Oct 27

50

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

18.1.6.7 Packet 26 processing

18.3 VPS acquisition

One of the uses of packet 26 is to transmit characters

which are not in the basic teletext character set. The family

automatically decodes packet 26 data and, if a character

corresponding to that being transmitted is available in the

character set, automatically writes the appropriate

character code into the correct location in the teletext

memory. This is not a full implementation of the packet 26

specification allowed for in level 2 teletext, and so is often

referred to as level 1.5.

When the TXT0.VPS ON bit is set, any VPS data present

on line 16, field 0 of the CVBS signal at the input of the

teletext decoder is error checked and stored in row 25,

block 9 of the basic page memory. The device

automatically detects whether teletext or VPS is being

transmitted on this line and decodes the data

appropriately.

Each VPS byte in the memory consists of 4 biphase

decoded data bits (bits 0 to 3), a biphase error flag (bit 4)

and three logic 0s (bits 5 to 7).

By convention, the packets 26 for a page are transmitted

before the normal packets. To prevent the default

character data overwriting the packet 26 data the device

incorporates a mechanism which prevents packet 26 data

from being overwritten. The mechanism is disabled when

the Spanish national option is detected as the Spanish

transmission system sends even parity (i.e. incorrect)

characters in the basic page locations corresponding to

the characters sent via packet 26 and these will not

overwrite the packet 26 characters anyway. The special

treatment of Spanish national option is prevented if

TXT12.ROM VER3 is logic 0 or if the TXT8.DISABLE

SPANISH is set.

The TXT13.VPS RECEIVED bit is set by the hardware

whenever VPS data is acquired.

Full details of the VPS system can be found in the

“Specification of the Domestic Video Programme Delivery

Control System (PDC); EBU Tech. 3262-E”.

18.4 WSS acquisition

The Wide Screen Signalling data transmitted on line 23

gives information on the aspect ratio and display position

of the transmitted picture, the position of subtitles and on

the camera/film mode. Some additional bits are reserved

for future use. A total of 14 data bits are transmitted.

Packet 26 data is processed regardless of the

TXT1.EXT PKT OFF bit, but setting theTXT1.X26 OFF

disables packet 26 processing.

All of the available data bits transmitted by the Wide

Screen Signalling signal are captured and stored in SFRs

WSS1, WSS2 and WSS3. The bits are stored as groups of

related bits, and an error flag is provided for each group to

indicate when a transmission error has been detected in

one or more of the bits in the group.

The TXT8.PKT26 RECEIVED bit is set by the hardware

whenever a character is written into the page memory by

the packet 26 decoding hardware. The flag can be reset by

writing a logic 0 into the SFR bit.

Wide screen signalling data is only acquired when the

TXT8.WSS ON bit is set.

18.1.7 WST ACQUISITION

The family is capable of acquiring Level 1.5 625-line and

525-line World System Teletext.

The TXT8.WSS RECEIVED bit is set by the hardware

whenever wide screen signalling data is acquired. The flag

can be reset by writing a logic 0 into the SFR bit.

18.2 Broadcast service data detection

When a packet 8/30 is detected, or a packet 4/30 when the

device is receiving a 525 line transmission, the

TXT13. PKT 8/30 flag is set. The flag can be reset by

writing a 0 into the SFR bit.

column

0

handbook, full pagewidth

9

10

11 12

13 14

15 16

17 18

19 20

VPS

byte 4

21 22

23

teletext page

VPS

byte 5

row 25 header data byte 11 byte 12 byte 13 byte 14 byte 15

MBK964

Fig.21 VPS data storage.

51

1999 Oct 27

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

19 DISPLAY

• Level 1.5 WST features

• Single/Double/Quadruple Width and Height for

characters

The display section is based on the requirements for a

Level 1.5 WST Teletext. There are some enhancements

for use with locally generated OSDs.

• Variable flash rate controlled by software

• Fixed character matrix (H × V) 12 × 10

The display section reads the contents of the Display

memory and interprets the control/character codes. From

this information and other global settings, the display

produces the required RGB signals and Video/Data (Fast

Blanking) signal for a TV signal processing device.

• Soft colours using Colour Look Up Table (CLUT) with

4096 colour palette

• Fringing (Shadow) selectable from N-S-E-W direction

• Fringe colour selectable

The display is synchronised to the TV signal processing

device by way of horizontal and vertical sync signals

provided by external circuits (Slave Sync mode). From

these signals all display timings are derived.

• Meshing of defined area

• Contrast reduction of defined area

• Cursor

• 1 WST Character set (G0/G2) in single device (e.g.

Latin or Cyrillic or Greek or Arabic)

19.1 Display features

• Teletext and Enhanced On-Screen Display (OSD)

modes

• G1 Mosaic graphics, Limited G3 Line drawing

characters.

CLK

VSYNC

handbook, full pagewidth

HSYNC

DISPLAY

TIMING

address

data

PARALLEL/SERIAL

CONVERTER

AND FRINGING

address

data

control

MICROPROCESSOR

INTERFACE

FUNCTION

REGISTERS

address

data

DISPLAY DATA

ADDRESSING

ATTRIBUTE

HANDLING

to memory interface

from memory interface

data

DATA

BUFFER

CLUT RAM

data

CHARACTER

ROM

CHARACTER

FONT

ADDRESSING

AND

DRCs

address

DAC

G

DAC

MBK965

R

B

FB

Fig.22 Display block diagram.

1999 Oct 27

52

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

19.2 Display mode

Any two consecutive combination of ‘double width’ or

‘double size’ (0EH/BEH/0FH/BFH) activates quadruple

width characters, provided quadruple width characters are

enabled by TXT4.QUAD WIDTH ENABLE.

The display is configured as WST with additional serial and

global attributes. The display is configured as a fixed

25 rows with 40 characters per row.

Three vertical sizes are available normal (×1), double (×2),

quadruple (×4). The control characters ‘normal size’

(0CH/BCH) enable normal size, the ‘double height’ or

‘double size’ (0DH/BDH/0FH/BFH) enable double height

characters. Quadruple height characters are achieved by

using double height characters and setting the global

attributes TXT7.DOUBLE HEIGHT (expand) and

TXT7.BOTTOM/TOP.

19.3 Display feature descriptions

19.3.1 FLASH

Flashing causes the foreground colour pixel to be

displayed as the background pixels.The flash frequency is

controlled by software setting and resetting the MMR

Status (see Table 24) at the appropriate interval.

This attribute is set by the control character ‘flash’ (08H)

(see Fig.26) and remains valid until the end of the row or

until reset by the control character ‘steady’ (09H).

If double height characters are used in Teletext mode,

single height characters in the lower row of the double

height character are automatically disabled.

19.3.2 BOXES

19.3.4 COLOURS

Two types of boxes exist, the Teletext box and the

OSD box. The Teletext box is activated by the ‘start box’

control character (0BH), two start box characters are

required to begin a Teletext box, with the box starting

between the two characters. The box ends at the end of

the line or after a ‘end box’ control character.

19.3.4.1 Colour Look Up Table (CLUT)

A CLUT with 16 colour entries is provided. The colours are

programmable out of a palette of 4096 (4 bits per

R, G and B). The CLUT is defined by writing data to a RAM

that resides in the MOVX address space of the 80C51.

OSD boxes are started using size implying OSD control

characters (BCH, BDH, BEH and BFH). The box starts

after the control character (‘set after’) and ends either at

the end of the row or at the next size implying OSD

character (‘set at’). The attributes flash, Teletext box,

conceal, separate graphics, twist and hold graphics are all

reset at the start of an OSD box, as they are at the start of

the row. OSD boxes are only valid in TV mode which is

defined by TXT5 = 03H and TXT6 = 03H.

Table 14 CLUT colour values

RED<3:0>

GRN<3:0>

BLUE<3:0> COLOUR

(B11 TO B8) (B7 TO B4)

(B3 TO B0)

ENTRY

0000

...

0000

...

0000

1111

...

0

1

...

14

15

1111

0000

1111

19.3.3 SIZE

19.3.5 FOREGROUND COLOUR

The size of the characters can be modified in both the

horizontal and vertical directions.

The foreground colour is selected via a control character

(see Fig.26). The colour control characters take effect at

the start of the next character (set-after) and remain valid

until the end of the row, or until modified by a control

character. Only 8 foreground colours are available.

Three horizontal sizes are available normal (×1),

double (×2), quadruple (×4). The control characters

‘normal size’ (0CH/BCH) enables normal size, the ‘double

width’ or ‘double size’ (0EH/BEH/0FH/BFH) enables

double width characters.

The TEXT foreground control characters map to the CLUT

entries as shown in Table 15.

1999 Oct 27

53

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

Table 15 Foreground CLUT mapping

19.3.7 FRINGING

The display of fringing is controlled by the TXT4.SHADOW

bit.

CONTROL

CODE

DEFINED

COLOUR

CLUT ENTRY

00H

01H

02H

03H

04H

05H

06H

07H

black

red

0

1

2

3

4

5

6

7

When set all the alphanumeric characters being displayed

are shadowed, graphics characters are not shadowed.

green

yellow

blue

19.3.8 MESHING

The attribute effects the background colour being

displayed. Alternate pixels are displayed as the

background colour or video. The structure is offset by

1 pixel from scan line to scan line, thus achieving a

checker board display of the background colour and video.

magenta

cyan

white

TXT: There are two meshing attributes one that only

affects black background colours TXT4.B MESH ENABLE

and a second that only affects backgrounds other than

black TXT4.C MESH ENABLE. A black background is

defined as CLUT entry 8, a non-black background is

defined as CLUT entry 9 to 15.

19.3.6 BACKGROUND COLOUR

The control character new background (1DH) is used to

change the background colour to the current foreground

colour. The selection is immediate (set at) and remains

valid until the end of the row or until otherwise modified.

The TEXT background control characters map to the

CLUT entries as shown in Table 16.

19.3.9 CURSOR

The cursor operates by reversing the background and

foreground colours in the character position pointed to by

the active cursor position. The cursor is enabled using

TXT7.CURSOR ON. When active, the row the cursor

appears on is defined by TXT9.R<4:0> and the column is

defined by TXT10.C<5:0>. The position of the cursor can

be fixed using TXT9.CURSOR FREEZE.

Table 16 Background CLUT mapping

CONTROL

CODE

DEFINED

COLOUR

CLUT ENTRY

00H + 1DH

01H + 1DH

02H + 1DH

03H + 1DH

04H + 1DH

05H + 1DH

06H + 1DH

07H + 1DH

black

red

8

9

The valid range for row positioning is 0 to 24. The valid

range for column is 0 to 39.

green

yellow

blue

10

11

12

13

14

15

magenta

cyan

white

1999 Oct 27

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Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

handbook, full pagewidth

MBK972

Fig.23 South and south-west fringing.

handbook, full pagewidth

MBK973

Fig.24 Meshing and meshing/fringing (south + west).

handbook, full pagewidth

A B C D E F

MBK971

Fig.25 Cursor display.

55

1999 Oct 27

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

19.4 Character and attribute coding

The character coding is in a serial format, with only one

attribute being changed at any single location. The serial

attributes take effect either at the position of the attribute

(set at), or at the following location (set after). The attribute

remains effective until either modified by new serial

attributes or until the end of the row.

The default settings at the start of a row is:

• Foreground colour white (CLUT address 7)

• Background colour black (CLUT address 8)

• Horizontal size ×1, vertical size ×1 (normal size)

• Alphanumeric on

• Contiguous Mosaic Graphics

• Release Mosaics

• Flash off

• Box off

• Conceal off

• Twist off.

The attributes have individual codes which are defined in

the basic character table (see Fig.26).

1999 Oct 27

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Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

19.5 Screen and global controls

The use of teletext boxes for OSD messages has been

superseded in this device by the OSD box concept, but

these bits remain to allow teletext boxes to be used, if

required.

A number of attributes are available that affect the whole

display region, and cannot be applied selectively to

regions of the display.

19.6 Screen colour

19.5.1 DISPLAY MODES

Screen colour is displayed from 10.5 to 62.5 ms after the

active edge of the HSYNC input and on TV lines 23 to 310

inclusive, for a 625-line display, and lines 17 to 260

inclusive for a 525-line display.

The display mode is controlled by the bits in the TXT5 and

TXT6. There are three control functions: Text on,

Background on and Picture on. Separate sets of bits are

used inside and outside teletext boxes so that different

display modes can be invoked. TXT6 is used if the

newsflash (C5) or subtitle (C6) bits in row 25 of the basic

page memory are set, otherwise TXT5 is used. This allows

the software to set up the type of display required on

newsflash and subtitle pages (e.g. text inside boxes,

TV picture outside) this will be invoked without any further

software intervention when such a page is acquired.

The register bits TXT17.SCREEN COL<2:0> can be used

to define a colour to be displayed in place of TV picture

and the black background colour. If the bits are all set to

zero, the screen colour is defined as ‘transparent’ and

TV picture and background colour are displayed as

normal. Otherwise the bits define CLUT entries 9 to 15.

19.7 Text display control

When teletext box control characters are present in the

display page memory, the appropriate box control bit must

be set, TXT7.BOX ON 0, TXT7.BOX ON 1 − 23 or

TXT7.BOX ON 24. This allows the display mode to be

different inside the Teletext box compared to outside.

These bits are present to allow boxes in certain areas of

the screen to be disabled.

The display is organised as a fixed size of 25 rows

(0 to 24) of 40 columns (0 to 39), This is the standard size

for teletext transmissions. The control data in row 25 is not

displayed but is used to configure the display page

correctly.

Table 17 TXT display control bits

PICTURE ON

TEXT ON

BACKGROUND ON

EFFECT

Text mode, black screen

0

1

0

1

0

1

X

0

1

X

0

1

Text mode, background always black

Text mode

Video mode

Mixed text and TV mode

Text mode, TV picture outside text area

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SAA55xx

handbook, full pagewidth

0

39

Row 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

control data

non-displayable data

byte 10 reserved

0

9 10

23

MBK968

Fig.27 TXT text area.

1999 Oct 27

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Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

19.8 Display positioning

The screen colour extends over a large vertical and

horizontal range so that no offset is needed. The text area

is offset in both directions relative to the vertical and

horizontal sync pulses.

The display consists of the screen colour covering the

whole screen and the text area that is placed within the

visible screen area.

handbook, full pagewidth

horizontal sync

6 lines

offset

screen colour

offset = 8 µs

text

vertical

offset

SCREEN COLOUR AREA

horizontal

sync

delay

vertical

sync

TEXT AREA

0.25 character

offset

text area start

text area end

MGL150

56 µs

Fig.28 Display area positioning.

1999 Oct 27

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Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

19.8.1 SCREEN COLOUR DISPLAY AREA

Note that the Text Position Vertical Register should not be

set to 00H as the Display Busy interrupt is not generated

in these circumstances.

This area is covered by the screen colour. The screen

colour display area starts with a fixed offset of 8 µs from

the leading edge of the horizontal sync pulse in the

horizontal direction. A vertical offset is not necessary.

19.9 Character set

A set can consist of alphanumeric characters as required

by WST Teletext or customer definable OSD characters.

Table 18 Screen colour display area

Two character sets can be displayed at once. These are

the basic G0 set or the alternate G2 set (Twist Set).

The basic set is selected using TXT18.BS<1:0>.

The alternate/twist character set is defined by

TXT19.TS<1:0>. Since the alternate character set is an

option it can be enabled or disabled using TXT19.TEN,

and the language code that is defined for the alternate set

is defined by TXT19.TC<2:0>.

VECTOR

DESCRIPTION

Horizontal

Start at 8 µs after leading edge of

horizontal sync for 56 µs.

Vertical

Line 9, ﬁeld 1 (321, ﬁeld 2) to leading

edge of vertical sync (line numbering

using 625 standard).

19.8.2 TEXT DISPLAY AREA

19.10 Display synchronization

The text area can be defined to start with an offset in both

the horizontal and vertical direction.

The horizontal and vertical synchronizing signals from the

TV deflection are used as inputs. Both signals can be

inverted before being delivered to the Phase Selector

section.

Table 19 Text display area

VECTOR

DESCRIPTION

SFRs bits TXT1.HPOLARITY and TXT1.VPOLARITY

control the polarity.

Horizontal

Up to 40 full sized characters per row.

Start position setting from 8 to 64

characters from the leading edge of

horizontal sync. Fine adjustment in

quarter characters.

A line locked 12 MHz clock is derived from the 12 MHz free

running oscillator by the Phase Selector. This line locked

clock is used to clock the whole of the Display block.

Vertical

256 lines (nominal 41 to 297). Start

position setting from leading edge of

vertical sync, legal values are 4 to 64

lines. (line numbering using

625 standard).

The horizontal and vertical sync signals are synchronized

with the 12 MHz clock before being used in the Display

section.

19.11 Video/data switch (fast blanking) polarity

The polarity of the Video/data (fast blanking) signal can be

inverted. The polarity is set with the VDSPOL bit in the

MMR RGB Brightness.

The horizontal offset is set in the MMR Text Area Start.

The offset is done in full width characters using TAS<5:0>

and quarter characters using HOP<1:0> for fine setting.

The values 00H to 08H for TAS<5:0> will result in a

corrupted display.

Table 20 Fast blanking signal polarity

VDSPOL

VDS

CONDITION

RGB display

Video display

RGB display

Video display

The width of the text area is defined in the MMR Text Area

End by setting the end character value TAE<5:0>. This

number determines where the background colour of the

text area will end if set to extend to the end of the row. It will

also terminate the character fetch process thus eliminating

the necessity of a row end attribute. This entails however

writing to all positions.

0

1

0

1

The vertical offset is set in the MMR Text Position Vertical

Register. The offset value VOL<5:0> is done in number of

TV scan lines.

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SAA55xx

19.12 Video/data switch adjustment

20 MEMORY MAPPED REGISTERS (MMR)

To take into account the delay between the RGB values

and the VDS signal due to external buffering, the VDS

signal can be moved in relation to the RGB signals.

The VDS signal can be set to be either a clock cycle before

or after the RGB signal, or coincident with the RGB signal.

This is done using VDEL<2:0> in the MMR Configuration.

The memory mapped registers are used to control the

display. The registers are mapped into the microcontroller

MOVX address space, starting at address 87F0H and

extending to 87FFH.

Table 22 MMR address summary

REGISTER

NO.

MEMORY

ADDRESS

19.13 RGB brightness control

FUNCTION

A brightness control is provided to allow the RGB upper

output voltage level to be modified. The nominal value is

1 V into a 15 Ω resistor, but can be varied between

0.7 and 1.2 V.

1

2

87F1H

87F2H

87F3H

87F4H

87F7H

87F8H

87FCH

87FDH

87FFH

Text Position Vertical

Text Area Start

Fringing Control

Text Area End

RGB Brightness

Status

3

4

The brightness is set in the RGB Brightness Register.

7

Table 21 RGB brightness

8

12

13

15

HSYNC Delay

VSYNC Delay

Conﬁguration

BRI3 TO BRI0

RGB BRIGHTNESS

lowest value

0000

...

1111

highest value

19.14 Contrast reduction

The COR bits in SFRs TXT5 and TXT6 control when the

COR output of the device is activated (i.e. pulled LOW).

This output is intended to act on the TVs display circuits to

reduce contrast of the video when it is active. The result of

contrast reduction is to improve the readability of the text

in a mixed teletext and video display.

The bits in the TXT5 and TXT6 SFRs allow the display to

be set up so that, for example, the areas inside teletext

boxes will be contrast reduced when a subtitle is being

displayed but that the rest of the screen will be displayed

as normal video.

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Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

Table 23 MMR map

ADD R/W

NAME

7

6

5

4

3

2

1

0

RESET

87F1 R/W Text Position

Vertical

−

VOL5

VOL4

VOL3

VOL2

VOL1

VOL0

00H

87F2 R/W Text Area

Start

HOP1

FRC3

−

HOP0

TAS5

FRC1

TAE5

−

TAS4

FRC0

TAE4

−

TAS3

TAS2

TAS1

TAS0

FRDW

TAE0

BRI0

00H

87F3 R/W Fringing

Control

FRC2

FRDN FRDE FRDS

87F4 R/W Text Area

End

−

TAE3

BRI3

TAE2

BRI2

TAE1

BRI1

87F7 R/W RGB

Brightness

VDSPOL

87F8

R

Status

BUSY

FIELD

−

FLR

−

00H

W

−

FLR

−

87FC R/W HSYNC

Delay

HSD6

HSD5

HSD4

HSD3 HSD3 HSD1

HSD0

87FD R/W VSYNC

Delay

−

VSD6

VSD5

VSD4

VSD3 VSD2 VSD1

VSD0

00H

87FF R/W Conﬁguration

VDEL2 VDEL1 VDEL0 TXT/V

−

Table 24 MMR bit deﬁnition

REGISTER

FUNCTION

Text Position Vertical

VOL5 to VOL0

display start vertical offset from VSYNC (lines)

Text Area Start

HOP1 to HOP0

TAS5 to TAS0

ﬁne horizontal offset in quarter of characters

text area start

Fringing Control

FRC3 to FRC0

FRDN

fringing colour, value address of CLUT

fringe in north direction (logic 1)

fringe in east direction (logic 1)

fringe in south direction (logic 1)

fringe in west direction (logic 1)

FRDE

FRDS

FRDW

Text Area End

TAE5 to TAE0

RGB Brightness

VDSPOL

text area end, in full characters

VDS polarity

0 = RGB (1), Video (0)

1 = RGB (0), Video (1)

RGB brightness control

BRI3 to BRI0

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On-Screen Display (OSD)

SAA55xx

REGISTER

Status read

FUNCTION

BUSY

FIELD

FLR

access to display memory could cause display problems (logic 1)

even ﬁeld (logic 1)

active ﬂash region background only displayed (logic 1)

Status write

FLR

active ﬂash region background colour only displayed (logic 1)

HSYNC delay, in full size characters

HSYNC Delay

HSD6 to HSD0

VSYNC Delay

VSD6 to VSD0

Conﬁguration

VSYNC delay in number of 8-bit 12 MHz clock cycles

VDEL2 to VDEL0 pixel delay between VDS and RGB output

000 = VDS switched to video, not active

001 = VDS active one pixel earlier then RGB

010 = VDS synchronous to RGB

100 = VDS active one pixel after RGB

TXT/V

BUSY signal switch; horizontal (logic 1)

1999 Oct 27

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Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

21 LIMITING VALUES

In accordance with Absolute Maximum Rating System (IEC 134).

SYMBOL

V_DDX

PARAMETER

CONDITIONS

MIN.

−0.5

MAX.

UNIT

supply voltage (all supplies)

input voltage (any input)

+4.0

V

V_I

note 1

−0.5

−

V_DD+ 0.5 or 4.1

V_DD+ 0.5

±10

V

V_O

I_O

output voltage (any output)

output current (each output)

DC input or output diode current

operating ambient temperature

storage temperature

V

mA

°C

I_IOK

T_amb

T_stg

−

±20

−20

−55

+70

+125

Note

1. This maximum value refers to 5 V tolerant I/Os and may be 6 V maximum but only when V_DDis present.

22 CHARACTERISTICS

V_DD= 3.3 V ± 10%; V_SS= 0 V; T_amb= −20 to +70 °C; unless otherwise speciﬁed.

SYMBOL

Supplies

V_DDX

I_DDP

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

any supply voltage (V_DDto V_SS

periphery supply current

core supply current

)

3.0

1

3.3

3.6

−

V

note 1

−

mA

I_DDC

−

15

18

6

I_DDC(id)

I_DDC(pd)

Idle mode core supply current

−

4.6

0.76

Power-down mode core supply

current

−

1

I_DDC(stb)

Standby mode core supply

current

−

5.11

6.50

mA

I_DDA

analog supply current

−

45

48

1

mA

I_DDA(id)

I_DDA(pd)

Idle mode analog supply current

0.87

0.45

Power-down mode analog

supply current

0.7

I_DDA(stb)

Standby mode analog supply

current

−

0.95

1.20

mA

Digital inputs

RESET

V_IL

LOW-level input voltage

HIGH-level input voltage

−

1.34

5.5

V

V_IH

1.49

0.44

V_hys

hysteresis voltage of Schmitt

trigger input

0.58

I_LI

input leakage current

V_I= 0

−

0.17

µA

kΩ

R_pd

equivalent pull-down resistance V_I= V_DD

55.73

70.71

92.45

1999 Oct 27

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Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

HSYNC, VSYNC

V_IL

LOW-level input voltage

HIGH-level input voltage

−

1.31

V

V_IH

V_hys

1.44

0.40

5.5

hysteresis voltage of Schmitt

trigger input

0.56

I_LI

input leakage current

V_I= 0 to V_DD

−

0.00

µA

Digital outputs

FRAME, VDS

V_OL

V_OH

t_r

LOW-level output voltage

HIGH-level output voltage

output rise time

I_OL= 3 mA

I_OH= 3 mA

−

0.13

−

V

2.84

7.50

V

10% to 90%;

C_L= 70 pF

8.85

10.90

ns

t_f

output fall time

10% to 90%;

C_L= 70 pF

6.70

7.97

10.00

ns

COR (OPEN-DRAIN OUTPUT)

V_OL

V_OH

LOW-level output voltage

I_OL= 3 mA

−

0.14

V

HIGH-level pull-up output

voltage

I_OL= −3 mA;

push-pull

2.84

−

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

output rise time

−

0.00

5.50

0.12

11.10

V

0.00

−

V

V_I= 0 to V_DD

−

µA

ns

t_r

10% to 90%;

C_L= 70 pF

7.20

8.64

t_f

output fall time

10% to 90%;

C_L= 70 pF

4.90

7.34

9.40

ns

Digital input/outputs

P0.0 TO P0.4, P0.7, P1.0 TO P1.1, P2.1 TO P2.7, P3.0 TO P3.7

V_IL

LOW-level input voltage

HIGH-level input voltage

−

1.28

5.50

0.55

V

V_IH

V_hys

1.43

0.41

hysteresis voltage of Schmitt

trigger input

I_LI

input leakage current

V_I= 0 to V_DD

I_OL= 4 mA

−

0.01

0.18

5.50

µA

V

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

−

I_OH= −4 mA;

2.81

V

push-pull

t_r

t_f

output rise time

output fall time

10% to 90%;

C_L= 70 pF

push-pull

6.50

5.70

8.47

7.56

10.70

10.00

ns

10% to 90%;

C_L= 70 pF

1999 Oct 27

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Standard TV microcontrollers with

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SAA55xx

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

P1.2, P1.3 AND P2.0

V_IL

LOW-level input voltage

HIGH-level input voltage

−

1.29

V

V_IH

V_hys

1.45

0.42

5.50

0.56

hysteresis voltage of Schmitt

trigger input

I_LI

input leakage current

V_I= 0 to V_DD

I_OL= 4 mA

−

0.02

0.17

5.50

µA

V

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

−

I_OH= −4 mA;

2.81

V

push-pull

t_r

output rise time

output fall time

10% to 90%;

C_L= 70 pF;

push-pull

7.00

5.40

8.47

7.36

10.50

9.30

ns

t_f

10% to 90%;

C_L= 70 pF

P0.5 AND P0.6

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

−

1.28

5.50

0.11

0.58

V

1.43

−

V

V_I= 0 to V_DD

I_OL= 8 mA

µA

V

V_hys

hysteresis voltage of Schmitt

trigger input

0.42

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

−

0.20

5.50

V

I_OH= −8 mA;

2.76

push-pull

t_r

t_f

output rise time

output fall time

10% to 90%;

C_L= 70 pF;

push-pull

7.40

4.20

8.22

4.57

8.80

5.20

ns

10% to 90%;

C_L= 70 pF

P1.4 TO P1.7 (OPEN-DRAIN)

V_IL

LOW-level input voltage

−

1.45

5.50

0.60

V

V_IH

V_hys

HIGH-level input voltage

1.62

0.49

hysteresis voltage of Schmitt

trigger input

I_LI

input leakage current

LOW-level output voltage

output fall time

V_I= 0 to V_DD

I_OL= 8 mA

−

0.13

µA

V

V_OL

t_f

−

0.35

10% to 90%;

C_L= 70 pF

69.70

83.67

103.30

ns

1999 Oct 27

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Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Analog inputs

CVBS0 AND CVBS1

V_sync

sync voltage amplitude

0.1

0.7

0.3

0.6

1.4

V

V_vid(p-p)

video input voltage amplitude

(peak-to-peak value)

1.0

Z_source

V_IH

source impedance

HIGH-level input voltage

input capacitance

0

−

250

Ω

3.0

−

V_DDA+ 0.3

10

V

C_I

pF

IREF

R_gnd

resistor to ground

resistor

−

24

−

kΩ

tolerance 2%

ADC0 TO ADC3

V_IH

C_I

HIGH-level input voltage

input capacitance

−

V_DDA

10

V

pF

VPE

V_IH

HIGH-level input voltage

−

9.0

V

Analog outputs

R, G AND B

I_OL

I_OH

output current (black Level)

V_DDA= 3.3 V

−10

−

+10

7.3

µA

output current (maximum

Intensity)

V_DDA= 3.3 V

Intensity level

code = 15 dec

6.0

6.67

mA

output current (70% of full

Intensity)

V

_DDA= 3.3 V

4.2

4.7

5.1

mA

Intensity level

code = 0 dec

R_load

C_L

load resistor to V_SSA

load capacitance

resistor

tolerance 5%

−

150

−

Ω

−

15

pF

Analog input/output

SYNC_FILTER

C_sync

V_sync

storage capacitor to ground

−

100

−

nF

V

sync ﬁlter level voltage for

nominal sync amplitude

0.35

0.55

0.75

Crystal oscillator

XTALIN

V_IL

V_IH

C_I

LOW-level input voltage

HIGH-level input voltage

input capacitance

V_SSA

−

V

−

V_DDA

10

V

pF

1999 Oct 27

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Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

SYMBOL

XTALOUT

C_O

Crystal speciﬁcation; notes 2 and 3

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

output capacitance

−

10

pF

f_xtal

nominal frequency

fundamental

mode

12

−

MHz

C_L

C₁

R_r

crystal load capacitance

crystal motional capacitance

resonance resistance

−

-

30

20

60

−

pF

fF

T_amb= 25 °C

−

Ω

C_osc

C₀

T_xtal

X_j

capacitors at XTALIN, XTALOUT T_amb= 25 °C

−

note 4

pF

°C

crystal holder capacitance

temperature range

adjustment tolerance

drift

T_amb= 25 °C

−

note 5

−20

−

+25

−

+85

±50 × 10⁻⁶

±100 × 10⁻⁶

X_d

−

Notes

1. Peripheral current is dependent on external components and voltage levels on I/Os.

2. Crystal order number 4322 143 05561.

3. If the 4322 143 05561 crystal is not used, then the formulae in the crystal specification should be used. Where

C_IO= 7 pF, the mean of the capacitances due to the chip at XTALIN and at XTALOUT. C_extis a value for the mean

of the stray capacitances due to the external circuit at XTALIN and XTALOUT. The maximum value for the crystal

holder capacitance is to ensure start-up, C_oscmay need to be reduced from the initially selected value.

4. C_osc(typ)= 2C_L− C_IO− C_ext

5. C_0(max)= 35 − ¹⁄₂(C_osc+ C_IO+ C_ext

)

1999 Oct 27

69

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

22.1 I²C-bus characteristics

Table 25 I²C-bus characteristics

FAST-MODE I²C-bus

MIN. MAX.

400

SYMBOL

f_SCL

PARAMETER

UNIT

SCL clock frequency

bus free time between a STOP and START condition

0

kHz

µs

t_BUF

1.3

−

t_HD;STA

hold time (repeated) START condition. After this period, the 0.6

ﬁrst clock pulse is generated.

µs

t_LOW

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

LOW period of the SCL clock

1.3

0.6

0

−

µs

ns

µs

pF

HIGH period of the SCL clock

−

set-up time for a repeated START condition

data hold time; notes 1 and 2

−

0.9

−

data set-up time, note 3

100

20

0.6

−

rise time of both SDA and SCL signals

fall time of both SDA and SCL signals

set-up time for STOP condition

capacitive load for each bus line

300

−

t_f

t_SU;STO

C_b

400

Notes

1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IL(min)of the SCL

signal) in order to bridge the undefined region of the falling edge of SCL.

2. The maximum f_HD;DAThas only to be met if the device does not stretch the LOW period t_LOWof the SCL signal.

3. A fast-mode I²C-bus device can be used in a standard mode I²C-bus system but the requirement t_SU;DAT≥250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.

If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

t

_r(max)+ t_SU;DAT= 1000 + 250 +1250 ns (according to the standard mode I²C-bus specification) before the SCL line

is released.

1999 Oct 27

70

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

23 QUALITY AND RELIABILITY

This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated

Circuits SNW-FQ-611-Part E”. The principal requirements are shown in Tables 26 to 29.

23.1 Group A

Table 26 Acceptance tests per lot

TEST

REQUIREMENTS⁽¹⁾

Mechanical

Electrical

cumulative target: <80 ppm

cumulative target: <100 ppm

Note

1. ppm = fraction of defective devices, in parts per million.

23.2 Group B

Table 27 Processability tests (by package family)

TEST

REQUIREMENTS

Solderability

0/16 on all lots

0/15 on all lots

Mechanical

Solder heat resistance

23.3 Group C

Table 28 Reliability tests (by process family)

TEST

CONDITIONS

168 hours at T_j= 150 °C

REQUIREMENTS⁽¹⁾

<1000 FPM at T_j= 150 °C

Operational life

Humidity life

temperature, humidity, bias 1000 hours, <2000 FPM

85 °C, 85% RH (or equivalent test)

Temperature cycling performance T_stg(min)to T_stg(max)

<2000 FPM

Note

1. FPM = fraction of devices failing at test condition, in Failures Per Million.

Table 29 Reliability tests (by device type)

TEST

ESD and latch-up

CONDITIONS

ESD Human body model 100 pF, 1.5 kΩ 2000 V

REQUIREMENTS

ESD Machine model 200 pF, 0 Ω

200 V

100 mA, 1.5 × V_DD(absolute maximum)

latch-up

1999 Oct 27

71

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

25 ELECTROMAGNETIC COMPATIBILITY (EMC)

GUIDELINES

Using a device socket will unfortunately add to the area

and inductance of the external bypass loop.

Optimization of circuit return paths and minimisation of

common mode emission will be assisted by using a double

sided Printed-Circuit Board (PCB) with low inductance

ground plane.

A ferrite bead or inductor with resistive characteristics at

high frequencies may be utilised in the supply line close to

the decoupling capacitor to provide a high impedance.

To prevent pollution by conduction onto the signal lines

(which may then radiate) signals connected to the V_DD

supply via a pull-up resistor should not be connected to

the IC side of this ferrite component.

On a single sided printed-circuit board a local ground plane

under the whole Integrated Circuit (IC) should be present

as shown in Fig.30. This should be connected by the

widest possible connection back to the printed-circuit

board ground connection, and bulk electrolytic decoupling

capacitor. It should preferably not connect to other

grounds on the way, and no wire links should be present in

this connect. The use of wire links increases ground

bounce by introducing inductance into the ground.

OSCGND should be connected only to the crystal load

capacitors and not to the local or circuit ground.

Physical connection distances to associated active

devices should be short.

Output traces should be routed with close proximity to

mutually coupled ground return paths.

The supply pins can be decoupled at the pin to the ground

plane under the IC. This is easily accomplished using

surface mount capacitors, which are more effective than

leaded components at high frequency.

GND +3.3 V

handbook, full pagewidth

electrolytic decoupling capacitor (2 µF)

ferrite beads

other

GND

connections

SM decoupling capacitors (10 to 100 nF)

under-IC GND plane

GND connection

note: no wire links

IC

V

SSA

SSC

MBK979

Fig.30 Power supply connections for EMC.

73

1999 Oct 27

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

26 PACKAGE OUTLINES

SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)

SOT247-1

D

M

E

A

2

A

L

A

1

c

e

(e )

1

w M

Z

b

1

M

H

b

52

27

pin 1 index

E

1

26

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

A

2

max.

(1)

Z

1

w

UNIT

b

c

D

E

e

L

M

H

1

E

min.

max.

1.3

0.8

0.53

0.40

0.32

0.23

47.9

47.1

14.0

13.7

3.2

2.8

15.80

15.24

17.15

15.90

mm

5.08

0.51

4.0

1.778

15.24

0.18

1.73

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

90-01-22

95-03-11

SOT247-1

1999 Oct 27

74

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm

SOT407-1

y

X

A

51

75

50

26

(1)

76

Z

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

L

pin 1 index

detail X

100

1

25

Z

D

v

M

A

B

e

w M

b

p

D

B

H

v

M

5

D

0

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

θ

1

2

3

p

E

p

D

E

max.

7^o

0^o

0.20 1.5

0.05 1.3

0.28 0.18 14.1 14.1

0.16 0.12 13.9 13.9

16.25 16.25

15.75 15.75

0.75

0.45

1.15 1.15

0.85 0.85

mm

1.6

0.25

0.5

1.0

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-12-19

97-08-04

SOT407-1

1999 Oct 27

75

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

27 SOLDERING

The total contact time of successive solder waves must not

exceed 5 seconds.

27.1 Introduction to soldering through-hole mount

packages

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

This text gives a brief insight to wave, dip and manual

soldering. A more in-depth account of soldering ICs can be

found in our “Data Handbook IC26; Integrated Circuit

Packages” (document order number 9398 652 90011).

Wave soldering is the preferred method for mounting of

through-hole mount IC packages on a printed-circuit

board.

27.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the

package, either below the seating plane or not more than

2 mm above it. If the temperature of the soldering iron bit

is less than 300 °C it may remain in contact for up to

10 seconds. If the bit temperature is between

27.2 Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joints for more than 5 seconds.

300 and 400 °C, contact may be up to 5 seconds.

27.4 Suitability of through-hole mount IC packages for dipping and wave soldering methods

SOLDERING METHOD

PACKAGE

DIPPING

WAVE

DBS, DIP, HDIP, SDIP, SIL

suitable

suitable⁽¹⁾

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

1999 Oct 27

76

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

28 DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

29 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

30 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1999 Oct 27

77

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

NOTES

1999 Oct 27

78

Philips Semiconductors

Preliminary speciﬁcation

Standard TV microcontrollers with

On-Screen Display (OSD)

SAA55xx

NOTES

1999 Oct 27

79

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For all other countries apply to: Philips Semiconductors,

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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

68

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

545004/01/pp80

Date of release: 1999 Oct 27

Document order number: 9397 750 05048


型号：	SAA5553PS
厂家：	NXP
描述：	Standard TV Microcontrollers with On-Screen Display(OSD) 标准电视微控制器与屏幕显示（ OSD ）微控制器电视
文件：	总80页 (文件大小：336K)
中文：	中文翻译
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