SAA7111AH/03 [NXP]
IC SPECIALTY CONSUMER CIRCUIT, PQFP64, PLASTIC, SOT-393, QFP-64, Consumer IC:Other;型号: | SAA7111AH/03 |
厂家: | NXP |
描述: | IC SPECIALTY CONSUMER CIRCUIT, PQFP64, PLASTIC, SOT-393, QFP-64, Consumer IC:Other 商用集成电路 |
文件: | 总75页 (文件大小:479K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA7111A
Enhanced Video Input Processor
(EVIP)
1998 May 15
Product specification
Supersedes data of 1997 May 26
File under Integrated Circuits, IC22
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
CONTENTS
17.2.1
17.2.2
17.2.3
17.2.4
17.2.5
17.2.6
17.2.7
17.2.8
Subaddress 00
Subaddress 02
Subaddress 03
Subaddress 04
Subaddress 05
Subaddress 06
Subaddress 07
Subaddress 08
Subaddress 09
Subaddress 0A
Subaddress 0B
Subaddress 0C
Subaddress 0D
Subaddress 0E
Subaddress 10
Subaddress 11
Subaddress 12
Subaddress 13
Subaddress 15
Subaddress 16
Subaddress 17
1
2
3
4
5
6
7
8
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
17.2.9
17.2.10
17.2.11
17.2.12
17.2.13
17.2.14
17.2.15
17.2.16
17.2.17
17.2.18
17.2.19
17.2.20
17.2.21
17.2.22
17.2.23
17.2.24
17.2.25
PINNING
FUNCTIONAL DESCRIPTION
8.1
8.2
8.2.1
8.2.2
8.3
Analog input processing
Analog control circuits
Clamping
Gain control
Chrominance processing
Luminance processing
RGB matrix
8.4
8.5
8.6
VBI-data bypass
8.7
8.8
8.9
VPO-bus (digital outputs)
Reference signals HREF, VREF and CREF
Synchronization
Subaddress 1A (read-only register)
Subaddress 1B (read-only register)
Subaddress 1C (read-only register)
Subaddress 1F (read-only register)
8.10
8.11
8.12
8.13
8.13.1
Clock generation circuit
Power-on reset and CE input
RTCO output
The Line-21 text slicer
Suggestions for I2C-bus interface of the display
software reading line-21 data
18
FILTER CURVES
18.1
18.2
18.3
18.4
Anti-alias filter curve
TUF-block filter curve
Luminance filter curves
Chrominance filter curves
9
BOUNDARY-SCAN TEST
9.1
9.2
Initialization of boundary-scan circuit
Device identification codes
19
20
21
I2C-BUS START SET-UP
PACKAGE OUTLINES
SOLDERING
10
11
12
13
14
GAIN CHARTS
LIMITING VALUES
CHARACTERISTICS
TIMING DIAGRAMS
CLOCK SYSTEM
21.1
21.2
21.3
21.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
22
23
24
DEFINITIONS
14.1
14.2
Clock generation circuit
Power-on control
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
15
OUTPUT FORMATS
APPLICATION INFORMATION
Layout hints
16
16.1
17
I2C-BUS DESCRIPTION
17.1
17.2
I2C-bus format
I2C-bus detail
1998 May 15
2
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
1
FEATURES
• Four analog inputs, internal analog source selectors,
e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)
• Two analog preprocessing channels
• Fully programmable static gain for the main channels or
automatic gain control for the selected CVBS or Y/C
channel
• Odd/even field identification by a non interlace CVBS
input signal
• Switchable white peak control
• Fix level for RGB output format during horizontal
• Two built-in analog anti-aliasing filters
• Two 8-bit video CMOS analog-to-digital converters
• On-chip clock generator
blanking
• 720 active samples per line on the YUV bus
• One user programmable general purpose switch on an
output pin
• Line-locked system clock frequencies
• Built-in line-21 text slicer
• Digital PLL for horizontal-sync processing and clock
generation
• A 27 MHz Vertical Blanking Interval (VBI) data bypass
programmable by I2C-bus for INTERCAST applications
• Requires only one crystal (24.576 MHz) for all standards
• Horizontal and vertical sync detection
• Power-on control
• Two via I2C-bus switchable outputs for the digitized
CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0)
• Automatic detection of 50 and 60 Hz field frequency,
and automatic switching between PAL and NTSC
standards
• Chip enable function (reset for the clock generator and
power save mode up from chip version 3)
• Luminance and chrominance signal processing for
PAL BGHI, PAL N, PAL M, NTSC M, NTSC N,
NTSC 4.43, NTSC-Japan and SECAM
• Compatible with memory-based features (line-locked
clock)
• User programmable luminance peaking or aperture
• Boundary scan test circuit complies with the
correction
‘IEEE Std. 1149.1 − 1990’ (ID-Code = 0 F111 02 B)
• I2C-bus controlled (full read-back ability by an external
• Cross-colour reduction for NTSC by chrominance comb
filtering
controller)
• PAL delay line for correcting PAL phase errors
• Real time status information output (RTCO)
• Brightness Contrast Saturation (BCS) control on-chip
• The YUV (CCIR-601) bus supports a data rate of:
– 864 × fH = 13.5 MHz for 625 line sources
• Low power (<0.5 W), low voltage (3.3 V), small package
(LQFP64)
• 5 V tolerant digital I/O ports.
2
APPLICATIONS
– 858 × fH = 13.5 MHz for 525 line sources.
• Desktop/Notebook (PCMCIA) video
• Multimedia
• Data output streams for 16, 12 or 8-bit width with the
following formats:
• Digital television
• Image processing
• Video phone
– YUV 4 : 1 : 1 (12-bit)
– YUV 4 : 2 : 2 (16-bit)
– YUV 4 : 2 : 2 (CCIR-656) (8-bit)
– RGB (5, 6, and 5) (16-bit) with dither
– RGB (8, 8, and 8) (24-bit) with special application.
• Intercast.
1998 May 15
3
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
The pure 3.3 V CMOS circuit SAA7111A, analog
3
GENERAL DESCRIPTION
front-end and digital video decoder, is a highly integrated
circuit for desktop video applications. The decoder is
based on the principle of line-locked clock decoding and
is able to decode the colour of PAL, SECAM and NTSC
signals into CCIR-601 compatible colour component
values. The SAA7111A accepts as analog inputs CVBS
or S-video (Y/C) from TV or VTR sources. The circuit is
I2C-bus controlled. The SAA7111A then supports several
text features as Line 21 data slicing and a high-speed VBI
data bypass for Intercast.
The Enhanced Video Input Processor (EVIP) is a
combination of a two-channel analog preprocessing
circuit including source selection, anti-aliasing filter and
ADC, an automatic clamp and gain control, a Clock
Generation Circuit (CGC), a digital multi-standard
decoder (PAL BGHI, PAL M, PAL N, NTSC M,
NTSC-Japan NTSC N and SECAM), a
brightness/contrast/saturation control circuit, a colour
space matrix (see Fig.1) and a 27 MHz VBI-data bypass.
4
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
3.0
3.1
0
3.3
3.3
25
3.6
3.5
70
−
V
VDDA
Tamb
PA+D
analog supply voltage
V
operating ambient temperature
analog and digital power
°C
W
−
0.5
5
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
SAA7111AHZ
SAA7111AH
LQFP64
QFP64
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
SOT314-2
SOT393-1
plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14 × 14 × 2.7 mm
1998 May 15
4
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
6
BLOCK DIAGRAM
VBI DATA BYPASS
UPSAMPLING FILTER
BYPASS
14
AOUT
34 to 39
42 to 51
CHROMINANCE
CIRCUIT
AND
BRIGHTNESS
CONTRAST
SATURATION
CONTROL
ANALOG
PROCESSING
AND
ANALOG-TO-
DIGITAL
12
VPO
(0 : 15)
YUV-to-RGB
CONVERSION
AND
OUTPUT
FORMATTER
AI11
AI12
10
C/CVBS
UV
Y
CONVERSION
8
6
52
31
AI21
AI22
FEI
HREF
AD2 AD1
64
13
n.c.
V
SSS
2
Y
CON
I C-BUS
CONTROL
53
GPSW
ANALOG
PROCESSING
CONTROL
2
I C-BUS
LUMINANCE
CIRCUIT
61
62
63
IICSA
SDA
SCL
INTERFACE
Y/CVBS
10
n.c.
Y
9,5
V
V
SSA1-2
DDA1-2
SAA7111A
11,7
CLOCKS
TEST
CONTROL
BLOCK
54
55
XTAL
3
TDI
CLOCK
GENERATION
CIRCUIT
XTALI
59
4
TCK
21
22
FOR
SYNCHRONIZATION
CIRCUIT
LLC2
CREF
LLC
TMS
BOUNDARY
SCAN TEST
AND
58
TRST
POWER-ON
CONTROL
20
23
LFCO
2
SCAN TEST
TDO
RES
56,40,32,26,19
57,41,33,25,18
30
27
17
29
28
60
15
16
24
MGG061
V
V
VS HS
RTS0 RTS1 RTCO
V
V
VREF
CE
DDD1-5
SSD1-5
DDA0
SSA0
Fig.1 Block diagram.
5
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
7
PINNING
PIN
SYMBOL
I/O/P
DESCRIPTION
(L)QFP64
n.c.
1
2
−
O
I
Do not connect.
TDO
TDI
Test data output for boundary scan test; note 1.
Test data input for boundary scan test; note 1.
3
TMS
VSSA2
AI22
4
I
Test mode select input for boundary scan test or scan test; note 1.
Ground for analog supply voltage channel 2.
Analog input 22.
5
P
I
6
VDDA2
AI21
7
P
I
Positive supply voltage for analog channel 2 (+3.3 V).
Analog input 21.
8
VSSA1
AI12
9
P
I
Ground for analog supply voltage channel 1.
Analog input 12.
10
11
12
13
14
15
16
17
VDDA1
AI11
P
I
Positive supply voltage for analog channel 1 (+3.3 V).
Analog input 11.
VSSS
AOUT
VDDA0
VSSA0
VREF
P
O
P
P
O
Substrate ground connection.
Analog test output; for testing the analog input channels.
Positive supply voltage for internal Clock Generator Circuit (CGC) (+3.3 V).
Ground for internal CGC.
Vertical reference output signal (I2C-bit COMPO = 0) or inverse composite blanking
signal (I2C-bit COMPO = 1) (enabled via I2C-bus bit OEHV).
VDDD5
VSSD5
LLC
18
19
20
21
22
P
P
Digital supply voltage 5 (+3.3 V).
Ground for digital supply voltage 5.
Line-locked system clock output (27 MHz).
Line-locked clock 1⁄2 output (13.5 MHz).
O
O
O
LLC2
CREF
Clock reference output: this is a clock qualifier signal distributed by the internal CGC
for a data rate of LLC2. Using CREF all interfaces on the VPO bus are able to
generate a bus timing with identical phase. If CCIR 656 format is selected
(OFTS0 = 1 and OFTS1 = 1) an inverse composite blanking signal (pixel qualifier) is
provided on this pin.
RES
CE
23
24
O
I
Reset output (active LOW); sets the device into a defined state. All data outputs are
in high impedance state. The I2C-bus is reset (waiting for start condition).
Chip enable; connection to ground forces a reset, up from version 3 power save
function additionally available.
VDDD4
VSSD4
HS
25
26
27
P
P
O
Digital supply voltage input 4 (+3.3 V).
Ground for digital supply voltage input 4.
Horizontal sync output signal (programmable); the positions of the positive and
negative slopes are programmable in 8 LLC increments over a complete line
(equals 64 µs) via I2C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC
increments can be performed via I2C-bus bits HDEL1 and HDEL0.
RTS1
28
O
Two functions output; controlled by I2C-bus bit RTSE1.
RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the inverted and
non-inverted R − Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator;
a high state indicates that the internal horizontal PLL has locked.
1998 May 15
6
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
PIN
SYMBOL
I/O/P
DESCRIPTION
(L)QFP64
RTS0
29
O
Two functions output; controlled by I2C-bus bit RTSE0.
RTSE0 = 0: odd/even field identification (HIGH = odd field). RTSE0 = 1: vertical
locked indicator; a HIGH state indicates that the internal Vertical Noise Limiter (VNL)
has locked.
VS
30
31
O
O
Vertical sync signal (enabled via I2C-bus bit OEHV); this signal indicates the vertical
sync with respect to the YUV output. The HIGH period of this signal is approximately
six lines if the VNL function is active. The positive slope contains the phase
information for a deflection controller.
Horizontal reference output signal (enabled via I2C-bus bit OEHV); this signal is used
to indicate data on the digital YUV bus. The positive slope marks the beginning of a
new active line. The HIGH period of HREF is 720 Y samples long. HREF can be used
to synchronize data multiplexer/demultiplexer. HREF is also present during the
vertical blanking interval.
HREF
VSSD3
VDDD3
32
33
P
P
O
Ground for digital supply voltage input 3.
Digital supply voltage 3 (+3.3 V).
VPO
(15 to 10)
34 to 39
Digital VPO-bus (Video Port Out) signal; higher bits of the 16-bit VPO-bus or the
16-bit RGB-bus output signal. The output data rate, the format and multiplexing
scheme of the VPO-bus are controlled via I2C-bus bits OFTS0 and OFTS1. If I2C-bus
bit VIPB = 1 the six MSBs of the digitized input signal are connected to these outputs,
configured by the I2C-bus ‘MODE’ bits (see Figs 33 to 40):
LUMA → VPO15 to VPO8, CHROMA → VPO7 to VPO0.
VSSD2
VDDD2
40
41
P
P
O
Ground for digital supply voltage input 2.
Digital supply voltage 2 (+3.3 V).
VPO
(9 to 0)
42 to 51
Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the 16-bit RGB-bus
output signal. The output data rate, the format and multiplexing schema of the
VPO-bus are controlled via I2C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1
the digitized input signal are connected to these outputs, configured by the I2C-bus
‘MODE’ bits (see Figs 33 to 40): LUMA → VPO15 to VPO8,
CHROMA → VPO7 to VPO0.
FEI
52
53
I
Fast enable input signal (active LOW); this signal is used to control fast switching on
the digital YUV-bus. A HIGH at this input forces the IC to set its Y and UV outputs to
the high impedance state.
General purpose switch output; the state of this signal is set via I2C-bus control and
the levels are TTL compatible.
GPSW
O
XTAL
54
55
O
I
Second terminal of crystal oscillator; not connected if external clock signal is used.
XTALI
Input terminal for 24.576 MHz crystal oscillator or connection of external oscillator
with CMOS compatible square wave clock signal.
VSSD1
VDDD1
TRST
TCK
56
57
58
59
60
P
P
I
Ground for digital supply voltage input 1.
Digital supply voltage input 1 (+3.3 V).
Test reset input not (active LOW), for boundary scan test; notes 1, 2 and 3.
Test clock for boundary scan test; note 1.
I
RTCO
O
Real time control output: contains information about actual system clock frequency,
subcarrier frequency and phase and PAL sequence.
1998 May 15
7
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
PIN
SYMBOL
I/O/P
DESCRIPTION
(L)QFP64
IICSA
61
I
I2C-bus slave address select;
0 = 48H for write, 49H for read
1 = 4AH for write, 4BH for read.
SDA
SCL
n.c.
62
63
64
I/O
I/O
−
Serial data input/output (I2C-bus).
Serial clock input/output (I2C-bus).
Not connect.
Notes
1. In accordance with the ‘IEEE1149.1’ standard the pads TCK, TDI, TMS and TRST are input pads with an internal
pull-up transistor and TDO a 3-state output pad.
2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller
to the Test-Logic-Reset state (normal operation) at once.
3. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect the TRST pin
to ground.
1998 May 15
8
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
n.c.
1
2
48
47
VPO3
VPO4
TDO
TDI
3
46 VPO5
TMS
4
45
44
VPO6
VPO7
V
V
5
SSA2
AI22
6
43 VPO8
7
42
41
40
VPO9
DDA2
AI21
V
8
DDD2
SAA7111A
V
V
SSA1
AI12
9
SSD2
10
11
12
13
14
15
16
39 VPO10
V
38
37
36
35
34
33
VPO11
VPO12
VPO13
VPO14
VPO15
DDA1
AI11
V
SSS
AOUT
V
DDA0
V
V
SSA0
DDD3
MGG060
Fig.2 Pin configuration (LQFP64/QFP64).
1998 May 15
9
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.
8
FUNCTIONAL DESCRIPTION
Analog input processing
8.1
The SAA7111A offers four analog signal inputs, two
analog main channels with source switch, clamp circuit,
analog amplifier, anti-alias filter and video CMOS ADC
(see Fig.5).
8.2
Analog control circuits
controlled
ADC input level
handbook, halfpage
analog input level
maximum
The anti-alias filters are adapted to the line-locked clock
frequency via a filter control circuit. During the vertical
blanking time, gain and clamping control are frozen.
+4.5 dB
0 dB
range tbf
0 dB
(1 V(p-p) 27/47 Ω)
−7.5 dB
8.2.1
CLAMPING
minimum
The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.
MGG063
Fig.4 Automatic gain range.
8.3
Chrominance processing
The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90° phase relationship to the demodulator axis).
The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals (PAL and NTSC) or the 0 and 90° FM-signals
(SECAM).
TV line
analog line blanking
handbook, halfpage
255
GAIN
CLAMP
HCL
60
1
The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions:
MGL065
HSY
• AGC (Automatic Gain Control for chrominance
PAL and NTSC)
Fig.3 Analog line with clamp (HCL) and gain
range (HSY).
• Chrominance amplitude matching (different gain factors
for R − Y and B − Y to achieve CCIR-601 levels
Cr and Cb for all standards)
8.2.2
GAIN CONTROL
• Chrominance saturation control
Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 13 and 14) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.
• Luminance contrast and brightness
• Limiting YUV to the values 1 (min.) and 254 (max.) to
fulfil CCIR-601 requirements.
The gain control circuit receives (via the I2C-bus) the static
gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain
control (AGC) as part of the Analog Input Control (AICO).
1998 May 15
10
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
The SECAM-processing contains the following blocks:
The high frequency components of the luminance signal
can be peaked (control for sharpness improvement via
I2C-bus) in two band-pass filters with selectable transfer
characteristic. This signal is then added to the original
(unpeaked) signal. A switchable amplifier achieves
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the BCS control located in the
chrominance processing block (see Fig.7).
• Baseband ‘bell’ filters to reconstruct the amplitude and
phase equalized 0 and 90° FM-signals
• Phase demodulator and differentiator
(FM-demodulation)
• De-emphasis filter to compensate the pre-emphasised
input signal, including frequency offset compensation
(DB or DR white carrier values are subtracted from the
signal, controlled by the SECAM-switch signal).
8.5
RGB matrix
The burst processing block provides the feedback loop of
the chroma PLL and contains;
Y, Cr and Cb data are converted after interpolation into
RGB data in accordance with CCIR-601
recommendations. The realized matrix equations consider
the digital quantization:
• Burst gate accumulator
• Colour identification and killer
• Comparison nominal/actual burst amplitude (PAL/NTSC
standards only)
R = Y + 1.371 Cr
G = Y − 0.336 Cb − 0.698 Cr
B = Y + 1.732 Cb.
• Loop filter chrominance gain control (PAL/NTSC
standards only)
• Loop filter chrominance PLL (only active for PAL/NTSC
standards)
After dithering (noise shaping) the RGB data is fed to the
output interface within the VPO-bus output formatter.
• PAL/SECAM sequence detection, H/2-switch
generation
8.6
VBI-data bypass
• Increment generation for DTO1 with divider to generate
stable subcarrier for non-standard signals.
For a 27 MHz VBI-data bypass the offset binary CVBS
signal is upsampled behind the ADCs. Upsampling of the
CVBS signal from 13.5 to 27 MHz is possible, because the
ADCs deliver high performance at 13.5 MHz sample clock.
Suppressing of the back folded CVBS frequency
components after upsampling is achieved by an
interpolation filter (see Fig.42).
The chrominance comb filter block eliminates crosstalk
between the chrominance channels in accordance with the
PAL standard requirements. For NTSC colour standards
the chrominance comb filter can be used to eliminate
crosstalk from luminance to chrominance (cross-colour)
for vertical structures. The comb filter can be switched off
if desired. The embedded line delay is also used for
SECAM recombination (cross-over switches).
The TUF block on the digital top level performs the
upsampling and interpolation for the bypassed CVBS
signal (see Fig.6).
The resulting signals are fed to the variable Y-delay
compensation, RGB matrix, dithering circuit and output
interface, which contains the VPO output formatter and the
output control logic (see Fig.6).
For bypass details see Figs 8 to 10.
8.7
VPO-bus (digital outputs)
The 16-bit VPO-bus transfers digital data from the output
interfaces to a feature box or a field memory, a digital
colour space converter (SAA7192 DCSC), a video
enhancement and digital-to-analog processor
(SAA7165 VEDA2) or a colour graphics board
(Targa-format) as a graphical user interface.
8.4
Luminance processing
The 8-bit luminance signal, a digital CVBS format or a
luminance format (S-VHS, HI8), is fed through a
switchable prefilter. High frequency components are
emphasized to compensate for loss. The following
chrominance trap filter (f0 = 4.43 or 3.58 MHz centre
frequency selectable) eliminates most of the colour carrier
signal, therefore, it must be bypassed for S-video
(S-VHS and HI8) signals.
1998 May 15
11
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
The output data formats are controlled via the I2C-bus bits
OFTS0, OFTS1 and RGB888. Timing for the data stream
formats, YUV (4 : 1 : 1) (12-bit), YUV (4 : 2 : 2) (16-bit),
RGB (5, 6 and 5) (16-bit) and RGB (8, 8 and 8) (24-bit)
with an LLC2 data rate, is achieved by marking each
second positive rising edge of the clock LLC in conjunction
with CREF (clock reference) (except RGB (8, 8 and 8),
see special application in Fig.32). The higher output
signals VPO15 to VPO8 in the YUV format perform the
digital luminance signal. The lower output signals
VPO7 to VPO0 in the YUV format are the bits of the
multiplexed colour difference signals (B − Y) and (R − Y).
The arrangement of the RGB (5, 6 and 5) and
• VREF: The VREF output delivers a vertical reference
signal or an inverse composite blank signal controlled
via the I2C-bus [subaddress 11, inverse composite
blank (COMPO)]. Furthermore four different modes of
vertical reference signals are selectable via the I2C-bus
[subaddress 13, vertical reference output control
(VCTR1 and VCTR0)]. The description of VREF timing
and position is illustrated in Figs 15, 16, 24 and 25.
• CREF: The CREF output delivers a clock/pixel qualifier
signal for external interfaces to synchronize to the
VPO-bus data stream.
Four different modes for the clock qualifier signal are
selectable via the I2C-bus [subaddress 13, clock
reference output control (CCTR1 and CCTR0)].
The description of CREF timing and position is
illustrated in Figs 16, 18, 20 and 21.
RGB (8, 8 and 8) data stream bits on the VPO-bus is given
in Table 6.
The data stream format YUV 4 : 2 : 2 (the 8 higher output
signals VPO15 to VPO8) in LLC data rate fulfils the
CCIR-656 standard with its own timing reference code at
the start and end of each video data block.
8.9
Synchronization
The prefiltered luminance signal is fed to the
A pixel in the format tables is the time required to transfer
a full set of samples. If 16-bit 4 : 2 : 2 format is selected
two luminance samples are transmitted in comparison to
one (B − Y) and one (R − Y) sample within a pixel.
The time frames are controlled by the HREF signal.
synchronization stage. Its bandwidth is reduced to 1 MHz
in a low-pass filter. The sync pulses are sliced and fed to
the phase detectors where they are compared with the
sub-divided clock frequency. The resulting output signal is
applied to the loop filter to accumulate all phase
deviations. Internal signals (e. g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The output signals HS, VS, and PLIN are
locked to the timing reference, guaranteed between the
input signal and the HREF signal, as further improvements
to the circuit may change the total processing delay. It is
therefore not recommended to use them for applications
which require absolute timing accuracy on the input
signals. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO
(see Fig.7).
Fast enable is achieved by setting input FEI to LOW.
The signal is used to control fast switching on the digital
VPO-bus. HIGH on this pin forces the VPO outputs to a
high-impedance state (see Figs 18 and 19). The I2C-bus
bit OEYC has to be set HIGH to use this function.
The digitized PAL, SECAM or NTSC signals AD1 (7 to 0)
and AD2 (7 to 0) are connected directly to the VPO-bus
via I2C-bus bit VIPB = 1 and MODE = 4, 5, 6 or 7.
AD1 (7 to 0) → VPO (15 to 8) and
AD2 (7 to 0) → VPO (7 to 0).
The selection of the analog input channels is controlled via
I2C-bus subaddress 02 MODE select.
8.10 Clock generation circuit
The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency
The upsampled 8-bit offset binary CVBS signal (VBI-data
bypass) is multiplexed under control of the I2C-bus to the
digital VPO-bus (see Fig.8).
429
432
8.8
Reference signals HREF, VREF and CREF
6.75MHz =
× f
H
---------
• HREF: The positive slope of the HREF output signal
indicates the beginning of a new active video line.
The high period is 720 luminance samples long and is
also present during the vertical blanking.
The description of timing and position from HREF is
illustrated in Figs 15, 16, 21 and 23.
Internally the LFCO signal is multiplied by a factor of 2 or 4
in the PLL circuit (including phase detector, loop filtering,
VCO and frequency divider) to obtain the LLC and LLC2
output clock signals. The rectangular output clocks have
a 50% duty factor (see Fig.26).
1998 May 15
12
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
8.13.1 SUGGESTIONS FOR I2C-BUS INTERFACE OF THE
DISPLAY SOFTWARE READING LINE-21 DATA
8.11 Power-on reset and CE input
A missing clock, insufficient digital or analog VDDA0 supply
voltages (below 2.7 V) will initiate the reset sequence; all
outputs are forced to 3-state. The indicator output RES is
LOW for approximately 128LLC after the internal reset and
can be applied to reset other circuits of the digital TV
system.
There are two methods by which the software can acquire
the data:
1. Synchronous reading once per frame (or once per
field); It can use either the rising edge (Line-21 Field 1)
or both edges (Line-21 Field 1 or 2) of the ODD signal
(pin RTSO) to initiate an I2C-bus read transfer of the
three registers 1A, 1B and 1C.
It is possible to force a reset by pulling the chip enable
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2, CREF,
RTCO, RTS0, RTS1, GPSW and SDA return from 3-state
to active, while HREF, VREF, HS and VS remain in 3-state
and have to be activated via I2C-bus programming
(see Table 5).
2. Asynchronous reading; It can poll either the F1RDY bit
(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21
Field 1 or 2). After valid data has been read the
corresponding F*RDY bit is set to LOW until new data
has arrived. The polling frequency has to be slightly
higher than the frame or field frequency, respectively.
8.12 RTCO output
The real time control and status output signal contains
serial information about the actual system clock
(increment of the HPLL), subcarrier frequency [increment
and phase (via reset) of the FSC-PLL] and PAL sequence
bit. The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve clean
encoding (see Fig.20).
8.13 The Line-21 text slicer
The text slicer block detects and acquires Line-21 Closed
Captioning data from a 525-line CVBS signal. Extended
data services on Line-21 Field 2 are also supported.
If valid data is detected the two data bytes are stored in two
I2C-bus registers. A parity check is also performed and the
result is stored in the MSB of the corresponding byte.
A third I2C-bus register is provided for data valid and data
ready flags. The two bits F1VAL and F2VAL indicate that
the input signal carries valid Closed Captioning data in the
corresponding fields. The data ready bits F1RDY and
F2RDY have to be evaluated if asynchronous I2C-bus
reading is used.
1998 May 15
13
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TEST
SELECTOR
14
AOUT
AND
64
n.c.
BUFFER
9
V
V
SSA1
5
SSA2
AOSL (1 : 0)
ADC2
6
8
ANALOG
AMPLIFIER
DAC9
AI22
AI21
ANTI-ALIAS
FILTER
BYPASS
SWITCH
SOURCE
SWITCH
CLAMP
CIRCUIT
11
7
V
V
DDA1
DDA2
FUSE (1 : 0)
10
12
ANALOG
AMPLIFIER
DAC9
AI12
AI11
ANTI-ALIAS
FILTER
CLAMP
CIRCUIT
BYPASS
SWITCH
SOURCE
SWITCH
ADC1
FUSE (1 : 0)
VERTICAL
BLANKING
CONTROL
MODE
CONTROL
CLAMP
CONTROL
GAIN
CONTROL
ANTI-ALIAS
CONTROL
HCL
VBLNK
SVREF
VBSL
8
8
GLIMB HSY
GLIMT
WIPA
HOLDG
MODE 0
MODE 1
MODE 2
GAFIX
WPOFF
GUDL0-GUDL2
GAI20-GAI28
GAI10-GAI18
HLNRS
SLTCA
ANALOG
CONTROL
UPTCV
13
CROSS
MULTIPLEXER
V
SSS
MGC655
AD2BYP AD1BYP
LUM
CHR
Fig.5 Analog input processing.
ahdnbok,uflapegwidt
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d
AD2BYP AD1BYP
LUM
CHR
SECAM
PROCESSING
1
n.c.
sequential
UV signals
58
59
3
TRST
TCK
TDI
QUADRATURE
LEVEL
LOW-PASS
52
TEST
CONTROL
BLOCK
ADJUSTMENT,
BRIGHTNESS,
CONTRAST,
AND
SATURATION
CONTROL
DEMODULATOR
FEI
CHBW0
CHBW1
4
TMS
2
TDO
42 to 51
RGB MATRIX
interpolation
dithering
RGB
Y
OUTPUT
FORMATTER
AND
VPO
(9 : 0)
PHASE
DEMODULATOR
SUBCARRIER
GENERATION
57,41,33,
25,18
SUBCARRIER
INCREMENT
GENERATION
AND
AMPLITUDE
DETECTOR
INTERFACE
34 to 39
31
V
VPO
(15 : 10)
DDD1-5
RES
GAIN
CONTROL
AND Y-DELAY
COMPENSATION
DIT
CBR
COMB
POWER-ON
CONTROL
HUEC
BURST GATE
ACCUMULATOR
DIVIDER
UV
23
FILTERS
SECAM
HREF
LOOP FILTER
RECOMBINATION
CE CLOCKS
CODE
FCTC
GPSW
CSTD 1
CSTD 0
OFTS0
OFTS1
RGB888
OEYC
OEHV
FECO
BRIG
CONT
SATN
DCCF
RTSE1
RTSE0
VIPB
VLOF
COLO
COMPO
INCS
56,40,32,26,19
V
f
/2 switch signal
SSD1-5
H
VBI DATA BYPASS
TUF
VRLN
VSTA (8 : 0)
VSTO (8 : 0)
60
RTCO
MGG062
Y
LUM
Fig.6 Chrominance circuit.
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Y
LUM
LUMINANCE CIRCUIT
WEIGHTING
VARIABLE
CHROMINANCE
TRAP
AND
BAND-PASS
PREFILTER
ADDING
FILTER
STAGE
PREF
BYPS
VBLB
BPSS0
BPSS1
PREF
APER0
APER1
VBLB
MATCHING
AMPLIFIER
PREFILTER
SYNC
CLOCK CIRCUIT
CLOCKS
VBLB
22
20
21
CREF
LLC
LLC2
LINE-LOCKED
CLOCK
GENERATOR
LINE 21
TEXT
PHASE
DETECTOR
FINE
SYNC SLICER
SLICER
PHASE
DETECTOR
COARSE
15
16
24
V
V
CLOCK
GENERATION
CIRCUIT
DDA0
SSA0
BYTE1
BYTE2
STATUS
SYNCHRONIZATION CIRCUIT
DAC6
AUFD
HSB
HSS
FSEL
VTRC
CE
VNOI0
HPLL
VTRC
VTRC
EXFIL
2
I C BUS CONTROL
VNOI1
VTRC
HLCK
STTC
FIDT
INCS
55
54
2
CRYSTAL
CLOCK
GENERATOR
DISCRETE
TIME
OSCILLATOR 2
XTALI
XTAL
53
I C-BUS
LOOP FILTER
2
VERTICAL
PROCESSOR
GPSW
COUNTER
27
INTERFACE
61 63 62
30 29 17
28
MGC654
VS RTS0 VREF
HS
RTS1
IICSA SCL SDA
ahdnbok,uflapegwidt
Fig.7 Luminance and sync processing.
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
TBP7 to 0
0
0
1
AD1BYP
(CVBS)
MUX
MUX
BYP
UP
VPO15 to 8
CVBS
UP
1
REGISTER
(LUMA see Fig. 37)
Y or YUV
SWHI
BCHI1
BCHI0 SWHI
VBP0
VBP4
0
0
1
1
0
1
0
1
1
VIPB
I C-bus
2
0
VBP0
VBP4
BCHI1 to 0
2
I C-bus
0
0
1
AD2BYP
MUX
MUX
BYP
UP
VPO7 to 0
CVBS
UP
1
REGISTER
(CHROMA see Fig. 37)
UV or YUV
SWLO
BCLO1 BCLO0 SWLO
VBP0
VBP4
0
0
1
1
0
1
0
1
1
0
VBP0
VBP4
BCLO1 to 0
2
I C-bus
REG
4 × REG
VBP4
VBP0
V_GATE
(programmable)
EN
HREFINT
CLOCK 0
CLOCK 0
MGG064
HREFINT = internal horizontal reference.
TBP = upsampled CVBS input data (27 MHz).
AD1BYP/AD2BYP = digitized CVBS input data and Y/C input data (13.5 MHz).
VBP0 = programmable vertical reference signal.
VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).
Fig.8 Multiplexing of the CVBS signal to the VPO-bus.
17
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
REG
VREF CCIR 656
V
C
T
R
1
V
C
T
R
0
EN
VREFOUT
CLOCK 0
HREFINT
REG
0
0
1
1
0
1
0
1
VBP0
VBP4
VREFINT
HREF
VREF CCIR 656
VBP0
REG
EN
VBP4
VREFINT
HREFINT
CLK0
0
1
REG
VREF
MUX
CLOCK 0
VCTR1 to 0
CLOCK 0
COMPO
MGG065
VREF_CCIR 656 = vertical reference signal referring to the field interval definitions of CCIR656.
HREFINT = internal horizontal reference signal.
VREFINT = internal vertical reference signal.
VBP0 = programmable vertical reference signal.
VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).
Fig.9 VREF output signal generation.
C
C
T
R
1
C
C
T
R
0
CREFINT
CREFOUT
REG
CREF
selected
VREF
0
0
1
1
0
1
0
1
CREFINT
0 if VREF = 0
1 if VREF = 0
1 (always HIGH)
CCTR1 to 0
CLOCK 0
MGG066
CREFINT = internal clock qualifier signal.
Fig.10 CREF output signal generation.
18
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
9
BOUNDARY-SCAN TEST
9.2
Device identification codes
The SAA7111A has built in logic and 5 dedicated pins to
support boundary-scan testing which allows board testing
without special hardware (nails). The SAA7111A follows
the ‘IEEE Std. 1149.1 - Standard Test Access Port and
Boundary-Scan Architecture’ set by the Joint Test Action
Group (JTAG) chaired by Philips.
A Device Identification Register (DIR) is specified in ‘IEEE
Std. 1149.1-1990 - IEEE Standard Test Access Port and
Boundary-Scan Architecture’ (IEEE Std. 1149.1b-1994).
It is a 32-bit register which contains fields for the
specification of the IC manufacturer, the IC part number
and the IC version number. Its biggest advantage is the
possibility to check for the correct ICs mounted after
production and determination of the version number of
ICs during field service.
The 5 special pins are Test Mode Select (TMS), Test
Clock (TCK), Test Reset (TRST), Test Data Input (TDI)
and Test Data Output (TDO).
When the IDCODE instruction is loaded into the BST
instruction register, the identification register will be
connected between TDI and TDO of the IC.
The BST functions BYPASS, EXTEST, INTEST,
SAMPLE, CLAMP and IDCODE are all supported
(see Table 1). Details about the JTAG BST-TEST can be
found in the specification “EEE Std. 1149.1”. A file
containing the detailed Boundary-Scan Description
Language (BSDL) description of the SAA7111A is
available on request.
The identification register will load a component specific
code during the CAPTURE_DATA_REGISTER state of
the TAP controller and this code can subsequently be
shifted out. At board level this code can be used to verify
component manufacturer, type and version number.
The device identification register contains 32-bits,
numbered 31 to 0, where bit 31 is the Most Significant Bit
(MSB) (nearest to TDI) and bit 0 is the Least Significant
Bit (LSB) (nearest to TDO); see Fig.11.
9.1
Initialization of boundary-scan circuit
The Test Access Port (TAP) controller of an IC should be
in the reset state (TEST_LOGIC_RESET) when the IC is
in functional mode. This reset state also forces the
instruction register into a functional instruction such as
IDCODE or BYPASS.
To solve the power-up reset, the standard specifies that
the TAP controller will be forced asynchronously to the
TEST_LOGIC_RESET state by setting the TRST pin
LOW.
Table 1 BST instructions supported by the SAA7111A
INSTRUCTION
DESCRIPTION
BYPASS
This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO
when no test operation of the component is required.
EXTEST
SAMPLE
This mandatory instruction allows testing of off-chip circuitry and board level interconnections.
This mandatory instruction can be used to take a sample of the inputs during normal operation of
the component. It can also be used to preload data values into the latched outputs of the
boundary-scan register.
CLAMP
This optional instruction is useful for testing when not all ICs have BST. This instruction addresses
the bypass register while the boundary-scan register is in external test mode.
IDCODE
This optional instruction will provide information on the components manufacturer, part number and
version number.
INTEST
USER1
This optional instruction allows testing of the internal logic (no support for customers available).
This private instruction allows testing by the manufacturer (no support for customers available).
1998 May 15
19
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
MSB
LSB
31
28 27
12 11
1
0
TDI
0010
1111000100010001
16-bit part number
00000010101
1
TDO
4-bit
version
code
11-bit manufacturer
indentification
MGL111
Fig.11 32 bits of identification code.
1998 May 15
20
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
10 GAIN CHARTS
MGC648
handbook, halfpage
7.5
(
512
factor dB = 20 x log10 gain =
(
768 − i
dB
5.5
3.5
i > 256
bit [8] = 1
1.5
bit [8] = 0
i < 256
−0.5
−2.5
−4.5
(
257 + i
512
factor dB = 20 x log10 gain =
(
0
256
512
gain value (i)
Fig.12 Amplifier curve.
ANALOG INPUT
ADC
1
0
NO BLANKING ACTIVE
VBLK
<- CLAMP
GAIN ->
1
0
1
0
HCL
HSY
0
1
1
0
1
0
CLL
SBOT
WIPE
slow + GAIN
NO CLAMP
+ CLAMP
− CLAMP
fast − GAIN
+ GAIN
− GAIN
MGC647
WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)];
HSY = horizontal sync pulse; HCL = horizontal clamp pulse.
Fig.13 Clamp and gain flow.
1998 May 15
21
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
ANALOG INPUT
9
gain
AMPLIFIER
DAC
ANTI-ALIAS FILTER
ADC
8
LUMA/CHROMA DECODER
1
0
VBLK
1
NO ACTION
0
HOLDG
1
0
X
1
0
HSY
1
0
>254
1
1
1
0
0
0
<4
<1
>254
X = 1
X = 0
1
0
>248
+/− 0
+1/F
−
+1/LLC2 −1/LLC2
+1/L
1/LLC2
STOP
GAIN ACCUMULATOR (18 BITS)
ACTUAL GAIN VALUE 9-BIT (AGV) [−6/+6 dB]
1
0
X
1
0
HSY
1
0
Y
AGV
UPDATE
FGV
GAIN VALUE 9-BIT
MGC652
X = system variable; Y = IAGV − FGVI > GUDL; VBLK = vertical blanking pulse;
HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.
Fig.14 Gain flow chart.
22
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins connected together and all supply
pins connected together.
SYMBOL
VDDD
PARAMETER
digital supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+4.6
UNIT
V
VDDA
Vi(A)
analog supply voltage
−0.5
−0.5
+4.6
V
V
input voltage at analog inputs
VDDA + 0.5
(4.6 max.)
Vo(A)
Vi(D)
output voltage at analog output
input voltage at digital inputs and outputs
output voltage at digital outputs
voltage difference between VSSAall and VSSall
storage temperature
−0.5
−0.5
−0.5
−
VDDA + 0.5
+5.5
V
outputs in 3-state
outputs active
V
Vo(D)
∆VSS
Tstg
VDDD + 0.5
100
V
mV
°C
°C
°C
V
−65
0
+150
Tamb
Tamb(bias)
Vesd
operating ambient temperature
operating ambient temperature under bias
electrostatic discharge all pins
70
−10
−2000
+80
note 1
+2000
Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
12 CHARACTERISTICS
VDDD = 3.0 to 3.6 V; VDDA = 3.1 to 3.5 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD
IDDD
PD
digital supply voltage
digital supply current
digital power
3.0
3.3
3.6
70
−
V
−
63
mA
W
−
0.21
3.3
52
VDDA
IDDA
analog supply voltage
analog supply current
3.1
−
3.5
−
V
AOSL = [1:0] = 00b;
AOUT not connected
mA
PA
analog power
−
−
−
0.17
0.38
0.02
−
−
−
W
W
W
PA+D
Ppd
analog and digital power
analog and digital power in CE connected to ground
power-down mode
(since version 3)
Analog part
Iclamp
clamping current
VI = 0.9 V DC
−
±3.5
−
µA
Vi(p-p)
input voltage
(peak-to-peak value)
for normal video levels
[1 V (p-p)]; −3 dB
0.3
0.7
1.2
V
termination 27/47 Ω and
AC coupling required;
coupling capacitor = 22 nF
|Zi|
Ci
input impedance
input capacitance
clamping current off
200
−
−
−
kΩ
−
10
pF
1998 May 15
23
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
SYMBOL
αcs
PARAMETER
CONDITIONS
fi = 5 MHz
MIN.
TYP.
MAX.
−50
UNIT
dB
channel crosstalk
−
−
Analog-to-digital converters
B
bandwidth
at −3 dB
−
−
7
2
−
−
MHz
deg
φdiff
differential phase
(amplifier plus anti-alias
filter = bypass)
Gdiff
differential gain
−
2
−
%
(amplifier plus anti-alias
filter = bypass)
fclkADC
DLE
ADC clock frequency
12.8
−
14.3
MHz
LSB
DC differential linearity
error
−
0.7
−
ILE
DC integral linearity error
−
1
−
LSB
Digital inputs
VIL(SCL,SDA)
LOW level input voltage
pins SDA and SCL
−0.5
0.7VDDD
−0.3
2.0
−
−
−
−
−
−
+0.3VDDD
VDDD + 0.5
+0.8
V
V
V
V
V
V
VIH
HIGH level input voltage
pins SDA and SCL
VIL(xtal)
VIH(xtal)
VILn
LOW level CMOS input
voltage pin XTALI
HIGH level CMOS input
voltage pin XTALI
VDDD + 0.3
+0.8
LOW level input voltage all
other inputs
−0.3
2.0
VIHn
HIGH level input voltage
all other inputs
5.5
ILI
input leakage current
input capacitance
−
−
−
−
−
−
1
8
5
µA
pF
pF
Ci
outputs at 3-state
Ci(n)
input capacitance all other
inputs
Digital outputs
VOL(SCL,SDA) LOW level output voltage SDA/SCL at 3 mA (6 mA)
pins SDA and SCL sink current
−
−
0.4 (0.6)
V
VOL
LOW level output voltage VDDD = max; IOL = 2 mA
0
−
−
−
0.4
V
V
V
VOH
HIGH level output voltage VDDD = min, IOH = −2 mA
2.4
−0.5
VDDD + 0.5
+0.6
VOL(clk)
LOW level output voltage
for clocks
VOH(clk)
HIGH level output voltage
for clocks
2.4
−
−
VDDD + 0.5
10
V
ILO
FEI input timing
tSU;DAT input data set-up time
tHD;DAT input data hold time
output leakage current
at 3-state mode
−
µA
13
3
−
−
−
−
ns
ns
1998 May 15
24
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data and control output timing; note 1
CL
output load capacitance
output hold time
15
4
−
−
−
−
40
−
pF
tOHD;DAT
tPD
CL = 15 pF
CL = 25 pF
ns
ns
ns
propagation delay
−
20
20
tPDZ
propagation delay to
3-state
−
Clock output timing (LLC and LLC2); note 2
CL(LLC)
Tcy
output load capacitance
cycle time
15
35
70
40
−
−
−
−
40
39
78
60
pF
ns
ns
%
LLC
LLC2
δLLC
duty factors for tLLCH/tLLC
and tLLC2H/tLLC2
CL = 25 pF
tr
tf
rise time LLC, LLC2
fall time LLC, LLC2
−
−
−
−
5
ns
ns
ns
−
5
td
delay time LLC output to
LLC2 output
at 1.5 V;
LLC/LLC2 = 25 pF
−4
+8
Data qualifier output timing (CREF)
tOHD;CREF
tPD;CREF
output hold time
CL = 15 pF
CL = 25 pF
4
−
−
−
ns
ns
propagation delay from
positive edge of LLC
−
20
Clock input timing (XTALI)
δXTALI
duty factor for tXTALIH/tXTALI nominal frequency
40
−
60
%
Horizontal PLL
fHn
nominal line frequency
50 Hz field
60 Hz field
−
−
−
15625
15734
−
−
Hz
Hz
%
−
∆fH/fHn
permissible static deviation
5.7
Subcarrier PLL
fSCn
nominal subcarrier
frequency
PAL BGHI
−
−
−
−
4433619
3579545
3575612
3582056
−
−
−
−
−
−
Hz
Hz
Hz
Hz
Hz
NTSC M; NTSC-Japan
PAL M
PAL N
∆fSC
lock-in range
±400
Crystal oscillator
fn
nominal frequency
3rd harmonic; note 3
−
−
24.576
−
MHz
10−6
∆f/fn
permissible nominal
frequency deviation
−
±50
1998 May 15
25
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Crystal oscillator
fn
nominal frequency
3rd harmonic; note 3
−
−
24.576
−
MHz
10−6
∆f/fn
permissible nominal
frequency deviation
−
±50
∆Tf/fn
permissible nominal
frequency deviation with
temperature
−
−
−
±20
10−6
CRYSTAL SPECIFICATION (X1)
Tamb(X1)
operating ambient
0
70
°C
temperature
CL
Rs
C1
C0
load capacitance
8
−
−
−
−
−
pF
Ω
series resonance resistor
motional capacitance
parallel capacitance
40
80
−
1.5 ±20%
3.5 ±20%
fF
−
pF
Notes
1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL = 50 pF.
2. The effects of rise and fall times are included in the calculation of tOHD;DAT, tPD and tPDZ. Timings and levels refer to
drawings and conditions illustrated in Figs 15 and 16.
3. Order number: Philips 4322 143 05291.
Table 2 Processing delay
DIGITAL DELAY
ADCIN → VPO (LLC CLOCKS)
[YDEL(2 to 0) = 000]; note 1
TYPICAL ANALOG DELAY
AI22 → ADCIN (AOUT) (ns)
FUNCTION
Without amplifier or anti-alias filter
With amplifier, without anti-alias filter
With amplifier and anti-alias filter
15
25
75
179
Note
1. Digital processing delay (LLC CLOCKS) for VBI data is defined in Fig.23 ‘Horizontal timing diagram’.
1998 May 15
26
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
13 TIMING DIAGRAMS
t
LLC
CLOCK OUTPUT LLC
t
LLCL
2.6 V
1.5 V
0.6 V
t
f
t
r
t
LLCH
t
PD
t
OHD;DAT
2.4 V
0.6 V
OUTPUTS VPO, HREF,
VREF, VS, HS
MGC658
An explanation of the output formats is given in Table 6.
Fig.15 Clock/data timing (8-bit CCIR-656 format of the VPO-bus).
t
t
LLC
LLC
t
LLCL
2.6 V
1.5 V
0.6 V
CLOCK OUTPUT LLC
t
t
f
r
t
LLCH
t
t
PD
PD
2.4 V
0.6 V
OUTPUT CREF
t
t
OHD;CREF
t
OHD;CREF
t
dLLC2
dLLC2
2.6 V
1.5 V
0.6 V
CLOCK OUTPUT LLC2
t
PD
t
OHD;DAT
2.4 V
0.6 V
OUTPUTS VPO, HREF,
VREF, VS, HS
MGC659
An explanation of the output formats is given in Table 6. The FEI timing of the VPO-bus is illustrated in Figs 18 and 19.
Fig.16 Clock/data timing (12 and 16-bit CCIR-601 format of the VPO-bus).
27
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
t
t
LLC
CLOCK OUTPUT LLC
LLC
t
LLCL
2.4 V
1.5 V
0.6 V
t
t
r
f
t
LLCH
t
t
PD;CREF
OHD;CREF
2.4 V
1.5 V
0.6 V
OUTPUT CREF
t
t
t
OHD;CREF
OHD;CREF
PD;CREF
2.4 V
1.5 V
0.6 V
RGB (8, 8, 8) data
VPO15 to VPO8
R(7 : 3)
G(7 : 5)
t
t
OHD;DAT
OHD;DAT
2.4 V
1.5 V
0.6 V
R(2 : 0)
G(1 : 0)
B(2 : 0)
RGB (8, 8, 8) data
VPO7 to VPO0
G(4 : 2)
B(7 : 3)
MBH227
t
PD
An explanation of the output formats is given in Table 6.
Fig.17 Clock/data timing for RGB (8, 8 and 8) output format.
LLC
CREF
HREF
FEI
t
t
SU;DAT
t
HD;DAT
t
PDZ
t
OHD;DAT
PD
VPO
MGC656
to 3-state
from 3-state
I2C-bus bit FECO = 1.
Fig.18 FEI timing diagram (FEI sampling at CREF = HIGH) for OFTS = 0, 1 or 2).
28
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
LLC
CREF
HREF
FEI
t
t
SU;DAT
HD;DAT
t
PDZ
t
t
OHD;DAT
PD
VPO
MGC657
to 3-state
from 3-state
Timing is compatible with SAA7110; I2C-bus bit FECO = 0.
Fig.19 FEI timing diagram (FEI sampling at CREF = LOW) for OFTS = 0, 1 or 2).
transmitted once per line
SEQUENCE
LOW
(1)
DTO RESET
INCR
16
HIGH
INCR
14 13
RESERVED
50 Hz fields: 235
60 Hz fields: 232
HPLL
FSCPLL
45
128
1
3
2
BIT NO.:
15
0
8
7
9 6
5
1
0
22 21 20 19 18 17 16 15
19
12 11 10
4
3
2
0 1
63 67 68
TIME SLOT:
16
MGC649
(1) Set to zero for one transmission, if a phase reset of the fsc − DTO is applied via I2C-bus bit CDTO. RTCO sequence is generated in LLC/4.
The HPLL increment represents the actual LFCO frequency (fLFCO × 4 = fLLC); 16 LSB from 20, upper four bits are fixed to 0100b.
INCRHPLL × fXTAL
fLFCO
=
------------------------------------------------
2word length DTO2
Where: fXTAL = 24.576 MHz, word length DTO2 = 20 bits.
The fsc increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.
INCRFSCPLL × fXTAL INCRHPLL
f sc = ------------------------------------------------------ × ---------------------------
2word length DTO1
219
Where: word length DTO1 = 24 bits.
Fig.20 Real time control output.
29
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
LLC
CREF
LLC2
START OF ACTIVE LINE
HREF
0
1
2
3
4
Yn
U0
V0
U2
V2
U4
UVn
END OF ACTIVE LINE
HREF
Yn
715
716
717
718
719
V714
U716
V716
U718
V718
UVn
MGC646
Fig.21 HREF timing diagram.
LLC
t
t
HD
SU
FEI
t
OHD
VPO
MBH766
t
t
PD
PDZ
Fig.22 FEI timing in CCIR 656 mode [OFTS (1 : 0) = 3].
30
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
CVBS
burst
26 × 1/LLC
burst
VBI
179 × 1/LLC
(2)
processing delay CVBS->VPO
sync clipped
Y - output
0
HREF (50 Hz)
12 × 2/LLC
144 × 2/LLC
720 × 2/LLC
27 × 2/LLC
43 × 2/LLC
(1)
RTS1 (PLIN)
4/LLC
HS
HS (50 Hz)
programming range
(step size: 8/LLC)
−107
108
0
HREF (60 Hz)
23 × 2/LLC
16 × 2/LLC
138 × 2/LLC
720 × 2/LLC
HS (60 Hz)
HS (60 Hz)
programming range
(step size: 8/LLC)
107
−106
0
MGD701
(1) PLIN is switched to output RTS1 via I2C-bus bit RTSE1 = 0.
(2) See Table 2.
(3) HDEL (1 : 0) = 0 0, YDEL (2 : 0) = 0 0 0.
Fig.23 Horizontal timing diagram.
31
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
625
1
2
3
4
5
6
7
8
22
23
622
623
624
input CVBS
HREF
(2)
(2)
VREF
VREF
VRLN = 1
VRLN = 0
535 x 2/LLC
VS
(1)
RTS0 (ODD)
(a) 1st field
310
312
315
316
318
319
320
335
336
337
313
314
317
311
input CVBS
HREF
(2)
VREF
VREF
VRLN = 1
(2)
VRLN = 0
77 x 2/LLC
VS
(1)
RTS0 (ODD)
MGG069
(b) 2nd field
(1) ODD is switched to output RTS0 via I2C-bus bit RTSE0 = 0.
(2) Additional VREF positions can be achieved via I2C-bits VCTR1 and VCTR0 (see Fig.9).
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.24 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
32
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
525
(3)
1
(4)
2
(5)
3
(6)
4
(7)
5
(8)
6
(9)
7
(10)
17
(20)
18
(21)
19
(22)
(2)
524
(2)
522
(525)
523
(1)
8
(11)
input CVBS
HREF
(3)
VRLN = 1
VREF
VREF
(3)
VRLN = 0
520 x 2/LLC
VS
(1)
RTS0 (ODD)
(a) 1st field
260
(263)
263
264
265
266
267
268
269
270
271
262
280
281
259
(262)
282
261
(264)
(265) (266) (267) (268) (269) (270) (271) (272) (273) (274)
(283) (284) (285)
(2)
input CVBS
HREF
(3)
VRLN = 1
VREF
VREF
(3)
VRLN = 0
81 x 2/LLC
VS
(1)
RTS0 (ODD)
MGG070
(b) 2nd field
(1) ODD is switched to output RTS0 via I2C-bus bit RTSE0 = 0.
(2) Line numbers in parenthesis refer to CCIR line counting.
(3) Additional VREF positions can be achieved via I2C-bus bits VCTR1 and VCTR0 (see Fig.9).
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.25 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
33
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
Table 3 Digital output control
14 CLOCK SYSTEM
14.1 Clock generation circuit
VPO
15 to 8
VPO
7 to 0
OEYC
FEI
TCLO(1)
The internal CGC generates the system clocks LLC, LLC2
and the clock reference signal CREF. The internally
generated LFCO (triangular waveform) is multiplied by 4
via the analog PLL (including phase detector, loop filter,
VCO and frequency divider). The rectangular output
signals have a 50% duty factor.
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
Z
active
Z
Z
Z
active
Z
Z
Z
Z
Z
Table 4 Clock frequencies
CLOCK
FREQUENCY (MHz)
Z
XTAL
LLC
24.576
27
Note
LLC2
LLC4
LLC8
13.5
6.75
3.375
1. Only active in 656-format (OFTS = 3).
ZERO
CROSS
DETECTION
BAND PASS
FC = LLC/4
PHASE
DETECTION
LOOP
FILTER
LFCO
OSCILLATOR
LLC
DIVIDER
1/2
DIVIDER
1/2
LLC2
CREF
DELAY
MGC632
Fig.26 Block diagram of clock generation circuit.
1998 May 15
34
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
14.2 Power-on control
Power-on reset is activated at power-on, chip enable, PLL clock generation failure and if the supply voltage falls below
2.7 V. The RES signal can be applied to reset other circuits of the digital picture processing system.
POC V
POC V
DDA
DDD
ANALOG
DIGITAL
CLOCK
PLL
LLC
POC
LOGIC
POC
DELAY
RES
CE
CLK0
CE
XTAL
LLCINT
RESINT
LLC
RES
20 to 200 µs
PLL-delay
896 LCC
digital delay
MGC633
some ms
128 LCC
<
1 ms
CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock;
RESINT = internal reset; LLC = line-locked clock output; RES = reset output (active LOW).
Fig.27 Power-on control circuit.
1998 May 15
35
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
Table 5 Power-on control sequence
INTERNAL POWER-ON CONTROL
PIN OUTPUT STATUS
FUNCTION
SEQUENCE
Directly after power-on
asynchronous reset
VPO15 to VPO0, RTCO, RTS0, RTS1, direct switching to high impedance for
GPSW, HREF, VREF, HS, VS, LLC,
LLC2 and CREF are in high-impedance
state
20 to 200 ms
Synchronous reset sequence
LLC, LLC2, CREF, RTCO, RTS0,
internal reset sequence
RTS1, GPSW and SDA become active;
VPO15 to VPO0, HREF, VREF, HS and
VS are held in high-impedance state
Status after power-on control
sequence
VPO15 to VPO0, HREF, VREF, HS and after power-on (reset sequence) a
VS are held in high-impedance state
complete I2C-bus transmission is
required
15 OUTPUT FORMATS
Table 6 Output formats of the VPO bus (note 1)
BUS
SIGNAL
422
(16-BIT)(2)
411 (12-BIT)
CCIR-656 (8-BIT)(3)
RGB (16-BIT)(4)
RGB (24-BIT)(4)
VPO15
VPO14
VPO13
VPO12
VPO11
VPO10
VPO9
VPO8
VPO7
VPO6
VPO5
VPO4
VPO3
VPO2
VPO1
VPO0
Y07 Y17 Y27 Y37
Y06 Y16 Y26 Y36
Y05 Y15 Y25 Y35
Y04 Y14 Y24 Y34
Y03 Y13 Y23 Y33
Y02 Y12 Y22 Y32
Y01 Y11 Y21 Y31
Y00 Y10 Y20 Y30
U07 U05 U03 U01
U06 U04 U02 U00
V07 V05 V03 V01
V06 V04 V02 V00
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
U05
U04
U03
U02
U01
U00
0
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
V07
V06
V05
V04
V03
V02
V01
V00
1
U07 Y07 V07 Y17
U06 Y06 V06 Y16
U05 Y05 V05 Y15
U04 Y04 V04 Y14
U03 Y03 V03 Y13
U02 Y02 V02 Y12
U01 Y01 V01 Y11
U00 Y00 V00 Y10
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
−
R7
R6
R7
R6
R5
R5
R4
R4
R3
R3
G7
G6
G5
G4
G3
G2
B7
G7
G6
G5
R2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R1
R0
G1
G0
B2
X
X
X
X
0
X
X
X
X
1
X
X
X
X
2
X
X
X
X
3
B6
B5
B4
B1
B3
B0
Pixel
0
1
note 5
note 6
order Y
Pixel
order UV
0
0
0
−
−
−
Data rates
LLC2
LLC2
LLC
LLC2
I2C-bus
control
signals
OFTS0 = 0
OFTS1 = 1
RGB888 = X
OFTS0 = 1
OFTS1 = 0
RGB888 = X
OFTS0 = 1
OFTS1 = 1
OFTS0 = 0
OFTS1 = 0
RGB888 = 0
OFTS0 = 0
OFTS1 = 0
RGB888 = 1
RGB888 = X
1998 May 15
36
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
Notes to Table 5
1. VPO bus allows connection to 5 V video data bus systems.
2. Values in accordance with CCIR 601.
3. Before and after the video data, video timing codes are inserted in accordance with CCIR 656.
a) VPO15 to VPO8 = VPO7 to VPO0 = CCIR 656 data if I2C-bus bit TCLO = 0
b) VPO15 to VPO8 = CCIR 656 data, VPO7 to VPO0 = 3-state if I2C-bus bit TCLO = 1.
4. During HREF = LOW RGB levels are set to 16 (10 hex). RGB 16-bit is achieved by dropping the LSBs of the 8-bit
signals (after dithering if desired).
5. CREF = 0 (see Fig.17).
6. CREF = 1 (see Fig.17).
+255
+255
+240
+255
+240
blue 100%
blue 75%
red 100%
red 75%
white
+235
+212
+212
colourless
colourless
LUMINANCE 100%
+128
+128
+128
U-COMPONENT
V-COMPONENT
yellow 75%
cyan 75%
+44
+16
0
+44
+16
0
yellow 100%
cyan 100%
black
+16
0
MGC634
a. Y output range.
b. U output range (Cb).
c. V output range (Cr).
CCIR Rec. 602 digital levels.
Equations for modification to the YUV levels via BCS control I2C-bus bytes BRIG, CONT and SATN.
Luminance:
CONT
YOUT = Int ----------------- × (Y – 128) + BRIG
71
Chrominance:
SATN
UVOUT = Int ---------------- × (Cr, Cb – 128) + 128
64
It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.
Fig.28 VPO output signal range with default BCS settings.
1998 May 15
37
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
+255
+209
+255
+199
white
white
LUMINANCE
LUMINANCE
black
black shoulder
+71
+60
black shoulder = black
+60
SYNC
SYNC
1
1
sync bottom
sync bottom
MGD700
a. For sources containing 7.5 IRE black level offset (e.g. NTSC−M).
VBI data levels are not dependent on BCS settings.
b. For sources not containing black level offset.
Fig.29 VBI data bypass output range.
quartz (3rd harmonic)
24.576 MHz
XTAL
XTAL
54
55
54
55
C =
10 pF
SAA7111A
SAA7111A
XTALI
XTALI
MGG072
L = 10 µH ± 20%
C =
10 pF
C =
1 nF
a. With quartz crystal.
b. With external clock.
Order number: Philips 4322 143 05291.
Fig.30 Oscillator application.
38
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
16 APPLICATION INFORMATION
V
DD
C15
V
DDA
C9
C14
100 nF
C13
C8
100 nF
100 nF
C12
BST
C7
100 nF
V
100 nF
C11
SS
n.c.
n.c.
4
n.c.
100 nF
100 nF
V
SSA
V
100 nF
SS
15 11
7
59 58
18
3
2
57 41
33 25
15
C4
R10
34
35
AI22
6
14
13
12
11
27 Ω
R4
22 nF
36
37
38
39
42
43
44
45
46
47
48
49
50
51
V
47 Ω
SSA
C3
R9
10
9
8
7
6
5
4
3
2
1
0
8
AI21
27 Ω
R3
22 nF
V
47 Ω
VPO(15 : 0)
SSA
C2
R8
AI12
10
27 Ω
R2
22 nF
V
47 Ω
SSA
C1
R7
AI11
12
24
SAA7111A
27 Ω
R1
22 nF
V
47 Ω
SSA
R5
31
17
27
30
60
28
29
53
HREF
V
DDD
SCL
VREF
1 kΩ
63
62
HS
VS
SDA
FEI
RTCO
RTS1
RTS0
GPSW
AOUT
52
R6 1 kΩ
V
SS
XTAL
14
20
LLC
54
55
Q1(24.576 MHz)
21
22
23
LLC2
CREF
XTALI
RES
10
L1
µH
C17
C18
C16
1 nF
1
16
9
13
40
26
61
19
5
56
32
64
10 pF
10 pF
V
n.c.
SS
MGG071
V
n.c.
V
V
SS
SS
SSA
Fig.31 Application diagram.
39
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
VPO (15 : 11)
R (7 : 3)
15
14
13
12
11
10
9
34
35
36
37
38
39
42
43
3
G (7 : 5)
G (4 : 2)
VPO (10 : 8)
VPO (7 : 5)
VPO
(15 : 8)
3
3
8
V
SS
V
V
OEN
D7
DD
O7
DD
R (2 : 0)
7
6
5
4
3
2
1
0
44
45
46
47
48
49
50
51
R (7 : 0)
3
8
D6
O6
O5
O4
O3
O2
O1
00
D5
G (1 : 0)
B (2 : 0)
e.g.
D4
G (7 : 0)
B (7 : 0)
VPO
(7 : 0)
2
3
8
8
74HCT574
D3
D2
D1
D0
V
CLK
SS
V
SS
VPO (4 : 0)
SAA7111A
B (7 : 3)
5
HREF
31
17
27
30
60
28
29
53
14
20
21
32
VREF
HS
VS
RTCO
RTS1
RTS0
GPSW
AOUT
LLC
e.g. 74HCT240
LLC2
LLC2N
CREF
RES
23
MGG073
I2C-bus control bits:
OFTS(1 : 0) = 00 (subaddress 10H, bits D7 and D6).
RGB888 = 1 (subaddress 12H, bit D3).
Fig.32 Application diagram for RGB 24-bit output format.
Place the coupling (clamp) capacitors close to the analog
input pins. Place the termination resistors close to the
coupling capacitors. Care should be exercised concerning
the hidden layout capacitors around the crystal
application. To avoid reflection effects use serial resistors
in the clock, sync and data lines.
16.1 Layout hints
Use separate ground planes for analog and digital ground.
Connect these planes at one point directly under the
device, by using a zero Ω resistor. Use separate supply
lines for analog and digital supply. Place the supply
decoupling capacitors close to the supply pins.
1998 May 15
40
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17 I2C-BUS DESCRIPTION
17.1 I2C-bus format
Table 7 Write procedure
S
SLAVE ADDRESS W
ACK-s
SUBADDRESS
ACK-s
DATA (N BYTES)
ACK-s
P
P
Table 8 Read procedure (combined format)
S
SLAVE ADDRESS W
SLAVE ADDRESS R
ACK-s
ACK-s
SUBADDRESS
DATA (N BYTES)
ACK-s
ACK-m
Sr
Table 9 Description of I2C-bus format
CODE
DESCRIPTION
S
START condition
Sr
repeated START condition
Slave address W 0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)
Slave address R
ACK-s
0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)
acknowledge generated by the slave
acknowledge generated by the master
subaddress byte; see Table 10
ACK-m
Subaddress
Data
data byte; see Table 10; note 1
P
STOP condition
X = LSB slave
address
read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)
Slave address
Subaddresses
read = 49H or 4BH; note 2
write = 48H or 4AH
IICSA = 0 or 1
00H chip version
read and write; note 3
01H reserved
−
02h to 05H front-end part
06H to 13H decoder part
14H reserved
read and write
read and write
−
15H to 17H decoder part
18H to 19H reserved
1AH to 1CH Line-21 text slicer part
1DH to 1EH reserved
1FH status byte
read and write
−
read only
−
read only
Notes
1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.
2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with
the I2C-bus specification).
3. The I2C-bus subaddress 00 has to be initialized with 0 before being read.
1998 May 15
41
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
Table 10 I2C-bus receiver/transmitter overview
READ
WRITE
IICSA
SLAVE ADDRESS
49H
4BH
48H
4AH
0
1
REGISTER
FUNCTION
SUB-
ADDR
D7
D6
D5
D4
D3
D2
D1
D0
Chip version
00
01
02
03
04
05
06
07
08
09
0A
ID07
(1)
ID06
(1)
ID05
(1)
ID04
(1)
ID03
(1)
ID02
(1)
ID01
(1)
ID00
(1)
Reserved
Analog input contr 1
Analog input contr 2
Analog input contr 3
Analog input contr 4
Horizontal sync start
Horizontal sync stop
Sync control
FUSE1 FUSE0 GUDL2 GUDL1
GUDL0
HOLDG
GAI13
GAI23
HSB3
MODE2
GAFIX
GAI12
GAI22
HSB2
MODE1
GAI28
GAI11
GAI21
HSB1
MODE0
GAI18
GAI10
GAI20
HSB0
(1)
HLNRS VBSL WPOFF
GAI17
GAI27
HSB7
HSS7
AUFD
BYPS
GAI16
GAI26
HSB6
HSS6
FSEL
GAI15
GAI25
HSB5
HSS5
EXFIL
GAI14
GAI24
HSB4
HSS4
(1)
HSS3
HSS2
HSS1
HSS0
VTRC
VBLB
HPLL
VNOI1
APER1
BRIG1
VNOI0
APER0
BRIG0
Luminance control
PREF BPSS1 BPSS0
UPTCV
BRIG2
Luminance
brightness
BRIG7 BRIG6 BRIG5 BRIG4
BRIG3
Luminance contrast
Chroma saturation
Chroma Hue control
Chroma control
Reserved
0B
0C
0D
0E
CONT7 CONT6 CONT5 CONT4
SATN7 SATN6 SATN5 SATN4
HUEC7 HUEC6 HUEC5 HUEC4
CDTO CSTD2 CSTD1 CSTD0
CONT3
SATN3
HUEC3
CONT2
SATN2
HUEC2
CONT1
SATN1
HUEC1
CONT0
SATN0
HUEC0
DCCF
(1)
FCTC
(1)
CHBW1
CHBW0
(1)
(1)
(1)
(1)
(1)
(1)
0F
Format/delay control
Output control 1
Output control 2
Output control 3
Reserved
10
OFTS1 OFTS0 HDEL1 HDEL0
GPSW CM99 FECO COMPO
RTSE1 RTSE0 TCLO CBR
VCTR1 VCTR0 CCTR1 CCTR0
VRLN
OEYC
YDEL2
OEHV
DIT
YDEL1
VIPB
YDEL0
COLO
AOSL0
11
12
RGB888
AOSL1
13
BCHI1
(1)
BCHI0
(1)
BCLO1
BCLO0
(1)
(1)
(1)
(1)
(1)
(1)
14
V_GATE1_START
V_GATE1_STOP
V_GATE1_MSB
Reserved
15
VSTA7 VSTA6 VSTA5 VSTA4
VSTO7 VSTO6 VSTO5 VSTO4
VSTA3
VSTA2
VSTA1
VSTO1
VSTA0
VSTO0
16
VSTO3
VSTO2
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
17
VSTO8
VSTA8
(1)
(1)
(1)
(1)
18-19
1A
Text slicer status
F2VAL
F2RDY
F1VAL
F1RDY
1B
P1
BYTE16 BYTE15 BYTE14 BYTE13
BYTE26 BYTE25 BYTE24 BYTE23
BYTE12 BYTE11 BYTE10
BYTE22 BYTE21 BYTE20
Decoded bytes of
the text slicer
1C
1D-1E
1F
P2
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
Status byte
STTC
HLCK
FIDT
GLIMT
GLIMB
WIPA
SLTCA
CODE
Note
1. All unused control bits must be programmed with logic 0.
1998 May 15
42
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2 I2C-bus detail
The I2C-bus receiver slave address is 48H/49H. Subaddresses 0F, 14, 18, 19, 1D and 1E are reserved; subaddress 01
is reserved for chip version.
17.2.1 SUBADDRESS 00
Table 11 Chip version SA00; note 1
LOGIC LEVELS
FUNCTION
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
V1
V2
0
0
0
0
0
1
1
0
X
X
X
X
X
X
X
X
Chip version
Note
1. X = reserved.
17.2.2 SUBADDRESS 02
Table 12 Analog control 1 SA02; note 1
CONTROL BITS D2 TO D0
FUNCTION(2)
MODE 2
MODE 1
MODE 0
Mode 0 : CVBS (automatic gain)
Mode 1 : CVBS (automatic gain)
Mode 2 : CVBS (automatic gain)
Mode 3 : CVBS (automatic gain)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Mode 4 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
Mode 5 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
Mode 6 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)
Mode 7 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)
Notes
1. Mode select (see Figs 33 to 40).
2. For modes 0 to 3 use BYPS(SA09,D7) = 0 (chrominance trap active), for modes 4 to 7 use BYPS = 1 (chrominance
trap bypassed).
Table 13 Analog control 1 SA 02, D5 to D3 (see Fig.14)
CONTROL BITS D5 TO D3
DECIMAL VALUE
UPDATE HYSTERESIS FOR 9-BIT GAIN
GUDL 2
GUDL 1
GUDL 0
0....
....7
off
0
1
0
1
0
1
±7 LSB
1998 May 15
43
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
Table 14 Analog control
CONTROL BITS D7 AND D6
ANALOG FUNCTION SELECT FUSE
FUSE 1
FUSE 0
Amplifier plus anti-alias filter bypassed
0
0
1
1
0
1
0
1
Amplifier active
Amplifier plus anti-alias filter active
AI22
AI21
handbook, halfpage
handbookA, hI2a2lfpage
AI21
AD2
AD1
AD2
AD1
CHROMA
CHROMA
AI12
AI11
LUMA
AI12
AI11
LUMA
MGC638
MGC637
Fig.33 Mode 0; CVBS (automatic gain).
Fig.34 Mode 1; CVBS (automatic gain).
handbookA, hI2al2fpage
AI22
AI21
handbook, halfpage
AD2
AD1
AD2
AD1
AI21
CHROMA
CHROMA
AI12
AI11
LUMA
AI12
AI11
LUMA
MGC639
MGC640
Fig.35 Mode 2; CVBS (automatic gain).
Fig.36 Mode 3; CVBS (automatic gain).
handbookA, hI2al2fpage
handbookA, hI2al2fpage
AD2
AD1
AD2
AD1
AI21
CHROMA
AI21
CHROMA
AI12
AI11
LUMA
AI12
AI11
LUMA
MGC641
MGC642
Fig.37 Mode 4 Y (automatic gain) + C
(gain channel 2 fixed to GAI2 level).
Fig.38 Mode 5 Y (automatic gain) + C
(gain channel 2 fixed to GAI2 level).
1998 May 15
44
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbookA, hI2al2fpage
AI21
handbookA, hI2al2fpage
AD2
AD1
AD2
AD1
CHROMA
AI21
CHROMA
AI12
AI11
LUMA
AI12
AI11
LUMA
MGC643
MGC644
Fig.39 Mode 6 Y (automatic gain) + C
(gain channel 2 adapted to Y gain).
Fig.40 Mode 7 Y (automatic gain) + C
(gain channel 2 adapted to Y gain).
17.2.3 SUBADDRESS 03
Table 15 Analog control 2 (AICO2) SA03
FUNCTION
BIT NAME
GAI18
LOGIC LEVEL
see Table 16
see Table 17
CONTROL BIT
Static gain control channel 1 (GAI18) (see SA04)
Sign bit of gain control
D0
D1
Static gain control channel 2 (GAI28) (see SA05)
Sign bit of gain control
GAI28
Gain control fix (GAFIX)
Automatic gain controlled by MODE 1 and MODE 0
Gain control is user programmable via GAI1 + GAI2
GAFIX
GAFIX
0
1
D2
D2
Automatic gain control integration (HOLDG)
AGC active
HOLDG
HOLDG
0
1
D3
D3
AGC integration hold (freeze)
White peak off (WPOFF)
White peak control active
White peak off
WPOFF
WPOFF
0
1
D4
D4
Vertical blanking select (VBSL)
Long vertical blanking
Short vertical blanking
VBSL
VBSL
0
1
D5
D5
HL not reference select (HLNRS)
Normal clamping by HL not
Reference select by HL not
HLNRS
HLNRS
0
1
D6
D6
1998 May 15
45
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.4 SUBADDRESS 04
Table 16 Gain control analog (AIC03); static gain control channel 1 GAI1 SA 04, D7 to D0
SIGN
BIT
CONTROL BITS D7 TO D0
DECIMAL
VALUE
GAIN
(dB)
GAI18
GAI17
GAI16
GAI15
GAI14
GAI13
GAI12
GAI11
GAI10
0....
−5.98
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
....255
256....
....511
0
5.98
17.2.5 SUBADDRESS 05
Table 17 Gain control analog (AIC04); static gain control channel 2 GAI2 SA 05, D7 to D0
SIGN BIT
(SA 03, D1)
CONTROL BITS D7 to D0
GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20
DECIMAL
VALUE
GAIN
(dB)
GAI28
0....
−5.98
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
....255
256....
....511
0
5.98
17.2.6 SUBADDRESS 06
Table 18 Horizontal sync begin SA 06, D7 to D0
CONTROL BITS D7 to D0
HSB4 HSB3
DELAY TIME
(STEP SIZE = 8/LLC)
HSB7
HSB6
HSB5
HSB2
HSB1
HSB0
−128...−108
−107...
forbidden (outside available central counter range)
1
0
0
0
1
1
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
1
...108 (50Hz)
...107 (60Hz)
109...127 (50Hz)
108...127 (60Hz)
forbidden (outside available central counter range)
1998 May 15
46
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.7 SUBADDRESS 07
Table 19 Horizontal sync stop SA 07, D7 to D0
CONTROL BITS D7 to D0
HSS5 HSS4 HSS3
forbidden (outside available central counter range)
DELAY TIME
(STEP SIZE = 8/LLC)
HSS7
HSS6
HSS2
HSS1
HSS0
−128...−108
−107...
1
0
0
0
1
1
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
1
...108 (50Hz)
...107 (60Hz)
109...127 (50Hz)
108...127 (60Hz)
forbidden (outside available central counter range)
17.2.8 SUBADDRESS 08
Table 20 Sync control SA 08, D7 to D5, D3 to D0
FUNCTION
BIT NAME
LOGIC LEVEL CONTROL BIT
Vertical noise reduction (VNOI)
Normal mode
VNOI1
VNOI0
VNOI1
VNOI0
VNOI1
VNOI0
VNOI1
VNOI0
0
0
0
1
1
0
1
1
D1
D0
D1
D0
D1
D0
D1
D0
Searching mode
Free running mode
Vertical noise reduction bypassed
Horizontal PLL (HPLL)
PLL closed
HPLL
HPLL
0
1
D2
D2
PLL open, horizontal frequency fixed
TV/VTR mode select (VTRC)
TV mode
VTRC
VTRC
0
1
D3
D3
(recommended for poor quality TV signals only)
VTR mode (recommended as default setting)
Extended loop filter (EXFIL)
Word width of the loop filter (LF2) amplification = 16-bit
Word width of the loop filter (LF2) amplification = 14-bit
EXFIL
EXFIL
0
1
D5
D5
Field selection (FSEL)
50 Hz, 625 lines
FSEL
FSEL
0
1
D6
D6
60 Hz, 525 lines
Automatic field detection (AUFD)
Field state directly controlled via FSEL
Automatic field detection
AUFD
AUFD
0
1
D7
D7
1998 May 15
47
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.9 SUBADDRESS 09
Table 21 Luminance control SA 09, D7 to D0
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Aperture factor (APER)
Aperture factor = 0
APER1
APER0
APER1
APER0
APER1
APER0
APER1
APER0
0
0
0
1
1
0
1
1
D1
D0
D1
D0
D1
D0
D1
D0
Aperture factor = 0.25
Aperture factor = 0.5
Aperture factor = 1.0
Update time interval for AGC value (UPTCV)
Horizontal update (once per line)
UPTCV
UPTCV
0
1
D2
D2
Vertical update (once per field)
Vertical blanking luminance bypass (VBLB)
Active luminance processing
VBLB
VBLB
0
1
D3
D3
Luminance bypass during vertical blanking
Aperture band pass (centre frequency) (BPSS)
Centre frequency = 4.1 MHz
BPSS1
BPSS0
BPSS1
BPSS0
BPSS1
BPSS0
BPSS1
BPSS0
0
0
0
1
1
0
1
1
D5
D4
D5
D4
D5
D4
D5
D4
Centre frequency = 3.8 MHz; note 1
Centre frequency = 2.6 MHz; note 1
Centre frequency = 2.9 MHz; note 1
Prefilter active (PREF)
Bypassed
PREF
PREF
0
1
D6
D6
Active
Chrominance trap bypass (BYPS)
Chrominance trap active; default for CVBS mode
BYPS
BYPS
0
1
D7
D7
Chrominance trap bypassed; default for S-Video mode
Note
1. Not to be used with bypassed chrominance trap.
1998 May 15
48
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.10 SUBADDRESS 0A
Table 22 Luminance brightness control BRIG7 to BRIG0 SA 0A
CONTROL BITS D7 to D0
OFFSET
BRIG7
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
255 (bright)
128 (CCIR level)
0 (dark)
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
17.2.11 SUBADDRESS 0B
Table 23 Luminance contrast control CONT7 to CONT0 SA 0B
CONTROL BITS D7 to D0
GAIN
CONT7
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
CONT0
1.999 (maximum)
1.109 (CCIR level)
1.0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0 (luminance off)
−1 (inverse luminance)
−2 (inverse luminance)
17.2.12 SUBADDRESS 0C
Table 24 Chrominance saturation control SATN7 to SATN0 SA 0C
CONTROL BITS D7 to D0
GAIN
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
SATN0
1.999 (maximum)
1.0 (CCIR level)
0 (colour off)
0
0
0
1
1
1
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
−1 (inverse
chrominance)
−2 (inverse
1
0
0
0
0
0
0
0
chrominance)
17.2.13 SUBADDRESS 0D
Table 25 Chrominance hue control HUEC7 to HUEC0 SA 0D
CONTROL BITS D7 to D0
HUE PHASE (DEG)
HUEC7
HUEC6
HUEC5
HUEC4
HUEC3
HUEC2
HUEC1
HUEC0
+178.6....
....0....
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
....−180
1998 May 15
49
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.14 SUBADDRESS 0E
Table 26 Chrominance control SA 0E
LOGIC
LEVEL
CONTROL
BIT
FUNCTION
BIT NAME
Chroma bandwidth (CHBW0 and CHBW1)
Small bandwidth (≈ 620 kHz)
CHBW1
CHBW0
CHBW1
CHBW0
CHBW1
CHBW0
CHBW1
CHBW0
0
0
0
1
1
0
1
1
D1
D0
D1
D0
D1
D0
D1
D0
Nominal bandwidth (≈ 800 kHz)
Medium bandwidth (≈ 920 kHz)
Wide bandwidth (≈ 1000 kHz)
Fast colour time constant (FCTC)
Nominal time constant
Fast time constant
FCTC
FCTC
0
1
D2
D2
Disable chrominance comb filter (DCCF)
Chrominance comb filter on (during VREF = 1) (see Figs 24 and 25)
Chrominance comb filter off
DCCF
DCCF
0
1
D3
D3
Colour standard (CSTD0 to CSTD2); logic levels 100, 110 and 111 are reserved, do not use
Colour standard control automatic switching between PAL BGHI and
NTSC M (NTSC-Japan with special level adjustment; luminance
brightness subaddress 0A = 95H, luminance contrast
subaddress 0BH = 48H)
CSTD2
CSTD1
CSTD0
0
0
0
D6
D5
D4
Colour standard control automatic switching between NTSC 4.43 (50 Hz)
and PAL 4.43 (60 Hz)
CSTD2
CSTD1
CSTD0
CSTD2
CSTD1
CSTD0
CSTD2
CSTD1
CSTD0
CSTD2
CSTD1
CSTD0
0
0
1
0
1
0
0
1
1
1
0
1
D6
D5
D4
D6
D5
D4
D6
D5
D4
D6
D5
D4
Colour standard control automatic switching between PAL N and
NTSC 4.43 (60 Hz)
Colour standard control automatic switching between NTSC N and
PAL M
Colour standard control automatic switching between SECAM and
PAL 4.43 (60 Hz)
Clear DTO (CDTO)
Disabled
CDTO
CDTO
0
1
D7
D7
Every time CDTO is set, the internal subcarrier DTO phase is reset to 0°
and the RTCO output generates a logic 0 at time slot 68 (see RTCO
description Fig.20). So an identical subcarrier phase can be generated by
an external device (e.g. an encoder).
1998 May 15
50
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.15 SUBADDRESS 10
Table 27 Format/delay control SA 10
CONTROL BITS D2 to D0
YDEL1
LUMINANCE DELAY COMPENSATION
(STEPS IN 2/LLC)
YDEL2
YDEL0
−4...
...0...
...3
1
0
0
0
0
1
0
0
1
Table 28 VREF pulse position and length VRLN SA 10 (D3)
VREF at 60 Hz 525 LINES(1)
VRLN
VREF at 50 Hz 625 LINES(1)
0
1
0
1
Length
240
242
286
288
Line number
Field 1(2)
Field 2(2)
first
last
258 (261)
first
last
259 (262)
first
24
last
309
622
first
23
last
310
623
19 (22)
18 (21)
282 (285) 521 (524) 281 (284) 522 (525)
337
336
Notes
1. Additional VREF positions can be achieved via I2C-bus bits VCTR1 and VCTR0 (see Fig.9).
2. The numbers given in parenthesis refer to CCIR line counting.
Table 29 Fine position of HS HDEL0 and HDEL1 SA 10
CONTROL BITS D5 and D4
FINE POSITION OF HS WITH A STEP SIZE
OF 2/LLC
HDEL1
HDEL0
0
1
2
3
0
0
1
1
0
1
0
1
Table 30 Output format selection OFTS0 and OFTS1 SA 10
CONTROL BITS D7 and D6
FORMATS
OFTS1
OFTS0
RGB (5, 6 and 5), RGB (8, 8 and 8)
(dependent on control bit RGB888); see
Table 32
0
0
YUV 422 16 bits
YUV 411 12 bits
0
1
1
1
0
1
YUV CCIR-656 8 bits
1998 May 15
51
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.16 SUBADDRESS 11
Table 31 Output control 1 SA 11
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Colour on (COLO)
Automatic colour killer
Colour forced on
COLO
COLO
0
1
D0
D0
Decoder VIP bypassed (VIPB)
DMSD data to YUV output
VIPB
VIPB
0
1
D1
D1
ADC data to YUV output; dependent on mode settings
Output enable horizontal/vertical sync (OEHV)
HS, HREF, VREF and VS high-impedance inputs
Outputs HS, HREF, VREF and VS active
OEHV
OEHV
0
1
D2
D2
Output enable YUV data (OEYC)
VPO-bus high-impedance inputs
Output VPO-bus active
OEYC
OEYC
0
1
D3
D3
Inverse composite blank (COMPO)
VREF is vertical reference
COMPO
COMPO
0
1
D4
D4
VREF is inverse composite blank
FEI control (FECO)
FEI sampling at CREF = LOW
(SAA7110 compatible); (see Fig.19)
FECO
FECO
0
1
D5
D5
FEI sampling at CREF = HIGH
Compatibility to SAA7199 (CM99)
Default value
CM99
CM99
0
1
D6
D6
To be set if SAA7199 (digital encoder) is used for
re-encoding in conjunction with RTCO
General purpose switch (GPSW)
Switches directly pin 64 GPSW
GPSW
GPSW
0
1
D7
D7
1998 May 15
52
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.17 SUBADDRESS 12
Table 32 Output control 2 SA 12, D7 to D6, D4 to D0
FUNCTION
Analog test select (AOSL)
BIT NAME
LOGIC LEVEL
CONTROL BIT
AOUT connected to internal test point 1
AOSL1
AOSL0
AOSL1
AOSL0
AOSL1
AOSL0
AOSL1
AOSL0
0
0
0
1
1
0
1
1
D1
D0
D1
D0
D1
D0
D1
D0
AOUT connected to input AD1
AOUT connected to input AD2
AOUT connected to internal test point 2
Dithering (noise shaping) control (DIT)
Dithering off
DIT
DIT
0
1
D2
D2
Dithering on
RGB output format selection (RGB888)
RGB (5, 6 and 5)
RGB (8, 8 and 8)
RGB888
RGB888
0
1
D3
D3
Chrominance interpolation filter function (CBR)
Cubic interpolation (default)
CBR
CBR
0
1
D4
D4
Linear interpolation (lower bandwidth)
3-state control VPO7 to VPO0 (TCLO)
VPO7 to VPO0 depends on OEYC, FEI only (default)
(see Figs 18, 19 and 22)
TCLO
TCLO
0
1
D5
D5
VPO7 to VPO0 in 3-state [and OFTS (1 : 0) = 3]
(see Tables 3 and 6)
Real time outputs mode select (RTSE0)
ODD switched to output pin 40
VL switched to output pin 40
RTSE0
RTSE0
0
1
D6
D6
Real time outputs mode select (RTSE1)
PLIN switched to output pin 39
RTSE1
RTSE1
0
1
D7
D7
HL switched to output pin 39
1998 May 15
53
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.18 SUBADDRESS 13
Table 33 Output control 3 SA 13
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Bypass control LOW for VPO7 to VPO0
No bypass
BCLO1
BCLO0
BCLO1
BCLO0
BCLO1
BCLO0
BCLO1
BCLO0
0
0
0
1
1
0
1
1
D1
D0
D1
D0
D1
D0
D1
D0
Permanent bypass
Bypass controlled by V_GATE
Bypass controlled by delayed V_GATE
Bypass control HIGH for VPO15 to VPO8
No bypass
BCHI1
BCHI0
BCHI1
BCHI0
BCHI1
BCHI0
BCHI1
BCHI0
0
0
0
1
1
0
1
1
D3
D2
D3
D2
D3
D2
D3
D2
Permanent bypass
Bypass controlled by V_GATE
Bypass controlled by delayed V_GATE
Clock Reference Output Control
CREF is independent of VREF
CCTR1
CCTR0
CCTR1
CCTR0
CCTR1
CCTR0
CCTR1
CCTR0
0
0
0
1
1
0
1
1
D5
D4
D5
D4
D5
D4
D5
D4
CREF is LOW if VREF = 0
CREF is HIGH if VREF = 0
CREF always = 1
Vertical Reference Output Control (VREF)
Internal VREF
VCTR1
VCTR0
VCTR1
VCTR0
VCTR1
VCTR0
VCTR1
VCTR0
0
0
0
1
1
0
1
1
D7
D6
D7
D6
D7
D6
D7
D6
VREF_CCIR
Programmable V_GATE
Delayed programmable V_GATE
1998 May 15
54
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17.2.19 SUBADDRESS 15
Table 34 Start of decoded data on VPO-port SA 15; note 1
MSB
(SA 17,
D0)
FRAME
CONTROL BITS D7 to D0
DECIMA
L VALUE
FIELD
LINE(2)
COUNTING
VSTA8
VSTA7
VSTA6
VSTA5
VSTA4
VSTA3
VSTA2
VSTA1
VSTA0
50 Hz 1st
2nd
1
314
312
0....
1
0
0
1
1
1
0
0
0
1st
2
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
1
0
0
1
2nd
315
1st
312
....310
262
2nd
625
60 Hz 1st
2nd
1 (4)
264 (267)
2 (5)
1st
0....
2nd
265 (268)
262 (265)
525 (3)
1st
....260
2nd
Notes
1. Start of decoded data on VPO-port (end of bypassed region; start of VREF if selected by VCTR1 and VCTR0; see Figs 8 and 10).
2. Line numbers in brackets refer to CCIR line counting.
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17.2.20 SUBADDRESS 16
TABLE 35 STOP OF DECODED DATA ON VPO-PORT SA 16; NOTE 1
MSB
FRAME
CONTROL BITS D7 to D0
DECIMAL
(SA 17, D0)
FIELD
LINE(2)
COUNTING
VALUE
VSTO8
VSTO7
VSTO6
VSTO5
VSTO4
VSTO3
VSTO2
VSTO1
VSTO0
50 Hz 1st
2nd
1
314
312
1
0
0
1
1
1
0
0
0
1st
2
0....
....310
262
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
1
0
0
1
2nd
315
1st
312
2nd
625
60 Hz 1st
2nd
1 (4)
264 (267)
2 (5)
1st
0....
2nd
265 (268)
262 (265)
525 (3)
1st
....260
2nd
NOTES
1. STOP OF DECODED DATA ON VPO-PORT (BEGIN OF BYPASSED REGION; STOP OF VREF IF SELECTED BY VCTR1 AND VCTR0; SEE FIGS 8 AND 10).
2. LINE NUMBERS IN BRACKETS REFER TO CCIR LINE COUNTING.
17.2.21 SUBADDRESS 17
Table 36 Sign bits of the VBI-data stream control
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
VBI-data stream start (VSTA8); see SA 15
Sign bit VBI-data stream start
VSTA8
VSTO8
see Table 34
see Table 35
D0
D1
VBI-data stream stop (VSTO8); see SA 16
Sign bit VBI-data stream stop
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.22 SUBADDRESS 1A (READ-ONLY REGISTER)
Table 37 Line-21 text slicer status SA 1A, D3 to D0
I2C-BUS
STATUS BIT
NAME
FUNCTION
STATUS BIT
F1RDY
F1VAL
F2RDY
F2VAL
new data on field 1 has been acquired (for asynchronous reading); active HIGH
line-21 of field 1 carries valid data; active HIGH
D0
D1
D2
D3
new data on field 2 has been acquired (for asynchronous reading); active HIGH
line-21 of field 2 carries valid data; active HIGH
17.2.23 SUBADDRESS 1B (READ-ONLY REGISTER)
Table 38 First decoded data byte of the text slicer SA 1B
I2C-BUS
TEXT DATA
BITS
FUNCTION
DATA BITS
BYTE1 (6 to 0) data bit 6 to 0 of first data byte
D6 to D0
D7
P1
parity error flag bit; bit goes HIGH when a parity error has occurred
17.2.24 SUBADDRESS 1C (READ-ONLY REGISTER)
Table 39 Second decoded data byte of the text slicer SA 1C
I2C-BUS
TEXT DATA
BITS
FUNCTION
DATA BITS
BYTE2 (6 to 0) data bit 6 to 0 of second data byte
D6 to D0
D7
P2
parity error flag bit; bit goes HIGH when a parity error has occurred
17.2.25 SUBADDRESS 1F (READ-ONLY REGISTER)
Table 40 Status byte SA 1F
I2C-BUS
STATUS BIT
NAME
FUNCTION
STATUS BIT
CODE
colour signal in accordance with selected standard has been detected; active
HIGH
D0
SLTCA
WIPA
slow time constant active in WIPA-mode; active HIGH
D1
D2
D3
D4
D5
D6
D7
white peak loop is activated; active HIGH
GLIMB
GLIMT
FIDT
gain value for active luminance channel is limited [min (bottom)]; active HIGH
gain value for active luminance channel is limited [max (top)]; active HIGH
identification bit for detected field frequency; LOW = 50 Hz, HIGH = 60 Hz
status bit for locked horizontal frequency; LOW = locked, HIGH = unlocked
HLCK
STTC
status bit for horizontal phase loop; LOW = TV time-constant,
HIGH = VTR time-constant
1998 May 15
57
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
18 FILTER CURVES
18.1 Anti-alias filter curve
MGD138
6
V
(dB)
0
−6
−12
−18
−24
−30
−36
−42
0
2
4
6
8
10
12
14
f (MHz)
Fig.41 Anti-alias filter.
18.2 TUF-block filter curve
MGG067
6
V
(dB)
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
Fig.42 Interpolation filter for the upsampled CVBS-signal.
58
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
18.3 Luminance filter curves
MGD139
18
V
Y
(dB)
(1)
6
−6
(2)
(4)
(3)
(1)
(2)
(4)
(3)
−18
−30
0
2
4
6
8
f
Y (MHz)
(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.
Fig.43 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on, different aperture bandpass centre
frequencies.
MGD140
18
V
Y
(dB)
6
(1)
(2)
(3)
(4)
−6
−18
−30
(4)
(3)
(2)
(1)
0
2
4
6
8
f
Y (MHz)
(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.
Fig.44 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on, different aperture factors.
1998 May 15
59
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
MGD141
18
V
Y
(dB)
6
(1)
(2)
(4)
(3)
−6
−18
−30
(1)
(2)
(4)
(3)
0
2
4
6
8
f
Y (MHz)
(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.
Fig.45 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter off, different aperture band-pass centre
frequencies.
MGD142
18
V
Y
(dB)
(1)
(2)
(3)
(4)
6
−6
−18
−30
0
2
4
6
8
f
Y (MHz)
(1) = C0H; (2) = C1H; (3) = C2H; (4) = C3H.
Fig.46 Luminance control SA 09H, Y/C mode, prefilter on, different aperture factors.
60
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
MGD143
18
V
Y
(dB)
6
(1)
(2)
(3)
(4)
−6
−18
−30
0
2
4
6
8
f
Y (MHz)
(1) = 80H; (2) = 81H; (3) = 82H; (4) = 83H.
Fig.47 Luminance control SA 09H, Y/C mode, prefilter off, different aperture factors.
MGD144
18
V
Y
(dB)
6
(1)
(2)
(1)
(4)
(2)
(4)
(3)
(3)
−6
−18
−30
0
2
4
6
8
f
Y (MHz)
(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.
Fig.48 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on, different aperture band-pass centre
frequencies.
1998 May 15
61
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
MGD145
18
V
Y
(dB)
6
(1)
(2)
(3)
(4)
(4)
(3)
(2)
(1)
−6
−18
−30
0
2
4
6
8
f
Y (MHz)
(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.
Fig.49 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on, different aperture factors.
MGD146
18
V
Y
(dB)
6
(1)
(2)
(4)
(3)
(1)
(2)
(4)
(3)
−6
−18
−30
0
2
4
6
8
f
Y (MHz)
(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.
Fig.50 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter off, different aperture band-pass centre
frequencies.
1998 May 15
62
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
18.4 Chrominance filter curves
MGD147
6
V
(dB)
0
−6
(1)
(2)
(3)
(4)
−12
−18
−24
−30
−36
−42
−48
−54
(4)
(1)
(3)
(2)
0
0.54
1.08
1.62
2,16
2.7
f
(MHz)
(1) Transfer characteristics of the chrominance low-pass dependent on CHBW[1 : 0] settings. CHBW [1 : 0] = 00; (2) CHBW [1 : 0] = 01; (3)
CHBW [1 : 0] = 10; (4) CHBW [1 : 0] = 11.
Fig.51 Chrominance filter.
19 I2C-BUS START SET-UP
• The given values force the following behaviour of the SAA7111A:
– The analog input AI11 expects a signal in CVBS format; analog anti-alias filter active
– Automatic field detection
– YUV 4 : 2 : 2 16-bit output format enabled
– Outputs HS, HREF, VREF and VS active
– Contrast, brightness and saturation control in accordance with CCIR standards
– Chrominance processing with nominal bandwidth (800 kHz).
1998 May 15
63
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
Table 41 I2C-bus start set-up values
VALUES (BIN)
(HEX)
SUB
(HEX)
FUNCTION
chip version
NAME(1)
7
6
5
4
3
2
1
0
START
00
01
02
ID07 to ID00; see Table 9
read only
reserved
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
00
analog input control 1
FUSE1 and FUSE0, GUDL2 to GUDL0,
MODE2 to MODE0
C0
03
analog input control 2
X, HLNRS, VBSL, WPOFF, HOLDG,
GAFIX, GAI28 and GAI18
0
0
1
0
0
0
1
1
33
04
05
06
07
08
analog input control 3
analog input control 4
horizontal sync start
horizontal sync stop
sync control
GAI17 to GAI10
GAI27 to GAI20
HSB7 to HSB0
HSS7 to HSS0
0
0
1
1
1
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
00
00
EB
E0
88
AUFD, FSEL, EXFIL, X, VTRC, HPLL,
VNOI1 and VNOI0
09
luminance control
BYPS, PREF, BPSS1 and BPSS0, VBLB,
UPTCV, APER1 and APER0
0
0
0
0
0
0
0
1
01
0A
0B
0C
0D
0E
luminance brightness
luminance contrast
BRIG7 to BRIG0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
80
47
40
00
01
CONT7 to CONT0
chrominance saturation SATN7 to SATN0
chroma hue control
chrominance control
HUEC7 to HUEC0
CDTO, CSTD2 to CSTD0, DCCF, FCTC,
CHBW1 and CHBW0
0F
10
reserved
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
00
40
format/delay control
OFTS1 and OFTS0, HDEL1 and HDEL0,
VRLN, YDEL2 to YDEL0
11
12
13
output control 1
output control 2
output control 3
GPSW, CM99, FECO, COMPO, OEYC,
OEHV, VIPB, and COLO
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1C
00
00
RTSE1 and RTSE0, TCLO, CBR,
RGB888 DIT, AOSL1 and AOSL0
CCTR1 and CCTR0, BCHI1 and BCHI0,
BCLO1 and BCLO0, VCTR1 and VCTR0
0
0
0
0
0
0
0
0
14
15
16
17
reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
VBI-data stream start
VBI-data stream stop
MSBs for VBI control
VSTA7 to VSTA0
VSTO7 to VSTO0
X, X, X, X, X, X, VSTO8, and VSTA8
18-19 reserved
1A
text slicer status
0, 0, 0, 0, F2VAL, F2RDY,
F1VAL, and F1RDY
read only register
1B
1C
decoded bytes of the
text slicer
P1, BYTE1 (6 to 0)
P2, BYTE2 (6 to 0)
1D-1E reserved
0
0
0
0
0
0
0
0
00
1F
status byte
STTC, HLCK, FIDT, GLIMT, GLIMB,
WIPA, SLTCA and CODE
read only register
Note
1. All X values must be set to LOW.
1998 May 15
64
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
20 PACKAGE OUTLINES
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
y
X
A
48
33
Z
49
32
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-01
SOT314-2
1998 May 15
65
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SOT393-1
y
X
A
48
33
32
49
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
L
p
b
pin 1 index
L
17
64
detail X
16
1
w M
v
M
A
b
p
Z
e
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.75
0.10 2.55
0.45 0.23 14.1 14.1
0.30 0.13 13.9 13.9
17.45 17.45
16.95 16.95
1.03
0.73
1.2
0.8
1.2
0.8
mm
3.00
0.25
0.8
1.60
0.16 0.16 0.10
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
96-05-21
97-08-04
SOT393-1
MS-022
1998 May 15
66
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
If wave soldering cannot be avoided, for LQFP and
QFP packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
21 SOLDERING
21.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
21.2 Reflow soldering
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering techniques are suitable for all LQFP and
QFP packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
21.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
21.3 Wave soldering
Wave soldering is not recommended for LQFP and QFP
packages. This is because of the likelihood of solder
bridging due to closely-spaced leads and the possibility of
incomplete solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all LQFP and
QFP packages with a pitch (e) equal or less than
0.5 mm.
1998 May 15
67
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
22 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
23 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
24 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 May 15
68
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
NOTES
1998 May 15
69
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
NOTES
1998 May 15
70
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
NOTES
1998 May 15
71
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
655102/1200/04/pp72
Date of release: 1998 May 15
Document order number: 9397 750 03118
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PAL delay line for correcting PAL phase errors
Wired communications
Wireless communications
l
l
l
Real time status information output (RTCO)
Brightness Contrast Saturation (BCS) control on-chip
The YUV (CCIR-601) bus supports a data rate of:
Catalog by System
Automotive
Consumer Multimedia
Systems
– 864 ´ f = 13.5 MHz for 625 line sources
H
– 858 ´ f = 13.5 MHz for 525 line sources.
H
Communications
PC/PC-peripherals
l
Data output streams for 16, 12 or 8-bit width with the following formats:
– YUV 4 :1 :1 (12-bit)
– YUV 4 :2 :2 (16-bit)
Cross reference
– YUV 4 :2 :2 (CCIR-656) (8-bit)
– RGB (5, 6and 5) (16-bit) with dither
– RGB (8, 8and 8) (24-bit) with special application.
Models
Packages
l
l
l
l
l
l
Odd/even field identification by a non interlace CVBS input signal
Fix level for RGB output format during horizontal blanking
720 active samples per line on the YUV bus
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
One user programmable general purpose switch on an output pin
Built-in line-21 text slicer
A 27 MHz Vertical Blanking Interval (VBI) data bypass programmable by I PC-bus for INTERCAST applications
2
l
l
Power-on control
Two via I PC-bus switchable outputs for the digitized CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0)
2
Relevant Links
l
l
l
l
Chip enable function (reset for the clock generator and power save mode up from chip version 3)
Compatible with memory-based features (line-locked clock)
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Boundary scan test circuit complies with the ‘IEEE Std. 1149.1- 1990’ (ID-Code = 0 F111 02 B)
I PC-bus controlled (full read-back ability by an external controller)
2
l
l
Low power (<0.5 W), low voltage (3.3 V), small package (LQFP64)
5 V tolerant digital I/O ports.
SAA7111A
SAA7111A
Applications
l Desktop/Notebook (PCMCIA) video
l Multimedia
l Digital television
l Image processing
l Video phone
l Intercast.
Datasheet
File
size
(kB)
Publication
release date Datasheet status
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count
Type nr.
Title
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SAA7111A Enhanced Video Input Processor
(EVIP)
15-May-98
Product
Specification
72
441
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
Standard Marking * Tray Dry
Pack, Bakeable, Single
SAA7111AH/02
SAA7111AHBG-S
SAA7111AHBG
9352 327 00551
SOT393 Full production
SOT393 Full production
SOT393 Full production
SOT393 Full production
SOT393 Full production
SOT314 Full production
SOT314 Full production
SOT314 Full production
SOT314 Full production
SOT314 Full production
-
-
-
Standard Marking * Tray Dry
Pack, Bakeable, Multiple
9352 327 00557
9352 636 52557
9352 600 18551
9352 600 18557
9352 327 10518
9352 327 10551
9352 327 10557
9352 600 17551
9352 600 17557
Standard Marking * Tray Dry
Pack, Bakeable, Multiple
SAA7111AH/02/S5
SAA7111AH/03
Standard Marking * Tray Dry
Pack, Bakeable, Single
Standard Marking * Tray Dry
Pack, Bakeable, Multiple
Standard Marking * Reel Dry
Pack, SMD, 13"
SAA7111AHZ/02
SAA7111AHZ/03
-
-
-
Standard Marking * Tray Dry
Pack, Bakeable, Single
SAA7111AHZBD-S
SAA7111AHZBD
Standard Marking * Tray Dry
Pack, Bakeable, Multiple
Standard Marking * Tray Dry
Pack, Bakeable, Single
Standard Marking * Tray Dry
Pack, Bakeable, Multiple
Please read information about some discontinued variants of this product.
Find similar products:
SAA7111A links to the similar products page containing an overview of products that are similar in function or related to the part
number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides
and products from the same functional category.
Copyright © 2000
Royal Philips Electronics
All rights reserved.
Terms and conditions.
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