SAA7130HLBE_技术文档

INTEGRATED CIRCUITS

DATA SHEET

SAA7130HL

PCI video broadcast decoder

Product speciﬁcation

2002 Apr 23

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

CONTENTS

12

PACKAGE OUTLINE

SOLDERING

13

1

FEATURES

13.1

Introduction to soldering surface mount

packages

Reflow soldering

Wave soldering

Manual soldering

1.1

1.2

1.3

1.4

PCI and DMA bus mastering

TV video decoder and video scaling

Peripheral interface

13.2

13.3

13.4

13.5

General

2

GENERAL DESCRIPTION

Suitability of surface mount IC packages for

wave and reflow soldering methods

2.1

2.2

2.3

Introduction

Overview of TV decoders with PCI bridge

Related documents

• Data sheets of other devices referred to in this

document, e.g:

This document describes the functionality and

characteristics of the SAA7130HL.

– TDA8961: DTV channel decoder

– TD1316: ATV+DVB-T tuner

– TDA10045: DVB channel decoder

– TDA9886: Analog IF-PLL

– TDA9889: Digital IF-PLL.

Other documents related to the SAA7130HL are:

• User manual SAA7130HL/34HL, describing the

programmability

• Application note SAA7130HL/34HL, pointing out

recommendations for system implementation

• Demonstration and reference boards, including

description, schematics, etc.:

– Proteus-Pro: TV capture PCI card for analog TV

(standards: B/G, I, D/K and L/L’)

– Europa: hybrid DVB-T and analog TV capture PCI

card for European broadcasting.

3

QUICK REFERENCE DATA

SYMBOL

V_DD

PARAMETER

CONDITIONS

MIN.

3.0

TYP.

3.3

MAX.

3.6

UNIT

supply voltage

V

P_tot

total power dissipation

standby power dissipation

ambient temperature

−

0

1.0

−

W

°C

P_standby

T_amb

D3-hot of ACPI

0.02

70

25

4

ORDERING INFORMATION

PACKAGE

TYPE

NUMBER

NAME

DESCRIPTION

VERSION

SAA7130HL

LQFP128 plastic low proﬁle quad ﬂat package; 128 leads; body 14 × 20 × 1.4 mm

SOT425-1

2002 Apr 23

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Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

6

PINNING

SYMBOL

The SAA7130HL is packaged in a rectangular LQFP (low

proﬁle quad ﬂat package) with 128 pins (see Fig.3).

FRAME#

IRDY#

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

In Section 6.1 all the pins are sorted by number.

TRDY#

The pin description for the functional groups is given in

Tables 2 to 7:

DEVSEL#

STOP#

PERR#

SERR#

PAR

• Power supply pins

• PCI interface pins

• Analog interface pins

• Joint Test Action Group (JTAG) test interface pins for

boundary scan test

• I²C-bus multimaster interface

CBE#1

AD15

AD14

AD13

AD12

V_DDD

• General purpose interface (pins GPIO) and the main

functions.

The characteristics of the pin types are detailed in Table 8.

V_SSD

6.1

Pins sorted by number

SYMBOL

PCI_CLK

AD11

AD10

AD9

V_DDD

1

2

GNT#

REQ#

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

3

AD8

4

CBE#0

AD7

5

6

AD6

7

AD5

8

AD4

9

AD3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

AD2

AD1

CBE#3

IDSEL

AD23

AD22

AD21

AD20

AD19

V_DDD

AD0

V_DDD

V_SSD

GPIO23

GPIO22

GPIO21

GPIO20

GPIO19

GPIO18

XTALI

XTALO

V_SSD

AD18

AD17

AD16

CBE#2

V_DDD

2002 Apr 23

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Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

SYMBOL

V_CLK

GPIO17

GPIO16

GPIO15

GPIO14

GPIO13

GPIO12

V_DDD

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

V_REF3

V_SSA

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

CV2_C

V_DDA

V_REF4

DRCV_Y

V_SSA

CV0_Y

V_DDA

V_SSD

GPIO11

GPIO10

GPIO9

GPIO8

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

GPIO27

GPIO26

GPIO25

SCL

CV1_Y

DRCV_C

CV3_C

V_SSA

CV4

TRST

TCK

TMS

TDO

TDI

INT_A

PCI_RST#

V_SSD

SDA

V_DDD

V_SSD

LEFT2

V_DDA

LEFT1

V_SSA

RIGHT1

V_REF0

RIGHT2

V_REF1

V_REF2

OUT_RIGHT

OUT_LEFT

PROP_RST

SIF

2002 Apr 23

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Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

6.2

Table 2 Power supply pins

SYMBOL PIN

V_SSA

Pins grouped by function

TYPE

DESCRIPTION

97, 108, 113 AG

and 119

analog ground for integrated analog signal processing

V_DDA

V_SSD

95, 110

and 115

AS

analog supply voltage for integrated analog signal processing

digital ground for digital circuit, core and I/Os

20, 39, 55, VG

64, 74, 93

and 128

V_DDD

1, 19, 38, 54, VS

65, 73

digital supply voltage for digital circuit, core and I/Os

and 92

Table 3 PCI interface pins; note 1

SYMBOL

TYPE

PI

DESCRIPTION

PCI_CLK

40

PCI clock input: reference for all bus transactions, up to 33.33 MHz

PCI reset input: will 3-state all PCI pins (active LOW)

PCI_RST#

AD31 to AD0

127

4 to 11,

14 to 18,

21 to 23,

34 to 37,

41 to 44 and

46 to 53

PIO and multiplexed address and data input or output: bi-directional, 3-state

T/S

CBE3# to

CBE0#

12, 24, 33

and 45

PIO and command code input or output: indicates type of requested transaction and

T/S

PIO and parity input or output: driven by the data source, even parity over all pins AD

T/S and CBE#

PIO and frame input or output: driven by the current bus master (owner), to indicate

S/T/S the beginning and duration of a bus transaction (active LOW)

PIO and target ready input or output: driven by the addressed target, to indicate

S/T/S readiness for requested transaction (active LOW)

PIO and initiator ready input or output: driven by the initiator, to indicate readiness to

S/T/S continue transaction (active LOW)

PIO and stop input or output: target is requesting the master to stop the current

byte enable, for byte aligned transactions (active LOW)

PAR

32

25

27

26

29

13

28

3

FRAME#

TRDY#

IRDY#

STOP#

IDSEL

DEVSEL#

REQ#

S/T/S

transaction (active LOW)

PI

initialization device select input: this input is used to select the SAA7130HL

during conﬁguration read and write transactions

PIO and device select input or output: driven by the target device, to acknowledge

S/T/S

address decoding (active LOW)

PO

PCI request output: the SAA7130HL requests master access to PCI-bus

(active LOW)

GNT#

2

PI

PCI grant input: the SAA7130HL is granted to master access PCI-bus

(active LOW)

2002 Apr 23

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Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

SYMBOL

INT_A

TYPE

PO and interrupt A output: this pin is an open-drain interrupt output, conditions

O/D assigned by the interrupt register

PIO and parity error input or output: the receiving device detects data parity error

S/T/S (active LOW)

DESCRIPTION

126

PERR#

SERR#

30

31

PO and system error output: reports address parity error (active LOW)

O/D

Note

1. PCI-bus pins are located on the long side of the package to simplify PCI board layout requirements.

Table 4 Analog interface pins; note 1

SYMBOL

XTALI

TYPE

CI

DESCRIPTION

62

63

94

95

96

quartz oscillator input: 32.11 or 24.576 MHz

quartz oscillator output

XTALO

LEFT2

V_DDA

CO

AI

analog audio stereo left 2 input or mono input

analog supply voltage (3.3 V)

AS

AI

LEFT1

analog audio stereo left 1 input or mono input; default analog pass-through

to pin OUT_LEFT after reset

V_SSA

97

98

AG

AI

analog ground (for audio)

RIGHT1

analog audio stereo right 1 input or mono input; default analog pass-through

to pin OUT_RIGHT after reset

V_REF0

99

AR

analog reference ground for audio Sigma Delta ADC; to be connected

directly to analog ground (V_SSA

)

RIGHT2

n.c.

100

101

102

103

AI

−

analog audio stereo right 2 input or mono input

not connected

n.c.

−

not connected

OUT_RIGHT

AO

analog audio stereo right channel output; 1 V (RMS) line-out, feeding the

audio loop back cable via a coupling capacitor of 2.2 µF

OUT_LEFT

104

AO

analog audio stereo left channel output; 1 V (RMS) line-out, feeding the

audio loop back cable via a coupling capacitor of 2.2 µF

PROP_RST

n.c.

105

106

107

AO

−

analog output for test and debug purpose (active LOW)

not connected

V_REF3

AR

analog reference voltage for audio FIR-DAC and SCART audio input buffer;

to be supported with two parallel capacitors of 47 and 0.1 µF to analog

ground (V_SSA

)

V_SSA

108

109

110

111

112

AG

AI

analog ground

CV2_C

V_DDA

composite video input (mode 2) or C input (modes 6 and 8)

analog power supply (3.3 V)

AS

−

n.c.

not connected

DRCV_Y

AR

differential reference connection (for CV0 and CV1); to be supported with a

capacitor of 47 nF to analog ground (V_SSA

)

V_SSA

113

114

115

AG

AI

analog ground

CV0_Y

V_DDA

composite video input (mode 0) or Y input (modes 6 and 8)

analog supply voltage (3.3 V)

AS

2002 Apr 23

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Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

SYMBOL

CV1_Y

TYPE

AI

DESCRIPTION

116

117

composite video input (mode 1) or Y input (modes 7 and 9)

DRCV_C

AR

differential reference connection (for CV2, CV3 and CV4); to be supported

with a capacitor of 47 nF to analog ground (V_SSA

)

CV3_C

V_SSA

118

119

120

AI

composite video input (mode 3) or C input (modes 7 and 9)

analog ground

AG

AI

CV4

composite video input (mode 4)

Note

1. The SAA7130HL offers an interface for analog video and audio signals. The related analog supply pins are included

in this table.

Table 5 JTAG test interface pins

SYMBOL

TRST

TYPE

DESCRIPTION

121

122

123

124

125

I

test reset input: drive LOW for normal operating (active LOW)

test clock input: drive LOW for normal operating

TCK

TMS

TDO

TDI

test mode select input: tie HIGH or let ﬂoat for normal operating

test serial data output: 3-state

O

I

test serial data input: tie HIGH or let ﬂoat for normal operating

Table 6 I²C-bus multimaster interface

SYMBOL

SCL

TYPE

IO2

DESCRIPTION

90

91

serial clock output; always available

SDA

IO2

GO

serial data input and output; always available

propagate reset and D3-hot output; to peripheral board circuitry

PROP_RST

105

2002 Apr 23

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Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

Table 7 GPIO pins and functions; note 1

FUNCTION

SYMBOL

TYPE

AUDIO AND VIDEO

PORT OUTPUTS

TS CAPTURE

INPUTS

RAW DTV/DVB

OUTPUTS

GPIO

R/W

GPIO27

GPIO26

GPIO25

V_CLK

87

88

89

66

56

57

GIO

−

GIO

GO

R/W

−

V_CLK (also gated)

HSYNC

ADC_CLK (out)

GPIO23

GPIO22

GIO

ADC_C[0] (LSB) R/W, INT

VSYNC

TS_LOCK (channel

decoder locked)

−

R/W, INT

GPIO21

58

GIO

−

TS_S_D

−

R/W

(bit-serial data)

GPIO20

GPIO19

GPIO18

GPIO17

GPIO16

59

60

61

67

68

GIO

−

TS_CLK (<33 MHz)

−

R/W

−

TS_SOP (packet start)

−

R/W

VAUX2

−

X_CLK_IN

R/W, INT

VAUX1 (e.g. VACTIVE)

−

ADC_Y[0] (LSB) R/W

−

TS_VAL (valid ﬂag)

−

R/W, INT

GPIO15 to

GIOPIO8

69 to 72 GIO

and

75 to 78

VP[7:0] for formats:

ITU-R BT.656, VMI,

VIP (1.1, 2.0), etc.

−

ADC_Y[8:1]

R/W

GPIO7 to

GPIO0

79 to 86 GIO

VP extension for 16-bit

formats: ZV, VIP-2,

DMSD, etc.

TS_P_D[7:0]

(byte-parallel data)

ADC_C[8:1]

R/W

Note

1. The SAA7130HL offers a peripheral interface with General Purpose Input/Output (GPIO) pins. Dedicated functions

can be selected:

a) Digital Video Port (VP): output only; in 8-bit and 16-bit formats, such as VMI, DMSD (ITU-R BT.601); zoom-video,

with discrete sync signals; ITU-R BT.656; VIP (1.1 and 2.0), with sync encoded in SAV and EAV codes.

b) Transport Stream (TS) capture input: from the peripheral DTV/DVB channel decoder; synchronized by Start Of

Packet (SOP); in byte-parallel or bit-serial protocol.

c) Digitized raw DTV/DVB samples stream output: from internal ADCs; to feed the peripheral DTV/DVB channel

decoder.

d) GPIO: as default (no other function selected); static (no clock); read and write from or to individually selectable

pins; latching ‘strap’ information at system reset time.

e) Peripheral interrupt (INT) input: enabled by interrupt enable register; routed to PCI interrupt (INT_A).

2002 Apr 23

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Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

6.3

Pin description

Table 8 Characteristics of pin types and remarks

PIN TYPE

DESCRIPTION

AG

AI

analog ground

analog input; video, audio and sound

analog output

AO

AR

AS

CI

analog reference support pin

analog supply voltage (3.3 V)

CMOS input; 3.3 V level (not 5 V tolerant)

CMOS output; 3.3 V level (not 5 V tolerant)

digital input (GPIO); 3.3 V level (5 V tolerant)

digital input/output (GPIO); 3.3 V level (5 V tolerant)

digital output (GPIO); 3.3 V level (5 V tolerant)

JTAG test input

CO

GI

GIO

GO

I

IO2

O

digital input and output of the I²C-bus interface; 3.3 and 5 V compatible, auto-adapting

JTAG test output

O/D

open-drain output (for PCI-bus); multiple clients can drive LOW at the same time, wired-OR,

ﬂoating back to 3-state over several clock cycles

PI

input according to PCI-bus requirements

PIO

PO

input and output according to PCI-bus requirements

output according to PCI-bus requirements

S/T/S

sustained 3-state (for PCI-bus); previous owner drives HIGH for one clock cycle before leaving

to 3-state

T/S

VG

VS

3-state I/O (for PCI-bus); bi-directional

ground for digital supply

supply voltage (3.3 V)

With overscore or # this pin or ‘signal’ is active LOW, i.e. the function is ‘true’ if the logic level is LOW

2002 Apr 23

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Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

handbook, full pagewidth

V

n.c.

1

2

3

4

5

6

7

8

9

102

101

100

99

DDD

n.c.

GNT#

REQ#

AD31

AD30

AD29

AD28

AD27

AD26

RIGHT2

V

REF0

RIGHT1

98

V

97

SSA

96 LEFT1

V

95

94

93

92

DDA

LEFT2

V

AD25 10

AD24 11

CBE#3 12

IDSEL 13

AD23 14

AD22 15

AD21 16

AD20 17

AD19 18

SSD

V

DDD

91 SDA

SCL

90

89 GPIO25

88 GPIO26

87 GPIO27

86 GPIO0

85 GPIO1

84 GPIO2

83 GPIO3

82 GPIO4

81 GPIO5

80 GPIO6

79 GPIO7

V

19

20

DDD

SAA7130HL

V

SSD

AD18 21

AD17 22

AD16 23

CBE#2 24

FRAME# 25

IRDY# 26

TRDY# 27

DEVSEL# 28

STOP# 29

PERR# 30

SERR# 31

PAR 32

78

77

76

75

74

73

GPIO8

GPIO9

GPIO10

GPIO11

V

SSD

V

DDD

72 GPIO12

71 GPIO13

70 GPIO14

69 GPIO15

68 GPIO16

67 GPIO17

CBE#1 33

AD15 34

AD14 35

AD13 36

V_CLK

AD12 37

66

65

V

38

DDD

MHC168

Fig.3 Pin configuration.

15

2002 Apr 23

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

7

FUNCTIONAL DESCRIPTION

Overview of internal functions

7.1

The SAA7130HL is able to capture TV signals over the PCI-bus in personal computers by a single chip (see Fig.4).

GPIO

handbook, full pagewidth

5 analog

transport

reset stream input

video

inputs

digital video

output

stereo

output

stereo stereo

input 1 input 2

2

I C-bus

INPUT SELECTION

2

ANALOG AUDIO I/O

DTV-TS p/s

VIDEO PORT

(DIGITAL)

I C-BUS

INTERFACE

2

PASS-THROUGH (DEFAULT)

CLAMP AND GAIN

CONTROL

I S-BUS

INPUT

9-BIT ADC 9-BIT ADC

DECODER

(NTSC, PAL, SECAM)

PROPAGATE

RESET

LLC

ADAPTIVE

COMB FILTER

SAA7130HL

VIDEO SCALER

3-D

MATRIX

GAMMA

FORMAT

RAW VBI

PROGRAM PROGRAM

SET

VIDEO FIFOS

TS FIFOS

DMA CONTROL

BOUNDARY

SCAN TEST

OSCILLATOR

DMA CONTROL

ACPI POWER

MANAGEMENT

PCI-BUS INTERFACE

PCI-bus

MHC171

test

crystal

Fig.4 Functional block diagram.

16

2002 Apr 23

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

The SAA7130HL incorporates two 9-bit video ADCs and

the entire decoding circuitry of any analog TV signal:

NTSC, PAL and SECAM, including non-standard signals,

such as playback from a VCR. The adaptive multi-line

comb filter provides superb picture quality, component

separation, sharpness and high bandwidth. The video

stream can be cropped and scaled to the needs of the

application. Scaling down as well as zooming up is

supported in the horizontal and vertical direction, and an

adaptive filter algorithm prevents aliasing artifacts. With

the acquisition unit of the scaler two different ‘tasks’ can be

defined, e.g. to capture video to the CPU for compression,

and write video to the screen from the same video source

but with different resolution, colour format and frame rate.

7.2

Application examples

The SAA7130HL enables PC TV capture applications

both on the PC mother board and on PCI add-on

TV capture cards. Figures 5 and 6 illustrate some

examples of add-on card applications.

Figure 5 shows the basic application to capture video from

analog TV sources. The proposed tuner types incorporate

the RF tuning function and the IF downconversion. Usually

the IF downconversion stage also includes a single

channel and analog sound FM demodulator. The Philips

tuner FI1216MK2 is dedicated to the 50 Hz system

B/G standard as used in Europe. The FI1236MK2 is the

comparable type for the 60 Hz system M standard for the

USA. Both types are suited for terrestrial broadcast and for

cable reception. The tuner provides composite video and

baseband audio as mono or ‘multiplexed’ (mpx) in case of

BTSC. These analog video and sound signals are fed to

the appropriate input pins of the SAA7130HL.

The SAA7130HL incorporates analog audio pass-through

and support for the analog audio loop back cable to the

sound card function.

The decoded video streams are fed to the PCI-bus, and

are also applied to a peripheral streaming interface, in ITU,

VIP or VMI format. A possible application extension is

on-board hardware MPEG compression, or other feature

processing. The compressed data is fed back through the

peripheral interface, in parallel or serial format, to be

captured by the system memory through the PCI-bus. The

Transport Stream (TS) from a DTV/DVB channel decoder

can be captured through the peripheral interface in the

same way.

Further analog video input signals, CVBS and/or Y-C, can

be connected via the board back-panel, or the separate

front connectors, e.g. from a camcorder. Accompanying

stereo audio signals can also be fed to the SAA7130HL.

Video is digitized and decoded to YUV. The digital streams

are pumped via DMA into the PCI memory space.

The SAA7130HL incorporates means for legacy analog

audio signal routing. The analog audio input signal is fed

via an analog audio loop back cable into the line-in of a

legacy sound card. An external audio signal, that would

have otherwise connected directly to the sound card, is

now routed through the SAA7130HL. This analog

Video and transport streams are collected in a

configurable FIFO with a total capacity of 1 kbyte. The

DMA controller monitors the FIFO filling degree and

master-writes the audio and video stream to the

associated DMA channel. The virtual memory address

space (from OS) is translated into physical (bus)

addresses by the on-chip hardware Memory Management

Unit (MMU).

pass-through is enabled as default by a system reset, i.e.

without any driver involvement and before system set-up.

During the power-up procedure, the SAA7130HL will

investigate the on-board EEPROM to load the board

specific system vendor ID and board version ID into the

related places of the PCI configuration space. The board

vendor can store other board specific data in the EEPROM

that is accessible via the I²C-bus.

The application of the SAA7130HL is supported by

reference designs and a set of drivers for the Windows

operating system (Video for Windows and Windows Driver

Model compliant).

2002 Apr 23

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Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

handbook, full pagewidth

TV CAPTURE PCI CARD

TV cable

or

terrestrial

TV TUNER AND

IF-PLL

2

I C-bus

CVBS

AF sound

(mono)

analog

audio

loop back

cable

CVBS

S-video

audio

DECODER FOR

TV VIDEO

SOUND

CARD

line-in

DMA MASTER

INTO PCI

2

I C-BUS EEPROM

SYSTEM

VENDOR ID

SAA7130HL

PCI-bus:

digital video, raw VBI, TS

AGP

SOUTH

BRIDGE

NORTH

BRIDGE

VGA AND

LOCAL MEMORY

ISA

SYSTEM

MEMORY

CPU AND

CACHE MEMORY

FSB

MHC172

Fig.5 TV mono capture card.

2002 Apr 23

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Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

handbook, full pagewidth

HYBRID TV CAPTURE PCI CARD

ATV cable

or terrestrial

and

IF

DIGITAL

IF-PLL

TV TUNER

DVB terrestrial

IF

DVB-T

CHANNEL

DECODER

ANALOG IF-PLL

AF TS

CVBS

S-video

audio

analog audio

loop back

cable

DECODER FOR

TV VIDEO

SOUND

CARD

2

line-in

I C-bus

DMA MASTER

INTO PCI

2

I C-BUS EEPROM

SYSTEM

VENDOR ID

SAA7130HL

PCI-bus:

digital video, raw VBI, TS

AGP

SOUTH

BRIDGE

NORTH

BRIDGE

VGA AND

LOCAL MEMORY

ISA

SYSTEM

MEMORY

CPU AND

CACHE MEMORY

FSB

MHC173

Fig.6 Hybrid TV capture board for digital TV (DVB-T) and analog TV reception.

Figure 6 shows an application extension with a hybrid

TV tuner front-end and digital terrestrial channel decoding

for DTV-T.

The SAA7130HL captures this TS via the dedicated

peripheral interface into the configurable internal FIFO for

DMA into the PCI memory space.

The single-conversion tuner TD1316 provides two

dedicated IF signals for the analog IF-PLL (TDA9886) and

the digital IF-PLL (TDA9889). The CVBS (video) and AUD

(audio, mono) output signals of the analog IF-PLL can be

routed to one of the video inputs and the audio (left or right)

input of the SAA7130HL for analog video decoding and

direct audio streaming to the sound card. On the other

hand, the 2nd IF signal of the digital IF-PLL is fed directly

to the interface of the channel decoder (TDA10045), which

decodes the signal into a digital DVB-T Transport

Stream (TS).

The packet structure as decoded by the TDA10045 is

maintained in a well-defined buffer structure in the system

memory, and therefore can easily be sorted

(de-multiplexed) by the CPU for proper MPEG decoding.

The Broadcast Driver Architecture (BDA) for Windows

operating systems supports this type of hybrid TV capture

application, sharing one capture board for analog and

digital TV reception.

2002 Apr 23

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Philips Semiconductors

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PCI video broadcast decoder

SAA7130HL

7.3

Software support

7.3.1

DEVICE DRIVER

A complex and powerful software packet is provided for the SAA7130HL. This packet includes plug-and-play driver and

capture driver installations for all commonly used 32-bit Windows platforms.

All platform related drivers support the following:

• Video preview and capture interfaces

• Audio control and audio capture interfaces

• Custom application interface, that enables the development of specialized applications in cases where the published

Windows Application Program Interface (API) such as WDM or VfW is not sufficient.

Table 9 Microsoft Operation System (MOS) support

MOS

DRIVER SUPPORT

Windows 95

Device access is contained within a VxD. The Video for Windows (VfW) capture driver interface is a

16-bit user-mode interface.

Windows NT4

Windows 98

Device access is contained in a kernel-mode driver. The VfW capture driver interface is a 32-bit

user-mode interface.

Device access is contained with a kernel-mode Windows Driver Model (WDM) driver. The capture

driver interface is also kernel-mode WDM.

Windows 2000

Windows ME

Windows XP

The driver is binary-compatible with the Windows 98 driver.

7.3.2

SUPPORTING WDM

The WDM driver for Windows 98 and Windows 2000 (see Fig.7) is a kernel-mode driver that implements a Kernel

Streaming (KS) filter with output pins for audio, video preview, video capture and VBI, together with a crossbar for input

source selection and optional connections for other on-board devices as child drivers. The WDM driver is implemented

as a stream class mini-driver. It also exposes the external interfaces to support the user-mode 34API DLL. Custom

applications and debug tools will continue to work without the need to load different drivers.

handbook, full pagewidth

TV TUNER

XBAR

SAA7130HL

CAPTURE

DRIVER

video preview

video capture

VBI

external video inputs

audio inputs

transport stream in

MHC174

Fig.7 WDM capture driver filters.

20

2002 Apr 23

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

7.3.3

SUPPORTING VfW

• Capture transport streams (MPEG data) from a channel

decoder chip (OFDM, VSB, QAM) for supporting digital

TV applications, or from an on-board MPEG encoder

chip that is fed by the video output port of the

SAA7130HL

The traditional Video for Windows (VfW) interface is

supported for Windows 9x and for Windows NT4.0 (see

Fig.8). In both cases a 32-bit capture driver based on the

SAA713x user-mode API (34API.DLL) controls the video

functionality and the user-mode audio driver

implementation.

• Capture raw VBI sample stream to a stream of buffers

over the PCI-bus

• Access to the I²C-bus master for controlling other

peripheral circuits.

The capture driver supports direct draw surfaces for live

video and is able to capture video in packed data formats

and in planar formats. TV applications such as Intel

intercast and Philips teletext are supported by a private

VBI extension.

The 34API transfers the device driver functionality through

a proxy interface to the user-mode. The proxy interface

adapts to the different kernel-mode implementations, so

that the common 34API can be used on all Windows

operating systems in the same way.

In the event that VfW has to be implemented as a 16-bit

interface under Windows 9x, a thunk layer is included for

connecting the 16-bit interface to the 32-bit capture driver.

Old 16-bit applications using VfW are still supported in this

way.

The SDK for the SAA7130HL contains the detailed

description of all software components such as API

documentation for streaming, tuner control, dialogues and

direct draw control.

The provided sample code will introduce the user into

working with this interface.

All necessary header and library files are provided.

VidCap

VidCap32

(WIN 9x)

(WIN NT4.0)

34Vcap16.DLL

34Vcap32.EXE

34Vcap.DLL

34API.DLL

34Vcap32.DLL

34API.DLL

VBI extension for

intercast, CC, TXT

34W95.VxD

34WDM.SYS

34NT4.SYS

34W95.VxD

MHB995

MHB994

Fig.9 User program interface.

Fig.8 VfW driver structure.

7.3.4

SOFTWARE DEVELOPMENT KIT FOR CUSTOMER

RELATED APPLICATIONS

In addition to the capture driver, an Application

Programmers Interface (API) Dynamic Linked Library

(DLL) provides the whole range of functionality to control

the device (see Fig.9). This class library is built in c++ and

provides methods to:

• Capture video into a fixed buffer (including clipping)

• Capture video to a stream of buffers over VBI

2002 Apr 23

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Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

7.4

PCI interface

7.4.2

ACPI AND POWER STATES

7.4.1

PCI CONFIGURATION REGISTERS

The “PCI specification 2.2” requires support of “Advanced

Configuration and Power Interface specification 1.0”

(ACPI); more details are defined in the “PCI Power

Management Specification 1.0”.

The PCI interface of the SAA7130HL complies with the

“PCI specification 2.2” and supports power management

and Advanced Configuration and Power Interface (ACPI)

as required by the “PC Design Guide 2001”.

The power management capabilities and power states are

reported in the extended configuration space. The main

purpose of ACPI and PCI power management is to tailor

the power consumption of the device to the actual needs.

The PCI specification defines a structure of the PCI

configuration space that is investigated during the boot-up

of the system. The configuration registers (see Table 10)

hold information essential for plug-and-play, to allow

system enumeration and basic device set-up without

depending on the device driver, and support association of

the proper software driver. Some of the configuration

information is hard-wired in the device; some information

is loaded during the system start-up.

The SAA7130HL supports all four ACPI device power

states (see Table 11).

The pin PROP_RST of the peripheral interface is switched

active LOW during the PCI reset procedure, and for the

duration of the D3-hot state. Peripheral devices on board

of the add-on card should use the level of this

The device vendor ID is hard coded to 11 31H, which is the

code for Philips as registered with PCI-SIG.

signal PROP_RST to switch themselves in any

power-save mode (e.g. disable device) and reset to default

settings on the rising edge of signal PROP_RST. The

length of signal PROP_RST is programmable.

The device ID is hard coded to 71 30H.

During power-up, initiated by PCI reset, the SAA7130HL

fetches additional system information via the I²C-bus from

the on-board EEPROM, to load actual board type specific

codes for the system vendor ID, sub-system ID (board

version) and ACPI related parameters into the

configuration registers.

Table 10 PCI conﬁguration registers

REGISTER ADDRESS

VALUE

REMARK

(HEX)

FUNCTION

(HEX)

Device vendor ID

Device ID

00 and 01

02 and 03

08

11 31

71 30

00

for Philips

for SAA7130HL

or higher

Revision ID

Class code

09 to 0B

10 to 13

04 80 00

multimedia

Memory address space

required

XXXXXXXX XXXXXXXX

XXXXXX00 00000000 (b)

1 kbyte; note 1

System (board) vendor ID

2C and 2D

2E and 2F

loaded from EEPROM

Sub-system (board version) ID

Note

1. X = don’t care.

2002 Apr 23

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Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

Table 11 Power management table

POWER STATE

DESCRIPTION

D0

D1

Normal operation: all functions accessible and programmable. The default setting after reset and

before driver interaction (D0 un-initialized) switches most of the circuitry of the SAA7130HL into

the power-down mode, effectively such as D3-hot.

First step of reduced power consumption: no functional operation; program registers are not

accessible, but content is maintained. Most of the circuitry of the SAA7130HL is disabled with

exception of the crystal and real-time clock oscillators, so that a quick recovery from D1 to D0 is

possible.

D2

Second step of reduced power consumption: no functional operation; program registers are not

accessible, but content is maintained. All functional circuitry of the SAA7130HL is disabled,

including the crystal and clock oscillators.

D3-hot

Lowest power consumption: no functional operation. The content of the programming registers

gets lost and is set to default values when returning to D0.

7.4.3

DMA AND CONFIGURABLE FIFO

The association between the virtual (logic) address space

and the fragmented physical address space is defined in

page tables (system files); see Fig.10.

The SAA7130HL supports seven DMA channels to

master-write captured active video, raw VBI and DTV/DVB

Transport Streams (TS) into the PCI memory. Each DMA

channel contains inherently the definition of two buffers,

e.g. for odd and even fields in case of interlaced video.

The SAA7130HL incorporates hardware support (MMU) to

translate virtual to physical addresses on the fly, by

investigating the related page table information. This

hardware support reduces the demand for real-time

software interaction and interrupt requests, and therefore

saves system resources.

The DMA channels share in time and space one common

FIFO pool of 256 Dwords (1024 bytes) total. It is freely

configurable how much FIFO capacity can be associated

with which DMA channel. Furthermore, a preferred

minimum burst length can be programmed, i.e. the amount

of data to be collected before the request for the PCI-bus

is issued. This means that latency behaviour per DMA

channel can be tailored and optimized for a given

application.

7.4.5

STATUS AND INTERRUPTS ON PCI-BUS

The SAA7130HL provides a set of status information

about internal signal processing, video standard detection,

peripheral inputs and outputs (pins GPIO) and behaviour

on the PCI-bus. This status information can be

conditionally enabled to raise an interrupt on the PCI-bus,

e.g. completion of a certain DMA channel or buffer, or

change in a detected TV standard, or the state of

peripheral devices.

In the event that a FIFO of a certain channel overflows due

to latency conflict on the bus, graceful overflow recovery is

applied. The mount of data that gets lost because it could

not be transmitted, is monitored (counted) and the PCI-bus

address pointer is incremented accordingly. Thus new

data will be written to the correct memory place, after the

latency conflict is resolved.

The cause of an issued interrupt is reported in a dedicated

register, even if the original condition has changed before

the system was able to investigate the interrupt.

7.4.4

VIRTUAL AND PHYSICAL ADDRESSING

Most operating systems allocate memory to requesting

applications for DMA as continuous ranges in virtual

address space. The data flow over the PCI-bus points to

physical addresses, usually not continuous and split in

pages of 4 kbytes (Intel architecture, most UNIX systems,

Power PC).

2002 Apr 23

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Philips Semiconductors

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SAA7130HL

physical memory

real-time streams

handbook, full pagewidth

00000H

FIFO

POOL

00007H

DMA

ADDRESS

GENERATION

DMA DEFINITIONS

(VIRTUAL ADDRESS SPACE)

page table

000H

00001000H

00008000H

00009000H

0000A000H

0000D000H

00011000H

00014000H

00016000H

0001E000H

0000FH

VIRTUAL

TO

PHYSICAL

ADDRESS

TRANSLATION

007H

00017H

PCI

TRANSFER AND

CONTROL

015H

0001FH

physical address space on PCI

MHB996

= allocated memory space

= page table

Fig.10 MMU implementation (shown bit width indication is valid for 4 kbytes mode).

2002 Apr 23

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Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

7.5

Analog TV standards

Video signals from local consumer equipment, e.g. VCR,

camcorder, camera, game console, or even DVD player,

often do not follow the standard specification very

accurately.

Analog TV signals are described in three categories of

standards:

• Basic TV systems: defining frame rate, number of lines

per field, levels of synchronization signals, blanking,

black and white, signal bandwidth and the

RF modulation scheme

Playback from video tape cannot be expected to maintain

correct timing, especially not during feature mode (fast

forward, etc.).

Tables 12 to 14 list some characteristics of the various

TV standards.

• Colour transmission: defining colour coding and

modulation method

• Sound and stereo: defining coding for transmission.

The SAA7130HL decodes all colour TV standards and

non-standard signals as generated by video tape

recorders e.g. automatic video standard detection can be

applied, with preference options for certain standards, or

the decoder can be forced to a dedicated standard.

TV signals that are broadcasted usually conform fairly

accurately to the standards. Transmission over the air or

through a cable can distort the signal with noise, echoes,

crosstalk or other disturbances.

Table 12 Overview of basic TV standards

STANDARD

MAIN

PARAMETERS

UNIT

M

N

B

G, H

I

D/K

L

RF channel width

Video bandwidth

1st sound carrier

Field rate

6

4.2

6

4.2

7

5

7

5

8

5.5

7

6

8

6

MHz

Hz

−

4.5, FM

59.94006

525

4.5, FM

50

5.5, FM

50

5.5, FM

50

6.0, FM

50

6.5, FM

50

6.5, AM

50

Lines per frame

Line frequency

ITU clocks per line

Sync, set-up level

Gamma correction

625

15.734

1716

15.625

1728

−40, 7.5

2.2

15.625

1728

−43, 0

2.8

15.625

1728

−43, 0

2.8

15.625

1728

−43, 0

2.8

15.625

1728

−43, 0

2.8

15.625

1728

−43, 0

2.8

kHz

−

−40, 7.5

2.2

IRE

−

Associated colour NTSC, PAL

TV standards

PAL

SECAM,

PAL

SECAM

−

Associated stereo

TV sound systems EIAJ, A2

BTSC,

BTSC

dual FM,

A2

NICAM

Spain,

Malaysia, Northern

Europe

NICAM

UK,

NICAM,

A2

NICAM

−

Country examples

USA,

Japan,

Brazil

Argentina

part of

Europe,

Australia Singapore

China,

Eastern

Europe

France,

Eastern

Europe

2002 Apr 23

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Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

Table 13 TV system colour standards

MAIN

PARAMETERS

PAL

BGHID

SECAM

LDGHK

PAL 4.4

UNIT

NTSC M

PAL M

PAL N

(60 Hz)

Field rate

59.94

525

59.94

525

50

≈60

525

Hz

Lines per frame

625

Chrominance

subcarrier

3.580

3.576

3.582

4.434

4.406

4.250

4.434

MHz

f

_scto H ratio

227.5

−

227.25

−

229.25

50

283.75

50

282

−

272

−

n.a.

yes

f_scoffset (PAL)

Hz

Alternating phase

Country examples

no

yes

−

USA,

Japan,

Asia-Paciﬁc

Brazil

Middle

and South Common-

America

Europe,

France,

VCR

Eastern Europe,

Africa, Middle East

transcoding

NTSC-tape

to PAL

wealth,

China

Table 14 TV stereo sound standards

ANALOG SYSTEMS

EIAJ

DIGITAL CODING

NICAM

MAIN

PARAMETERS

UNIT

MONO

BTSC

A2 (DUAL FM)

Stereo coding

scheme

−

internal carrier (mpx)

AM FM

mono SAP on asalternative

2-Carrier Systems (2CS)

2nd FM carrier

DQPSK on FM

2nd language

−

as alternative to

stereo

mono on 1st carrier

internal FM

to stereo

Sound IF

M, N

1st

4.5

5.5

2nd

1st

2nd

4.5 FM

5.5 FM

6.0 FM

6.5 FM

6.5 AM

75

4.5

not used

−

4.5

not used

−

4.724

5.742

not used not used

MHz

µs

B, G, H

I

5.5

6.0

6.5

−

5.850

6.552

5.850

−

not used not used

DK (1)

6.5

−

6.742

6.258

5.742

DK (2)

DK (3)

−

L

not used

75, dBx

15

not used

50

not used not used

6.5

5.850

De-emphasis

Audio bandwidth

50 or 75

15

50 or J17

15

kHz

Country examples world-

wide

USA, South

America

Japan

part of Europe, Korea part of Europe, China

2002 Apr 23

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Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

7.6

Video processing

The video decoder of the SAA7130HL incorporates an

automatic standard detection, that does not only

distinguish between 50 and 60 Hz systems, but also

determines the colour standard of the video input signal.

Various preferences (‘look first’) for automatic standard

detection can be chosen, or a selected standard can be

forced directly.

7.6.1

ANALOG VIDEO INPUTS

The SAA7130HL provides five analog video input pins:

• Composite video signals (CVBS), from tuner or external

source

• S-video signals (pairs of Y-C), e.g. from camcorder

• DTV/DVB ‘low-IF’ signal, from an appropriate DTV or

7.6.4

ADAPTIVE COMB FILTER

combi-tuner.

The SAA7130HL applies adaptive comb filter techniques

to improve the separation of luminance and chrominance

components in comparison to the separation by a chroma

notch filter, as used in traditional TV colour decoder

technology. The comb filter compares the signals of

neighbouring lines, taking into account the phase shift of

the chroma subcarrier from line to line. For NTSC the

signal from three adjacent lines are investigated, and in the

event of PAL the comb filter taps are spread over four

lines.

Analog anti-alias filters are integrated on chip and

therefore, no external filters are required. The device also

contains automatic clamp and gain control for the video

input signals, to ensure optimum utilization of the ADC

conversion range. The nominal video signal amplitude is

1 V (p-p) and the gain control can adapt deviating signal

levels in the range of +3 dB to −6 dB. The video inputs are

digitized by two ADCs of 9-bit resolution, with a sampling

rate of nominal 27 MHz (the line-locked clock) for analog

video signals.

Comb filtering achieves higher luminance bandwidth,

resulting in sharper picture and detailed resolution. Comb

filtering further minimizes colour crosstalk artifacts, which

would otherwise produce erroneous colours on detailed

luminance structures.

7.6.2

VIDEO SYNCHRONIZATION AND LINE-LOCKED CLOCK

The SAA7130HL recovers horizontal and vertical

synchronization signals from the selected video input

signal, even under extremely adverse conditions and

signal distortions. Such distortions are ‘noise’, static or

dynamic echoes from broadcast over air, crosstalk from

neighbouring channels or power lines (hum), cable

reflections, time base errors from video tape play-back and

non-standard signal levels from consumer type video

equipment (e.g. cameras, DVD).

The comb filter as implemented in the SAA7130HL is

adaptive in two ways:

• Adaptive to transitions in the picture content

• Adaptive to non-standard signals (e.g. VCR).

The integrated digital delay lines are always exactly

correct, due to the applied unique line-locked sampling

scheme (LLC). Therefore the comb filter does not need to

be switched off for non-standard signals and remains

operating continuously.

The heart of this TV synchronization system is the

generation of the Line-Locked Clock (LLC) of nominal

27 MHz, as defined by ITU-R BT.601. The LLC ensures

orthogonal sampling, and always provides a regular

pattern of synchronization signals, that is a fixed and well

defined number of clock pulses per line. This is important

for further video processing devices connected to the

peripheral video port (pins GPIO). It is very effective to run

under the LLC of 27 MHz, especially for on-board

hardware MPEG encoding devices, since MPEG is

defined on this clock and sampling frequency.

7.6.5

MACROVISION DETECTION

The SAA7130HL detects if the decoded video signal is

copy protected by the Macrovision system. The detection

logic distinguishes the three levels of the copy protection

as defined in rev. 7.01, and are reported as status

information. The decoded video stream is not effected

directly, but application software and Operation System

(OS) has to ensure, that this video stream maintains

tagged as ‘copy protected’, and such video signal would

leave the system only with the reinforced copy protection.

The multi-level Macrovision detection on the video capture

side supports proper TV re-encoding on the output point,

e.g. by Philips TV encoders SAA712x or SAA7102.

7.6.3

VIDEO DECODING AND AUTOMATIC STANDARD

DETECTION

The SAA7130HL incorporates colour decoding for any

analog TV signal. All colour TV standards and flavours of

NTSC, PAL, SECAM and non-standard signals (VCR) are

automatically recognized and decoded into luminance and

chrominance components, i.e. Y-C_B-C_R, also known as

YUV.

2002 Apr 23

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Philips Semiconductors

Product speciﬁcation

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SAA7130HL

7.6.6

VIDEO SCALING

The scaling acquisition definition also includes cropping,

frame rate reduction, and defines the amount of pixels and

lines to be transported through DMA over the PCI-bus.

The SAA7130HL incorporates a filter and processing unit

to downscale or upscale the video picture in the horizontal

and vertical dimension, and in frame rate

(see Figs 11 and 12). The phase accuracy of the

re-sampling process is ¹⁄₆₄of the original sample distance.

This is equivalent to a clock jitter of less than 1 ns. The

filter depth of the anti-alias filter adapts to the scaling ratio,

from 10 taps horizontally for scaling ratios close to 1 : 1, to

up to 74 taps for an icon sized video picture.

Two programming pages are available to enable

re-programming of the scaler in the ‘shadow’ of the running

processing, without holding or disturbing the flow of the

video stream. Alternatively, the two programming pages

can be applied to support two video destinations or

applications with different scaler settings, e.g. firstly to

capture video to CPU for compression (storage, video

phone), and secondly to pre-view the picture on the

monitor screen. A separate scaling region is dedicated to

capture raw VBI samples, with a specific sampling rate,

and be written into its own DMA channel.

Most video capture applications will typically require for

downscaling. But some zooming is required for conversion

of ITU sampling to square pixel (SQP), or to convert the

240 lines of an NTSC field to 288 lines to comply with

CCITT video phone formats.

handbook, full pagewidth

VBI first sample

VBI last sample

1st field (odd, FID = 0)

sample rate

VBI DMA

VBI first line

VBI last line

1st buffer (A)

VBI region, raw samples

2nd buffer (A)

video region

- cropped

- scaled

scaling

active video area

2nd field (even, FID = 1)

video DMA (A)

e.g. interlaced

sample rate

VBI region, raw samples

1st buffer (upper field)

2nd buffer (lower field)

video first line

video last line

video region

- cropped

- scaled

scaling

active video area

video first pixel

MHB997

video last pixel

The capture acquisition for scaling and DMA has separate programming

parameters for VBI and video region and associated DMA channels.

Fig.11 Scaler processing with DMA interfacing.

2002 Apr 23

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Philips Semiconductors

Product speciﬁcation

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SAA7130HL

handbook, full pagewidth

1st field (odd, FID = 0)

VBI DMA

VBI region, raw samples

sample rate

1st buffer (A)

video region (A) - cropped

scaling

2nd buffer (A)

3rd buffer (B)

4th buffer (B)

active video area

2nd field (even, FID = 1)

VBI region, raw samples

sample rate

video DMA (A)

video region (A) - cropped

scaling

e.g. interlaced

1st buffer (upper field)

2nd buffer (lower field)

active video area

3rd field (odd, FID = 0)

VBI region, raw samples

sample rate

video region (B)

- skipped for field rate reduction

video DMA (B)

e.g. single FID

1st buffer

active video area

4th field (even, FID = 1)

VBI region, raw samples

sample rate

2nd buffer

(next frame)

video region - scaled down CIF

scaling

MHB998

active video area

alternating processing task A/B

Two video capture tasks can be processed in an alternating manner, without

need to reprogram any scaling parameters or DMA definition.

Fig.12 Scaler task processing with DMA interfacing.

2002 Apr 23

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Philips Semiconductors

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SAA7130HL

7.6.7

VBI DATA

The video components do not use the entire number

range, but leave some margin for overshoots and

intermediate values during processing. For the raw VBI

samples there is no official specification how to code, but

it is common practice to reserve the lower quarter of the

number range for the sync, and to leave some room for

overmodulation beyond the nominal white amplitude (see

Fig.14).

The Vertical Blanking Interval (VBI) is often utilized to

transport data over analog video broadcast. Such data can

closely relate to the actual video stream, or just be general

data (e.g. news). Some examples for VBI data types are:

• Closed Caption (CC) for the hearing impaired (CC, on

line 21 of first field)

• Intercast data [in US coded in North-American

Broadcast Text System (NABTS) format, in Europe in

World Standard Teletext (WST)], to transmit internet

related services, optionally associated with actual video

program content

The automatic clamp and gain control at the video input,

together with the automatic chroma gain control of the

SAA7130HL, ensures that the video components stream

at the output comply to the standard levels. Beyond that

additional brightness, contrast, saturation and hue control

can be applied to satisfy special needs of a given

application. The raw VBI samples can be adjusted

independent of the active video.

• Teletext, transporting news services and broadcast

related information, Electronic Program Guide (EPG),

widely used in Europe (coded in WST format)

• EPG, broadcaster specific program and schedule

information, sometimes with proprietary coding scheme

(pay service), usually carried on NABTS, WST, Video

Programming Service (VPS), or proprietary data coding

format

The SAA7130HL incorporates the YUV-to-RGB matrix

(optional), the RGB-to-YUV matrix and a three channel

look-up table in between (see Fig.15). Under nominal

settings, the RGB space will use the same number range

as defined by the ITU and shown in Fig.13a for luminance,

between 16 and 235. As graphic related applications are

based on full-scale RGB, i.e. 0 to 255, the range can be

stretched by applying appropriate brightness, contrast and

saturation values. The look-up table supports gamma

correction (freely definable), and allows other non-linear

signal transformation such as black stretching.

• Video Time Codes (VTC) as inserted in camcorders

e.g. use for video editing

• Copy Guard Management System (CGMS) codes, to

indicate copy protected video material, sometimes

combined with format information [Wide Screen

Signalling (WSS)].

The analog TV signal applies a quite strong gamma

pre-compensation (2.2 for NTSC and 2.8 for PAL).

As computer monitors exhibit a gamma (around 2.5), the

difference between gamma pre-compensation and actual

screen gamma has to be corrected, to achieve best

contrast and colour impression.

This information is coded in the unused lines of the vertical

blanking interval, between the vertical sync pulse and the

active visible video picture. So-called full-field data

transmission is also possible, utilizing all video lines for

data coding.

The SAA7130HL supports capture of VBI data by the

definition of a VBI region to be captured as raw VBI

samples, that will be sliced and decoded by software on

the host CPU. The raw sample stream is taken directly

from the ADC and is not processed or filtered by the video

decoder. The sampling rate of raw VBI can be adjusted to

the needs of the data slicing software.

The SAA7130HL offers a multitude of formats to write

video streams over the PCI-bus: YUV and RGB colour

space, 15-bit, 16-bit, 24-bit and 32-bit representation,

packed and planar formats. For legacy requirements

(VfW) a clipping procedure is implemented, that allows the

definition of 8 overlay rectangles. This process can

alternatively be used to associate ‘alpha’ values to the

video pixels.

7.6.8

SIGNAL LEVELS AND COLOUR SPACE

Analog TV video signals are decoded into its components

luminance and colour difference signals (YUV) or in its

digital form Y-C_B-C_R. ITU-R BT.601 defines 720 pixels

along the line (corresponding to a sampling rate of 27 MHz

divided by two), and a certain relationship from level to

number range (see Fig.13).

2002 Apr 23

30

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

+255

+235

+255

+240

+255

+240

blue 100%

blue 75%

red 100%

white

red 75%

+212

colourless

LUMINANCE 100%

+128

U-COMPONENT

V-COMPONENT

yellow 75%

cyan 75%

+44

+16

0

+44

+16

0

yellow 100%

cyan 100%

black

+16

0

MGC634

a. Y output range.

b. U output range (C_B).

c. V output range (C_R).

Fig.13 Nominal digital levels for YUV (Y-C_B-C_R) in accordance with ITU-R BT.601.

+255

+209

+255

+199

white

LUMINANCE

black

black shoulder

+71

+60

black shoulder = black

+60

SYNC

1

sync bottom

MGD700

a. Sources containing 7.5 IRE black

level offset (e.g. NTSC M).

b. Sources not containing black

level offset.

Fig.14 Nominal digital levels for CVBS and raw VBI samples.

31

2002 Apr 23

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

handbook, full pagewidth

three channel non-linear transformation

Y

U

V

R

G

B

R

G

B

Y

U

V

YUV

to

RGB

to

RGB

matrix

YUV

matrix

MHB999

Fig.15 Colour space conversion and look-up table.

7.6.9

VIDEO PORT, ITU AND VIP CODES

• ITU-R BT.601 direct (DMSD): 16-bit wide pixel stream,

clocked by LLC = 27 MHz, with discrete sync signals

HSYNC, VSYNC/FID and CREF

The decoded and/or scaled video stream can be captured

via PCI-DMA to the system memory, and/or can be made

available locally through the video side port (VP), using

some of the GPIO pins. Two types of applications are

intended:

• Raw DTV/DVB sample stream: 9-bit wide data, clocked

with a copy of signal X_CLK_IN.

The VIP standard can transport scaled video and

• Streaming real-time video to a video side port at the

VGA card, e.g. via ribbon cable over the top

discontinuous data stream by allowing the insertion of ‘00’

as marker for empty clock cycles. For the other video port

standards, a data valid flag or gated clock can be applied.

• Feeding video stream to a local MPEG compression

device on the same PCI board, e.g. for time shift viewing

applications.

7.7

Analog audio pass-through and loop back

cable

The video port of the SAA7130HL supports the following

8 and 16-bit wide YUV video signalling standards

(see Table 7):

Most operating systems are prepared to deal with audio

input at only one single entry point, namely at the sound

card function. Therefore the sound associated with video

has to get routed through the sound card.

• VMI: 8-bit wide data stream, clocked by LLC = 27 MHz,

with discrete sync signals HSYNC, VSYNC and

VACTIVE

The SAA7130HL supports analog audio pass-through and

the loop back cable on-chip. No external components are

required. The audio signal, that was otherwise connected

to the sound card line-in, e.g. analog sound from a

CD-ROM drive, has to be connected to one of the inputs of

the SAA7130HL. By default, after a system reset and

without involvement of any driver, this audio signal is

passed through to the analog audio output pins, that will

feed the loop back cable to the sound card line-in

• ITU-R BT.656, parallel: 8-bit wide data stream, clocked

by LLC = 27 MHz, synchronization coded in SAV and

EAV codes

• VIP 1.1 and 2.0: 8-bit or 16-bit wide data stream,

clocked by LLC = 27 MHz, synchronization coded in

SAV and EAV codes (with VIP extensions)

• Zoom Video (ZV): 16-bit wide pixel stream, clocked by

LLC/2 = 13.5 MHz, with discrete sync signals HSYNC

and VSYNC

connector. The AV capture driver has to open the default

pass-through and switch in the TV sound signal by will.

2002 Apr 23

32

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

7.8

DTV/DVB channel decoding and TS capture

7.9.2

PROPAGATE RESET

The SAA7130HL is optimum equipped to support the

application extension to capture digital TV signals, e.g. for

VSB (ATSC) or DVB (T/C/S). A hybrid TV tuner for analog

and digital TV broadcast reception usually provides a DTV

signal on low IF, i.e. downconverted into a frequency

range from 0 to 10 MHz. Such signals can be fed to one of

the 5 video inputs of the SAA7130HL for digitizing. The

digital raw DTV is output at the video port, and is sent to

the peripheral channel decoder, e.g. TDA8961 for VSB-8

decoding. The channel decoder provides the sampling

clock via the external clock input pin X_CLK_IN (up to

36 MHz input clock frequency), and adjusts the signal gain

in the tuner or in the video input path in front of the ADC.

Alternatively, the low IF DTV/DVB signal could be fed

directly to the channel decoder, depending on the

capability for digitizing the selected device.

The PCI system reset and ACPI power management

state D3 is propagated to peripheral devices by the

dedicated pin PROP_RST. This signal is switched to

active LOW by reset and D3, and is only switched HIGH

under control of the device driver ‘by will’. The intention is

that peripheral devices will use signal PROP_RST as

Chip-Enable (CE). The peripheral devices should enter a

low power consumption state if pin PROP_RST = LOW,

and reset into default setting at the rising edge.

7.9.3

GPIO

The SAA7130HL offers a set of General Purpose

Input/Output (GPIO) pins, to interface to on-board

peripheral circuits. These GPIOs are intended to take over

dedicated functions:

• Digital video port output: 8-bit or 16-bit wide (including

The peripheral channel decoder circuitry decodes the

digital transmission into bits and bytes, apply error

correction etc., and outputs a packed Transport Stream

(TS) accompanied by a clock and handshake signals. The

SAA7130HL captures the TS in parallel or serial protocol,

synchronized by Start Of Packet (SOP), and pumps it via

the dedicated DMA into the PCI memory space. The DMA

definition supports automatic toggling between two

buffers.

raw DTV)

• Transport stream input: parallel or serial (also applicable

as I²S-bus input)

• Peripheral interrupt input: four GPIO pins of the

SAA7130HL can be enabled to raise an interrupt on the

PCI-bus. By this means, peripheral devices can directly

intercept with the device driver on changed status or

error conditions.

Any GPIO pin that is not used for a dedicated function is

available for direct read and write access via the PCI-bus.

Any GPIO pin can be selected individually as input or

output (masked write). By these means, very tailored

interfacing to peripheral devices can be created via the

SAA7130HL capture driver running on Windows operating

systems.

7.9

Control of peripheral devices

7.9.1

I²C-BUS MASTER

The SAA7130HL incorporates an I²C-bus master to set-up

and control peripheral devices such as tuner, DTV/DVB

channel decoder, audio DSP co-processors, etc. The

I²C-bus interface itself is controlled from the PCI-bus on a

command level, reading and writing byte by byte. The

actual I²C-bus status is reported (status register) and, as

an option, can raise error interrupts on the PCI-bus.

At system reset (PCI reset) all GPIO pins will be set to

3-state and input, and the logic level present on the GPIO

pins at that moment will be saved into a special ‘strap’

register. All GPIO pins have an internal pull-down resistor

(LOW level), but can be strapped externally with a 4.7 kΩ

resistor to the supply voltage (HIGH level). The device

driver can investigate the strap register for information

about the hardware configuration of a given board.

At PCI reset time, the I²C-bus master receives board

specific information from the on-board EEPROM to update

the PCI configuration registers.

The I²C-bus interface is multi-master capable and can

assume slave operation too. This allows application of the

device in the stand-alone mode, i.e. with the PCI-bus not

connected. Under the slave mode, all internal

programming registers can be reached via the I²C-bus

with exception of the PCI configuration space.

2002 Apr 23

33

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

8

BOUNDARY SCAN TEST

To solve the power-up reset, the standard specifies that

the TAP controller will be forced asynchronously to the

TEST_LOGIC_RESET state by setting pin TRST to LOW

level.

The SAA7130HL has built-in logic and five dedicated pins

to support boundary scan testing which allows board

testing without special hardware (nails). The SAA7130HL

follows the “IEEE Std. 1149.1 - Standard Test Access Port

and Boundary - Scan Architecture” set by the Joint Test

Action Group (JTAG) chaired by Philips.

8.2

Device identiﬁcation codes

When the IDCODE instruction is loaded into the BST

instruction register, the identification register will be

connected internally between pins TDI and TDO of the IC.

The identification register will load a component specific

code during the CAPTURE_DATA_REGISTER state of

the TAP controller and this code can subsequently be

shifted out. At board level, this code can be used to verify

component manufacturer, type and version number. The

device identification register contains 32 bits, numbered

31 to 0, where bit 31 is the most significant bit (nearest to

TDI) and bit 0 is the least significant bit (nearest to TDO)

(see Fig.16).

The 5 special pins are: Test Mode Select (TMS), Test

Clock (TCK), Test Reset (TRST), Test Data Input (TDI)

and Test Data Output (TDO).

The Boundary Scan Test (BST) functions BYPASS,

EXTEST, SAMPLE, CLAMP and IDCODE are all

supported (see Table 15). Details about the JTAG

BST-test can be found in the specification “IEEE Std.

1149.1”. A file containing the detailed Boundary Scan

Description Language (BSDL) description of the

SAA7130HL is available on request.

A device identification register is specified in “IEEE Std.

1149.1b-1994”. It is a 32-bit register which contains fields

for the specification of the IC manufacturer, the IC part

number and the IC version number. Its biggest advantage

is the possibility to check for the correct ICs mounted after

production and determination of the version number of ICs

during field service.

8.1

Initialization of boundary scan circuit

The Test Access Port (TAP) controller of an IC should be

in the reset state (TEST_LOGIC_RESET) when the IC is

in the functional mode. This reset state also forces the

instruction register into a functional instruction such as

IDCODE or BYPASS.

Table 15 BST instructions supported by the SAA7130HL

INSTRUCTION

DESCRIPTION

BYPASS

This mandatory instruction provides a minimum length serial path (1 bit) between pins TDI and TDO

when no test operation of the component is required.

EXTEST

SAMPLE

This mandatory instruction allows testing of off-chip circuitry and board level interconnections.

This mandatory instruction can be used to take a sample of the inputs during normal operation of

the component. It can also be used to preload data values into the latched outputs of the boundary

scan register.

CLAMP

This optional instruction is useful for testing when not all ICs have BST. This instruction addresses

the bypass register while the boundary scan register is in external test mode.

IDCODE

This optional instruction will provide information on the components manufacturer, part number and

version number.

MSB

31

LSB

handbook, full pagewidth

28 27

12 11

1

0

TDI

TDO

0001

1

0111000100110000

16-bit part number

00000010101

4-bit

version

code

11-bit manufacturer

identification

mandatory

MHC175

Fig.16 32 bits of identification code.

34

2002 Apr 23

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

9

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and

grounded (0 V); all supply pins connected together.

SYMBOL

PARAMETER

digital supply voltage

CONDITIONS

MIN.

−0.5

MAX.

+4.6

UNIT

V_DDD

V_DDA

∆V_SS

V

analog supply voltage

−0.5

+4.6

100

voltage difference between

pins V_SSAand V_SSD

−

mV

V_IA

input voltage at analog inputs

−0.5

+4.6

V

V_I(n)

input voltage at pins XTALI, SDA and

SCL

V_DDD+ 0.5 V

V_ID

input voltage at digital I/O stages

outputs in 3-state

−0.5

+4.6

+5.5

V

outputs in 3-state;

3.0 V < V_DDD< 3.6 V

T_stg

storage temperature

−65

0

+150

70

°C

V

T_amb

V_esd

ambient temperature

electrostatic discharge voltage

note 1

note 2

−250

−3500

+200

+3500

V

Notes

1. Machine model: L = 0.75 µH, C = 200 pF and R = 0 Ω.

2. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.

10 THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

in free air

VALUE

UNIT

R_th(j-a)

thermal resistance from junction to ambient

34.6

K/W

2002 Apr 23

35

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

11 CHARACTERISTICS

V_DDD= 3.0 to 3.6 V; V_DDA= 3.0 to 3.6 V; T_amb= 25 °C; unless otherwise speciﬁed.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_DDD

V_DDA

P

digital supply voltage

analog supply voltage

power dissipation

3.0

3.3

3.6

V

3.3

V

power state

D0 for typical application

−

1.0

0.1

0.2

0.1

0.02

−

W

D0 after reset

D1

D2

D3-hot

Crystal oscillator

f_xtal(nom)

nominal crystal frequency

crystal 1; see Table 16

crystal 2; see Table 16

−

32.11

−

MHz

24.576 −

−

±70 × 10⁻⁶

∆f_xtal(n)

permissible nominal

frequency deviation

f_xtal

oscillator frequency range

24

32.11 33

MHz

mW

P_drive

crystal power level of drive

at pin XTALO

−

0.5

−

t_j

oscillator clock jitter

−

±100

ps

V

V_IH(XTALI)

HIGH-level input voltage at

pin XTALI

2

V_DDD+ 0.3

V_IL(XTALI)

LOW-level input voltage at

pin XTALI

−0.3

−

+0.8

V

PCI-bus inputs and outputs

V_IH

V_IL

I_LIH

HIGH-level input voltage

2

−

5.75

+0.8

10

V

LOW-level input voltage

−0.5

−

V

HIGH-level input leakage

current

V_I= 2.7 V; note 1

V_I= 0.5 V; note 1

µA

I_LIL

LOW-level input leakage

current

−

−10

µA

V_OH

V_OL

C_i

HIGH-level output voltage

LOW-level output voltage

input capacitance at

pin PCI_CLK

I_O= −2 mA

2.4

−

V

I_O= 3 or 6 mA; note 2

−

0.55

5

−

1

−

12

8

pF

pin IDSEL

pF

other input pins

10

5

pF

SR_r

SR_f

output rise slew rate

output fall slew rate

0.4 to 2.4 V; note 3

2.4 to 0.4 V; note 3

V/ns

5

2002 Apr 23

36

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

SYMBOL

t_val

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CLK to signal valid delay

see Fig.17; note 4

bused signals

2

−

11

12

−

ns

point-to-point signals

see Fig.17; note 5

see Fig.17; note 4

bused signals

−

ns

t_on

t_off

t_su

ﬂoat-to-active delay

active-to-ﬂoat delay

input set-up time to CLK

28

7

−

ns

µs

point-to-point signals

see Fig.17

10 (12)

0

t_h

input hold time from CLK

t_rst(CLK)

reset active time after CLK note 6

stable

100

t_rst(off)

reset active to output ﬂoat

delay

notes 5, 6 and 7

−

40

ns

I²C-bus interface, compatible to 3.3 and 5 V signalling (pins SDA and SCL)

f_bit

bit frequency rate

0

−

400

kbits/s

V

V_IL

V_IH

V_OL

LOW-level input voltage

HIGH-level input voltage

LOW-level output voltage

note 8

−0.5

+0.3V_DD(I2C)

note 8

0.7V_DD(I2C)

V_DD(I2C)+ 0.5 V

I_o(sink)= 3 mA

−

0.4

V

Analog video inputs

INPUTS (PINS CV0 TO CV4)

I_clamp

V_i(p-p)

clamping current

DC input voltage V_I= 0.9 V −

±8

−

µA

input voltage

note 9

0.375

0.75

1.07

V

(peak-to-peak value)

C_i

input capacitance

−

10

pF

9-BIT ANALOG-TO-DIGITAL CONVERTERS

α_cs

channel crosstalk

analog bandwidth

f_i< 5 MHz

−

−50

dB

B

at −3 dB; ADC only;

7

−

MHz

note 10

φ_dif

differential phase

differential gain

ampliﬁer plus anti-alias

ﬁlter bypassed

−

2

−

deg

%

G_dif

ampliﬁer plus anti-alias

ﬁlter bypassed

LE_DC(d)

LE_DC(i)

S/N

DC differential linearity error

DC integral linearity error

signal-to-noise ratio

−

1.4

2

−

LSB

dB

f_i= 4 MHz; anti-alias ﬁlter

bypassed; AGC = 0 dB

50

ENOB

effective number of bits

f_i= 4 MHz; anti-alias ﬁlter

bypassed; AGC = 0 dB

−

8

−

bit

2002 Apr 23

37

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) and outputs (pins OUT_LEFT and

OUT_RIGHT)

V_i(nom)(rms)

V_i(max)(rms)

V_o(max)(rms)

R_i

nominal input voltage

(RMS value)

note 11

−

200

−

2

−

mV

maximum input voltage

(RMS value)

THD < 3%; note 12

THD < 3%

1

V

maximum output voltage

(RMS value)

1

input resistance

V_i(max)= 1 V (RMS)

V_i(max)= 2 V (RMS)

−

145

48

250

−

kΩ

Ω

−

R_o

output resistance

150

10

−

375

−

R_L(AC)

C_L

AC load resistance

kΩ

nF

mV

%

output load capacitance

static DC offset voltage

−

12

30

0.3

V_offset(DC)

THD + N

−

10

0.1

total harmonic

distortion-plus-noise

V_i= V_o= 1 V (RMS);

f_i= 1 kHz; bandwidth

B = 20 Hz to 20 kHz

−

S/N

signal-to-noise ratio

reference voltage

70

75

−

dB

V_o= 1 V (RMS); f_i= 1 kHz;

“ITU-R BS.468” weighted;

quasi peak

α_ct

crosstalk attenuation

channel separation

between any analog input 60

pairs; f_i= 1 kHz

−

dB

α_cs

between left and right of

each input pair

60

All digital I/Os: GPIO pins and BST test pins (5 V tolerant)

PINS GPIO0 TO GPIO23, V_CLK, GPIO25 TO GPIO27, TDI, TDO, TMS, TCK AND TRST

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

input leakage current

I/O leakage current

2.0

−0.3

−

5.5

+0.8

1

V

I_LI

µA

I_L(I/O)

3.3 V signal levels at

_DDD≥ 3.3 V

−

10

V

C_i

input capacitance

I/O at high-impedance

V_I= V_DDD

−

8

pF

kΩ

V

R_pd

R_pu

V_OH

V_OL

pull-down resistance

pull-up resistance

−

50

−

V_I= 0

−

HIGH-level output voltage

LOW-level output voltage

I_O= −2 mA

I_O= 2 mA

2.4

0

V_DDD+ 0.5

0.4

−

V

Video port outputs (digital video stream from comb ﬁlter decoder or scaler)

LLC AND LLC2 CLOCK OUTPUT ON PIN V_CLK (see Fig.18)

C_L

load capacitance

cycle time

15

35

70

−

50

39

78

pF

ns

T_cy

LLC active

LLC2 active

2002 Apr 23

38

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

SYMBOL

PARAMETER

duty factor

CONDITIONS

MIN.

TYP.

MAX.

UNIT

δ

C_L= 40 pF; note 13

LCC active

35

−

65

5

%

LCC2 active

0.4 to 2.4 V

−

%

t_r

t_f

rise time

fall time

ns

2.4 to 0.4 V

−

5

VIDEO DATA OUTPUT (WITH RESPECT TO SIGNAL V_CLK) ON PINS GPIO0 TO GPIO17, GPIO22 AND GPIO23 (see Fig.18)

C_L

t_h

load capacitance

data hold time

15

−

50

pF

notes 14 and 15

LLC active

5

−

ns

LLC2 active

notes 14 and 15

LLC active

15

t_PD

propagation delay from

positive edge of

signal V_CLK

−

28

55

ns

LLC2 active

Raw DTV/DVB outputs (reuse of video ADCs in DVB/TV applications with TDA8960 and TDA8961 for VSB

reception)

CLOCK INPUT SIGNAL X_CLK_IN ON PIN GIPIO18

T_cy

δ

cycle time

duty factor

rise time

fall time

27.8

40

−

37

50

−

333

60

5

ns

%

note 13

t_r

0.8 to 2.0 V

2.0 to 0.8 V

ns

t_f

−

5

CLOCK OUTPUT SIGNAL ADC_CLK ON PIN V_CLK

C_L

T_cy

δ

load capacitance

cycle time

duty factor

rise time

−

25

−

pF

ns

%

27.8

40

−

C_L= 40 pF

0.4 to 2.4 V

2.4 to 0.4 V

60

5

t_r

ns

t_f

fall time

−

5

VSB DATA OUTPUT SIGNALS WITH RESPECT TO SIGNAL ADC_CLK

C_L

t_h

load capacitance

data hold time

25

5

−

50

pF

ns

inverted and not delayed;

note 14

−

t_PD

propagation delay from

positive edge of

inverted and not delayed;

notes 14 and 16

−

23

ns

signal ADC_CLK

TS capture inputs with parallel transport streaming (TS-P); e.g. DVB applications

CLOCK INPUT SIGNAL TS_CLK ON PIN GPIO20 (see Fig.19)

T_cy

δ

cycle time

duty factor

rise time

fall time

−

333

−

ns

%

note 13

40

−

60

5

t_r

0.8 to 2.0 V

2.0 to 0.8 V

−

ns

t_f

−

5

2002 Apr 23

39

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DATA AND CONTROL INPUT SIGNALS ON TS-P PORT (WITH RESPECT TO SIGNAL TS_CLK) ON PINS GPIO0 TO GPIO7,

GPIO16, GPIO19 AND GPIO22 (see Fig.19)

t_su(D)

t_h(D)

input data set-up time

input data hold time

2

5

−

ns

TS capture inputs with serial transport streaming (TS-S); e.g. DVB applications

CLOCK INPUT SIGNAL TS_CLK ON PIN GPIO20 (see Fig.19)

T_cy

δ

cycle time

duty factor

rise time

fall time

37

40

−

ns

%

note 13

60

5

t_r

0.8 to 2.0 V

2.0 to 0.8 V

ns

t_f

−

5

DATA AND CONTROL INPUT SIGNALS ON TS-S PORT (WITH RESPECT TO SIGNAL TS_CLK) ON PINS GPIO16, GPIO19,

GPIO21 AND GPIO22 (see Fig.19)

t_su(D)

t_h(D)

input data set-up time

input data hold time

2

5

−

ns

Notes

1. Input leakage currents include high-impedance output leakage for all bidirectional buffers with 3-state outputs.

2. Pins without pull-up resistors must have a 3 mA output current. Pins requiring pull-up resistors must have 6 mA;

these are pins FRAME#, TRDY#, IRDY#, DEVSEL#, SERR#, PERR#, INT_A and STOP#.

3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the

instantaneous rate at any point within the transition range.

4. REQ# and GNT# are point-to-point signals and have different output valid delay and input set-up times than bused

signals. GNT# has a set-up time of 10 ns. REQ# has a set-up time of 12 ns.

5. For purposes of active or float timing measurements, the high-impedance or ‘off’ state is defined to be when the total

current delivered through the device is less than or equal to the leakage current specification.

6. RST is asserted and de-asserted asynchronously with respect to CLK.

7. All output drivers floated asynchronously when RST is active.

8. V_DD(I2C)is the extended pull-up voltage of the I²C-bus (3.3 or 5 V bus).

9. Nominal analog video input signal is to be terminated by 75 Ω that results in 1 V (p-p) amplitude. This termination

resistor should be split into 18 Ω and 56 Ω, and the dividing tap should feed the video input pin, via a coupling

capacitor of 47 nF, to achieve a control range from −3 dB (attenuation) to +6 dB (amplification) for the internal

automatic gain control. See also application notes SAA7130HL/34HL.

10. See the user manuals of the SAA7130HL/34HL for Anti-Alias Filter (AAF).

11. Definition of levels and level setting:

a) The full-scale level for analog audio signals V_FS= 0.8 V (RMS). The nominal level at the digital crossbar switch

is defined at −15 dB (FS).

b) Nominal audio input levels: external, mono, V_i= 280 mV (RMS); −9 dB (FS).

12. The analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) are supported by two input levels: 1 V (RMS)

and 2 V (RMS), selectable via register setting VSEL0 (LEFT1, RIGHT1) and VSEL1 (LEFT2, RIGHT2).

t_H

13. The definition of the duty factor: δ =

--------

T_cy

14. The output timing must be measured with the load of a 30 pF capacitor to ground and a 500 Ω resistor to 1.4 V.

2002 Apr 23

40

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

15. Signal V_CLK inverted; not delayed (programming register vp_clk_ctr).

16. t_PD= 6 ns + 0.6T_{ADC_CLK}in ns (T_{ADC_CLK}= 28 ns).

2.4 V

0.4 V

handbook, full pagewidth

CLK

1.5 V

t

val

OUTPUT

DELAY

1.5 V

3-STATE

OUTPUT

t

on

t

off

t

h

su

2.4 V

0.4 V

INPUT

1.5 V

input valid

1.5 V

MGG280

Fig.17 PCI I/O timing.

2002 Apr 23

41

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

t

handbook, full pagewidth

PD

t

h

video data and

control output

(pins GPIO0 to GPIO

2.4 V

0.4 V

17,

)

22

GPIO and GPIO23

t

H

L

2.4 V

1.5 V

0.4 V

clock output

(pin V_CLK)

t

r

MHC002

f

Fig.18 Data output timing (video data, control outputs and raw DTV/DVB).

handbook, full pagewidth

TS data and

2.0 V

0.8 V

control input

(pins GPIO0 to GPIO

7,

16,

GPIO

GPIO19

and GPIO21)

t

h(D)

su(D)

2.0 V

1.5 V

0.8 V

TS_CLK

(pin GPIO20

)

MHC003

t

f

r

Fig.19 Data input timing (TS data and control inputs).

42

2002 Apr 23

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

Table 16 Speciﬁcation of crystals and related applications (examples); note 1

CRYSTAL FREQUENCY

32.11 MHz

24.576 MHz

UNIT

FUNDAMENTAL

3rd HARMONIC

1A

FUNDAMENTAL

3rd HARMONIC

2A

STANDARD

1B

1C

2B

2C

Crystal speciﬁcation

Typical load

capacitance

20

30

20

7

8

50

20

30

20

7

8

60

1

10

80

pF

Ω

Maximum series

resonance resistance

60

Typical motional

capacitance

13.5

3 ±1

1.5

fF

Maximum parallel

capacitance

4.3

3.3

3.5

pF

Maximum permissible ±30 × 10⁻⁶±30 × 10⁻⁶

deviation

Maximum temperature ±30 × 10⁻⁶±30 × 10⁻⁶

±30 × 10⁻⁶

±30 × 10⁻⁶±30 × 10⁻⁶

±50 × 10⁻⁶

±20 × 10⁻⁶

deviation

External components

Typical load

capacitance at

pin XTALI

33

10

15

27

5.6

18

pF

Typical load

capacitance at

pin XTALO

Typical capacitance of

LC ﬁlter

n.a.

1

n.a.

1

nF

Typical inductance of

LC ﬁlter

4.7

µH

Note

1. For oscillator application, see the application notes of the SAA7130HL/34HL.

2002 Apr 23

43

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

12 PACKAGE OUTLINE

LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm

SOT425-1

y

X

A

102

103

65

64

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

L

pin 1 index

detail X

39

38

128

1

v

M

A

Z

w M

D

b

p

e

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 14.1

0.17 0.09 19.9 13.9

22.15 16.15

21.85 15.85

0.75

0.45

0.81 0.81

0.59 0.59

mm

1.6

0.25

1.0

0.2 0.12 0.1

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

99-12-27

00-01-19

SOT425-1

136E28

MS-026

2002 Apr 23

44

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

13 SOLDERING

If wave soldering is used the following conditions must be

observed for optimal results:

13.1 Introduction to soldering surface mount

packages

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is

recommended.

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

13.2 Reﬂow soldering

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

13.4 Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

13.3 Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

To overcome these problems the double-wave soldering

method was specifically developed.

2002 Apr 23

45

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

13.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE

WAVE

not suitable

REFLOW⁽¹⁾

BGA, HBGA, LFBGA, SQFP, TFBGA

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS

PLCC⁽³⁾, SO, SOJ

suitable

not suitable⁽²⁾

suitable

LQFP, QFP, TQFP

not recommended⁽³⁾⁽⁴⁾suitable

not recommended⁽⁵⁾

suitable

SSOP, TSSOP, VSO

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

14 DATA SHEET STATUS

PRODUCT

DATA SHEET STATUS⁽¹⁾

DEFINITIONS

STATUS⁽²⁾

Objective data

Development This data sheet contains data from the objective specification for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

Preliminary data

Product data

Qualiﬁcation

This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

Production

This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Changes will be

communicated according to the Customer Product/Process Change

Notiﬁcation (CPCN) procedure SNW-SQ-650A.

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

2002 Apr 23

46

Philips Semiconductors

Product speciﬁcation

PCI video broadcast decoder

SAA7130HL

15 DEFINITIONS

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the

products, including circuits, standard cells, and/or

software, described or contained herein in order to

improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for

the use of any of these products, conveys no licence or title

under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that

these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified.

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

ICs with MPEG-2 functionality

Use of this product in

any manner that complies with the MPEG-2 Standard is

expressly prohibited without a license under applicable

patents in the MPEG-2 patent portfolio, which license is

available from MPEG LA, L.L.C., 250 Steele Street, Suite

300, Denver, Colorado 80206.

Application information

Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

ICs with MPEG-audio/AC-3 audio functionality

Purchase of a Philips IC with an MPEG-audio and/or AC-3

audio functionality does not convey an implied license

under any patent right to use this IC in any MPEG-audio or

AC-3 audio application. For more information please

contact the nearest Philips Semiconductors sales office or

e-mail: licensing.cip@philips.com.

16 DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

17 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

2002 Apr 23

47

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA74

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

753505/01/pp48

Date of release: 2002 Apr 23

Document order number: 9397 750 08669


型号：	SAA7130HLBE
厂家：	NXP
描述：	IC SPECIALTY CONSUMER CIRCUIT, PQFP128, 14 X 20 MM, 1.4 MM HEIGHT, MS-026, SOT-425-1, LQFP-128, Consumer IC:Other 解码器 PC
文件：	总48页 (文件大小：195K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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