SAA8200HL_技术文档

SAA8200HL

Ensation Base integrated wireless audio baseband

Rev. 02 — 17 October 2005

Preliminary data sheet

1. General description

The Ensation Base, SAA8200HL, is part of the integrated wireless audio system chip set

offered by Philips. This chip set enables the development of low cost wireless digital audio

systems. The chip set contains:

• An integrated wireless audio baseband chip (SAA8200HL)

• An integrated wireless audio radio chip (TEA7000).

RF

CHIP

TEA7000

analog

audio/voice SPDIF

in/out

audio/voice

in/out

BASEBAND

CHIP

BASEBAND

CHIP

2

I S-bus

SAA8200

2

I C-bus

data in/out

GPIO

peripherals/UI

001aab062

Fig 1. Ensation Link system example using two integrated wireless audio baseband and

radio ICs

Integrating a wireless audio link in a home theatre system to remove part of the wiring is a

logical application of wireless audio transmission. A very important property of this

wireless audio system is the low end-to-end (audio-in at transmit side to audio-out at

receive side) system latency, which is below 20 ms.

A second important property is the robustness and reliability of the wireless audio link, the

SAA8200HL which is handling the signal processing and the system control enables this.

Furthermore, the SAA8200HL provides the ﬂexibility to allow designers to make trade-offs

between air bit-rate, number of transported audio channels, audio formats, audio coding

bit-rates, range, number of receiving-slaves and more.

Due to its low power consuming design, the SAA8200HL enables battery powered

applications. The SAA8200HL does this all with a minimum of external components due to

its high level of integration.

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Together with the TEA7000, the SAA8200HL can be used to implement an indoor wireless

link for audio applications (system speciﬁc). Together with an AV-compliant Bluetooth

radio module, the SAA8200HL can be used to implement a Bluetooth wireless audio

functionality.

The SAA8200HL enables a low power, low cost two-chip solution with a maximum amount

of functions integrated on the SAA8200HL, taking into account strict time-to-market

constraints.

2. Features

2.1 General

■ Programmable baseband processor and system controller for cable replacement

wireless audio

■ Supports various audio compression formats

■ Wireless audio protocol can make trade-off between quality, number of channels,

bandwidth and range

■ Supports various transmission frequencies

■ High integration allows for two-chip applications

■ Embedded ROM with wireless audio software library.

2.2 Hardware

■ Audio PLL and system PLL

■ Read-Solomon encoder and decoder

■ SPDIF interface

■ Low cost low power EPICS7B DSP core with hardware debugger and JTAG interface

■ Integrated memories:

◆ 24/6 kWords program ROM/RAM (bit width: 32 bits)

◆ 12 kWords X data RAM (bit width: 24 bits)

◆ 12/2 kWords Y data ROM/RAM (bit width: 12 bits).

■ Interrupt controller

■ DMA controller

■ Oscillator and time base unit with programmable clocks

■ Embedded LDO regulators and DC-to-DC converters for on-chip and off-chip supply

voltage needs

■ Power control unit

■ Power on and power off switching with battery supply

■ Reed-Solomon codec unit

■ Serial radio interface unit

■ High speed UART

■ General purpose digital I/O block with 14 inputs, all of which generate interrupts

■ I²C-bus master/slave

■ I²C-bus for radio chip control

■ Control 10-bit ADC with four inputs

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

2 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

■ Two serial (I²S-bus/Japanese) digital audio inputs with independent clocks and

word-select

■ Two serial (I²S-bus/Japanese) digital audio outputs with shared clock and word-select

■ Integrated 16-bit stereo DAC (line output)

■ Integrated stereo headphone ampliﬁer

■ Programmable Gain Ampliﬁer (PGA) (line input)

■ Low noise microphone ampliﬁer (microphone input)

■ Integrated 16-bit stereo ADC

■ Watchdog timer.

2.3 Software

■ Stereo Sub Band Coding (SBC) encoder/decoder

■ Stereo MPEG layer 3 (MP3) decoder

■ Reed-Solomon encoder/decoder driver

■ Sample rate converter

■ I²C-bus master/slave driver

■ Serial radio interface driver

■ RF radio chip driver

■ UART driver

■ Control 10-bit ADC driver

■ Power consumption management

■ ADC, DAC and headphone driver

■ Wireless audio protocol library.

3. Applications

■ Wireless front speakers or wireless surround speakers for home theatre

■ Wireless indoor headphones

■ Wireless second room audio sets

■ Wireless headsets.

4. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

SAA8200HL

LQFP100

plastic low proﬁle quad ﬂat package; 100 leads;

SOT407-1

body 14 × 14 × 1.4 mm

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

3 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

5. Block diagram

64

JTAG_TDI

65

JTAG_TMS

JTAG_TDO

JTAG_TCK

JTAG_TRST_N

HARDWARE

DEBUGGER

66

67

68

JTAG

AUDIO CONFIGURATION

29

SPDIF_IN

SPDIF

I2SIN_1

I2SIN_2

I2SOUT_2

MEMORIES

72

73

74

2

3

I2SIN_1_DATA

I2SIN_1_WS

I2SIN_1_BCK

IIC_MS_SCL

IIC_MS_SDA

SYSTEM I2C

RSC

84

87

7

I2SIN_2_DATA

I2SIN_2_WS

I2SIN_2_BCK

94

95

96

97

98

99

SRI_FSYNC_P

SRI_FSYNC_N

SRI_GCHCLK_P

SRI_GCHCLK_N

SRI_DATA_P

78

I2SOUT_2_DATA

76,

77

SRI

I2SOUT_WS,

I2SOUT_BCK

2

SRI_DATA_N

79

I2SOUT_1_DATA

I2SOUT_1

EPICS7B

100

1

IIC_SRI_SCL

IIC_SRI_SDA

SRI I2C

TIMESTAMP

COUNTER

39

40

41

42

ADC10B_GPA0

ADC10B_GPA1

ADC10B_GPA2

ADC10B_GPA3

CONTROL

ADC

14

15

DAC_OUTL

DAC_OUTR

AUDIO DAC

WATCHDOG

16

20

HP_OUTL

HP_OUTR

HEADPHONE

AMPLIFIER

EVENT

ROUTER

23

24

25

ADC_INR

ADC_INL

PGA

LNA

AUDIO ADC

AUDIO PLL

80

81

82

83

ADC_MIC_PGA

UART_NRTS

UART_NCTS

UART_RXS

UART_TXS

26

27

UART

ADC_MIC_LNA

ADC_MIC_IN

80

81

82

83

7

GPIO_04

GPIO_05

GPIO_06

GPIO_07

GPIO_10

GPIO_11/SRI_INT

GPIO_12

GPIO_13

GPIO_03

GPIO_02/MODE_1

GPIO_01/MODE_0

GPIO_00

GPIO_08

GPIO_09

CGU

SYSTEM PLL

8

9

71

75

92

91

CLK_OUT1

CLK_OUT2

XTALH_IN

IO

CONFIG-

URATION

10

47

48

49

50

84

87

CRYSTAL

OSCILLATOR

XTALH_OUT

3.3 V/1.8 V SUPPLY

DC/DC

CONVERTOR

4

55

63

SAA8200HL

RSTIN_N

V

BAT(DCDC)

USB(DCDC)

001aab054

Pins 7, 80 to 84 and 87 are multiplexed functions pins.

Fig 2. Block diagram

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

4 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

6. Pinning information

6.1 Pinning

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

IIC_SRI_SDA

IIC_MS_SCL

IIC_MS_SDA

RSTIN_N

CLK_OUT2

2

I2SIN_1_BCK

I2SIN_1_WS

I2SIN_1_DATA

CLK_OUT1

3

4

5

V

SSI1

DDI1

6

V

DDE1

V

SSE1

7

GPIO_10/I2SIN_2_BCK

GPIO_11/SRI_INT

GPIO_12

8

JTAG_TRST_N

JTAG_TCK

JTAG_TDO

JTAG_TMS

JTAG_TDI

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GPIO_13

DAC_REFN

DAC_REFP

V

SAA8200HL

V

DDA(3V3_DAC)

USB(DCDC)

DAC_OUTL

DAC_OUTR

HP_OUTL

DCDC_OUT3V3

DCDC_LX1

V

SS12(DCDC)

V

DCDC_LX2

SSA(HP)

HP_OUTC

DCDC_SW

V

DCDC_IN3V3

DCDC_OUT1V8

DDA(3V3_HP)

HP_OUTR

HP_COM

V

BAT(DCDC)

SSA(DCDC)

V

SSA(ADC)

ADC_INR

ADC_INL

DCDC_PLAY

52 DCDC_STOP

51

ADC_MIC_PGA

DCDC_DOWNSEL

001aab020

Fig 3. Pin conﬁguration

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

5 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

6.2 Pin description

Table 2:

Symbol

Pin description

Pin Special^[1]Type

Description

Digital supply voltage pins

V_SSI1

5

VSSI

core ground

V_DDI1

6

VDDI

core supply voltage

core ground

V_SSE1

69

70

88

89

45

46

85

86

VSSE3V3

VDDE3V3

VSSE3V3

VDDE3V3

VDDCO

VSSCO

VDDCO

VSSCO

V_DDE1

core supply voltage

core ground

V_SSE2

V_DDE2

core supply voltage

core ground

V_DDI2

V_SSI2

V_DDI3

core supply voltage

core ground

V_SSI3

DC-to-DC converter

V_USB(DCDC)

63

A

VDDCO

USB supply voltage (linear

regulator)

DCDC_OUT3V3

DCDC_LX1

62

61

60

A

VDDCO

VSSCO

3.3 V output voltage

coil connection for 3.3 V converter

V_SSI2(DCDC)

ground for switches 1.8 V and 3.3

V converter

DCDC_LX2

DCDC_SW

59

58

57

56

55

54

A

VDDCO

VSSCO

coil connection for 1.8 V converter

switch node

DCDC_IN3V3

DCDC_OUT1V8

V_BAT(DCDC)

3.3 V input voltage

1.8 V output voltage

battery supply voltage

V_SSA(DCDC)

ground double bonded clean and

substrate

DCDC_PLAY

DCDC_STOP

DCDC_DOWNSEL

Crystal oscillator

V_SSA(XTALH)

53

52

51

A

APIO

play button signal

stop button signal

one ore two battery selection

90

91

92

93

VSSCO

APIO

analog ground

XTALH_OUT

XTALH_IN

11.025 MHz clock output

11.025 MHz clock input

analog supply voltage

APIO

V_{DDA(1V8_XTALH)}

PLL

V_{DDA(1V8_PLL)}

V_SSA(PLL)

VDDCO

38

37

VDDCO

VSSCO

analog supply voltage

analog ground

Serial radio interface

SRI_FSYNC_P

SRI_FSYNC_N

SRI_GCHCLK_P

94

95

96

A

APIO

frame sync positive

frame sync negative

gated channel clock positive

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

6 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 2:

Symbol

Pin description …continued

Pin Special^[1]Type

Description

SRI_GCHCLK_N

97

98

99

A

APIO

gated channel clock negative

data positive

SRI_DATA_P

SRI_DATA_N

data negative

Serial radio interface I²C-bus

IIC_SRI_SCL

IIC_SRI_SDA

Audio ADC

ADC_COM

ADC_REFP

ADC_REFN

ADC_REF

100

1

IIC400KT5V

clock input

data input or output

36

35

34

33

31

32

22

23

24

25

26

27

A

APIO

common mode reference voltage

positive reference voltage

negative reference voltage

reference voltage

APIO

V_{DDA(3V3_ADC)}

V_{DDA(1V8_ADC)}

V_SSA(ADC)

VDDCO

VSSCO

APIO

analog supply voltage (3.3 V)

analog supply voltage (1.8 V)

analog ground

ADC_INR

right input voltage

ADC_INL

APIO

left input voltage

ADC_MIC_PGA

ADC_MIC_LNA

ADC_MIC_IN

Audio DAC

DAC_REFN

DAC_REFP

V_{DDA(3V3_DAC)}

DAC_OUTL

DAC_OUTR

Headphone

HP_COM

APIO

PGA input for AC coupling

LNA output for AC coupling

microphone input

APIO

11

12

13

14

15

A

APIO

negative reference voltage

positive reference voltage

analog supply voltage

left line output voltage

right line output voltage

APIO

VDDCO

APIO

21

20

19

18

17

16

A

APIO

common mode reference voltage

right output voltage

HP_OUTR

APIO

V_{DDA(3V3_HP)}

HP_OUTC

VDDCO

APIO

analog supply voltage

common output voltage

analog ground

V_SSA(HP)

VSSCO

APIO

HP_OUTL

left output voltage

SPDIF

V_{DDA(3V3_SPDIF)}

SPDIF_IN

30

29

28

A

VDDCO

APIO

analog supply voltage

input voltage

V_SSA(SPDIF)

I²S-bus input

I2SIN_1_DATA

I2SIN_1_WS

I2SIN_1_BCK

VSSCO

analog ground

72

I

IPTHT5V

serial data channel 1

73 I/O

74 I/O

BPTS10THT5V word select channel 1

BPTS10THT5V bit clock channel 1

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

7 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 2:

Symbol

Pin description …continued

Pin Special^[1]Type

Description

GPIO_10/I2SIN_2_BCK

7

I/O

BPTS10THT5V general purpose IO/I²S-bus input

bit clock channel 2

GPIO_09/I2SIN_2_WS

87 I/O

BPTS10THT5V general purpose IO/I²S-bus input

word select channel 1

GPIO_08/I2SIN_2_DATA 84 I/O

BPTS10THT5V general purpose IO/I²S-bus input

serial data channel 2

I²S-bus output

I2SOUT_WS

76 I/O

77 I/O

BPTS10THT5V word select

BPTS10THT5V bit clock

I2SOUT_BCK

I2SOUT_2_DATA

I2SOUT_1_DATA

Control ADC

V_SSA(ADC10B)

78

79

O

OTS10CT5V

serial data channel 2

serial data channel 1

44

43

42

41

40

39

A

VSSCO

VDDCO

APIO

analog ground

V_{DDA(3V3_ADC10B)}

ADC10B_GPA3

ADC10B_GPA2

ADC10B_GPA1

ADC10B_GPA0

GPIO

analog supply voltage

analog general purpose input 3

analog general purpose input 2

analog general purpose input 1

analog general purpose input 0

APIO

GPIO_13

10 I/O

BPTS10THT5V general purpose IO

GPIO_12

9

8

7

I/O

GPIO_11/SRI_INT

GPIO_10/I2SIN_2_BCK

<tbd>

general purpose IO

BPTS10THT5V general purpose IO/I²S-bus input

bit clock channel 2

GPIO_09/I2SIN_2_WS

87 I/O

BPTS10THT5V general purpose IO/I²S-bus input

word select channel 1

GPIO_08/I2SIN_2_DATA 84 I/O

BPTS10THT5V general purpose IO/I²S-bus input

serial data channel 2

GPIO_07/UART_TXS

GPIO_06/UART_RXS

GPIO_05/UART_NCTS

GPIO_04/UART_NRTS

GPIO_03

83 I/O

82 I/O

81 I/O

80 I/O

47 I/O

48 I/O

BPTS10THT5V general purpose IO

GPIO_02/MODE_1

BPTS10THT5V general purpose IO/boot-up mode

selection pin 1

GPIO_01/MODE_0

49 I/O

50 I/O

BPTS10THT5V general purpose IO/boot-up mode

selection pin 0

GPIO_00

BPTS10THT5V general purpose IO

System I²C-bus

IIC_MS_SCL

IIC_MS_SDA

Other

2

3

IIC400KT5V

clock input or output

data input or output

CLK_OUT2

75

O

OTS10CT5V

clock output 2

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

8 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 2:

Symbol

Pin description …continued

Pin Special^[1]Type

Description

CLK_OUT1

71

4

O

I

OTS10CT5V

IPTHU5V

clock output 1

system reset input

RSTIN_N

JTAG

JTAG_TRST_N

JTAG_TCK

JTAG_TDI

JTAG_TMS

JTAG_TDO

68

67

64

65

66

I

IPTHDT5V

OTS10CT5V

reset input

I

clock input

I

data input

I

mode select input

data output

O

[1] A = analog.

I = input.

O = output.

Table 3:

Cell types description

Deﬁnition

Cell name

IPTHT5V

input pad; push pull; TTL with hysteresis; 5 V tolerant

IPTHU5V

IPTHDT5V

OTS10CT5V

input pad; push pull; TTL with hysteresis; pull-up; 5 V tolerant

input pad; push pull; TTL with hysteresis; pull-down; 5 V tolerant

output pad; 3-state; 10 ns slew rate control; 5 V tolerant

BPTS10THT5V bi-directional pad; plain input; 3-state output; 10 ns slew rate control; TTL with

hysteresis; 5 V tolerant

IIC400KT5V

APIO

I²C-bus pad; 400 kHz I²C-bus speciﬁcation; 5 V tolerant

analog pad; analog input/output

VDDI

V_DDpad connected to core V_DDand internal V_DDsupply voltage rail in I/O ring

V_DDpad connected to core V_DD

VDDCO

VDDE3V3

VSSCO

VSSE3V3

VSSI

V_DDpad connected to external 3.3 V V_DDsupply voltage rail

V_SSpad connected to core V_SS

V_SSpad connected to external 3.3 V V_SSsupply voltage rail

V_SSpad connected to core V_SS; internal V_SSsupply voltage rail in I/O ring and

substrate rail in I/O ring

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

9 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

7. Functional description

7.1 EPICS7B

The EPICS7B core has only access to four of the ﬁve memory spaces, PMEM, XMEM,

YMEM and DIO. Memory space IO is only accessible via the DMA. To distinguish between

the memory spaces, 18-bit addressing is used, of which the two Most Signiﬁcant (MS) bits

determine which space the address is in, see Table 4. The EPICS7B only knows about the

16 least signiﬁcant bits and uses special instructions to access DIO space.

EPICS7B access:

XMEM is accessed by EPICS7B when using X in its instructions

YMEM is accessed by EPICS7B when using Y in its instructions

PMEM is accessed by EPICS7B when it is fetching instructions

DIO is accessed by EPICS7B when using D in its instructions.

All 18 bits are used when accessing memory via DMA.

Table 4:

Memory spaces

Two MS bits

Memory space

XMEM

00

01

10

11

YMEM

PMEM

DIO or IO

The memory map of the system is described in Table 5 and Figure 4.

Table 5:

Address

IO

Memory map

Type

Words

64

Bits

0x[3]FFFF

0x[3]FFFE

DSP control register

32

EPICS7B instruction register

0x[3]FFC0 to 0x[3]FFFD user deﬁned

DIO

64

0x[3]FF00 to 0x[3]FF3F DIO registers

PMEM

24

0x[2]8000 to 0x[2]97FF PRAM

0x[2]0000 to 0x[2]5FFF PROM^[1]

0x[2]0000 to 0x[2]00FF BIOSROM^[1]

YMEM

6144

24576

0x[1]8000 to 0x[1]87FF YRAM

0x[1]0000 to 0x[1]2FFF YROM

XMEM

2048

12288

0x[0]FFC0 to 0x[0]FFFF memory mapped registers

0x[0]0000 to 0x[0]2FFF XRAM

12288

[1] DSP control register bit 0 is selecting PROM or BIOSROM.

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

10 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

[ ]

0x 3 FFFF

DSP control register

EPICS instruction register

user defined

[ ]

0x 3 FFFE

[ ]

0x 3 FFFD

[ ]

0x 3 FFC0

[ ]

0x 3 FFBF

IO and DIO

not used

[ ]

0x 3 FF40

[ ]

0x 3 FF3F

DIO register

not used

[ ]

0x 3 FF00

[ ]

0x 3 FEFF

[ ]

0x 3 0000

[ ]

0x 2 FFFF

not used

PRAM

[ ]

0x 2 9800

[ ]

0x 2 97FF

[ ]

0x 2 8000

[ ]

0x 2 7FFF

PMEM

not used

[ ]

0x 2 6000

[ ]

0x 2 5FFF

PROM

[ ]

0x 2 0100

[ ]

0x 2 00FF

PROM or BIOSROM

[ ]

0x 2 0000

[ ]

0x 1 FFFF

not used

[ ]

0x 1 8800

[ ]

0x 1 87FF

YRAM

[ ]

0x 1 8000

YMEM

[ ]

0x 1 7FFF

not used

[ ]

0x 1 3000

[ ]

0x 1 2FFF

YROM

[ ]

0x 1 0000

[ ]

0x 0 FFFF

memory map

[ ]

0x 0 FFC0

[ ]

0x 0 FFBF

not used

XMEM

[ ]

0x 0 3000

[ ]

0x 0 2FFF

XRAM

[ ]

0x 0 0000

001aab383

Fig 4. Memory map

The control registers are split in two different spaces. One space is accessible only via

DMA while the other space is accessible both via DMA and the DSP core. This space is

therefore X-memory mapped.

The location and deﬁnition of the control registers is described in Table 6.

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

11 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 6:

Control registers description

Register name

Address

R/W

Description

Reset

DSP

PC

0x0 FFFF

0x0 FFFE

0x0 FFFD

0x0 FFFC

0x0 FFFB

0x0 FFFA

0x3 FFFF

0x3 FFFE

W

program counter register

status register 1

undeﬁned

0x00 0000

0x00 0FFD

0x00 0000

SR1

SR2

status register 2

RTI_STACK

IO_DIR

interrupt stack register

conﬁguration register 1

conﬁguration register 2

control register I/O mapped

EPICS7B instruction register

IO_MODE

CR

EIR

Interrupt controller

INTC_POL

INTC_MODE

INTC_MASK

INTC_STATUS

INTC_TEST

INTC_SWCLR

INTC_SLCT

DMA controller

DMAC_IC

0x0 FFF9

0x0 FFF8

0x0 FFF7

0x0 FFF6

0x0 FFF5

0x0 FFF4

0x0 FFF3

W

R

polarity select

mode select

mask

0x03 FFFF

undeﬁned

0x00 0001

0x00 0000

status

W

test

software clear

user ﬂag

0x0 FFF2

R

IRQ counter value

0x00 0000

The interrupts and connection order are described in Table 7.

Table 7:

Interrupt ﬂags

Interrupt ﬂag Symbol

Description

0

FI_DMAC

DMAC interrupt

1

FI_SRI_DMA_RX_RDY SRI RX DMA block transfer interrupt

2

FI_FLSTART

FSL start interrupt

3

FI_EVENTROUTER

event router interrupt

4

FI_SRI_DMA_TX_RDY SRI TX DMA block transfer interrupt

5

FI_I2SIN_1

I²S-bus input 1 interrupt

I²S-bus input 2 interrupt

SPDIF input interrupt

6

FI_I2SIN_2

7

FI_SPDIF

8

FI_ADC

ADC input interrupt

9

FI_DACALL

FI_RSC_ENCRDY

FI_RSC_DECRDY

FI_RSC_DMARDY

FI_VPB0

I²S-bus and DAC outputs interrupt

RSC encoder ready interrupt

RSC decoder ready interrupt

10

11

12

13

14

15

16

17

RSC DMA block transfer ready interrupt

VPB0 interrupt

FI_VBP1

VPB1 interrupt

FI_UART

UART interrupt

I²C-bus M/S DMA block transfer interrupt

FI_I2C_DMARDY

FI_FSLFAST

FSL fast interrupt

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

12 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

The outputs of the ADC, I²S-bus inputs, SPDIF inputs and VPB buses are mapped to the

inputs of the EPICS7B.

Table 8:

DIO input registers

DIO input register

Register name Description

0

I2SIN_1L

I2SIN_1R

I2SIN_2L

I2SIN_2R

SPDIF L

I²S-bus input 1 left channel

1

I²S-bus input 1 right channel

I²S-bus input 2 left channel

I²S-bus input 2 right channel

SPDIF input left channel

2

3

4

5

SPDIF R

SPDIF input right channel

ADC input left channel

6

ADC_L

7

ADC_R

ADC input right channel

8

VPB0_DI1

VPB0_DI2

VPB1_DI

VPB0 data input 1 (bit 0 to bit 15)

VPB0 data input 2 (bit 16 to bit 31)

VPB1 data input (UART)

9

10

11

12

13

14

15

16

17

TS_COUNTER

I2SIN_1TS

I2SIN_2TS

SPDIF_TS

ADC_TS

time stamp counter i2sin1

time stamp counter i2sin2

time stamp counter spdif

time stamp counter adc

time stamp counter i2sout

I2SOUT_TS

TS_COUNTER

The control of the DAC, I²S-bus outputs and VPB buses are mapped to the outputs of the

EPICS7B.

Table 9:

DIO output registers

DIO output register Register name Description

0

I2SOUT_1L

I2SOUT_1R

I2SOUT_2L

I2SOUT_2R

DAC_L

I²S-bus output 1 left channel

I²S-bus output 1 right channel

I²S-bus output 2 left channel

I²S-bus output 2 right channel

DAC output left channel

1

2

3

4

5

DAC_R

DAC output right channel

6

not connected

VPB0_DO1

VPB0_DO2

VPB0_ADDR

VPB1_DO

7

8

VPB0 data output 1 (bit 0 to bit 15)

VPB0 data output 2 (bit 16 to bit 31)

VPB0 address

9

10

11

12

13

14

VPB1 data output (UART)

VPB1 address

VPB1_ADDR

not connected

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

13 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 9:

DIO output registers …continued

DIO output register Register name Description

15

16

17

not connected

7.1.1 User registers

The user registers are memory mapped control signals used to control integrated wireless

audio baseband functionality.

Table 10: User register description

Register name

Address

R/W

Description

Reset

SRI_TX_ADDR

0x0 FFDE

W

serial radio interface DMA

from MEM start address

0x000 0000

SRI_TX_BLKSIZE

SRI_MODE

0x0 FFDD

0x0 FFDC

0x0FFDB

0x0 FFDA

0x0 FFD9

0x0 FFD8

0x0 FFD7

W

serial radio interface DMA

from MEM block size

0x000 0000

serial radio interface mode

control

SRIM_TSTART

SRIM_TLINK

SRIM_TIDLE

SRIM_DLLEN

SRIM_ULLEN

serial radio interface master

mode start time

serial radio interface master

mode sync-link time

serial radio interface master

mode idle time

serial radio interface master

mode number downlink words

serial radio interface master

mode number uplink words

FSL_MODE

0x0 FFD6

0x0 FFD5

0x0 FFD4

0x0 FFD3

0x0 FFD2

0x0 FFD1

W

R

frame sync lock mode control 0x000 0000

audio PLL direct control 0x000 0000

audio PLL direct control select 0x000 0000

SPDIF status 0x000 0000

frame sync measured period 0x000 0000

APLL_CONTROL

APLL_SELECT

SPDIF_STATUS

FSY_INPERIOD

FSY_REFPERIOD

R

frame sync reference

measured period

0x000 0000

FSY_PHASEDIF

IWAB_BOOTCFG

0x0 FFD0

0x0 FFCF

R

frame sync phase difference 0x000 0000

W

SAA8200HL boot mode

conﬁguration

0x000 0000

SRI_STATUS

APLL_ACK

0x0 FFCE

0x0 FFCD

R

serial radio interface status

0x000 0000

audio PLL direct control

acknowledge

RSC_STATUS

RSC_CONTROL

RSC_ADDR

0x0 FFCC

0x0 FFCB

0x0 FFCA

R

Reed-Solomon status

Reed-Solomon control

0x000 0000

W

Reed-Solomon DMA start

address

RSC_BLKSIZE

0x0 FFC9

W

Reed-Solomon DMA block

size

0x000 0000

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

14 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 10: User register description …continued

Register name

Address

R/W

Description

Reset

SRI_RX_ADDR

SRI_RX_BLKSIZE

APLL_M

0x0FFC8

W

serial radio interface DMA to 0x000 0000

MEM start address

0x0FFC7

0x0FFC6

0x0FFC5

0x0FFC4

0x0FFC3

W

serial radio interface DMA to 0x000 0000

MEM block size

direct control of audio PLL M 0x000 0000

value

APLL_N

direct control of audio PLL N 0x000 0000

value

I2C_ADDR

master/slave I²C-bus DMA

memory address

0x002 8000

I2C_BLKSIZE

master/slave I²C-bus DMA

block size

0x000 0000

I2C_CONTROL

MPI_DEVADDR

0x0FFC2

0x0FFC1

W

master/slave I²C-bus control 0x000 0002

MPI device address 0x000 0048

7.2 VPB0 bridge

Section 7.2 speciﬁes the interfaces and function of the VPB0 bridge. The VPB0 bridge

acts as a bridge between a range of RTG IP blocks using the VPB bus and the EPICS7B

DIO interface. Two bridges are used one to connect to several slow blocks and an

additional one speciﬁcally for the UART.

The VPB0 bridge forms the bridge between the EPICS7B and the clock generation unit,

SRI I²C-bus, watchdog timer, event router, I/O conﬁguration and the audio conﬁguration

respectively.

7.2.1 VPB0 bridge address deﬁnitions

Table 11: VPB0 bridge interface description

Base address Offset

0x0000

Key

Description

clock generation unit

SCR_LP0

switch control register for system PLL clock

switch control register for audio PLL clock

switch control register for DC-to-DC converter clock

switch control register for SPDIF clock

switch control register for I2SIN_1 bit clock

switch control register for I2SIN_2 bit clock

switch control register for I2SOUT bit clock

switch control register for SRI gated channel clock

switch control register for CR output 1 clock

switch control register for CR output 2 clock

switch control register for SRI reference channel clock

frequency select side 1 for system PLL clock

frequency select side 1 for audio PLL clock

frequency select side 1 for DC-to-DC converter clock

frequency select side 1 for SPDIF clock

0x0004

SCR_HP0

0x0008

SCR_DCDC

0x000C

0x0010

SCR_SPDIF

SCR_I2SIN_1

SCR_I2SIN_2

SCR_I2SOUT

SCR_SRI_GCHCLK

SCR_CR_CLK_OUT1

SCR_CR_CLK_OUT2

SCR_SRI_CHCLK

FS1_ LP0

0x0014

0x0018

0x001C

0x0020

0x0024

0x0028

0x002C

0x0030

FS1_ HP0

0x0034

FS1_ DCDC

0x0038

FS1_ SPDIF

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

15 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 11: VPB0 bridge interface description …continued

Base address Offset

0x003C

0x0040

0x0044

0x0048

0x004C

0x0050

0x0054

0x0058

0x005C

0x0060

0x0064

0x0068

0x006C

0x0070

0x0074

0x0078

0x007C

0x0080

0x0084

0x0088

0x008C

0x0090

0x0094

0x0098

0x009C

0x00A0

0x00A4

0x00A8

Key

Description

FS1_ I2SIN_1

frequency select side 1 for I2SIN_1 bit clock

frequency select side 1 for I2SIN_2 bit clock

frequency select side 1 for I2SOUT bit clock

frequency select side 1 for SRI gated channel clock

frequency select side 1 for CR output 1 clock

frequency select side 1 for CR output 2 clock

frequency select side 1 for SRI reference channel clock

frequency select side 2 for system PLL clock

frequency select side 2 for audio PLL clock

frequency select side 2 for DC-to-DC converter clock

frequency select side 2 for SPDIF clock

FS1_ I2SIN_2

FS1_ I2SOUT

FS1_ SRI_GCHCLK

FS1_ CR_CLK_OUT1

FS1_ CR_CLK_OUT2

FS1_ SRI_CHCLK

FS2_ LP0

FS2_ HP0

FS2_ DCDC

FS2_ SPDIF

FS2_ I2SIN_1

frequency select side 2 for I2SIN_1 bit clock

frequency select side 2 for I2SIN_2 bit clock

frequency select side 2 for I2SOUT bit clock

frequency select side 2 for SRI gated channel clock

frequency select side 2 for CR output 1 clock

frequency select side 2 for CR output 2 clock

frequency select side 2 for SRI reference channel clock

frequency select status for system PLL clock

frequency select status for audio PLL clock

frequency select status for DC-to-DC converter clock

frequency select status for SPDIF clock

FS2_ I2SIN_2

FS2_ I2SOUT

FS2_ SRI_GCHCLK

FS2_ CR_CLK_OUT1

FS2_ CR_CLK_OUT2

FS2_ SRI_CHCLK

SSR_ LP0

SSR_ HP0

SSR_ DCDC

SSR_ SPDIF

SSR_ I2SIN_1

SSR_ I2SIN_2

SSR_ I2SOUT

SSR_ SRI_GCHCLK

SSR_ CR_CLK_OUT1

SSR_ CR_CLK_OUT2

frequency select status for I2SIN_1 bit clock

frequency select status for I2SIN_2 bit clock

frequency select status for I2SOUT bit clock

frequency select status for SRI gated channel clock

frequency select status for CR output 1 clock

frequency select status for CR output 2 clock

frequency select status for SRI reference channel clock

power control register for system clock

0x00AC SSR_ SRI_CHCLK

0x00B0

0x00B4

0x00B8

PCR_SPD_SYSCLK

PCR_SYSCLK_DIV4

PCR_UART_UCLK

power control register for 0.25 × f_ssystem clock

power control register for UART clock

0x00BC PCR_VPB1_PCLK

power control register for VPB1 bus clock

power control register for UART bus clock

power control register for DEBOUNCE bus clock

power control register for CGU bus clock

0x00C0

0x00C4

0x00C8

PCR_UART_PCLK

PCR_DEBOUNCE_PCLK

PCR_CGU_PCLK

0x00CC PCR_WDOG_PCLK

power control register for WDOG bus clock

power control register for control ADC bus clock

power control register for IO conﬁguration bus clock

power control register for event router bus clock

power control register for SRI I²C-bus clock

0x00D0

0x00D4

0x00D8

PCR_ADC_PCLK

PCR_IOCONF_PCLK

PCR_EVENT_ROUTER_PCLK

0x00DC PCR_SRI_I2C_PCLK

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

16 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 11: VPB0 bridge interface description …continued

Base address Offset

0x00E0

Key

Description

PCR_ADC_CLK

PCR_I2C_MS_PCLK

PCR_RSC_PCLK

power control register for control ADC system clock

power control register for M/S I²C-bus clock

power control register for RSC bus clock

0x00E4

0x00E8

0x00EC PCR_EXTDMACNTR_PCLK

power control register for external DMA controller clock

power control register for DIO2VPB0 bus clock

power control register for DIO2VPB1 bus clock

power control register for I2SIN_1 bus clock

power control register for I2SIN_2 bus clock

power control register for I2SOUT_1 bus clock

power control register for I2SOUT_2 bus clock

power control register for ADSS bus clock

power control register for audio conﬁguration bus clock

power control register for SPDIF bus clock

power control register for SRI bus clock

0x00F0

0x00F4

0x00F8

PCR_DIO2VPB0 _PCLK

PCR_DIO2VPB1_PCLK

PCR_I2SIN_1 _PCLK

0x00FC PCR_I2SIN_2 _PCLK

0x0100

0x0104

0x0108

0x010C

0x0110

0x0114

0x0118

0x011C

0x0120

0x0124

0x0128

0x012C

0x030

PCR_I2SOUT_1 _PCLK

PCR_I2SOUT_2_PCLK

PCR_ADSS _PCLK

PCR_AUDIO_CONFIG _PCLK

PCR_SPDIF _PCLK

PCR_SRI _PCLK

PCR_FRAMESYNCREF

PCR_CR_I2SIN_2_BCK

PCR_CR_I2SIN_1_BCK

PCR_CR_I2SOUT_BCK

PCR_CR_I2SIN_2_WS

PCR_CR_I2SIN_1_WS

PCR_CR_I2SOUT_WS

PCR_SDAC_NS_CLK

PCR_SDAC_DSPCLK

PCR_SADC_DECCLK

PCR_SADC_SYSCLK

power control register for SRI frame sync reference

power control register for I2SIN_2 bit clock

power control register for I2SIN_1 bit clock

power control register for I2SOUT bit clock

power control register for I2SIN_2 word select

power control register for I2SIN_1 word select

power control register for I2SOUT word select

power control register for SDAC new sample

power control register for SDAC DSP clock

power control register for SADC decimation ﬁlter clock

power control register for SADC system clock

0x0134

0x0138

0x013C

0x0140

0x0144

0x0148

0x014C

0x0150

0x0154

0x0158

0x015C

0x0160

0x0164

0x0168

0x016C

0x0170

0x0174

0x0178

0x017C

0x0180

PCR_DCDC_CONVERTER_CLK power control register for DC-to-DC converter clock

PCR_SPDIF_BCK

power control register for SPDIF bit clock from pad

power control register for I2SIN_1 bit clock from pad

power control register for I2SIN_2 bit clock from pad

power control register for I2SOUT bit clock from pad

power control register for SRI gated channel clock from pad

power control register for crystal output 1 from pad

power control register for crystal output 2 from pad

power control register for SRI channel clock

power status register for system clock

PCR_I2SIN_1_BCK

PCR_I2SIN_2_BCK

PCR_I2SOUT_BCK

PCR_SRI_GCC_SHO

PCR_CR_CLK_OUT1

PCR_CR_CLK_OUT2

PCR_SRI_CHCLK

PSR_SPD_SYSCLK

PSR_SYSCLK_DIV4

PSR_UART_UCLK

PSR_VPB1_PCLK

PSR_UART_PCLK

PSR_DEBOUNCE_PCLK

PSR_CGU_PCLK

power status register for 0.25 × f_ssystem clock

power status register for UART clock

power status register for VPB1 bus clock

power status register for UART bus clock

power status register for DEBOUNCE bus clock

power status register for CGU bus clock

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

17 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 11: VPB0 bridge interface description …continued

Base address Offset

0x0184

Key

Description

PSR_WDOG_PCLK

PSR_ADC_PCLK

power status register for WDOG bus clock

power status register for control ADC bus clock

power status register for IO conﬁguration bus clock

power status register for event router bus clock

power status register for SRI I²C-bus clock

power status register for control ADC system clock

power status register for M/S I²C-bus clock

power status register for RSC bus clock

0x0188

0x018C

PSR_IOCONF_PCLK

PSR_EVENT_ROUTER_PCLK

PSR_SRI_I2C_PCLK

PSR_ADC_CLK

0x0190

0x0194

0x0198

0x019C

PSR_I2C_MS_PCLK

PSR_RSC_PCLK

0x01A0

0x01A4

PSR_EXTDMACNTR_PCLK

PSR_DIO2VPB0 _PCLK

power status register for external DMA controller clock

power status register for DIO2VPB0 bus clock

power status register for DIO2VPB1 bus clock

power status register for I2SIN_1 bus clock

power status register for I2SIN_2 bus clock

power status register for I2SOUT_1 bus clock

power status register for I2SOUT_2 bus clock

power status register for ADSS bus clock

power status register for audio conﬁguration bus clock

power status register for SPDIF bus clock

power status register for SRI bus clock

0x01A8

0x01AC PSR_DIO2VPB1_PCLK

0x01B0

0x01B4

0x01B8

PSR_I2SIN_1 _PCLK

PSR_I2SIN_2 _PCLK

PSR_I2SOUT_1 _PCLK

0x01BC PSR_I2SOUT_2_PCLK

0x01C0

0x01C4

0x01C8

PSR_ADSS _PCLK

PSR_AUDIO_CONFIG _PCLK

PSR_SPDIF _PCLK

0x01CC PSR_SRI _PCLK

0x01D0

0x01D4

0x01D8

PSR_FRAMESYNCREF

power status register for SRI frame sync reference

power status register for I2SIN_2 bit clock

power status register for I2SIN_1 bit clock

power status register for I2SOUT bit clock

power status register for I2SIN_2 word select

power status register for I2SIN_1 word select

power status register for I2SOUT word select

power status register for SDAC new sample

power status register for SDAC DSP clock

power status register for SADC decimation ﬁlter clock

power status register for SADC system clock

PSR_CR_I2SIN_2_BCK

PSR_CR_I2SIN_1_BCK

0x01DC PSR_CR_I2SOUT_BCK

0x01E0

0x01E4

0x01E8

PSR_CR_I2SIN_2_WS

PSR_CR_I2SIN_1_WS

PSR_CR_I2SOUT_WS

0x01EC PSR_SDAC_NS_CLK

0x01F0

0x01F4

0x01F8

PSR_SDAC_DSPCLK

PSR_SADC_DECCLK

PSR_SADC_SYSCLK

0x01FC PSR_DCDC_CONVERTER_CLK power status register for DC-to-DC converter clock

0x0200

0x0204

0x0208

0x020C

0x0210

0x0214

0x0218

0x021C

0x0220

0x0224

PSR_SPDIF_BCK

power status register for SPDIF bit clock from pad

power status register for I2SIN_1 bit clock from pad

power status register for I2SIN_2 bit clock from pad

power status register for I2SOUT bit clock from pad

power status register for SRI gated channel clock from pad

power status register for crystal output 1 from pad

power status register for crystal output 2 from pad

power status register for SRI channel clock

PSR_I2SIN_1_BCK

PSR_I2SIN_2_BCK

PSR_I2SOUT_BCK

PSR_SRI_GCC_SHO

PSR_CR_CLK_OUT1

PSR_CR_CLK_OUT2

PSR_SRI_CHCLK

ESR_SPD_SYSCLK

ESR_SYSCLK_DIV4

enable fraction divider for system clock

enable fraction divider for 0.25 × f_ssystem clock

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

18 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 11: VPB0 bridge interface description …continued

Base address Offset

0x0228

0x022C

0x0230

0x0234

0x0238

0x023C

0x0240

0x0244

0x0248

0x024C

0x0250

0x0254

0x0258

0x025C

0x0260

0x0264

0x0268

0x026C

0x0270

0x0274

0x0278

0x027C

0x0280

0x0284

0x0288

0x028C

0x0290

0x0294

0x0298

0x029C

0x02A0

0x02A4

0x02A8

Key

Description

ESR_UART_UCLK

enable fraction divider for UART clock

ESR_VPB1_PCLK

enable fraction divider for VPB1 bus clock

enable fraction divider for UART bus clock

enable fraction divider for DEBOUNCE bus clock

enable fraction divider for CGU bus clock

enable fraction divider for WDOG bus clock

enable fraction divider for control ADC bus clock

enable fraction divider for IO conﬁguration bus clock

enable fraction divider for event router bus clock

enable fraction divider for SRI I²C-bus clock

enable fraction divider for control ADC system clock

enable fraction divider for M/S I²C-bus clock

enable fraction divider for RSC bus clock

enable fraction divider for external DMA controller clock

enable fraction divider for DIO2VPB0 bus clock

enable fraction divider for DIO2VPB1 bus clock

enable fraction divider for I2SIN_1 bus clock

enable fraction divider for I2SIN_2 bus clock

enable fraction divider for I2SOUT_1 bus clock

enable fraction divider for I2SOUT_2 bus clock

enable fraction divider for ADSS bus clock

enable fraction divider for audio conﬁguration bus clock

enable fraction divider for SPDIF bus clock

enable fraction divider for SRI bus clock

ESR_UART_PCLK

ESR_DEBOUNCE_PCLK

ESR_CGU_PCLK

ESR_WDOG_PCLK

ESR_ADC_PCLK

ESR_IOCONF_PCLK

ESR_EVENT_ROUTER_PCLK

ESR_SRI_I2C_PCLK

ESR_ADC_CLK

ESR_I2C_MS_PCLK

ESR_RSC_PCLK

ESR_EXTDMACNTR_PCLK

ESR_DIO2VPB0 _PCLK

ESR_DIO2VPB1_PCLK

ESR_I2SIN_1 _PCLK

ESR_I2SIN_2 _PCLK

ESR_I2SOUT_1 _PCLK

ESR_I2SOUT_2_PCLK

ESR_ADSS _PCLK

ESR_AUDIO_CONFIG _PCLK

ESR_SPDIF _PCLK

ESR_SRI _PCLK

ESR_FRAMESYNCREF

ESR_CR_I2SIN_2_BCK

ESR_CR_I2SIN_1_BCK

ESR_CR_I2SOUT_BCK

ESR_CR_I2SIN_2_WS

ESR_CR_I2SIN_1_WS

ESR_CR_I2SOUT_WS

ESR_SDAC_NS_CLK

ESR_SDAC_DSPCLK

enable fraction divider for SRI frame sync reference

enable fraction divider for I2SIN_2 bit clock

enable fraction divider for I2SIN_1 bit clock

enable fraction divider for I2SOUT bit clock

enable fraction divider for I2SIN_2 word select

enable fraction divider for I2SIN_1 word select

enable fraction divider for I2SOUT word select

enable fraction divider for SDAC new sample

enable fraction divider for SDAC DSP clock

enable fraction divider for SADC decimation ﬁlter clock

enable fraction divider for SADC system clock

0x02AC ESR_SADC_DECCLK

0x02B0

0x02B4

ESR_SADC_SYSCLK

ESR_DCDC_CONVERTER_CLK enable fraction divider for DC-to-DC converter clock

ESR_SPDIF_BCK

ESR_I2SIN_1_BCK

ESR_I2SIN_2_BCK

ESR_I2SOUT_BCK

ESR_SRI_GCC_SHO

no fractional divider supported for this clock

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

19 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

Table 11: VPB0 bridge interface description …continued

Base address Offset

Key

Description

0x02B8

ESR_CR_CLK_OUT1

enable fraction divider for crystal output 1 from pad

enable fraction divider for crystal output 2 from pad

enable fraction divider for SRI channel clock

base control register for system PLL clock

base control register for audio PLL clock

0x02BC ESR_CR_CLK_OUT2

0x02C0

0x02C4

0x02C8

0x2CC

0x2D0

ESR_SRI_CHCLK

BCR_LP0

BCR_HP0

FDC_SPD_SYSCLK

FDC_SYSCLK_DIV4

FDC_UART_UCLK

FDC_DEBOUNCE_PCLK

fractional divider control for system clock

fractional divider control for 0.25 × f_ssystem clock

fractional divider control for UART clock

0x02D4

0x02D8

fractional divider control for DEBOUNCE bus clock

fractional divider control for control ADC system clock

fractional divider control for DIO interface clock

fractional divider control for audio bus clock

fractional divider control for SRI frame sync reference

fractional divider control for I2SIN_2 bit clock

fractional divider control for I2SIN_1 bit clock

fractional divider control for I2SOUT bit clock

fractional divider control for I2S word select

fractional divider control for SDAC new sample

fractional divider control for audio system clock

0x02DC FDC_ADC_CLK

0x02E0

0x02E4

0x02E8

FDC_DIO_PCLK

FDC_AUDIO_PCLK

FDC_FRAMESYNCREF

0x02EC FDC_CR_I2SIN_2_BCK

0x02F0

0x2F4

FDC_CR_I2SIN_1_BCK

FDC_CR_I2SOUT_BCK

FDC_I2S_WS

0x02F8

0x02FC FDC_SDAC_NS_CLK

0x300

FDC_AUDIO_SYSCLK

0x0304

0x0308

0x030C

0x0310

0x0C00

0x0C04

0x0C08

0xC0C

0x0C10

0x0C14

0x0C18

FDC_DCDC_CONVERTER_CLK fractional divider control for DC-to-DC converter clock

FDC_CR_CLK_OUT1

FDC_CR_CLK_OUT2

FDC_SRI_CHCLK

CNF_POWERMODE

CNF_WD_BARK

reserved

fractional divider control for crystal output 1 from pad

fractional divider control for crystal output 2 from pad

fractional divider control for SRI channel clock

power-down CGU

watchdog bark register

reserved

OSC_ON

activate crystal oscillator

bypass crystal oscillator

reset for UART

OSC_BYPASS

CNF_UART_RST_N

0x0C1C CNF_I2SIN_1_RST_N

reset for I2S input 1

reset for I2S input 2

reset for I2S output 1

reset for I2S output 2

reset for decimation ﬁlter

reset for interpolation ﬁlter

reset for SPDIF

0x0C20

0x0C24

0x0C28

CNF_I2SIN_2_RST_N

CNF_I2SOUT_1_RST_N

CNF_I2SOUT_2_RST_N

0x0C2C CNF_DEC_RST_N

0x0C30

0x0C34

0xC38

CNF_INT_RST_N

CNF_SPDIF_RST_N

CNF_EPICS7B_RST_N

reset for EPICS7B

0x0C3C CNF_DIO2VPB0_RST_N

reset for VPB0 bridge

reset for UART VPB bridge

reset for M/S I²C-bus

0x0C40

0x0C44

CNF_DIO2VPB1_RST_N

CNF_MS_I2C_RST_N

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Ensation Base integrated wireless audio baseband

Table 11: VPB0 bridge interface description …continued

Base address Offset

Key

Description

0x0C48

CNF_SRI _RST_N

reset for serial radio interface

reset for Reed-Solomon codec

reset for SRI I²C-bus

0x0C4C CNF_RSC_RST_N

0x0C50

0x0C54

0x0C58

CNF_SRI_I2C_RST_N

CNF_AD10BIT_RST_N

CNF_FSL_RST_N

reset for control ADC

reset for frame sync lock

reset for gated channel clock

preset for control ADC

0x0C5C CNF_GCC_RST_N

0x0C60

0x0C64

0x0C68

CNF_AD10BIT_PRST_N

HP0_FIN_SELECT

HP0_MDEC

audio clock PLL input select

audio clock PLL M divider

audio clock PLL N divider

audio clock PLL P divider

audio clock PLL mode

0x0C6C HP0_NDEC

0x0C70

0x0C74

0x0C78

HP0_PDEC

HP0_MODE

HP0_STATUS

audio clock PLL status

0x0C7C HP0_ACK

audio clock PLL acknowledge

audio clock PLL change request

audio clock PLL input bandwidth selection

system clock PLL input select

system clock PLL power-down

system clock PLL bypass

system clock PLL in-lock

system clock PLL direct CCO control

system clock PLL M divider

system clock PLL P divider

SRI I²C-bus

0x0C80

0x0C84

0x0C88

HP0_REQ

HP0_INSELR

HP0_INSELI

0x0C8C HP0_INSELP

0x0C90

0x0C94

0x0C98

HP0_SELR

HP0_SELI

HP0_SELP

0x0C9C LP0_FIN_SELECT

0x0CA0 LP0_PWD

0x0CA4 LP0_BYPASS

0x0CA8 LP0_LOCK

0x0CAC LP0_DIRECT

0x0CB0 LP0_MSEL

0x0CB4 LP0_PSEL

0x1000

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0028

RX

receive FIFO

TX

transmit FIFO

STS

status register

CTL

control register

CLKHI

CLKLO

ADDR

TXS

clock divisor high

clock divisor low

I²C-bus address

slave transmit FIFO

0x2000

control ADC

0x0000

0x0004

0x0008

ADC_R0

ADC_R1

ADC_R2

ADC data channel 0

ADC data channel 1

ADC data channel 2

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Ensation Base integrated wireless audio baseband

Table 11: VPB0 bridge interface description …continued

Base address Offset

0x000C

0x0010

0x0014

0x0018

0x001C

0x0020

0x0024

0x0028

0x002C

0x0030

0x3000

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x003C

0x4000

0x0804

0x0808

0x080C

0x0810

0x0814

0x0818

0x081C

0x0820

0x0824

0x0828

0x082C

0x0830

0x0834

0x0838

0x0C00

0x0C20

0x0C40

0x6000

0x0000

0x0010

Key

Description

ADC_R3

ADC data channel 3

ADC_R4

ADC data channel 4

ADC_R5

ADC data channel 5

ADC_R6

ADC data channel 6

ADC_R7

ADC data channel 7

ADC_CON

control register

ADC_CSEL_RES

ADC_INT_ENABLE

ADC_INT_STATUS

ADC_INT_CLEAR

channel and resolution selection register

interrupt enable register

interrupt status register

interrupt clear register

watchdog timer

IR

interrupt register

TCR_REG

TC

timer control register

timer counter

PR_REG

PC

pre-scale register

pre-scale counter

MCR

MR0

match control register

match register 0

MR1

match register 1

EMR

external match register

event router

DTR_GP_13_IRQ

DTR_GP_12_IRQ

DTR_GP_11_IRQ

DTR_GP_10_IRQ

DTR_GP_9_IRQ

DTR_GP_8_IRQ

DTR_GP_7_IRQ

DTR_GP_6_IRQ

DTR_GP_5_IRQ

DTR_GP_4_IRQ

DTR_GP_3_IRQ

DTR_GP_2_IRQ

DTR_GP_1_IRQ

DTR_GP_0_IRQ

PEND

de-bounce time register for GP_13_IRQ

de-bounce time register for GP_12_IRQ

de-bounce time register for GP_11_IRQ

de-bounce time register for GP_10_IRQ

de-bounce time register for GP_9_IRQ

de-bounce time register for GP_8_IRQ

de-bounce time register for GP_7_IRQ

de-bounce time register for GP_6_IRQ

de-bounce time register for GP_5_IRQ

de-bounce time register for GP_4_IRQ

de-bounce time register for GP_3_IRQ

de-bounce time register for GP_2_IRQ

de-bounce time register for GP_1_IRQ

de-bounce time register for GP_0_IRQ

input event pending status

interrupt clear

INT_CLR

INT_SET

interrupt set

input/output conﬁguration

read pin values

IOC_PINS

IOC_MODE0

load mode 0

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Ensation Base integrated wireless audio baseband

Table 11: VPB0 bridge interface description …continued

Base address Offset

0x0014

0x0018

0x0020

0x0024

0x0028

0x7000

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x0020

0x0024

0x0028

0x002C

0x0030

0x0034

0x0038

0x003C

0x0040

0x0044

Key

Description

IOC_MODE0_SET

IOC_MODE0_RESET

IOC_MODE1

set mode 0

reset mode 0

load mode 1

IOC_MODE1_SET

IOC_MODE1_RESET

set mode 1

reset mode 1

audio conﬁguration

I²S-bus format settings

I²S-bus multiplexer settings

I2S_FORMAT_SETTINGS

I2S_MUX_SETTINGS

SPDIF_STATUS

SPDIF status

SPDIF_IRQ_EN

SPDIF interrupt enable

SPDIF_IRQ_STATUS

SPDIF_IRQ_CLEAR

SDAC_CTRL_INTI

SDAC_CTRL_INTO

SDAC_SETTINGS

SADC_CTRL_SDC

SADC_CTRL_ADC

SADC_CTRL_DECI

SADC_CTRL_DECO

E7B_IRQ

SPDIF interrupt status

SPDIF interrupt clear

audio DAC input interpolation ﬁlter control

audio DAC output interpolation ﬁlter control

audio DAC control

audio ADC ampliﬁers control

audio ADC control

audio ADC input decimation ﬁlter control

audio ADC output decimation ﬁlter control

EPICS7B interrupt request

power-down control ADC

DC-to-DC converter adjust output voltage (1.8 V)

DC-to-DC converter adjust output voltage (3.3 V)

DC-to-DC converter clock stable signal

PD_ADC10B

SET_DCDC1V8_ADJUST

SET_DCDC3V3_ADJUST

DCDC_CLOCKSTABLE

7.3 Clock generation unit

The Clock Generation Unit (CGU) generates all clock signals required for the

SAA8200HL, it contains:

• A crystal oscillator

• For low power mode the internal DC-to-DC converter clock can be used as system

clock

• An audio PLL to generate audio sample frequencies

• A system PLL to generate the clocks for the VPB bus and the DSP subsystem

• A clock switch block

• A conﬁguration register block

• A reset and power block.

An 11.2896 MHz oscillator or an external 11.025 MHz clock (provided by the TEA7000)

can be used in combination with the two PLLs and the external clocks to generate the

system frequencies.

All PLLs are programmed with the registers in the register conﬁguration block.

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7.3.1 Crystal oscillator

The crystal oscillator is a 50 MHz Pierce crystal oscillator with amplitude control. It can be

used in many applications e.g. as a digital reference for digital circuits, A/D and D/A

clocking, etc. It is a robust design and can be used across a large frequency range.

Features:

• On-chip biasing resistance

• Amplitude controlled

• Large frequency range: 1 MHz to 20 MHz

• Slave mode

• Power-down mode

• Bypass test mode.

7.3.2 Audio PLL

The audio PLL is a multi purpose PLL.

Features:

• Integrated PLL with on-chip Current Controlled Oscillator (CCO), no external

components for clock generation

• Input frequency range: 100 kHz to 150 MHz

• CCO output frequency: 275 MHz to 550 MHz

• Output frequency range: 4.3 MHz to 550 MHz

• Programmable pre-divider, feedback-divider and post-divider

• On the ﬂy adjustment of the clock possible

• Positive edge locking

• Frequency limiter to avoid hang-up of the PLL

• Lock detector

• Power-down mode

• Possibility to bypass whole PLL, the post-divider or the pre-divider

• Possibility to disable the output clock

• Skew mode

• Free running mode

• Scan mode

• Maximum peak cycle-to-cycle output jitter = 200 ps.

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7.3.3 System PLL

The DSP-PLL works in normal operating mode with feedback-divider and with

post-divider, this means that the base for the clock signal is the current controlled

oscillator (f_out= f_cco/P), running on 264.6 MHz. The output clock (f_out) is divided-by-2 to

generate a 132.3 MHz clock.

Features:

• Integrated PLL with on-chip Current Controlled Oscillator (CCO), no external

components for clock generation

• Functional down to 1.2 V (with reduced frequency range)

• 10 MHz to 25 MHz input frequency range

• 9.75 MHz to 160 MHz selectable output frequency with 50 % output duty cycle

• 156 MHz to 320 MHz CCO frequency range

• Power-down mode

• Input clock bypass mode

• Lock detector available

• Current consumption maximum 1 mA

• Maximum peak cycle-to-cycle output jitter = 300 ps.

7.4 Serial radio interface

Features:

• Interface between wireless audio baseband processor and wireless audio radio IC

• Bi-directional 3-wire serial interface

• Can be locked to audio sample frequencies

• Enables end-to-end audio clock synchronization

• Supports master and slave modes

• Supports continuous and high speed repetitive burst mode

• Control of the radio IC is handled via a separate I²C-bus interface

• Designed for minimal interference with the radio chip.

7.5 SRI I²C-bus

The I²C-bus master/slave module provides a serial interface that meets the I²C-bus

speciﬁcation and supports all transfer modes from and to the I²C-bus. It supports the

following functionality:

• It supports both the normal mode (100 kHz SCL) and the fast mode (400 kHz SCL)

• It has word (32-bit) access from the CPU side

• Interrupt generation on received or sent byte (and some special cases).

The purpose of the SRI I²C-bus is to allow the download of program code from an external

EEPROM at start-up, conﬁguration and monitoring of the radio IC (TEA7000), and

storage/retrieval of application speciﬁc parameters in an external data EEPROM.

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7.6 System I²C-bus interface

A master and slave DMA interface to the EPICS7B sub-system and the means to select

one or the other are provided. The I²C-bus master/slave module provides a serial

interface that meets the I²C-bus speciﬁcation and supports all transfer modes from and to

the I²C-bus.

Features:

• Supports both the normal mode (100 kHz SCL) and the fast mode (400 kHz SCL)

• 32-bit word access from the CPU side

• Interrupt generation on received or sent byte (and some special cases)

• Four modes of operation:

– master transmitter

– master receiver

– slave transmitter

– slave receiver.

7.7 Control ADC

This section describes the multi-channel 10-bit control ADC interface module, a module

that connects an ADC to a DSP. The ADC interface module can be used for observing

battery voltage.

The interface can be divided into two main modules; a 10-bit ADC and an ADC controller.

The 10-bit ADC is a 10-bit successive approximation ADC. The ADC controller module is

responsible for the communication between the ADC and DSP.

Features:

• Four analog input channels, selected by an analog multiplexer

• Programmable ADC resolution from 2-bit to 10-bit

• Single ADC scan mode and continuous ADC scan mode

• Converted digital values are stored in a 2 × 10-bit register

• Power-down mode.

7.8 Watchdog timer

Once the watchdog is enabled, it will monitor the programmed time out period and

generates a reset request when the period expires. In normal operation the watchdog is

triggered periodically, resetting the watchdog counter and ensuring that no reset is

generated. In the event of a software or hardware failure preventing the CPU from

triggering the watchdog, the time out will be exceeded and a reset requested from the

CGU.

The interrupt pin of this watchdog timer is not connected to the interrupt controller. Instead

of this, two pins M0 and M1 are used which will generate events. Pins M0 and M1 will

generate events when their match register matches the Timer Counter (TC) register.

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The watchdog timer in the SAA8200HL can be used as follows:

• As watchdog, the M1 output is used for generating an event to the CGU, which

requests a reset.

• As timer, the M0 output is used for generating an event to the event router, which

generates an interrupt to the interrupt controller.

• As watchdog and as timer, the value of the MCR0 has to be lower than the value of

MCR1 (otherwise unwanted resets could be generated by the CGU).

7.9 Reed-Solomon codec

The Reed-Solomon codec is an essential part of the baseband IC. It allows redundancy to

be added to the transmitted bits so that transmission errors can be corrected at the

receiving end. The Reed-Solomon codec will provide some ﬂexibility to the customer to

choose packet length. For SBC based applications the Reed-Solomon block length will be

such that it contains one or two SBC-encoded audio frames.

The Reed-Solomon codec is a hardware block that makes use of a locally attached

memory for I/O, work space and temporary storage. The communication between this

local RAM and the EPICS7B X-memory space will happen via the external DMA

controller.

Features:

• 8-bit; 1-byte symbols

• 256-byte blocks

• 16 parity bytes

• No interleaving (for latency reduction)

• Automatic zero insertion (virtual zero padding).

7.10 Event router

This module can be used in low power systems to request power-up or start a clock on an

external or internal event. It can also be used to generate interrupts as a result:

• Provides bus-controlled routing of input events to multiple outputs for use as interrupts

or wake-up signals

• Input events can be used either directly or latched (edge detected) as an interrupt

source:

– Direct interrupts will disappear when the event becomes inactive

– Latched interrupts will remain active until they are explicitly cleared.

• Interrupt events can be inverted (programmable)

• Each interrupt can be masked on event level

• Interrupt event detect status can be read per interrupt type

• Interrupt detection is fully asynchronous (no active clock required).

The event router provides bus control over the interrupt system. The event sources can be

deﬁned, their polarity and activation type selected, also each input can be routed to any

output(s) at reset.

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Table 12: Event router connections overview

Event

Input

0

Name

Description

SPDIF_IN

1

GP_13_IRQ

interrupt from general purpose pin

I²C-bus SRI event interrupt

2

GP_12_IRQ

3

GP_11_IRQ

4

GP_10_IRQ

5

GP_9_IRQ

6

GP_8_IRQ

7

GP_7_IRQ

8

GP_6_IRQ

9

GP_5_IRQ

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Output

0

GP_4_IRQ

GP_3_IRQ

GP_2_IRQ

GP_1_IRQ

GP_0_IRQ

I2C_SRI_NINTR

ADC10B_IRQ

FSL_START_IRQ

FSL_FAST_IRQ

XDMA_I2C_DMARDY

XDMA_MPIARDY

SRI_TXFIFO_EMPTYLEVEL

SRI_RXFIFO_FULLLEVEL

SRI_TXFIFO_UNDERRUN

SRI_RXFIFO_OVERRUN

WDT_NINT

Control ADC event interrupt

FrameSyncLock (FSL) start of frame

FrameSyncLock (FSL) fast interrupt for APLL control

block transfer I²C-bus MS ready

block transfer I²C-bus MPI ready

SRI TXFIFO reached empty level

SRI RXFIFO reached full level

exception: TXFIFO underrun occurred

exception: RXFIFO overrun occurred

watchdog timer event interrupt

watchdog time match 0

WDT_M0

WDT_M1

watchdog time match 1

SRI_ULD_REQ

SRI

CASCADED_INTERRUPT_0

WATCHDOG_CAP0_INT

CGU_WAKEUP

EPICS7B interrupt

1

2

CGU wake-up interrupt

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7.11 SPDIF inputs

One input is provided, this SPDIF input is fed through a bit slicer which is used to

re-generate the bitstream signal, allowing for a higher robustness of the link.

The SPDIF input hardware consists of a series connection of a bit slicer, which is an

analog module, the SPDIF decoder and a SPDIF input block. This SPDIF input block is

almost the same as the SPDIF input blocks which are connected to the SPDIF input pads.

The only difference between the SPDIF input blocks is that the input format of the SPDIF

input block is ﬁxed in hardware to accept only SPD3 format.

The SPDIF decoder is running on a dedicated clock, which should lie between 36 MHz

and 69 MHz. In this clock domain signal SPD3_BCK is generated, which is treated by the

I²S-bus input block as a bit clock. This bit clock is again routed via the CGU to be able to

insert the test clock during test mode. The SPDIF input decoder latches it’s output data on

the negative edge of SPD3_BCK. The I²S-bus input will latch the data on the positive

edge of the bit clock. This guarantees reliable data transfer even though the clock is

delayed by the path through the CGU.

The word select from the SPDIF input decoder is routed to the CGU. This makes it

possible to lock the audio PLL to the incoming SPDIF stream.

7.12 I²S-bus

The supported audio formats for the control modes are:

• I²S-bus

• LSB-justiﬁed, 16-bit

• LSB-justiﬁed, 18-bit

• LSB-justiﬁed, 20-bit

• LSB-justiﬁed, 24-bit (only for the output interface).

The bit clock BCK can be up to 128f_s, or in other words the BCK frequency is 128 times

the WS frequency or less: f_BCK≤ 128f_WS

.

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7.12.1 I²S-bus inputs

Two I²S-bus inputs are provided, one of the two has dedicated pins, the second is

multiplexed using pin GPIO8 to GPIO10.

The I²S-bus inputs can be used in slave and master mode. In slave mode an external

I²S-bus source generates the bit clock and in master mode the SAA8200HL generates the

bit clock. In slave mode the bit clock arrives on pad I2SIN_x_BCK and is led to the CGU

input xt_I2SIN_x_BCK. This input should be switched directly to the CGU output

I2SIN_x_BCK which delivers the bit clock for the I²S-bus blocks.

In slave mode the audio PLL needs to lock on the incoming source. This can best be done

on the bit clock or on the word select. The bit clock is the preferred source because of its

higher frequency. The audio PLL has problems with locking on frequencies below

100 kHz. If the ratio between the bit clock and the sample frequency is not known, the

source word select can be used. The digital audio source will put out the data and the

word select on the negative edge of the bit clock and these will be sampled by the I²S-bus

block on the positive edge of the bit clock.

7.12.2 I²S-bus outputs

Two I²S-bus outputs are provided, both have dedicated data pins but the word select and

bit clock for both outputs are shared.

Depending on the application the source of the audio PLL could have an other input, then

the fractional dividers should be programmed to account for the difference in clock

frequency.

The I2S_OUT can only be used in master mode. For this reason the output enable of the

I2S_OUT_WS and I2S_OUT_BCK pads is always active in functional mode. The bit clock

generated by the CGU is inverted with respect to the word select, such that word select

changes on a negative edge of the bit clock.

7.13 Time stamp counters

A time stamp counter has been included to allow the software to get an indication of the

audio clocks.

The time stamp counter output is hardwired to seven EPICS7B input registers. Each input

register will be latched by another strobe signal. These strobe signals are generated by

the audio interfaces I2SIN, SPDIF, ADC, I2SOUT and DAC. This way each sample of each

audio source and sink can be labeled with a time stamp. The time stamp increases by one

every DSP clock tick, and will wrap-round at value (2²⁴− 1).

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7.14 DMA controller

The purpose of the external DMA controller block is to share the external DMA channel of

the EPICS7B DSP sub system between a number of external peripherals: the serial radio

interface, the Reed-Solomon codec, the I²C-bus M/S and MPI. The controller needs to

arbitrate between those blocks.

Features:

• Interface between external DMA hardware blocks and the EPICS7B DSP subsystem

• Allows hardware blocks to read/write directly to X-, Y-, P-memory and to internal DSP

registers.

• Supports single word memory access and memory block transfers of programmable

length.

• Signals block transfer ready per requesting hardware device

• Arbiter priority schedule between four requesting sources (SRI, I²C-bus M/S, RSC

and MPI).

• Each requesting hardware block has its own start address and block transfer size

register

• Dispatches acknowledges and keeps track of progress of each block transfer

• Signals block transfer ready per requesting hardware device.

7.15 I/O conﬁguration

The input/output conﬁguration (IOCONF) is designed to provide developers a set of

registers. This can be used for conﬁguration of various on chip components especially a

pad multiplexer.

The IOCONF block is used to provide individual control and visibility for a set of pads. In

conjunction with a set of pad multiplexers, individual pads can be switched either in

normal operation mode, or in GPIO mode. In GPIO mode, a pad is fully controllable.

Through the IOCONF, individual pad levels can be observed in both normal and GPIO

modes.

Functional pads can be grouped into function blocks.

All output values in a function block can be set simultaneously by accessing a single

register. Changing modes for all pads within a function block requires at most two register

access. All input values in a function block can be read simultaneously by accessing a

single register. Input values are not registered and always read directly from the pad’s

input driver regardless of the mode of the pad.

For each function block there are two registers holding the control mode. MODE bit 1

leaves the IOCONF inverted as it is intended to be used as inverted (output-) enable.

Each register can be written and read, has conﬁgurable pad names per bit (maximum 32)

and provides set and clear access methods (SET/CLEAR bit when ‘1’), and conﬁgurable

reset value. Conﬁgurable pad names are provided in order to enhance readability and

consistency of both HDL and generated C header ﬁle.

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Ensation Base integrated wireless audio baseband

Table 13: Mode settings

MODE[1:0]

Pin multiplexer mode

GPIO; high-impedance

normal operation; controlled by subsystem

GPIO drive LOW

00

01

10

11

GPIO drive HIGH

7.16 VPB1 bridge

This section describes the interfaces and function of the VPB1 bridge. The VPB1 bridge

acts as a bridge between the UART and the EPICS7B DIO interface. Two bridges are

used; one to connect to several slow blocks and an additional one speciﬁcally for the

universal synchronous receiver transmitter, which is commonly used to implement a serial

interface. In any case where a device needs a low overhead, standard, low performance

interface, a UART can be used. The UART includes advanced features like a fractional

clock divider.

Table 14: VPB1 bridge interface description

Base address Offset

0x0000

Key

Description

UART

0x0000

UART_RBR

UART_THR

UART_IER

UART_IIR

receive FIFO

0x0000

transmit FIFO

0x0004

interrupt enable register

interrupt ID register

FIFO control register

line control register

modem control register

line status register

modem status register

scratch pad register

divisor latch LSB

divisor latch MSB

fractional divider register

0x0008

UART_FCR

UART_LCR

UART_MCR

UART_LSR

UART_MSR

UART_SCR

UART_DLL

UART_DLM

UART_FDR

0x000C

0x0010

0x0014

0x0018

0x001C

0x0000

0x0004

0x0028

7.17 UART conﬁguration

The UART interface is used to be implemented as a serial interface to, for example a

modem and is compatible with the industry standards 16650 UARTs.

No full modem interface is included, only the CTS and RTS modem signals are available.

The UART interface can also be conﬁgured as an IrDA (InfraRed Digital Association) SIR

(Serial InfraRed) interface, which has a pulse and polarity compliancy with the IrDA

Version 1.0 Physical Layer Speciﬁcation.

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7.18 Audio conﬁguration

The audio conﬁguration block gives access to the following system settings:

• I²S-bus input/output format settings

• Status of SPDIF module

• SPDIF interrupt request

• SDAC control and status registers

• SADC control and status registers

• Interrupt request to EPICS7B; with automatically clearing register

• Power-down of the multi-channel 10-bit control ADC

• DC-to-DC converter output voltage settings

• DC-to-DC clock-stable indicator.

7.19 Audio input

7.19.1 ADC analog front-end

The analog front-end of the ADC consists of one stereo ADC with a selector in front of it.

Using this selector one can either select the microphone input with the microphone

ampliﬁer (LNA) with a ﬁxed 30 dB gain or the line input. The microphone input as well as

the line inputs have a Programmable Gain Ampliﬁer (PGA) that allows gain control from

0 dB to 24 dB in steps of 3 dB.

The input impedance of the PGA (line in) is 12 kΩ, for the LNA this is 5 kΩ.

7.19.1.1 Applications and Power-down modes

The following Power-down and functional modes are supported:

• Power-down mode in which the current consumption is very low (only leakage

currents). In this mode there is no reference voltage at the line input.

• Line-in mode, in which the PGA can be used.

• Microphone mode in which the rest of the non-used PGAs and ADCs are powered

down. In this mode the mono microphone signal can be sent to both left and right

input of the decimation ﬁlter. This is done with a separate multiplexer in front of the

decimation input. This multiplexer is controlled by bit SEL_MIC in the I²C-bus control

interface.

• Mixed PGA and LNA mode with one line-in and one microphone input.

mic

LNA

PGA

SDC

left_out

ADC

left

right_out

right

001aab455

Fig 6. Analog front-end

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7.19.1.2 LNA

LNA, a Low Noise microphone Ampliﬁer with nominal gain of 30 dB.

7.19.1.3 PGA

The input signal is ampliﬁed with a gain set by control bits CTRL[3:0]. The resulting signal

will be available at V_out. If control bit CTRL3 = 1 the gain is set to 24 dB independent of the

other bits. If CTRL3 = 0 the gain is set for other (lower) settings. The PGA is based on an

inverting ampliﬁer architecture. The feedback resistance exists of a resistor string. By

switching between different resistors with the use of a 4-bit digital decoder the gain of the

ampliﬁer can be modiﬁed. The gain can be set in steps of 3 dB from 0 dB up to 24 dB (see

Table 15). The PGA is designed to handle a nominal 1 V (RMS) input level. A systematic

gain of −1.94 dB is added to accommodate the 800 mV (RMS) input level of a

single-to-differential converter that is normally connected to the PGA output. The

power-down signal is controlled by the digital core of the SAA8200HL.

Table 15: PGA gain settings

CTRL3

CTRL2

CTRL1

CTRL0

Gain

0 dB

0

1

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

3 dB

6 dB

9 dB

12 dB

15 dB

18 dB

21 dB

24 dB

7.19.1.4 Applications with 2 V (RMS) input

For the Line-in mode it is preferable to have 0 dB and 6 dB gain setting in order to be able

to apply both 1 V (RMS) and 2 V (RMS) (using series resistance). For this purpose a PGA

is used which has 0 dB to 24 dB gain with 3 dB steps.

external

resistor

PGA

12 kΩ

input signal

001aab456

Input signal is 2 V (RMS); V_DD= 3 V.

Fig 7. ADC front-end with PGA (line-in input)

In applications in which a 2 V (RMS) input signal is used, a 12 kΩ resistor must be used in

series with the input of the ADC. This forms a voltage divider together with the internal

ADC resistor and ensures that only 1 V (RMS) maximum is input to the SAA8200HL.

Using this application for a 2 V (RMS) input signal, the switch must be set to 0 dB. When a

1 V (RMS) input signal is input to the ADC in the same application, the gain switch must

be set to 6 dB.

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An overview of the maximum input voltages allowed against the presence of an external

resistor and the setting of the gain switch is given in Table 16; the power supply voltage is

assumed to be 3 V.

Table 16: Application modes using input gain stage

Resistor 12 kΩ

Present

input gain switch

maximum input voltage

2 V (RMS)

0 dB

6 dB

0 dB

6 dB

Present

1 V (RMS)

Absent

1 V (RMS)

Absent

0.5 V (RMS)

7.19.1.5 SDC

The Single-to-Differential Converter (SDC) consists of an inverting ampliﬁer and a ﬁlter

network. The input is DC coupled, which means that decoupling must be done in front of

this module in case the input signal has a different common mode level than the SDC. For

optional biasing conditions, the SDC requires a sourcing bias current (into an NMOS

transistor) that is preferably proportional to the analog supply voltage.

7.19.2 Decimation ﬁlter (ADC)

The decimation from 128fs is performed in two stages (see Figure 8). The ﬁrst stage

realizes sin(x)/x characteristics with decimation factor of 16. The second stage consists of

three half-band ﬁlters, each decimating by a factor of 2. The ﬁlter characteristics are

shown in Table 17.

Table 17: Filter characteristics

Description

Conditions

Value

Unit

Decimation ﬁlter

Pass band ripple

Stop band

up to 0.45f_s

from 0.55f_s

DC

±0.02

−60

3

dB

Overall gain

Dynamic range

Droop

up to 0.45f_s

at 0.45f_s

140

−0.18

DC blocking ﬁlter 1

Pass band ripple

Pass band gain

Droop

none

0

dB

at 0.00045f_s

up to 0.45f_s

0.5

DC attenuation

Dynamic range

DC blocking ﬁlter 2

Pass band ripple

Pass band gain

Droop

> 40

> 110

none

0

dB

at 0.00045f_s

up to 0.45f_s

0.031

> 40

> 110

DC attenuation

Dynamic range

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Table 17: Filter characteristics …continued

Description

Conditions

Value

Unit

Interpolation ﬁlter

pass band ripple

stop band

up to 0.4535f_s

from 0.5465f_s

pass band

±0.02

−72

dB

gain

−1.1

>143

dynamic range

up to 0.4535f_s

128f

8f

4f

2f

1f

s

DC

HPF1

VOL.

CTRL

DC

HPF2

COMB

HB3

HB2

HB1

sound features

halfband DSP

001aab457

Fig 8. Decimator data path

7.19.2.1 Volume control

The decimator is equipped with a digital volume control. This volume control is separate

for left and right and can be set via the SADC_CTRL_DECI register. The range is from

+24 dB down to −63 dB and mute in steps of 0.5 dB.

7.19.2.2 DC blocking ﬁlter

Two optional 1st order Inﬁnite Impulse Response (IIR) high-pass ﬁlters are provided to

remove unwanted DC components from the input (DC offset, DC dither) and/or volume

control output to avoid clipping when using large gain settings. These ﬁlters may be

bypassed by setting bits EN_DCFILTI (SADC_CTRL_DECI[20]) and/or EN_DCFILTO

(SADC_CTRL_DECI[19]) to a logic 0, which is necessary when fast settling of the

decimator is required.

On recovery from power-down or after a reset, the parallel output data on bits dout_l[23:0]

and DOUT_R[23:0] is held at logic 0 until valid data is available from the decimation ﬁlter.

This time depends on which of the DC-blocking ﬁlters is selected and if the ENABLE bit of

the delay timer is ON (EN_DELAY_DBLIN = SADC_CTRL_DECI[21]):

• EN_DELAY_DBLIN OFF:

t = 0 s

• DC ﬁlter 1 is off, DC ﬁlter 2 is off and EN_DELAY_DBLIN is on:

t = 44/f_s; t = 1 ms at f_s= 44.1 kHz

• DC ﬁlter 1 is ON, DC ﬁlter 2 is OFF and EN_DELAY_DBLIN is ON:

t = 17066/f_s; t = 387 ms at f_s= 44.1 kHz

• DC ﬁlter 2 is ON and EN_DELAY_DBLIN is ON:

t = 67473/f_s; t = 1.53 s at f_s= 44.1 kHz.

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7.19.2.3 Soft start-up after reset

After a reset of the decimation ﬁlter and if bit EN_DBLIN (SADC_CTRL_DECI[21]) is a

logic 1, the output gain of the decimator is increased from mute to −63.5 dB and at a rate

of 0.5 dB per f_speriod to 0 dB (dB linear) to avoid harsh audible plops. The time required

for a complete soft start-up if bit EN_DBLIN is a logic 1 for 128 f_speriods. This time is

without the time required if bit EN_DELAY_DBLIN (SADC_CTRL_DECI[21]) is a logic 1,

e.g. if bit EN_DBLIN and bit EN_DELAY_DBLIN are a logic 1, bit EN_DCFILTI and bit

EN_DCFILTO are logic 0 the total time required is (44 +128) f_speriods (see Table 18). The

decimator soft start-up function is illustrated in Figure 9.

Table 18: Required time after reset

EN_DELAY_DBLIN EN_DBLIN

EN_DCFILTI EN_DCFILTO Required time

0

1

0

1

0

1

X

0

1

X

0

1

X

0

1

0

1

0 s

128 periods of f_s

44 periods of f_s

17066 periods of f_s

67473 periods of f_s

(44 + 128) periods of f_s

(17066 + 128) periods of f_s

(67473 + 128) periods of f_s

44

128

periods of f

s

EN_DCFILTI = 0

EN_DCFILTO = 0

RESET = 0

ENABLE_DBLIN = 1

ABLE_DELAY_DBLIN = 1

DOUT

(analog representation)

001aab463

For readability, the parallel output data is shown in its analog representation.

Fig 9. Soft start-up function

7.19.2.4 Signal polarity

The polarity of the output signal is controlled by bit EN_POL_INV

(SADC_CTRL_DECI[17]). When this bit is enabled, the polarity of the output data is

inverted.

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7.19.2.5 Mute

When the left and right channel of the decimator are muted (bit EN_MUTE is a logic 1),

the gain in the decimator is decreased linearly to −63.5 dB with a ﬁnal step to mute at a

rate of 0.5 dB per f_speriod (dB linear). This is done to avoid harsh audible plops. The time

required for a complete mute depends on the initial gain setting. Maximum required time is

256 f_speriods. When a complete mute is achieved for both left and right channels, the bit

MUTE_STATE (SADC_CTRL_DECO[0]) is made logic 1. When the channels are

de-muted (bit EN_MUTE is a logic 0) the gain of the decimator is increased at the same

rate until the programmed gain setting is achieved.

7.19.2.6 Overﬂow detection

The output signal is used to indicate whenever the output data, in either the left or right

channel, is larger than −1.16 dB of the maximum possible digital swing. When this

condition is detected the overﬂow bit (SADC_CTRL_DECO[1]) is forced to a logic 1 for at

least 512 f_scycles (11.6 ms at f_s= 44.1 kHz) allowing even a slow microcontroller to poll

this event. This time-out is reset for each infringement.

7.19.2.7 AGC function

The decimation ﬁlter is equipped with an Automatic Gain Control (AGC) block. This

function is intended, when enabled, to keep the output signal at a constant level.

The AGC can be used for microphone applications in which the distance to the

microphone is not always the same.

The AGC can be enabled via the control register (SADC_CTRL_DECI[23]). In this case it

bypasses the digital volume control. Other features of the AGC, such as the attack, decay

and target level can be set via the same register.

The DC ﬁlter in front of the decimation ﬁlter must be enabled when AGC is in operation,

otherwise the output will be disturbed by the DC offset added in the ADC.

Table 19: AGC enable control

AGC_EN

AGC function

0

disabled, manual gain control via the left/right decimator volume

control, (default)

1

enabled, with manual microphone gain settings via PGA

Table 20: AGC target level settings

AGC_LEVEL1

AGC_LEVEL0

AGC target level value (dB)

0

1

0

1

0

1

−5.5

−8.0

−11.5

−14.0

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Table 21: AGC time constant settings

AGC_TIME2 AGC_TIME1 AGC_TIME0 AGC setting

44.1 kHz sampling

8 kHz sampling

Attack time (ms) Decay time (ms) Attack time (ms) Decay time (ms)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

11

16

11

16

21

11

16

21

100

200

400

61

551

88.2

61

551

1102

2205

88.2

116

61

88.2

116

7.20 Audio output

7.20.1 SDAC

The Stereo Digital-to-Analog Converter (SDAC) is a module with interpolation ﬁlters and

noise shaper for low frequency applications such as audio and TV-audio. In this section

the analog and digital part is described. The digital part consists of an interpolation ﬁlter

that increases the sample rate from 1f_sto 128f_sand a third order noise shaper that runs

on 128f_sor 256f_s.

The inputs to the SDAC are two 24-bit parallel input words, left and right, and a

synchronization signal (DIN_VALID) at f_s(f_s, the sample rate, is typically 44.1 kHz). The

output is a stereo analog signal (VOUT_LINEL and VOUT_LINER).

7.20.1.1 Features of the SDAC

• 24-bit data path with 16-bit coefﬁcients

• Full FIR ﬁlter implementation for all of the upsampling ﬁlter

• Digital dB-linear volume control in 0.25 dB steps

• Digital de-emphasis for 32 kHz, 44.1 kHz, 48 kHz and 96 kHz

• Selection for the 2f_sto 8f_supsampling ﬁlter characteristics (sharp/slow-roll-off)

• Support for 2f_sand 8f_sinput signals:

– 1f_swith full feature support, being de-emphasis, master volume control and soft

mute

– 2f_sinput with master volume and mute support: required for double speed mode

– 8f_sinput no features supported. This is intended for DSD support (grabbing data at

8f_sfrom an external DSD unit)

• Soft mute with a raised cosine function

• Controlled power-down sequence comprising a raised cosine mute function followed

by a DC ramp down to zero to avoid audible plops or clicks

• Integrated digital silence detection for left and right with selectable silence detection

time

• Polarity control

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• Simple switched resistors architecture

• Data-weighted averaging technique reducing distortion

• Large supply voltage range (0.8 V to 3.6 V)

• Low noise (N > 100 dBA).

SAA8200HL

V

DAC_REFN

DDA(3V3_DAC)

V

DD

V

SS

DAC_REFP

14 DAC_OUTL

[

]

DIN_L 23:0

DAC

16 HP_OUTL

18 HP_OUTC

20 HP_OUTR

SOUND CONTROL

INTERPOLATION FILTER

AND

DIN_VALID

HP

NOISESHAPER

15 DAC_OUTR

[

]

DIN_R 23:0

DAC

001aab465

Fig 10. Block diagram of the SDAC

7.20.1.2 Functional description

The SDAC comprises the following functions:

• Sound feature processor

• Digital upsampling ﬁlter

• Noise shaper

• DAC.

Digital de-emphasis can be set by a 3-bit control bus (bits CTRL_INTI[18:16]) for the

range of sample frequencies available (32 kHz, 44.1 kHz, 48 kHz and 96 kHz). The

de-emphasis ﬁlters are only in the signal path for normal speed mode (data input at 1f_s).

In the interpolation ﬁlter a three stage linear digital volume control is provided with a range

from 0 dB to −89 dB and −∞ dB. Down to the attenuation of −50 dB the step size equals

0.25 dB, from −50 dB to −83 dB it equals 3 dB and the last step to −89 dB is one of 6 dB.

The attenuation for the left channel is controlled by bits CTRL_INTI[15:8]; the attenuation

for the right channel is controlled by bits CTRL_INTI[7:0].

When the left and right channels of the interpolator are muted (bit CTRL_INTI[19] = 1), the

gain in the interpolator is decreased to −∞ dB conforming to a raised cosine function to

avoid harsh audible plops (soft mute). This mute function is completed after a period of

128 samples in normal mode i.e. 2.9 ms at f_s= 44.1 kHz. When a complete mute is

achieved for both left and right channels, the bit CTRL_INTO[0] is made a logic 1. The

interpolator mute function is illustrated in Figure 11.

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raised cosine roll-off (128 periods of f )

s

interpolator

4-bit output data

(analog representation)

[

]

CTRL_INTI 19 (mute)

[ ]

TRL_INTO 0 (mute state)

001aab466

Fig 11. Interpolator mute signals

7.20.1.3 Power-down

640 periods of f

s

interpolator

4-bit output data

(analog representation)

[

]

CTRL_INTI 25

[ ]

CTRL_INTO 1

[ ]

TRL_INTO 0 (mute state)

raised

cosine roll-off

DC ramp down

(512 periods of f )

s

(128 periods of f )

s

001aab467

Fig 12. Interpolator power-up and power-down sequence

When the interpolator is powered down (bit CTRL_INTI[25] = 1), the gain in the

interpolator is decreased to −∞ dB to conform to a raised cosine function. This is followed

by a DC ramp down to zero output data (000000h). The slope of this DC ramp can be set

by bit CTRL_INTI[24] to either 512 f_speriods (default) or 1024 f_speriods. The power-up

follows the reverse procedure, a DC ramp up to mid scale plus DC dither (2 to [6 + 2] to

[10 + 2] to 17) followed by a gain increase to conform to a raised cosine function. Total

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time required for a full power-up or power-down equals 128 f_speriods (raised cosine

function) plus 512 f_speriods (DC ramp up/down) making 640 f_speriods or 14.5 ms for

f_s= 44.1 kHz. The power-up and power-down function is illustrated in Figure 12.

7.20.1.4 Silence detection

The silence detection circuit counts the number of digital input samples equal to zero. It is

enabled by the control bit CTRL_INTI[30]. The number of zero samples before signalling

silence detected (bit CTRL_INTO[3] for left channel and bit CTRL_INTO[2] for right

channel) can be set by bits CTRL_INTI[29:28]. This feature is not used to control the

SDAC, it is simply a feature that can be used in the system.

7.20.1.5 Polarity control

The stereo output signal polarity of the C18INT can be changed by setting the

CTRL_INTI[26] to logic 1. Note that this single control bit affects both channels.

7.20.1.6 Digital upsampling ﬁlter

The interpolation from 1f_sto 128f_sis realized in four stages:

• The ﬁrst stage is a 99-tap half band ﬁlter (HB) which increases the sample rate from

1f_sto 2f_sand has a steep transition band to correct for the missing inherent ﬁlter

function of the SDAC.

• The second stage is a 31-tap FIR ﬁlter which increases the data rate from 2f_sto 8f_s,

scales the signal and compensates for the roll-off caused by the sample-and-hold

function prior to the noise shaper. For this ﬁlter three sets of coefﬁcients can be

chosen realizing three different transfer characteristics.

• The third stage is a simple hardware linear interpolator (LIN) function that increases

the sample rate from 8f_sto 16f_sand removes the 8f_scomponent in the output

spectrum. The main reason for upsampling to 16f_sis the fact that the SDAC only has a

ﬁrst order roll-off function.

• The fourth and last stage is a sample-and-hold function increasing the sample rate

from 16f_sto a selectable 128f_sor 256f_s, depending on the actual input data rate. For

input sample rates between 8 kHz and 32 kHz the noise shaper and DAC must run on

256f_sinstead of the typical 128f_sto avoid a signiﬁcant noise increase in the audible

frequency band of 0 kHz to 20 kHz.

1f

2f

8f

16f

128f

or

s

normal

speed

256f

s

DEEM

2

HB

VC

MT

4

FIR

double

speed

2f

s

LIN

S&H

8f

DSD

001aab468

Fig 13. Interpolator data path

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The SDAC has three modes of operation which are set by the control input bits

CTRL_INTI[21:20]:

• Normal 1f_sinput mode used for input data rates between 8 kHz and 96 kHz using

sharp ﬁlter roll-off. De-emphasis (DEEM), volume control (VC) and mute (MT)

functions are all available in this mode

• 2f_sinput mode which may be used as:

– Double speed input when the data rate is between 96 kHz and 200 kHz

– A means to get slow roll-off by skipping the ﬁrst half band ﬁlter (HB). In this mode

the de-emphasis (DEEM) is not available

• 8f_sor DSD input mode, in which case the input is obtained form an external DSD

block. De-emphasis (DEEM), volume control (VC) and mute (MT) features are

unavailable in this mode.

7.20.1.7 Noise shaper

The 3rd-order noise shaper operates at either 128f_sor 256f_sdepending on the mode of

operation deﬁned by bits CTRL_INTI[23:20]. It shifts in-band quantization noise to

frequencies well above the audio band. This noise shaping technique enables high

signal-to-noise ratios to be achieved at low frequencies. The noise shaper output is

converted into an analog signal using a 4-bit switched resistor digital-to-analog converter.

7.20.1.8 SDAC

The 4-bit SDAC is based on a switched resistor architecture which is merely a controlled

voltage divider between the positive and negative reference supplies VREF_DACP and

VREF_DACN. The 4-bit input data from the noise shaper is ﬁrst decoded to a 15 level

thermometer code controlling the 15 taps of the converter. Added to the decoding is a

selectable Data Weighted Averaging (DWA) technique which guarantees that there is no

correlation between the input signal and the resistors used for that input signal.

After decoding and DWA the buffers connect the resistors to either the VREF_DACP or

VREF_DACN. In doing this the reference voltage will be divided depending on the input

signal. The result is an analog output voltage with a rail-to-rail maximum output swing. The

output impedance of this DAC is approximately 1 kΩ. By applying an external capacitor of

3.3 nF to the line output (VOUTLINEL or VOUT_LINER) a low pass post ﬁlter is

introduced with a −3 dB roll off at 48 kHz (dimensioned for f_s= 44.1 kHz). This will thus

reduce the 3rd order noise shaped output spectrum of the DAC to a noise spectrum

increasing with 2nd order. The value of this capacitor depends on the actual sample

frequency used.

7.20.1.9 Data weighting averaging

The SDAC features two DWA algorithms which can be selected independently for the left

(bit CTRL_DAC[1]) and right (bit CTRL_DAC[0]) channels. By setting these bits to a

logic 0 the uni-directional DWA algorithm is chosen which is best suited for good S/N

ﬁgures. By setting these bits to a logic 1 the bi-directional DWA algorithm is chosen which

is best for low distortion.

SAA8200HL_2

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7.20.2 Headphone

7.20.2.1 Headphone driver

The headphone driver can deliver 22 mW (at 3.0 V power supply) into16 Ω load.

The headphone driver does not need external DC decoupling capacitors because it can

be DC-coupled with respect to a special headphone output reference voltage. This saves

two external capacitors. Changes in the load on the DAC outputs inﬂuence the output of

the headphone. This is because the headphone inputs are directly connected to the DAC

outputs.

7.20.2.2 Headphone Limiter

To protect the headphone ampliﬁer from serious damage due to short-circuiting of the

outputs (e.g. during the connection of a headphone jack plug) a current limiter is

incorporated. The activation of this current limiter is signaled by individual logic clip

signals (CLIP_L, CLIP_R and CLIP_C). The level at which the current limiter is activated

can be set to four different levels for each ampliﬁer.

The current level to which the output stage is limited can be set with the bits

SET_LIMITER_L/R/C[1:0] inputs from 80 mA to 140 mA for the left and right channels and

from 180 mA to 240 mA for the common channel (see Table 22). The maximum current for

the common ground channel is larger (double on average) as this channel must be able to

sink and source the left and right channel output currents. When the current through the

output stage exceeds the programmed current level, the monitor bit CLIP_L, CLIP_R or

CLIP_C is set to a logic 1 and the output stage is shut down.

These values are based on the worst case situation of two in-phase full scale input signals

of 1.0 V (RMS) and a minimum headphone impedance of 16 Ω. This results in left and

right channel peak output currents of 1.41 V / 16 Ω = 88.4 mA and a common ground peak

output current of 2 × 88.4 mA = 176.8 mA. The maximum current that is actually ﬂowing in

the common ground ampliﬁer is always the sum of the left and right channel maximum

currents.

Table 22: Output current limiter settings

SET_LIMITER_L[1:0],

SET_LIMITER_R[1:0],

SET_LIMITER_C[1:0]

Maximal output current

Left and right channel

Common channel

00

01

10

11

OFF

100 mA (default)

120 mA

200 mA (default)

220 mA

140 mA

240 mA

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7.21 DC-to-DC converter

The SAA8200HL needs two supply voltages, 3.3 V for analog functions and 1.7 V for

digital functions. For normal operation one or two batteries of 1.5 V will be used as an

energy source, from which the DC-to-DC converter must generate the required voltage

levels, see Figure 14. Two inductive DC-to-DC converters will be used when the chip is

battery operated. The V_DDEpins are externally connected to pin DCDC_OUT3V3, The

V_DDIpins are connected to pin DCDC_OUT1V8. When the SAA8200HL is supplied from

USB, the outputs of the DC-to-DC converters will be overruled by two linear regulators. In

that case the supply voltages will be 3.3 V and 1.8 V. This is independent from the USB

voltage (4.0 V to 5.5 V) so a reference circuit is needed.

DC

DCDC_OUT3V3

V

BAT(DCDC)

DC

switching regulator 1

vin

LDO1

vout

vin

LDO2

vout

V

USB(DCDC)

LINEAR REGULATOR 1

LINEAR REGULATOR 2

vusb_present

DC

DCDC_OUT1V8

DC

switching regulator 2

V

< 1.6 V

BAT(DCDC)

VDD_ALWAYS

DC to DC - controller

ANALOG DIGITAL

vref

LOW VOLTAGE

BANDGAP

RING OSC

DELAY

PLL

POR

adjust

12 MHz

XOSC

DIGITAL CORE

001aac002

Fig 14. DC-to-DC converter block schematic

During the start-up sequence the DC-to-DC controller uses the RING OSC to control the

switching regulators. After start-up the 12 MHz from the digital core is fed to the DC-to-DC

controller. In battery operation mode the output voltage DCDC_OUT1V8 and

DCDC_OUT3V3 can be controlled by three adjust bits. Care has to be taken with signal

levels (level shifters) and the start-up and shut-down from battery to USB and from USB to

battery transitions. A delay circuit uses RING OSC clocks to generate a delay of about

1 ms for the RESET_B pulse. In USB mode the delay can be generated otherwise.

The DC-to-DC converter has to operate from a single or from two batteries. This has no

consequence for the ﬁrst DC-to-DC converter, this is always an up converter. In case a

single battery is used the second converter is also an up converter but it is a down

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converter when two batteries are used. Pin DOWNSEL selects the type of converter and

thus how many batteries are connected. If pin DOWNSEL is HIGH the SAA8200HL

operates from two batteries and the second DC-to-DC converter is a down converter. If

pin DOWNSEL is LOW the SAA8200HL operates from one battery and the second

DC-to-DC converter is an up converter, see Figure 15

upconverter

downconverter

001aac003

Fig 15. Up and down converter topology

7.21.1 Controller

The controller consists of an analog and a digital part. The analog part compares the

output voltage VOUT[1,2] with a programmable voltage window in eight possible adjust

settings. The digital part computes the switching time such that the output voltage stays

within this window. In the analog part is one restive divider with a programmable output,

see Figure 16.

Together with reference voltage V_refthe voltage window is deﬁned. The output of the

resistive divider is compared to the reference voltage with comparators with added offset.

The outputs VTH (voltage too high) and VTL (voltage too low) are based on the

comparison.

When VTH is asserted means that VIN is higher than the upper limit of the window,

indicating to the digital part of the controller that the output voltage must be lowered.

When VTL is asserted it indicates that VIN is lower than the lower limit of the window,

indicating to the digital part of the controller that the output voltage must be higher. When

neither is asserted, VIN is between the lower and upper limit of the window, indicating to

the digital part of the controller that the output voltage is in the limits of the window and it

does not have to change the output voltage. This is the normal mode of operating and is

called continuous mode because the coil continuously carries current.

In continuous mode the digital part of the controller generates switching cycles at a ﬁxed

frequency. During the ﬁrst part of such a cycle (t1) switch 1 will be closed and switch 2 will

be opened, during the last part of the cycle (t2) switch 2 will be closed and switch 1 will be

opened. The length of t1 as a fraction of the cycle time is set such that the required output

voltage is generated. When the output voltage runs outside the window this length is

updated such that the output voltage falls within the window again.

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V

BAT(DCDC)

bias

clk

VOUT[1,2] DCDC[1,2]_ADJUST[2

comparator

VTH[1,2]

comparator

VTL[1,2]

7 ×

V

ss(clean)

001aac004

ss

ref

Fig 16. Analog part of the controller

See Figure 17 for a coil current cycle in continuous mode. The average coil current is

equal to the average current demanded by the load. The lengths of t1 and t2 are

determined by the battery voltage and the output voltage of the DC-to-DC converter. The

output voltage is allowed to vary within a certain window. This means that there will be a

voltage ripple with a frequency that is largely correlated to the frequency content of the

load current. The peak-to-peak amplitude of the ripple will be more or less equal to the

window height. There will be ripple at the switching frequency too, this is mainly caused by

the fact that the coil current will run through parasitic resistances of the load circuit.

I

L

(A)

t (s)

t1

t2

t1

t2

t1

001aac005

Fig 17. Coil current cycle in continuous mode

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See Figure 18 for a coil current cycle in ramp-up mode. The controller enters this mode

when there is an increased demand for energy (voltage falls to below the lower limit). By a

one-time increase of t1 the coil current is increased to a higher average.

I

L

(A)

t (s)

t1

t2

t1

t2

t1

t2

t1

t2

t1

t2

001aac006

Fig 18. Coil current cycle in ramp-up mode

See Figure 19 for a coil current cycle in discontinuous mode. In this mode the coil current

does not ﬂow continuously. Dependent on energy demand a cycle is generated. So

instead of changing the duty cycle as in continuous mode the frequency is changed. This

mode is intended for low power operation. During the ﬁrst phase the battery ramps up the

current from zero and during the second phase it is ramped down to zero by the load. The

coil current is made to decrease to zero by opening both switches shortly before the

current reaches zero. The moment when the switches are to be closed is learned from the

behavior of the DC-to-DC converter in continuous mode.

I

L

(A)

t (s)

t1

t2

t1

t2

001aac007

Fig 19. Coil current cycle in discontinuous mode

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The digital part of the controller consists of a state machine that enables the controller to

switch modes. A decision to jump to a different state is taken on the basis of the outputs of

the analog part. As a result of some of the jumps, the duration of the ﬁrst phase of the

cycle is increased or decreased, see Figure 20.

sample

VTH

VTL

inc. t1

VTL

DISCONTINUOUS

MODE

CONTINUOUS

MODE

RAMP-UP

MODE

dec. t1

VTH

VTL AND VTH

VTL

inc. t1

001aac008

The controller will be in discontinuous mode if adjusted DCDC_OUT1V8 ≤ V_BAT(DCDC)

.

No forward diode from V_BAT(DCDC)to DCDC_OUT1V8 allowed.

Fig 20. Digital part of the controller

7.21.2 Linear regulators

The linear regulators will be implemented as Low Drop voltage Output (LDO) regulators

for a ﬁxed output voltage, see Figure 21. One LDO has to handle input signals in the order

of 5.0 V so a special construction with thick gate oxide is needed. The other LDO handles

an input signal of 3.3 V thus a normal construction with thick gate oxide is sufﬁcient. For

the loop stability the choice is made that the dominant pole lies externally. The series

resistance of Cext (ESR) gives a zero and degrades the stability and thus limited to a

maximum value. For an accurate output voltage a reference voltage is needed. This

voltage can be made with a band gap circuit. A fraction of the output voltage is fed back to

the operation ampliﬁer. In Stop mode the LDOs should be stable to deliver only small

currents.

DCDC_OUT

VIN

EF

ESR

self-biased

operational amplifier

capacitor

ON

Cext

V

SS

SS(clean)

PCB

star ground

001aac009

The on terminal is connected to VUSB_PRESENT.

Fig 21. Principle of LDO

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7.21.3 Timing speciﬁcation

7.21.3.1 Play and stop with battery supply

A negative edge at pin DCDC_PLAY starts the DC-to-DC converter, see Figure 22. When

minimum supply voltages are detected for DCDC_OUT1V8 and DCDC_OUT3V3 by the

POR, the signal SUPPLY_OK is made logic 1. After about 1 ms signal RESET_B

becomes logic 1. When the supply voltages are correct the voltages to the application

control switches rises from V_BAT(DCDC)to DCDC_OUT3V3. New negative edges on pin

DCDC_PLAY has no inﬂuence. When pin DCDC_STOP becomes HIGH the DC-to-DC

converter stops and directly the signal SUPPLY_OK becomes a logic 0.

V

BAT(DCDC),

DCDC_OUT3V3

0

DCDC_PLAY

DCDC_ON

SUPPLY_OK

1 ms

RESET_B

PLAYDET

DCDC_STOP

001aac010

Fig 22. Play and stop with battery supply

The reference circuit, ring oscillator and the POR will be fed by V_DD(ALWAYS). Signal

RESET_B stays at logic 0 for about 1 ms for proper reset. Not shown in Figure 22 is signal

CLK_STABLE, showing the moment for the core clock to become available to the

DC-to-DC converters. As soon as a stable core clock is detected the DC-to-DC converters

will switch to this clock in order to be in-phase with the DAC clock, which will minimize

interference into the audio signal. The SAA8200HL is started up when this has happened.

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7.21.3.2 Play and stop with USB supply

A start-up from the USB supply gives also a RESET_B pulse, see Figure 23. The signal

VUSB is shaped by the bonding pad supplies V_DDIand V_DDE. The disconnection of

V_USB(DCDC)generates a stop pulse.

0

V

USB(DCDC)

DCDC_O

SUPPLY_OK

RESET_B

1 ms

STOP

V

USB_PRESENT

USB_DET

(internal iwab signal)

"V

"

USB

001aac011

Fig 23. Play and stop with USB supply

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7.21.3.3 Change from battery to USB supply

Figure 24 shows the timing diagram with a wireless transceiver changed to USB supply.

The USB supply has the priority. When the USB plug is disconnected the device goes to

the off state. In Idle mode the supplies DCDC_OUT1V8 and DCDC_OUT3V3 has still to

be present, but the LDOs have to deliver only a small current. The total device may not

draw more than 500 mA from the USB supply so a quiescent current of the few active

circuits has to be less then 100 mA each.

V

BAT(DCDC)

0

DCDC_ON

V

USB(DCDC)

supply transients from DCDC to LDO and LDO to off

DCDC_OUT3V3

DCDC_OUT1V8

0

SUPPLY_OK

RESET_B

V

_

USB PRESENT

USB_DET

(internal iwab signal)

STOP

PLAY

PLAYDET

"V

"

USB

DCDC_OUT3V3 and DCDC_OUT1V8

001aac012

Fig 24. Change from battery to USB supply

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8. Limiting values

Table 23: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

V_DDI

core supply voltage

(internal)

−0.5

2.5

V

V_DDE

core supply voltage

(external)

−0.5

4.6

V

V_DDA(1V8)

V_DDA(3V3)

V_I

1.8 V supply voltage

3.3 V supply voltage

input voltage

−0.5

2.5

V

4.6

normal digital input pins

V_DDE+ 0.5

6.0

5 V tolerant digital input

pins

analog input pins

pin XTALH_IN

−0.5

−20

−40

−65

-

V_DDA3v3+ 0.5

2.0

V

T_amb

T_j

ambient temperature

junction temperature

storage temperature

crystal temperature

+70

°C

V

+125

150

T_stg

T_xtal

V_BAT(DCDC)battery voltage

single battery

double battery

0.9

1.8

4.0

1.6

3.2

V

V_USB(DCDC)USB voltage range

5.5

V

[1]

[2]

V_esd

electrostatic

discharge voltage

V

[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.

[2] Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor.

9. Thermal characteristics

Table 24: Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

K/W

R_th(j-a)

thermal resistance from junction to

ambient

in free air

<tbd>

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10. Characteristics

Table 25: Supply voltage characteristics

Symbol

V_DDI

Parameter

Conditions

Min

1.7

2.7

1.7

3.0

2.7

1.7

2.7

4.0

Typ

1.8

3.3

1.8

3.3

1.8

3.3

5.0

Max

2.0

3.6

2.0

3.6

2.0

3.6

5.5

Unit

V

core supply voltage (internal)

core supply voltage (external)

V_DDE

MPMC pins

other

V

V_{DDA(1V8_XTALH)}

V_{DDA(3V3_SPDIF)}

crystal oscillator supply voltage

SPDIF supply voltage

V

V_{DDA(3V3_ADC10B)}control ADC supply voltage

V

V_{DDA(1V8_ADC)}

V_{DDA(3V3_ADC)}

V_{DDA(3V3_DAC)}

V_{DDA(3V3_HP)}

V_USB(DCDC)

audio ADC supply voltage

audio DAC supply voltage

headphone supply voltage

USB supply voltage

V

Table 26: 5 V tolerant cells characteristics

Symbol Parameter

Input circuits

Conditions

Min

Typ

Max

Unit

V_IH

V_IL

HIGH-level input voltage

2.0

-

V

LOW-level input voltage

hysteresis voltage

0.8

-

V_hys

0.4

Output circuits

[1]

V_OH

V_OL

I_OH

HIGH-level output voltage

I_OHdepends on I/O cell type

I_OLdepends on I/O cell type

10 ns slew rate output;

V

_DDE− 0.4

-

V

LOW-level output voltage

-

0.4

-

V

HIGH-level output current

−5

mA

V

_OH= V_DDE− 0.4 V

10 ns slew rate output;

_OL= 0.4 V

HIGH-level short circuit current 10 ns slew rate output;

_OH= 0 V

LOW-level short circuit current 10 ns slew rate output;

_OL= V_DDE

[1]

[2]

I_OL

LOW-level output current

4

-

mA

V

I_sc(H)

I_sc(L)

−45

50

V

-

V

[1] Accounts for 100 mV voltage drop in all supply lines.

[2] Allowed for a short time period.

Table 27: Control ADC characteristics

Symbol Parameter

Conditions

Min

Typ

Max

_REFP− 2

Unit

V_REFN

V_REFP

f_smpl

Z_i

negative reference voltage

positive reference voltage

sampling rate

V_SSA

V_REFN+ 2

400

-

V

V_DDA

1500

39

V

kHz

kΩ

V

input impedance REFN to REFP

input voltage

20

V_i

V_REFN

-

V_REFP

4.5

f_clk

clock frequency

MHz

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Table 27: Control ADC characteristics …continued

Symbol Parameter

Conditions

Min

Typ

Max

10

Unit

bit

N

resolution

2

-

INL

DNL

E_OS

E_FS

t_conv

integral non-linearity

differential non-linearity

offset error

-

±1

LSB

mV

-

±1

−20

-

+20

-

full scale error

conversion time

(N + 1)

cycles

Table 28: Static audio characteristics

Symbol

Audio DAC

V_REFN

Parameter

Conditions

Min

Typ

Max

Unit

negative reference voltage

positive reference voltage

output voltage

-

V_SSA(DAC)

-

V

V_REFP

-

V_{DDA(3V3_DAC)}

-

V

V_O

digital silence

-

0.5V_{DDA(3V3_DAC)}

-

V

[1]

[2]

[3]

during power-down

-

0

1

-

V

R_O

output resistance

load resistance

0.7

>75

-

1.3

kΩ

R_L

-

R_INT

resistance between V_REFPand

V_REFN

4

Headphone ampliﬁer

V_{HP_COM}

V_O(cm)

V_offset

R_L

reference input voltage

-

0.5V_{DDA(3V3_VREFP)}

-

V

common mode output voltage

input offset voltage

-

V_I(ref)

-

V

−10

16

80

180

+10

-

mV

Ω

load resistance

-

I_sc

output current at short circuit

left and right

center

100

200

140

240

mA

Audio ADC

V_{ADC_REFP}positive reference voltage

V_{ADC_REFN}negative reference voltage

V_{ADC_COM}common mode reference voltage

-

V_{DDA(3V3_ADC)}

-

V

0

V

0.5V_{DDA(3V3_ADC)}

V

R_I

C_I

input resistance

12

24

kΩ

pF

input capacitance

Low noise ampliﬁer

R_I

input resistance

output offset voltage

3.5

-

5

-

kΩ

V_offset

1

mV

[1] Set headphone ampliﬁer in Power-down mode before setting audio DAC in Power-down mode because the line output is connected to

the headphone driver the output of the headphone clips towards its analog supply.

[2] Exclusive the input load of the headphone driver which is 10 kΩ.

[3] The output of the DAC is already connected with the headphone driver which has an input load of 10 kΩ.

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Table 29: Dynamic audio characteristics

V_DDA(3V3)= 3.3 V; f_i= 1 kHz at −1 dB; T_amb= 25 °C; R_L= 100 kΩ; f_s= 48 kHz; all voltages measured with respect to ground;

unless otherwise speciﬁed.

Symbol

Audio DAC

V_o(rms)

Parameter

Conditions

Min

Typ

Max

Unit

[1]

output voltage (RMS

value)

at 0 dBFS digital input;

-

1

-

V

∆V_o

unbalance between

channels

<0.1

dB

V_O

output voltage

digital silence

-

0.5V_{DDA(3V3_DAC)}

-

V

during power-down

at 0 dB

0

V

(THD+N)/S total harmonic

distortion-plus-noise to

−80

−40

dB

at −60 dB; A-weighted

signal ratio

S/N

signal-to-noise ratio

code = 0; A-weighted;

bidirectional DWA

-

100

90

-

dB

α_cs

channel separation

Headphone ampliﬁer

P_o(rms)output power (RMS

value)

(THD+N)/S total harmonic

distortion-plus-noise to

at 0 dBFS digital input;

R_L= 16 Ω

-

35

-

mW

at 0 dB; R_L= 16 Ω

at 0 dB; R_L= 5 kΩ

-

62

82

35

97

−52

dB

-

signal ratio

at −60 dB; A-weighted

code = 0; A-weighted

R_L= 16 Ω

S/N

signal-to-noise ratio

channel separation

α_cs

no decoupling capacitors

with decoupling capacitors

−36

−90

-

dB

Audio ADC

∆V_i

unbalance between

channels

-

<1

-

dB

S/N

signal-to-noise ratio

channel separation

V_i= 0 V; A-weighted

f_ripple= 1 kHz;

-

95

-

dB

α_cs

110

PSRR

power supply rejection

ratio

V_ripple(p-p)= 30 mV

V_{DDA(3V3_ADC)}

V_{DDA(3V3_REFP)}

-

−55

−65

−1

-

dB

-

dB

D_o

digital output level

0 dB setting; V_i(rms)= 1.0 V

3 dB setting; V_i(rms)= 708 mV

6 dB setting; V_i(rms)= 501 mV

9 dB setting; V_i(rms)= 354 mV

12 dB setting; V_i(rms)= 252 mV

15 dB setting; V_i(rms)= 178 mV

18 dB setting; V_i(rms)= 125 mV

21 dB setting; V_i(rms)= 89 mV

24 dB setting; V_i(rms)= 63 mV

−2.5

−1

dBFS

SAA8200HL_2

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Table 29: Dynamic audio characteristics …continued

V_DDA(3V3)= 3.3 V; f_i= 1 kHz at −1 dB; T_amb= 25 °C; R_L= 100 kΩ; f_s= 48 kHz; all voltages measured with respect to ground;

unless otherwise speciﬁed.

Symbol

(THD+N)/S total harmonic

distortion-plus-noise to

signal ratio

Parameter

Conditions

at −1 dBFS

Min

Typ

Max

Unit

0 dB setting

3 dB setting

6 dB setting

9 dB setting

12 dB setting

15 dB setting

18 dB setting

21 dB setting

at −60 dBFS

0 dB setting

3 dB setting

6 dB setting

9 dB setting

12 dB setting

15 dB setting

18 dB setting

21 dB setting

24 dB setting

-

−85

−87

−88

−87

−85

−83

−80

-

dB

-

−35

−34

−32

−30

−28

−26

−23

−20

-

dB

LNA plus ADC

V_i(rms)

input voltage (RMS

value)

at 0 dBFS digital output;

R_S= 2.2 kΩ

-

35

mV

(THD+N)/S total harmonic

distortion-plus-noise to

V_o= 600 mV

-

−75

−25

-

dB

at −60 dB; A-weighted

signal ratio

S/N

signal-to-noise ratio

V_i= 0 V; A-weighted

-

85

-

dB

[1] The output voltage of the DAC is proportional to the DAC power supply voltage and the headphone is in Power-down mode.

[2] Exclusive the input load of the headphone driver which is 10 kΩ.

[3] The output of the DAC is already connected with the headphone driver which has an input load of 10 kΩ.

Table 30: DC-to-DC converter characteristics

Symbol

Parameter

Conditions

Min

0.9

1.8

4.0

Typ

1.35

2.7

Max

1.6

3.2

5.5

Unit

V

V_bat

battery voltage

single battery

double battery

V

V_USB

USB voltage

5.0

V

DC-to-DC converter for 3.3 V

V_O

output voltage

3.0

-

3.4

-

3.7

V

V_O(tol)

output voltage tolerance

100

mV

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Table 30: DC-to-DC converter characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_O

output current

V_bat= 2.4 V;

200

-

mA

R_L= 0.3 Ω

V_bat= 2.0 V;

150

-

200

mA

R_L= 0.3 Ω

I_su

start-up current

switch current

switching frequency

clock frequency

efﬁciency

-

25

-

mA

MHz

%

I_sw

f_switch

f_clk

η

-

<tbd>

-

1

-

12

-

V_bat= 2.4 V;

I_O= 100 mA;

R_L= 0.3 Ω

90

93

R_P

PMOST switch on resistance

NMOST switch on resistance

maximum ESR_C

-

0.3

-

Ω

R_N

-

ESR_C

0.7

DC-to-DC converter for 1.8 V

V_O

output voltage

1.3

-

1.85

2.0

50

-

V

V_O(tol)

I_O

output voltage tolerance

output current

-

mV

mA

V_bat= 2.4 V;

100

R_L= 0.3 Ω

V_bat= 2.0 V;

50

-

200

mA

R_L= 0.3 Ω

I_su

start-up current

switch current

switching frequency

clock frequency

efﬁciency

-

10

-

mA

MHz

%

I_sw

f_switch

f_clk

η

-

<tbd>

-

1

-

12

-

V_bat= 2.4 V;

I_O= 50 mA;

R_L= 0.3 Ω

92

95

R_P

PMOST switch on resistance

NMOST switch on resistance

maximum ESRC

-

0.9

-

Ω

R_N

-

ESR_C

0.7

Low-drop-out converter for 3.3 V

V_O

output voltage

unloaded

-

3.5

-

V

I_O= 100 mA

-

3.4

-

V

V_O(tol)

I_O

output voltage tolerance

output current

-

100

200

100

mV

mA

µA

V_USB= 5 V

150

-

I_IDLE

idle current

Low-drop-out converter for 1.8 V

V_O

output voltage

unloaded

-

1.95

-

V

I_O= 50 mA

-

1.85

-

V

V_O(tol)

I_O

output voltage tolerance

output current

-

50

100

mV

mA

V_USB= 5 V

50

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Table 30: DC-to-DC converter characteristics …continued

Symbol

Ring oscillator

I_DDA

Parameter

Conditions

Min

Typ

Max

Unit

current consumption

-

100

-

µA

f_OSC

oscillator output frequency

12

MHz

Table 31: SRI characteristics

Symbol

LVDS buffer

Static

I_DDA

Parameter

Conditions

Min

Typ

Max

Unit

supply current

-

150

-

µA

pF

I_DDA(pd)

C_L

power-down supply current

load capacitor

-

1

5

-

R_O

output voltage as ratio of the digital

supply voltage

0.25

V_I(det)

input voltage required for detection

-

100

-

mV

Dynamic

f_clk(max)

maximum clock frequency

1

MHz

Table 32: Timing characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Crystal oscillator

Static

C_{i(XTALH_IN)}

parasitic input capacitance pin

XTALH_IN

<tbd>

100

pF

Ω

R_{i(XTALH_IN)}

parasitic input resistance pin

XTALH_IN

f_i= 12 MHz

P_drive

Dynamic

f_osc

crystal level of driver power

-

500

µW

oscillator frequency

duty cycle

-

12

-

MHz

%

α_cl

50

t_su

start-up time

500

ms

Serial interface input and output data timing; see Figure 25

f_BCK

bit clock frequency

bit clock cycle time

-

128f_s

Hz

s

1

T_cy(BCK)

T_cy(s)is sample

frequency cycle

time

⁄₁₂₈T_cy(s)

t_BCKH

t_BCKL

t_r

bit clock HIGH time

bit clock LOW time

rise time

30

-

ns

20

-

t_f

fall time

-

t_su(WS)

t_h(WS)

t_su(I2SIN)

t_h(I2SIN)

SAA8200HL_2

word select setup time

word select hold time

data input setup time

data input hold time

10

-

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Table 32: Timing characteristics …continued

Symbol

Parameter

Conditions

Min

Typ

Max

-

Unit

ns

t_h(I2SOUT)

data output hold time

data output to bit clock delay

data output to word select delay

0

-

t_{d(I2SOUT_BCK)}

t_{d(I2SOUT_WS)}

30

ns

-

ns

Standard mode I²C-bus; SDA and SCL lines

100 kHz mode

f_SCL

SCL clock frequency

0

-

100

kHz

µs

t_LOW

SCL clock LOW period

SCL clock HIGH period

hold time start condition

setup time start condition

setup time stop condition

4.7

4.0

4.7

4.0

4.7

-

t_HIGH

t_HD;STA

t_SU;STA

t_SU;STO

t_BUF

bus free time between a stop and

start condition

t_HD;DAT

t_SU;DAT

t_r

data hold time

5.0

-

0.9

-

µs

ns

data setup time

250

rise time SDA and SCL

fall time SDA and SCL

-

1000

300

t_f

400 kHz mode

f_SCL

SCL clock frequency

0

-

400

kHz

µs

t_LOW

SCL clock LOW period

SCL clock HIGH period

hold time start condition

setup time repeated start

setup time stop condition

1.3

0.6

1.3

-

t_HIGH

t_HD;STA

t_SU;STA

t_SU;STO

t_BUF

bus free time between a stop and

start condition

t_HD;DAT

data hold time

0

-

µs

ns

pF

t_SU;DAT

data setup time

100

-

t_r

rise time SDA and SCL

fall time SDA and SCL

pulse width of spikes

capacitive load for each bus line

20 + 0.1C_b

300

50

400

t_f

20 + 0.1C_b

t_SP

C_b

0

-

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WS

t

h(WS)

r

f

d(I2SOUT_BCK)

BCKH

t

su(WS)

BCK

t

BCKL

t

d(I2SOUT_WS)

h(I2SOUT)

T

cy(BCK)

I2SIN

t

su(I2SIN)

t

h(I2SIN)

I2SOUT

001aab634

Fig 25. Serial interface input data timing

Table 33: Filter characteristics

Description

Conditions

Value

Unit

Decimation ﬁlter

Pass band ripple

Stop band

up to 0.45f_s

from 0.55f_s

DC

±0.02

−60

3

dB

Overall gain

Dynamic range

Droop

up to 0.45f_s

at 0.45f_s

140

−0.18

DC blocking ﬁlter 1

Pass band ripple

Pass band gain

Droop

none

0

dB

at 0.00045f_s

up to 0.45f_s

0.5

DC attenuation

Dynamic range

DC blocking ﬁlter 2

Pass band ripple

Pass band gain

Droop

> 40

> 110

none

0

dB

at 0.00045f_s

up to 0.45f_s

0.031

> 40

> 110

DC attenuation

Dynamic range

Interpolation ﬁlter

pass band ripple

stop band

up to 0.4535f_s

from 0.5465f_s

pass band

±0.02

−72

dB

gain

−1.1

>143

dynamic range

up to 0.4535f_s

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12. Package outline

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm

SOT407-1

y

X

A

51

75

50

26

(1)

76

Z

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

detail X

100

1

25

Z

D

v

M

A

B

e

w M

b

p

D

B

H

v

M

5

D

0

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

θ

1

2

3

p

E

p

D

E

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 14.1 14.1

0.17 0.09 13.9 13.9

16.25 16.25

15.75 15.75

0.75

0.45

1.15 1.15

0.85 0.85

mm

1.6

0.25

0.5

1

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-02-01

03-02-20

SOT407-1

136E20

MS-026

Fig 28. Package outline SOT407-1 (LQFP100)

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13. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

integrated circuits.

14. Soldering

14.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

14.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

14.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

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• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

14.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

14.5 Package related soldering information

Table 34: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

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[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

15. Additional soldering information

15.1 Lead-free solder

Lead-free solder can be used for soldering the TEA7000.

15.2 MSL level

MSL level: <tbd>

16. Revision history

Table 35: Revision history

Document ID

SAA8200HL_2

Modiﬁcations:

Release date Data sheet status

20051017 Preliminary data sheet

• Audio ADC supply voltages added (Table 25).

Change notice Doc. number

Supersedes

-

SAA8200HL_1

• Audio DAC R_Lvalue revised; V_{HP_COM}value corrected; V_{ADC_COM}value added (Table 28).

• Dynamic audio characteristics revised (Table 29).

SAA8200HL_1

20041217

Objective data sheet

-

9397 750 13236

-

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17. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

18. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

20. Trademarks

Notice — All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.

Ensation — is a trademark of Koninklijke Philips Electronics N.V.

19. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

21. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

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22. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.19.2.3 Soft start-up after reset . . . . . . . . . . . . . . . . . 38

7.19.2.4 Signal polarity. . . . . . . . . . . . . . . . . . . . . . . . . 38

7.19.2.5 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.19.2.6 Overﬂow detection . . . . . . . . . . . . . . . . . . . . . 39

7.19.2.7 AGC function . . . . . . . . . . . . . . . . . . . . . . . . . 39

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1

2.2

2.3

7.20

7.20.1

Audio output . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3

4

5

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.20.1.1 Features of the SDAC . . . . . . . . . . . . . . . . . . 40

7.20.1.2 Functional description . . . . . . . . . . . . . . . . . . 41

7.20.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.20.1.4 Silence detection . . . . . . . . . . . . . . . . . . . . . . 43

7.20.1.5 Polarity control . . . . . . . . . . . . . . . . . . . . . . . . 43

7.20.1.6 Digital upsampling ﬁlter . . . . . . . . . . . . . . . . . 43

7.20.1.7 Noise shaper . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.20.1.8 SDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.20.1.9 Data weighting averaging. . . . . . . . . . . . . . . . 44

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

7.1

7.1.1

7.2

7.2.1

7.3

7.3.1

7.3.2

7.3.3

7.4

7.5

7.6

Functional description . . . . . . . . . . . . . . . . . . 10

EPICS7B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

User registers . . . . . . . . . . . . . . . . . . . . . . . . . 14

VPB0 bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 15

VPB0 bridge address deﬁnitions . . . . . . . . . . 15

Clock generation unit . . . . . . . . . . . . . . . . . . . 23

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 24

Audio PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Serial radio interface. . . . . . . . . . . . . . . . . . . . 25

SRI I²C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

System I²C-bus interface . . . . . . . . . . . . . . . . 26

Control ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 26

Reed-Solomon codec . . . . . . . . . . . . . . . . . . . 27

Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPDIF inputs. . . . . . . . . . . . . . . . . . . . . . . . . . 29

I²S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

I²S-bus inputs . . . . . . . . . . . . . . . . . . . . . . . . . 31

I²S-bus outputs . . . . . . . . . . . . . . . . . . . . . . . . 31

Time stamp counters . . . . . . . . . . . . . . . . . . . 31

DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 32

I/O conﬁguration . . . . . . . . . . . . . . . . . . . . . . . 32

VPB1 bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 33

UART conﬁguration. . . . . . . . . . . . . . . . . . . . . 33

Audio conﬁguration. . . . . . . . . . . . . . . . . . . . . 34

Audio input . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

ADC analog front-end. . . . . . . . . . . . . . . . . . . 34

7.20.2

Headphone. . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.20.2.1 Headphone driver. . . . . . . . . . . . . . . . . . . . . . 45

7.20.2.2 Headphone Limiter. . . . . . . . . . . . . . . . . . . . . 45

7.21

DC-to-DC converter . . . . . . . . . . . . . . . . . . . . 46

Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Linear regulators . . . . . . . . . . . . . . . . . . . . . . 50

Timing speciﬁcation . . . . . . . . . . . . . . . . . . . . 51

7.21.1

7.21.2

7.21.3

7.21.3.1 Play and stop with battery supply. . . . . . . . . . 51

7.21.3.2 Play and stop with USB supply . . . . . . . . . . . 52

7.21.3.3 Change from battery to USB supply. . . . . . . . 53

7.7

7.8

7.9

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 54

Thermal characteristics . . . . . . . . . . . . . . . . . 54

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 55

Application information . . . . . . . . . . . . . . . . . 64

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 65

Handling information . . . . . . . . . . . . . . . . . . . 66

7.10

7.11

7.12

7.12.1

7.12.2

7.13

7.14

7.15

7.16

7.17

7.18

7.19

7.19.1

9

10

11

12

13

14

14.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 66

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 66

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 67

Package related soldering information. . . . . . 67

14.2

14.3

14.4

14.5

7.19.1.1 Applications and Power-down modes. . . . . . . 34

7.19.1.2 LNA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.19.1.3 PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.19.1.4 Applications with 2 V (RMS) input . . . . . . . . . 35

7.19.1.5 SDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

15

15.1

15.2

Additional soldering information. . . . . . . . . . 68

Lead-free solder. . . . . . . . . . . . . . . . . . . . . . . 68

MSL level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

16

17

18

19

Revision history . . . . . . . . . . . . . . . . . . . . . . . 68

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 69

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.19.2

Decimation ﬁlter (ADC). . . . . . . . . . . . . . . . . . 36

7.19.2.1 Volume control . . . . . . . . . . . . . . . . . . . . . . . . 37

7.19.2.2 DC blocking ﬁlter. . . . . . . . . . . . . . . . . . . . . . . 37

continued >>

SAA8200HL_2

Preliminary data sheet

Rev. 02 — 17 October 2005

70 of 71

SAA8200HL

Philips Semiconductors

Ensation Base integrated wireless audio baseband

20

21

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Contact information . . . . . . . . . . . . . . . . . . . . 69

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 17 October 2005

Document number: SAA8200HL_2

Published in The Netherlands


型号：	SAA8200HL
厂家：	NXP
描述：	Ensation Base integrated wireless audio baseband Ensation基地集成无线音频基带处理商用集成电路无线
文件：	总71页 (文件大小：288K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAA8200HL [NXP]

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