SAF3560HV1101 [NXP]
Terrestrial digital radio processor Providing new data services; 地面数字无线电处理器提供了新的数据服务
| 型号： | SAF3560HV1101 |
| 厂家： | 
NXP |
| 描述： | Terrestrial digital radio processor Providing new data services |
| 文件： | 总20页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SAF3560
Terrestrial digital radio processor
Rev. 03 — 15 September 2010
Product short data sheet
1. General description
The SAF3560 is a digital radio processor that demodulates and processes digital
terrestrial baseband signals, such as HD Radio signals, into audio signals and digital data
signals.
OPTIONAL AUDIO POST
blended
audio (analog)
PROCESSING
AND STEREO
AUDIO DAC
TUNER1
IF PROCESSING
baseband blend digital
2
I S
audio
interface
SERIAL NOR-FLASH
MEMORY
SPI2
SAF3560
SDRAM
2
I C-bus or SPI1
2
baseband I S
interface
RENDERING
OF DATA:
TUNER2
IF PROCESSING
MICROPROCESSOR
LIVE TRAFFIC REPORTS
WEATHER
SPORTS SCORES
STOCK TICKER
001aal423
(1) Second input only supported by specific types (see Table 3)
Fig 1. System block diagram
Major benefits of terrestrial radio processor systems with SAF3560 are:
• Compatibility with conventional baseband radio reception ICs
• Dramatically improved reception and sound quality
• CD-sound quality without noise, interference and multipath fading for FM
• Providing new data services
• HD Radio reception including audio processing
• Voltage partitioning of I/Os
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
System designers can add digital terrestrial radio capability in a simple and inexpensive
way through the SAF3560. The SAF3560 decodes digital radio input to provide digital
audio and also processes digital data. Multiple interfaces give flexibility while integrating
the SAF3560 into the receiver system.
2. Features and benefits
2.1 HD Radio technology
HD Radio signal decoding for AM and FM digital audio
Dual HD Radio support for support of 2nd station for background scanning and data
service
Front-end to baseband interface support through serial baseband I2S-bus type
interface
Secondary baseband interface for dual tuner applications
Metadata support for HD Radio reception
Data services support for HD Radio reception
Advanced HD Radio feature support, such as1:
Conditional Access (CA)
Store and replay
Apple ID3 tag
Multicasting
Electronic Program Guide (EPG)
2.2 Digital audio
Up to 6 channel (5.1) audio support through I2S-bus serial audio interface
Optional SRC (8 kHz to 48 kHz) for up to 6 channels of I2S-bus audio output
I2S-bus serial audio input for auxiliary processing
Optional SRC (8 kHz to 48 kHz) for I2S-bus input
Optional restricted support for 96 kHz input and output sample-rate conversion
Optional digital audio output through S/PDIF (without SRC)
Basic audio processing for external digital audio sources
Advanced audio processing (please contact NXP for a list of supported audio
processing features: Section 14 “Contact information”)
2.3 Memory
Supports SDR-SDRAM controller (up to 512 Mbit in 16-bit configuration)
Supports serial NOR-Flash memory with various sizes depending on the actual
application
1. Please contact NXP for a detailed list of supported feature sets: Section 14 “Contact information”.
SAF3560_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product short data sheet
Rev. 03 — 15 September 2010
2 of 20
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
2.4 Other peripheral interfaces
Two I2C-bus interfaces
Three Serial Peripheral Interfaces (SPI)
One UART interface
Five individual GPIO pins for applications and diagnostics
One JTAG interface for diagnostics
2.5 Miscellaneous
One internal clock oscillator and two internal Phase-Locked Loops (PLL)
Powerful signal and audio processing core architecture
Qualified in accordance with AEC-Q100
3. Quick reference data
Table 1.
Power supply characteristics
After power-up the SAF3560 needs a reset pulse for at least 2 ms.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Supply voltages
VDDA(OSC)(1V2)
VDDA(PLL)(1V2)
VDDD(C)(1V2)
oscillator analog supply voltage (1.2 V)
PLL analog supply voltage (1.2 V)
core digital supply voltage (1.2 V)
DAB digital supply voltage (3.3 V)
DSP digital supply voltage (3.3 V)
JTAG digital supply voltage (3.3 V)
microcontroller digital supply voltage (3.3 V)
memory digital supply voltage (1.2 V)
1.14 1.2
1.14 1.2
1.14 1.2
1.32
1.32
1.32
3.6
V
V
V
V
V
V
V
V
V
VDDD(DAB)(3V3)
VDDD(DSP)(3V3)
VDDD(JTAG)(3V3)
VDDD(MC)(3V3)
VDDD(MEM)(1V2)
3.0
3.0
3.0
3.0
3.3
3.3
3.3
3.3
3.6
3.6
3.6
1.14 1.2
1.32
3.6
VDDD(SDRAM)(3V3) SDRAM digital supply voltage (3.3 V)
3.0
3.3
Supply currents
[1]
[2]
IDD
supply current
all core related blocks
all I/O related blocks
-
-
90
28
116
37
mA
mA
Power dissipation
Ptot
total power dissipation
-
0.2
0.5
W
[1] Through pins VDDA(OSC)(1V2), VDDA(PLL)(1V2), VDDD(C)(1V2) and VDDD(MEM)(1V2)
.
[2] Through pins VDDD(DAB)(3V3), VDDD(DSP)(3V3), VDDD(JTAG)(3V3), VDDD(MC)(3V3) and VDDD(SDRAM)(3V3)
.
SAF3560_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product short data sheet
Rev. 03 — 15 September 2010
3 of 20
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
4. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
SAF3560HV/V1100
SAF3560HV/V1101
SAF3560HV/V1102
SAF3560HV/V1103
HLQFP144 plastic thermal enhanced low profile quad flat package; 144 leads;
SOT612-4
SOT612-4
SOT612-4
SOT612-4
body 20 × 20 × 1.4 mm; exposed die pad
HLQFP144 plastic thermal enhanced low profile quad flat package; 144 leads;
body 20 × 20 × 1.4 mm; exposed die pad
HLQFP144 plastic thermal enhanced low profile quad flat package; 144 leads;
body 20 × 20 × 1.4 mm; exposed die pad
HLQFP144 plastic thermal enhanced low profile quad flat package; 144 leads;
body 20 × 20 × 1.4 mm; exposed die pad
Table 3.
Main applications
Type number
Main application
Option
SAF3560HV/V1100
SAF3560HV/V1101
SAF3560HV/V1102
SAF3560HV/V1103
HD Radio 1.0
single tuner
single tuner
dual tuner
dual tuner
HD Radio 1.0 + Conditional Access (CA)
HD Radio 1.5
HD Radio 1.5 + Conditional Access (CA)
SAF3560_SDS
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© NXP B.V. 2010. All rights reserved.
Product short data sheet
Rev. 03 — 15 September 2010
4 of 20
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xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
RESET_N
RESET
XTAL
JTAG
JTAG
CONTROLLER
CGU
CLOCK
SAF3560
SPI1 (host)
SPI2 (FLASH)
SPI3 (tuner)
FLASH
I/O
2
2 × I C-bus
CONTROLLER
internal bus
SDRAM
MEMORY
CONTROLLER
GPIO
UART
SDRAM
I/O
MUX
RADIO
AUDIO
SUB SYSTEM
SUB SYSTEM
baseband interface 1
(HD Radio)
DUAL
CHANNEL
RADIO
SINGLE
CHANNEL
AUDIO
FILTER
AND
SRC
3 × audio
AUDIO
SRC
2
I S output
baseband interface 2
(HD Radio)
(1 × audio and
data
(optional S/PDIF)
1 × data only)
2
001aal422
audio I S input
BLEND
Fig 2. Block diagram of SAF3560
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
6. Pinning information
6.1 Pinning
SAF3560
1
108
36
73
001aah072
Fig 3. Pin configuration (HLQFP144)
Table 4.
Pin allocation table (HLQFP144)
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol
1
CLKOUT
2
RESET_N
3
I2C1_SCL
I2C2_SCL
SPI1_SI
4
I2C1_SDA
I2C2_SDA
SPI1_SCLK
SPI2_MI
5
I2C1_DA
6
VDDD(MC)(3V3)
SPI1_SO
VDDD(C)(1V2)
SPI2_SCLK
SPI2_SS3_N
UART_RTS
SPI3_MISO
VDDD(DAB)(3V3)
GPIO2
7
8
9
I2C2_DA
10
14
18
22
26
30
34
38
42
46
50
54
58
62
66
70
74
11
15
19
23
27
31
35
39
43
47
51
55
59
63
67
71
75
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
13
17
21
25
29
33
37
41
45
49
53
57
61
65
69
73
SPI1_SS_N
SPI2_MO
VDDD(MC)(3V3)
UART_RD
UART_CTS
SPI3_SS1_N
GPIO1
VDDD(MC)(3V3)
SPI2_SS1_N
SPI2_SS4_N
VDDD(C)(1V2)
SPI3_MOSI
SPI3_SS2_N
GPIO3
SPI2_SS2_N
UART_TD
VDDD(MC)(3V3)
SPI3_SCLK
GPIO0
GPIO4
[1]
-
VDDD(DAB)(3V3)
-
-
-
-
-
-
-
-
-
-
-
-
BB1_I2S_BCK
BB2_I2S_BCK
VDDD(C)(1V2)
I2S1_O_WS
VDDD(DSP)(3V3)
I2S_I_BCK
BB1_I2S_WS
BB2_I2S_WS
VDDD(DSP)(3V3)
I2S1_O_SD
I2S2_O_SD
I2S_I_SD
BB1_I2S_I
BB2_I2S_I
HBCKOUT
BLEND
BB1_I2S_Q
BB2_I2S_Q
I2S1_O_BCK
VDDD(MEM)(1V2)
I2S_I_WS
I2S3_O_SD/
SPDIF_O
77
81
85
89
SDRAM_DIO0
SDRAM_DIO3
78
82
SDRAM_DIO1
SDRAM_DIO4
SDRAM_DIO7
79
83
87
SDRAM_DIO2
SDRAM_DIO5
SDRAM_DIO8
VDDD(C)(1V2)
80
84
88
92
VDDD(SDRAM)(3V3)
SDRAM_DIO6
SDRAM_DIO9
SDRAM_DIO11
VDDD(SDRAM)(3V3) 86
SDRAM_DIO10 90
VDDD(SDRAM)(3V3) 91
SAF3560_SDS
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© NXP B.V. 2010. All rights reserved.
Product short data sheet
Rev. 03 — 15 September 2010
6 of 20
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
Table 4.
Pin allocation table (HLQFP144) …continued
Pin Symbol Pin Symbol
SDRAM_DIO12 94 SDRAM_DIO13 95 SDRAM_DIO14 96
SDRAM_DIO15 98 SDRAM_WE_N 99 SDRAM_DQM0 100 SDRAM_DQM1
103 SDRAM_BA0 104 SDRAM_BA1
106 SDRAM_RAS_N 107 VDDD(SDRAM)(3V3) 108 SDRAM_CAS_N
Pin Symbol
Pin Symbol
VDDD(SDRAM)(3V3)
93
97
101 VDDD(SDRAM)(3V3) 102 VDDD(MEM)(1V2)
105 SDRAM_CS_N
109 SDRAM_CLKE
113 SDRAM_AO2
117 SDRAM_AO5
121 SDRAM_AO9
125 SDRAM_AO11
110 SDRAM_AO0
114 SDRAM_AO3
118 SDRAM_AO6
111 SDRAM_AO1
115 SDRAM_AO4
119 SDRAM_AO7
112 VDDD(SDRAM)(3V3)
116 VDDD(SDRAM)(3V3)
120 SDRAM_AO8
124 VDDD(C)(1V2)
128 SDRAM_CLKIN
132 TCK
122 VDDD(SDRAM)(3V3) 123 SDRAM_AO10
126 SDRAM_AO12
127 SDRAM_CLK
131 TRST_N
[2]
129 VDDD(SDRAM)(3V3) 130 VSS
133 TMS
134 VDDD(C)(1V2)
135 TDI
136 TDO
[2]
137 VSS
138 VDDD(JTAG)(3V3)
142 XTALO
139 VDDA(PLL)(1V2)
143 VDDD(MEM)(1V2)
140 VDDA(OSC)(1V2)
[2]
141 XTALI
144 VSS
[1] See Table 14 for unused pins.
[2] Global VSS pin at backside contact
6.2 Pin description
Table 5.
Pin description overview
Pin category
Details
Table number
Table 6
Power supply pins
analog and digital supply pins
baseband and audio pins (I2S-bus)
GPIO and SPI3 pins
Baseband interface pins
Generic interface pins
SDRAM interface pins
Serial NOR-Flash interface pins
Table 7
Table 8
data, address and control pins
SPI2 pins
Table 9
Table 10
Table 11
External host microcontroller
interface pins
SPI1, I2C1, I2C2, UART, CLKOUT
and RESET_N pins
JTAG interface pins
Crystal oscillator pins
JTAG pins
Table 12
Table 13
XTALI and XTALO pins
Table 6.
Symbol
Pin description (power supplies)
Pin
Type[1] Description
Global ground supply
VSS
130, 137, 144 and
G
analog and digital global ground supply
backside contact
Analog supplies
VDDA(OSC)(1V2)
VDDA(PLL)(1V2)
Digital supplies
VDDD(C)(1V2)
140
139
P
P
oscillator analog supply voltage (1.2 V)
PLL analog supply voltage (1.2 V)
14, 27, 63, 91, 124 and
134
P
P
core digital supply voltage (1.2 V)
DAB digital supply voltage (3.3 V)
VDDD(DAB)(3V3)
34 and 42
SAF3560_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product short data sheet
Rev. 03 — 15 September 2010
7 of 20
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
Table 6.
Pin description (power supplies) …continued
Symbol
Pin
Type[1] Description
VDDD(DSP)(3V3)
VDDD(JTAG)(3V3)
VDDD(MC)(3V3)
64 and 71
138
P
P
P
DSP digital supply voltage (3.3 V)
JTAG digital supply voltage (3.3 V)
6, 15, 21 and 28
microcontroller digital supply voltage
(3.3 V)
VDDD(SDRAM)(3V3) 80, 85, 90, 96, 101, 107,
112, 116, 122 and 129
P
P
SDRAM digital supply voltage (3.3 V)
VDDD(MEM)(1V2)
70, 102 and 143
memory digital supply voltage (1.2 V)
[1] Table 15 defines the pin type.
Table 7.
Symbol
Pin description (baseband interface)
Pin
Type[1] Description
Baseband interface
BB1_I2S_BCK 55
IOZU-H bit clock input and output of first baseband interface
BB1_I2S_I
BB1_I2S_Q
BB1_I2S_WS
BLEND
57
58
56
69
IZU-H
IZU-H
I data input line of first baseband interface
Q data input line of first baseband interface
IOZU-H word select input and output line of first baseband interface
OL
blend indicator output,
HIGH = digital audio / LOW = analog radio[2]
BB2_I2S_BCK 59
IOZU-H bit clock input and output of second baseband interface
BB2_I2S_I
61
62
60
IZU-H
IZU-H
I data input line of second baseband interface
Q data input line of second baseband interface
BB2_I2S_Q
BB2_I2S_WS
IOZU-H word select input and output line of second baseband
interface
Audio interface
HBCKOUT
I2S_I_BCK
I2S_I_SD
65
75
76
74
73
IOZU
IOZU-H bit clock input and output line of I2S-bus input interface
IZU-H
serial data input line of I2S-bus input interface
IOZU-H word select input and output line of I2S-bus input interface
high-speed bit clock output[3]
I2S_I_WS
I2S3_O_SD/
SPDIF_O
OL
serial data output line of third I2S-bus output interface;
in alternative Sony/Philips digital output interface
I2S2_O_SD
I2S1_O_BCK
I2S1_O_SD
I2S1_O_WS
72
66
68
67
OL
serial data output line of second I2S-bus output interface
IOZU-H bit clock input and output line of first I2S-bus output interface
OL
serial data output line of first I2S-bus output interface
IOZU-H word select input and output line of first I2S-bus output
interface
[1] Table 15 defines the pin type.
[2] Required for seamless switching between digital and analog AM/FM modes in HD Radio applications under
bad reception conditions.
[3] 256 × fS output, required by some external DACs.
SAF3560_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product short data sheet
Rev. 03 — 15 September 2010
8 of 20
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
Table 8.
Symbol
GPIO interface
Pin description (generic tuner interface)
Pin
Type[1] Description
GPIO4
40
IOZU
IOZU
IOZU
IOZU
IOZU
general purpose input and output port 4
general purpose input and output port 3
GPIO3
39
38
37
36
GPIO2
general purpose input and output port 2
general purpose input and output port 1
general purpose input and output port 0
GPIO1
GPIO0
SPI3 interface
SPI3_MISO 30
SPI3_MOSI 31
SPI3_SCLK 32
SPI3_SS1_N 33
SPI3_SS2_N 35
IOZU-H master input, slave output of third SPI interface
IOZU-H master output, slave input of third SPI interface
IOZU-H serial clock input and output of third SPI interface
IOZU-H slave select 1 input and output of third SPI interface (active LOW)
OZU
slave select 2 output of third SPI interface (active LOW)
[1] Table 15 defines the pin type.
Table 9.
Symbol
Pin description (SDRAM interface)
Pin
Type[1] Description
Data input and output interface
SDRAM_DIO15
SDRAM_DIO14
SDRAM_DIO13
SDRAM_DIO12
SDRAM_DIO11
SDRAM_DIO10
SDRAM_DIO9
SDRAM_DIO8
SDRAM_DIO7
SDRAM_DIO6
SDRAM_DIO5
SDRAM_DIO4
SDRAM_DIO3
SDRAM_DIO2
SDRAM_DIO1
SDRAM_DIO0
97
95
94
93
92
89
88
87
86
84
83
82
81
79
78
77
IOL
IOL
IOL
IOL
IOL
IOL
IOL
IOL
IOL
IOL
IOL
IOL
IOL
IOL
IOL
IOL
data input and output bit 15
data input and output bit 14
data input and output bit 13
data input and output bit 12
data input and output bit 11
data input and output bit 10
data input and output bit 9
data input and output bit 8
data input and output bit 7
data input and output bit 6
data input and output bit 5
data input and output bit 4
data input and output bit 3
data input and output bit 2
data input and output bit 1
data input and output bit 0
Address output interface
SDRAM_AO12
SDRAM_AO11
SDRAM_AO10
SDRAM_AO9
SDRAM_AO8
SDRAM_AO7
SDRAM_AO6
126
125
123
121
120
119
118
OZU
OZU
OZU
OZU
OZU
OZU
OZU
address output bit 12
address output bit 11
address output bit 10
address output bit 9
address output bit 8
address output bit 7
address output bit 6
SAF3560_SDS
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© NXP B.V. 2010. All rights reserved.
Product short data sheet
Rev. 03 — 15 September 2010
9 of 20
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
Table 9.
Pin description (SDRAM interface) …continued
Symbol
Pin
117
115
114
113
111
110
Type[1] Description
SDRAM_AO5
SDRAM_AO4
SDRAM_AO3
SDRAM_AO2
SDRAM_AO1
SDRAM_AO0
Control interface
SDRAM_BA1
SDRAM_BA0
OZU
OZU
OZU
OZU
OZU
OZU
address output bit 5
address output bit 4
address output bit 3
address output bit 2
address output bit 1
address output bit 0
104
103
OZU
OZU
OZU
OZU
OZU
IZU
bit 1 of bank address output
bit 0 of bank address output
SDRAM_CAS_N 108
column address selector output (active LOW)
clock output
SDRAM_CLK
127
109
128
105
100
99
SDRAM_CLKE
SDRAM_CLKIN
SDRAM_CS_N
SDRAM_DQM1
SDRAM_DQM0
clock enable output
clock input for re-synchronization
chip select output (active LOW)
MSByte of data qualifier mask output
LSByte of data qualifier mask output
row address selector output (active LOW)
write enable output (active LOW)
OZU
OL
OL
SDRAM_RAS_N 106
SDRAM_WE_N 98
OZU
OZU
[1] Table 15 defines the pin type.
Table 10. Pin description (serial NOR-Flash interface)
Symbol
Pin
Type[1] Description
SPI2 interface
SPI2_MI
16
17
IZU
master input of second SPI interface
SPI2_MO
OZD
OZU
OZU
OZU
OZU
OZU
master output of second SPI interface
SPI2_SCLK 18
SPI2_SS1_N 19
SPI2_SS2_N 20
SPI2_SS3_N 22
SPI2_SS4_N 23
serial clock output of second SPI interface
slave select 1 output of second SPI interface (active LOW)
slave select 2 output of second SPI interface (active LOW)
slave select 3 output of second SPI interface (active LOW)
slave select 4 output of second SPI interface (active LOW)
[1] Table 15 defines the pin type.
SAF3560_SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product short data sheet
Rev. 03 — 15 September 2010
10 of 20
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
Table 11. Pin description (external host microcontroller interface)
Symbol
Pin
Type[1] Description
CLKOUT
1
OL
clock output; clock source and clock frequency are
programmable through software
RESET_N
2
IZU-H
master reset input from host microcontroller (active LOW)
I2C-bus interface (master and slave)
I2C2_DA
9
7
8
5
3
4
IOZD-H data acknowledge input and output of the I2C-bus interface 2
I2C2_SCL
I2C2_SDA
I2C1_DA
IOZU
serial clock input and output of the I2C-bus interface 2
serial data input and output of the I2C-bus interface 2
IOZU
IOZD-H data acknowledge input and output of the I2C-bus interface 1
IOZU
serial clock input and output of the I2C-bus interface 1
IOZU-H serial data input and output of the I2C-bus interface 1
I2C1_SCL
I2C1_SDA
SPI1 interface
SPI1_SCLK 12
IZU-H
IZU-H
OL
serial clock input of first SPI interface
slave input of first SPI interface
SPI1_SI
11
10
SPI1_SO
slave output of first SPI interface
SPI1_SS_N 13
UART interface
UART_CTS 29
IZU-H
slave select input of first SPI interface (active LOW)
IZU
IZU
OH
OH
UART clear-to-send signal input
UART receive data input
UART_RD
UART_RTS 26
UART_TD 24
25
UART ready-to-send signal output
UART transmit data output
[1] Table 15 defines the pin type.
Table 12. Pin description (JTAG interface)
Symbol
TCK
Pin
132
135
136
133
131
Type[1] Description
IZU
IZU
OL
test clock input
TDI
test serial data input
TDO
test serial data output
TMS
IZU
IZU
test mode select input
TRST_N
test reset input; drive LOW for normal operating
[1] Table 15 defines the pin type.
Table 13. Pin description (crystal oscillator)
Symbol
XTALI
Pin
141
142
Type[1] Description
AI
crystal oscillator analog input
crystal oscillator analog output
XTALO
AO
[1] Table 15 defines the pin type.
Table 14. Pin description (internally connected pins)
Symbol
Pin
Type
Description
i.c.
41,
-
internally connected; leave open
43 to 54
SAF3560_SDS
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Product short data sheet
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SAF3560
NXP Semiconductors
Terrestrial digital radio processor
Table 15. Pin type description
Type Description
Generic pin types
Unused pins[1]
AI
analog input pin
always connect to quartz crystal
always connect to quartz crystal
use all ground pins
AO
G
analog output pin
ground pin
IOL
IOZD
IOZU
IZU
OH
OL
digital input and output; drives LOW after reset
can be left open
digital input and output pin with weak pull-down can be left open
digital input and output pin with weak pull-up
digital input pin with weak pull-up
digital output; drives HIGH after reset
digital output; drives LOW after reset
digital output pin with weak pull-down
digital output pin with weak pull-up
power supply pin
can be left open
can be left open
can be left open
can be left open
can be left open
can be left open
use all power supply pins
OZD
OZU
P
Specific pin types
-H pins with hysteresis
see generic types
[1] Applications, which do not need all pins from SAF3560, can treat unused pins as indicated without damage
or malfunction of the device.
SAF3560_SDS
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Product short data sheet
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SAF3560
NXP Semiconductors
Terrestrial digital radio processor
7. Limiting values
Table 16. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−0.5
−0.5
−0.5
−0.5
−0.5
−0.5
−40
−65
-
Max
+1.7
+1.7
+1.7
+3.9
+3.9
+3.9
+3.9
+3.9
+1.7
+85
Unit
V
VDDA(OSC)(1V2)
VDDA(PLL)(1V2)
VDDD(C)(1V2)
oscillator analog supply voltage (1.2 V)
PLL analog supply voltage (1.2 V)
core digital supply voltage (1.2 V)
DAB digital supply voltage (3.3 V)
DSP digital supply voltage (3.3 V)
JTAG digital supply voltage (3.3 V)
microcontroller digital supply voltage (3.3 V)
V
V
VDDD(DAB)(3V3)
VDDD(DSP)(3V3)
VDDD(JTAG)(3V3)
VDDD(MC)(3V3)
V
V
V
V
VDDD(SDRAM)(3V3) SDRAM digital supply voltage (3.3 V)
V
VDDD(MEM)(1V2)
Tamb
memory digital supply voltage (1.2 V)
ambient temperature
V
°C
°C
V
Tstg
storage temperature
+150
±2000
[1]
[2]
VESD
electrostatic discharge voltage
human body model
charged device model
corner pins
-
±750
±500
+100
V
other pins
-
V
[2]
Ilu
latch-up current
all supply voltages
below the maximum
values listed in this
table
−100
mA
[1] Class 2 according to JEDEC JESD22-A114.
[2] According to AEC-Q100-G.
8. Thermal characteristics
The SAF3560 has no special thermal requirements. The backside contact is needed for
electrical reasons. For soldering considerations, see Section 10.
Table 17. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
[1]
Rth(j-a)
thermal resistance from junction in free air
to ambient
26.3
K/W
[1] The overall Rth(j-a) is based on JEDEC conditions and can vary depending on the board layout. To minimize
the effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly.
An ample amount of copper area directly under the SAF3560 with a number of through-hole plating, which
connect to the ground layer (four-layer board: second layer), can also reduce the effective Rth(j-a). Do not
use any solder-stop varnish under the chip. In addition the use of soldering glue with a high thermal
conductance after curing is recommended.
SAF3560_SDS
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Product short data sheet
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SAF3560
NXP Semiconductors
Terrestrial digital radio processor
9. Package outline
HLQFP144: plastic thermal enhanced low profile quad flat package; 144 leads;
body 20 x 20 x 1.4 mm; exposed die pad
SOT612-4
c
y
exposed die pad
X
D
h
A
108
109
73
72
Z
E
e
A
2
E
h
H
E
A
E
(A )
3
A
1
θ
M
w
L
p
b
p
detail X
pin 1 index
L
144
37
1
36
M
v
A
Z
D
M
w
e
b
p
D
B
H
D
M
v
B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
1
A
2
A
3
b
c
D
D
h
E
E
e
H
D
H
E
L
L
v
w
y
Z
Z
E
θ
p
h
p
D
max
°
°
0.12 1.45
0.05 1.35
0.27 0.20 20.1 4.3 20.1 4.3
0.17 0.09 19.9 4.1 4.1
22.15 22.15
21.85
21.85
0.75
0.45
1.4
1.1
1.4
1.1
7
0
mm
1.6
0.25
0.5
1
0.2 0.08 0.08
19.9
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
07-12-11
08-01-18
SOT612-4
MS-026
Fig 4. Package outline SOT612-4 (HLQFP144)
SAF3560_SDS
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Product short data sheet
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NXP Semiconductors
Terrestrial digital radio processor
10. Soldering
Footprint information for reflow soldering of HLQFP144 package
SOT612-4
Hx
Gx
(0.125)
P2
P1
SPx
nSPx
SPy
SLy
Hy Gy
By
Ay
nSPy
SPx tot
SLx
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste
nSPx nSPy
occupied area
4
4
DIMENSIONS in mm
P1 P2 Ax
Ay
Bx
By
C
D1
D2
Gx
Gy
Hx
Hy
SLx SLy SPx tot SPy tot SPx SPy
0.500 0.560 23.300 23.300 20.300 20.300 1.500 0.280 0.400 20.500 20.500 23.550 23.550 4.500 4.500 4.400
4.400 0.750 0.750
Fig 5. Soldering footprint SOT612-4 (HLQFP144)
SAF3560_SDS
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Product short data sheet
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SAF3560
NXP Semiconductors
Terrestrial digital radio processor
11. Abbreviations
Table 18. Abbreviations
Acronym
AEC
AM
Description
Automotive Electronics Council
Amplitude Modulation
Bit ClocK
BCK
CA
Conditional Access
Compact Disc
CD
CGU
CTS
DAB
DAC
DSP
EPG
FM
Clock Generation Unit
Clear To Send
Digital Audio Broadcasting
Digital-to-Analog Converter
Digital Signal Processor
Electronic Program Guide
Frequency Modulation
General Purpose Input and Output
Intermediate Frequency
Inter-IC bus
GPIO
IF
I2C-bus
I2S
Inter-IC Sound
I/O
Input/Output
JEDEC
JTAG
MUX
PLL
Joint Electronic Device Engineering Council
Joint Test Action Group
MUltipleXer
Phase-Locked Loop
RAM
RS232
RTS
SD
Random Access Memory
Recommended Standard 232[1]
Ready To Send
Secure Digital memory card
Single Data Rate
SDR
SDRAM
SPI
Synchronous Dynamic RAM
Serial Peripheral Interface
Sony/Philips Digital InterFace
Sample-Rate Converter
Universal Asynchronous Receiver Transmitter
Word Select
S/PDIF
SRC
UART
WS
[1] A serial interface.
SAF3560_SDS
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Terrestrial digital radio processor
12. Revision history
Table 19. Revision history
Document ID
Release date
20100915
Data sheet status
Change notice
Supersedes
SAF3560_SDS v.3
Modifications:
Product short data sheet
-
SAF3560_SDS v.2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted where appropriate.
• Minor text changes
SAF3560_SDS v.2
20100503
Product short data sheet
-
-
SAF3560_SDS
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NXP Semiconductors
Terrestrial digital radio processor
13. Legal information
13.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
suitable for use in medical, military, aircraft, space or life support equipment,
13.2 Definitions
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
13.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
SAF3560_SDS
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Product short data sheet
Rev. 03 — 15 September 2010
18 of 20
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
13.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
I2C-bus — logo is a trademark of NXP B.V.
HD Radio — is a trademark of iBiquity Digital Corporation.
HD Radio — logo is a registered trademark of iBiquity Digital Corporation.
13.4 Licenses
ICs with HD Radio functionality
NXP Semiconductors ICs with HD Radio functionality are manufactured
under license from iBiquity Digital Corporation. Sale or distribution of
equipment that includes this device requires a license, which may be
obtained at: iBiquity Digital Corporation, 6711 Columbia Gateway Drive,
Suite 500, Columbia MD 21046, USA. Telephone: +1 (443) 539 4290, fax:
+1 (443) 539 4291, e-mail: info@ibiquity.com.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
SAF3560_SDS
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Product short data sheet
Rev. 03 — 15 September 2010
19 of 20
SAF3560
NXP Semiconductors
Terrestrial digital radio processor
15. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
HD Radio technology . . . . . . . . . . . . . . . . . . . . 2
Digital audio . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Other peripheral interfaces. . . . . . . . . . . . . . . . 3
Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
2.2
2.3
2.4
2.5
3
4
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
Thermal characteristics . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
8
9
10
11
12
13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
13.1
13.2
13.3
13.4
13.5
14
15
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 September 2010
Document identifier: SAF3560_SDS
相关型号：
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