SC16C2552IA44_技术文档

SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Rev. 03 — 20 June 2003

Product data

1. Description

The SC16C2552 is a two channel Universal Asynchronous Receiver and Transmitter

(UART) used for serial data communications. Its principal function is to convert

parallel data into serial data, and vice versa. The UART can handle serial data rates

up to 5 Mbits/s.

The SC16C2552 is pin compatible with the PC16C552 and ST16C2552. It will

power-up to be functionally equivalent to the 16C2450. The SC16C2552 provides

enhanced UART functions with 16 byte FIFOs, modem control interface, DMA mode

data transfer and concurrent writes to control registers of both channels. The DMA

mode data transfer is controlled by the FIFO trigger levels and the RXRDY and

TXRDY signals. On-board status registers provide the user with error indications and

operational status. System interrupts and modem control features may be tailored by

software to meet speciﬁc user requirements. An internal loop-back capability allows

on-board diagnostics. Independent programmable baud rate generators are provided

to select transmit and receive baud rates.

The SC16C2552 operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature

range, and is available in a plastic PLCC44 package.

2. Features

■ Industrial temperature range (−40 °C to +85 °C)

■ 5 V, 3.3 V and 2.5 V operation

■ Pin-to-pin and functionally compatible to PC16C552, ST16C2552

■ Software compatible with INS8250, NS16C550

■ Up to 5 Mbits/s data rate at 5 V and 3 V, and 3 Mbits/s at 2.5 V

■ 16-byte transmit FIFO

■ 16-byte receive FIFO with error ﬂags

■ Independent transmit and receive UART control

■ Four selectable Receive FIFO interrupt trigger levels; ﬁxed XMIT FIFO interrupt

trigger level

■ Modem control signals (CTS, RTS, DSR, DTR, RI, CD)

■ DMA operation and DMA monitoring via package I/O pins, TXRDY/RXRDY

■ UART internal register sections A and B may be written to concurrently

■ Multi-function output allows more package functions with fewer I/O pins

■ Programmable character lengths (5, 6, 7, 8), with even, odd, or no parity

SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

plastic leaded chip carrier; 44 leads

Version

SC16C2552IA44

PLCC44

SOT187-2

4. Block diagram

SC16C2552

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTERS

REGISTER

D0–D7

IOR

IOW

DATA BUS

AND

CONTROL LOGIC

RESET

RECEIVE

FIFO

RECEIVE

SHIFT

RXA, RXB

REGISTERS

REGISTER

A0–A2

CS

CHSEL

REGISTER

SELECT

LOGIC

DTRA, DTRB

RTSA, RTSB

MFA, MFB

MODEM

CONTROL

LOGIC

CTSA, CTSB

RIA, RIB

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

CDA, CDB

DSRA, DSRB

002aaa123

XTAL1

XTAL2

Fig 1. SC16C2552 block diagram.

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SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

5. Pinning information

5.1 Pinning

D5

D6

D7

7

8

9

39 RXA

38 TXA

37 DTRA

36 RTSA

35 MFA

A0 10

XTAL1 11

GND 12

XTAL2 13

A1 14

SC16C2552IA44

34 INTA

33

V

cc

32 TXRDYB

31 RIB

A2 15

CHSEL 16

INTB 17

30 CDB

29 DSRB

002aaa124

Fig 2. PLCC44 pin conﬁguration.

5.2 Pin description

Table 2:

Symbol

A2-A0

Pin description

Type

Description

10, 14,

15

I

Register select. A0-A2 are used during read and write operations to select the UART

register to read from or write to.

CHSEL

CS

16

I

Channel Select. UART channel A or B is selected by the logical state of this pin when

the CS is a logic 0. A logic 0 on CHSEL selects the UART channel ‘B’, while a logic 1

selects UART channel ‘A’.

18

I

Chip Select (Active-LOW). This function is selects channel ‘A’ or ‘B’, in accordance

with the logical state of the CHSEL pin. This allows data to be transferred between the

user CPU and the SC16C2552, or the SC16C2552 and the CPU for a channel selected

by CHSEL. MF[0] overrides CHSEL while in the write cycle mode, allowing the user to

write both channel registers simultaneously with one write cycle.

D0-D7

GND

2-9

I/O

I

Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for transferring

information to or from the controlling CPU. D0 is the least signiﬁcant bit and the ﬁrst

data bit in a transmit or receive serial data stream.

12, 22

Signal and power ground.

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SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

Table 2:

Pin description…continued

Symbol

Type

Description

INTA, INTB

34, 17

O

Interrupt A, B (Active-HIGH). This function is associated with individual channel

interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1,

interrupts are enabled in the interrupt enable register (IER), and when an interrupt

condition exists. Interrupt conditions include: receiver errors, available receiver buffer

data, transmit buffer empty, or when a modem status ﬂag is detected.

IOR

24

I

Read strobe (Active-LOW). A logic 0 transition on this pin will load the contents of an

internal register deﬁned by address bits A0-A2 onto the SC16C2552 data bus (D0-D7)

for access by external CPU.

IOW

20

I

Write strobe (Active-LOW). A logic 0 transition on this pin will transfer the contents of

the data bus (D0-D7) from the external CPU to an internal register that is deﬁned by

address bits A0-A2.

MFA, MFB

35, 19

O

Multi-Function A, B. This function is associated with an individual channel function, ‘A’

or ‘B’. User programmable bits 1-2 of the Alternate Function Register (AFR), selects a

signal function or output on these pins. OP2 (interrupt enable), BAUDOUT, and RXRDY

are signal functions that may be selected by the AFR. These signal functions are

described as follows:

OP2. When OP2 (interrupt output enable function) is selected, the MF pin is a logic 1

when INTA, INTB is set to the 3-State mode (disabled), or a logic 0 when INTA, INTB

is enabled. (See MCR[3].) A logic 1 is the default signal condition that is available

following a master reset or power-up.

BAUDOUT. When BAUDOUT function is selected, the 16× baud rate clock output is

available at this pin.

RXRDY. RXRDY is primarily intended for monitoring DMA mode 1 transfers for the

receive data FIFOs. A logic 0 indicates there is receive data to read/unload, i.e.,

receive ready status with one or more RX characters available in the FIFO/RHR. This

pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level

has not been reached. This signal can also be used for single mode transfers (DMA

mode 0).

RESET

21

I

Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers and all the

outputs. The UART transmitter output and the receiver input will be disabled during

reset time. (See Section 7.11 “SC16C2552 external reset conditions” for initialization

details.)

TXRDYA,

TXRDYB

1, 32

O

Transmit Ready A, B (Active-LOW). These outputs provide the TX FIFO/THR status

for individual transmit channels (A-B). TXRDYn is primarily intended for monitoring

DMA mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA,

TXRDYB buffer ready status is indicated by logic 0, i.e., at least one location is empty

and available in the FIFO or THR. This pin goes to a logic 1 when there are no more

empty locations in the FIFO or THR. This signal can also be used for single mode

transfers (DMA mode 0).

V_CC

33, 44

11

I

Power supply input.

XTAL1

Crystal or external clock input. Functions as a crystal input or as an external clock

input. A crystal can be connected between this pin and XTAL2 to form an internal

oscillator circuit. Alternatively, an external clock can be connected to this pin to provide

custom data rates. (See Section 6.5 “Programmable baud rate generator”.)

XTAL2

13

O

I

Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal

oscillator output or buffered clock output. Should be left open if an external clock is

connected to XTAL1.

CDA, CDB

42, 30

Carrier Detect (Active-LOW). These inputs are associated with individual UART

channels A through B. A logic 0 on this pin indicates that a carrier has been detected by

the modem for that channel.

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SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

Table 2:

Symbol

Pin description…continued

Type

Description

CTSA, CTSB 40, 28

I

Clear to Send (Active-LOW). These inputs are associated with individual UART

channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is

ready to accept transmit data from the SC16C2552. Status can be tested by reading

MSR[4].

DSRA, DSRB 41, 29

DTRA, DTRB 37, 27

I

Data Set Ready (Active-LOW). These inputs are associated with individual UART

channels, A through B. A logic 0 on this pin indicates the modem or data set is

powered-on and is ready for data exchange with the UART.

O

Data Terminal Ready (Active-LOW). These outputs are associated with individual

UART channels, A through B. A logic 0 on this pin indicates that the SC16C2552 is

powered-on and ready. This pin can be controlled via the modem control register.

Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This

pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset.

RIA, RIB

43, 31

I

Ring Indicator (Active-LOW). These inputs are associated with individual UART

channels, A through B. A logic 0 on this pin indicates the modem has received a ringing

signal from the telephone line. A logic 1 transition on this input pin will generate an

interrupt.

RTSA, RTSB 36, 23

O

Request to Send (Active-LOW). These outputs are associated with individual UART

channels, A through B. A logic 0 on the RTS pin indicates the receiver is ready to

receive data. Writing a logic 1 in the modem control register MCR[1] will set this pin to a

logic 0, indicating that the receiver is ready to receive data. After a reset this pin will be

set to a logic 1.

RXA, RXB

TXA, TXB

39, 25

38, 26

I

Receive data A, B. These inputs are associated with individual serial channel data to

the SC16C2552 receive input circuits, A-B. The RX signal will be a logic 1 during reset,

idle (no data), or when the transmitter is disabled. During the local loop-back mode, the

RX input pin is disabled and TX data is connected to the UART RX input, internally.

O

Transmit data A, B. These outputs are associated with individual serial transmit

channel data from the SC16C2552. The TX signal will be a logic 1 during reset, idle (no

data), or when the transmitter is disabled. During the local loop-back mode, the TX

output pin is disabled and TX data is internally connected to the UART RX input.

9397 750 11636

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Rev. 03 — 20 June 2003

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SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

6. Functional description

The SC16C2552 provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data

stream into parallel data that is required with digital data systems. Synchronization for

the serial data stream is accomplished by adding start and stop bits to the transmit

data to form a data character. Data integrity is insured by attaching a parity bit to the

data character. The parity bit is checked by the receiver for any transmission bit

errors. The SC16C2552 is fabricated with an advanced CMOS process.

The SC16C2552 is an upward solution that provides a dual UART capability with

16 bytes of transmit and receive FIFO memory, instead of none in the 16C450. The

SC16C2552 is designed to work with high speed modems and shared network

environments that require fast data processing time. Increased performance is

realized in the SC16C2552 by the transmit and receive FIFOs. This allows the

external processor to handle more networking tasks within a given time. In addition,

the four selectable receive FIFO trigger interrupt levels are uniquely provided for

maximum data throughput performance especially when operating in a multi-channel

environment. The FIFO memory greatly reduces the bandwidth requirement of the

external controlling CPU, increases performance, and reduces power consumption.

The SC16C2552 is capable of operation to 1.5 Mbits/s with a 24 MHz. With a crystal

or external clock input of 7.3728 MHz, the user can select data rates up to

460.8 kbits/s.

The rich feature set of the SC16C2552 is available through internal registers.

Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem

interface controls are all standard features.

6.1 UART A-B functions

The UART provides the user with the capability to bi-directionally transfer information

between an external CPU, the SC16C2552 package, and an external serial device. A

logic 0 on chip select pin CS, and a logic 1 on CHSEL allows the user to conﬁgure,

send data, and/or receive data via UART channel A. A logic 0 on chip select pin CS

and a logic 0 on CHSEL allows the user to conﬁgure, send data, and/or receive data

via UART channel B. Individual channel select functions are shown in Table 3.

Table 3:

Serial port selection

Chip Select

CS = 1

Function

none

CS = 0

UART channel selected as follows:

CHSEL = 1: UART Channel A

CHSEL = 0: UART Channel B

During a write mode cycle, the setting of AFR[0] to a logic 1 will override the CHSEL

selection and allow a simultaneous write to both UART channel sections. This

functional capability allow the registers in both UART channels to be modiﬁed

concurrently, saving individual channel initialization time. Caution should be

considered, however, when using this capability. Any in-process serial data transfer

may be disrupted by changing an active channel’s mode.

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SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

6.2 Internal registers

The SC16C2552 provides two sets of internal registers (A and B) consisting of

12 registers each for monitoring and controlling the functions of each channel of the

UART. These registers are shown in Table 4. The UART registers function as data

holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO

control register (FCR), line status and control registers (LCR/LSR), modem status

and control registers (MCR/MSR), programmable data rate (clock) control registers

(DLL/DLM), a user accessible scratchpad register (SPR), and an Alternate Function

Register (AFR).

Table 4:

A2

Internal registers decoding

A0 READ mode

A1

WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Line Status Register

Modem Status Register

Scratchpad Register

n/a

Scratchpad Register

Register set 2 (DLL/DLM/AFR)^[2]

0

1

0

1

0

LSB of Divisor Latch

MSB of Divisor Latch

Alternate Function Register

MSB of Divisor Latch

Alternate Function Register

[1] The General Register sets are accessible only when CS is a logic 0 and LCR[7] is a logic 0.

[2] The Baud Rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is

a logic 1 for the register set (A/B) being accessed.

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SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

6.3 FIFO operation

The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control

Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but

not the transmit trigger level. The transmit interrupt trigger level is set to 16 following a

reset. The receiver FIFO section includes a time-out function to ensure data is

delivered to the external CPU. An interrupt is generated whenever the Receive

Holding Register (RHR) has not been read following the loading of a character or the

receive trigger level has not been reached.

6.4 Time-out interrupts

The interrupts are enabled by IER[0-3]. Care must be taken when handling these

interrupts. Following a reset the transmitter interrupt is enabled, the SC16C2552 will

issue an interrupt to indicate that Transmit Holding Register is empty. This interrupt

must be serviced prior to continuing operations. The LSR register provides the

current singular highest priority interrupt only. It could be noted that CTS and RTS

interrupts have lowest interrupt priority. A condition can exist where a higher priority

interrupt may mask the lower priority CTS/RTS interrupt(s). Only after servicing the

higher pending interrupt will the lower priority CTS/RTS interrupt(s) be reﬂected in the

status register. Servicing the interrupt without investigating further interrupt conditions

can result in data errors.

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time Out have the same

interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the

number of characters have reached the programmed trigger level. In this case, the

SC16C2552 FIFO may hold more characters than the programmed trigger level.

Following the removal of a data byte, the user should re-check LSR[0] for additional

characters. A Receive Time Out will not occur if the receive FIFO is empty. The

time-out counter is reset at the center of each stop bit received or each time the

receive holding register (RHR) is read. The actual time-out value is 4 character time.

6.5 Programmable baud rate generator

The SC16C2552 supports high speed modem technologies that have increased input

data rates by employing data compression schemes. For example, a 33.6 kbit/s

modem that employs data compression may require a 115.2 kbit/s input data rate.

A 128.0 kbit/s ISDN modem that supports data compression may need an input

data rate of 460.8 kbit/s.

A baud rate generator is provided for each UART channel, allowing independent

TX/RX channel control. The programmable Baud Rate Generator is capable of

accepting an input clock up to 80 MHz, as required for supporting a 5 Mbits/s data

rate. The SC16C2552 can be conﬁgured for internal or external clock operation. For

internal clock oscillator operation, an industry standard microprocessor crystal is

connected externally between the XTAL1 and XTAL2 pins. Alternatively, an external

clock can be connected to the XTAL1 pin to clock the internal baud rate generator for

standard or custom rates (see Table 5).

The generator divides the input 16× clock by any divisor from 1 to 2¹⁶− 1. The

SC16C2552 divides the basic external clock by 16. The basic 16× clock provides

table rates to support standard and custom applications using the same system

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SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

design. The rate table is conﬁgured via the DLL and DLM internal register functions.

Customized Baud Rates can be achieved by selecting the proper divisor values for

the MSB and LSB sections of baud rate generator.

Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)

provides a user capability for selecting the desired ﬁnal baud rate. The example in

Table 5 shows the selectable baud rate table available when using a 1.8432 MHz

external clock input.

1.5 kΩ

X1

1.8432 MHz

C1

47 pF

C2

100 pF

C1

22 pF

C2

47 pF

002aaa169

Fig 3. Crystal oscillator connection.

Table 5:

Baud rate generator programming table using a 1.8432 MHz clock

Output

User

DLM

DLL

baud rate

16× clock divisor 16× clock divisor program value

program value

(HEX)

(decimal)

(HEX)

900

600

300

180

C0

60

(HEX)

09

06

03

01

00

50

2304

1536

768

384

192

96

00

80

C0

60

30

18

10

0C

06

03

02

01

75

150

300

600

1200

2400

4800

7200

9600

19.2 k

38.4 k

57.6 k

115.2 k

48

30

24

18

16

10

12

0C

06

6

3

03

2

02

1

01

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SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

6.6 DMA operation

The SC16C2552 FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. LSR[5,6] provide an indication when the transmitter is empty or has

an empty location(s). The user can optionally operate the transmit and receive FIFOs

in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and

the DMA mode is de-activated (DMA Mode 0), the SC16C2552 activates the interrupt

output pin for each data transmit or receive operation. When DMA mode is activated

(DMA Mode 1), the user takes the advantage of block mode operation by loading or

unloading the FIFO in a block sequence determined by the receive trigger level and

the transmit FIFO. In this mode, the SC16C2552 sets the interrupt output pin when

characters in the transmit FIFO is below 16, or the characters in the receive FIFOs

are above the receive trigger level.

6.7 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the loop-back mode,

the normal modem interface pins are disconnected and reconﬁgured for loop-back

internally. MCR[0-3] register bits are used for controlling loop-back diagnostic testing.

In the loop-back mode, INT enable and MCR[2] in the MCR register (bits 2-3) control

the modem RI and CD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are

used to control the modem CTS and DSR inputs, respectively. The transmitter output

(TX) and the receiver input (RX) are disconnected from their associated interface

pins, and instead are connected together internally (see Figure 4). The CTS, DSR,

CD, and RI are disconnected from their normal modem control inputs pins, and

instead are connected internally to DTR, RTS, INT enable, and MCR[2]. Loop-back

test data is entered into the transmit holding register via the user data bus interface,

D0-D7. The transmit UART serializes the data and passes the serial data to the

receive UART via the internal loop-back connection. The receive UART converts the

serial data back into parallel data that is then made available at the user data

interface D0-D7. The user optionally compares the received data to the initial

transmitted data for verifying error-free operation of the UART TX/RX circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem

Control Interrupts are also operational. However, the interrupts can only be read

using lower four bits of the Modem Status Register (MSR[0-3]) instead of the four

Modem Status Register bits 4-7. The interrupts are still controlled by the IER.

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SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

SC16C2552

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTERS

REGISTER

D0–D7

IOR

IOW

DATA BUS

AND

CONTROL LOGIC

RESET

MCR[4] = 1

RECEIVE

FIFO

REGISTERS

RECEIVE

SHIFT

REGISTER

RXA, RXB

RTSA, RTSB

A0–A2

CS

CHSEL

REGISTER

SELECT

LOGIC

DSRA, DSRB

DTRA, DTRB

MODEM

CONTROL

LOGIC

CTSA, CTSB

OP1A, OP1B

RIA, RIB

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

OP2A, OP2B

CDA, CDB

002aaa126

XTAL1

XTAL2

Fig 4. Internal loop-back mode diagram.

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SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Philips Semiconductors

7. Register descriptions

Table 6 details the assigned bit functions for the SC16C2552 internal registers. The

assigned bit functions are further deﬁned in Section 7.1 through Section 7.11.

Table 6:

SC16C2552 internal registers

A2 A1 A0 Register Default^[1]Bit 7

General Register Set^[2]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

0

bit 6

0

bit 5

0

bit 4

0

bit 3

bit 2

bit 1

bit 0

modem receive

status line

interrupt status

interrupt interrupt

XMIT RCVR

FIFO FIFO

transmit receive

holding holding

register register

0

1

0

1

0

1

FCR

ISR

00

01

00

60

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

0

DMA

FIFO

enable

mode

select

reset

FIFOs

enabled enabled

FIFOs

INT

priority

bit 2

INT

priority

bit 1

INT

priority

bit 0

INT

status

LCR

MCR

LSR

divisor

latch

enable

set

break

set parity even

parity

enable

stop bits word

length

word

length

bit 0

bit 1

0

loop

back

OP A/B, OP1

INTA/B

enable

RTS

DTR

FIFO

data

error

THR and THR

TSR

empty

break

interrupt error

framing parity

overrun receive

error

empty

error

data

ready

1

0

1

MSR

SPR

X0

FF

CD

RI

DSR

bit 5

CTS

bit 4

∆CD

∆RI

∆DSR

∆CTS

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

Special Register Set^[3]

0

1

0

1

0

DLL

DLM

AFR

XX

00

bit 7

bit 15

bit 7

bit 6

bit 14

bit 6

bit 5

bit 13

bit 5

bit 4

bit 12

bit 4

bit 3

bit 11

bit 3

bit 2

bit 10

bit 2

bit 1

bit 9

bit 1

bit 0

bit 8

bit 0

[1] The value shown in represents the register’s initialized HEX value; X = n/a.

[2] The General Register sets are accessible only when CS is a logic 0 and LCR[7] is a logic 0. Set A is accessible when CHSEL is a

logic 1, and set is accessible when CHSEL is a logic 0.

[3] The Baud Rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a logic 1 for the register set (A/B)

being accessed.

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Dual UART with 16-byte transmit and receive FIFOs

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7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to

the TSR and UART via the THR, providing that the THR is empty. The THR empty

ﬂag in the LSR register will be set to a logic 1 when the transmitter is empty or when

data is transferred to the TSR. Note that a write operation can be performed when the

THR empty ﬂag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location

available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and

a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2552

and receive FIFO by reading the RHR register. The receive section provides a

mechanism to prevent false starts. On the falling edge of a start or false start bit, an

internal receiver counter starts counting clocks at the 16× clock rate. After 7-¹⁄₂

clocks, the start bit time should be shifted to the center of the start bit. At this time the

start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in

this manner prevents the receiver from assembling a false character. Receiver status

codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready,

transmitter empty, line status and modem status registers. These interrupts would

normally be seen on the INTA, INTB output pins.

Table 7:

Interrupt Enable Register bits description

Bit

7-4

3

Symbol

IER[7-4]

IER[3]

Description

Not used; initialized to logic 0.

Modem Status Interrupt. This interrupt will be issued whenever

there is a modem status change as reﬂected in MSR[0-3].

Logic 0 = Disable the modem status register interrupt (normal

default condition).

Logic 1 = Enable the modem status register interrupt.

2

1

IER[2]

IER[1]

Receive Line Status interrupt. This interrupt will be issued

whenever a receive data error condition exists as reﬂected in

LSR[1-4].

Logic 0 = Disable the receiver line status interrupt (normal

default condition).

Logic 1 = Enable the receiver line status interrupt.

Transmit Holding Register interrupt. In the 16C450 mode, this

interrupt will be issued whenever the THR is empty, and is

associated with LSR[5]. In the FIFO modes, this interrupt will be

issued whenever the FIFO and THR are empty.

Logic 0 = Disable the Transmit Holding Register Empty (TXRDY)

interrupt (normal default condition).

Logic 1 = Enable the TXRDY (ISR level 3) interrupt.

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Dual UART with 16-byte transmit and receive FIFOs

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Table 7:

Interrupt Enable Register bits description…continued

Bit

Symbol

Description

0

IER[0]

Receive Holding Register. In the 16C450 mode, this interrupt will

be issued when the RHR has data, or is cleared when the RHR is

empty. In the FIFO mode, this interrupt will be issued when the

FIFO has reached the programmed trigger level or is cleared when

the FIFO drops below the trigger level.

Logic 0 = Disable the receiver ready (ISR level 2, RXRDY)

interrupt (normal default condition).

Logic 1 = Enable the RXRDY (ISR level 2) interrupt.

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)

are enabled, the receive interrupts and register status will reﬂect the following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit

and the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred

from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is

empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated

when the transmit FIFO is empty due to the unloading of the data by the TSR and

UART for transmission via the transmission media. The interrupt is cleared either

by reading the ISR register, or by loading the THR with new data characters.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2552 in the FIFO

polled mode of operation. In this mode, interrupts are not generated and the user

must poll the LSR register for TX and/or RX data status. Since the receiver and

transmitter have separate bits in the LSR either or both can be used in the polled

mode by selecting respective transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[1-4] will provide the type of receive errors, or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are

empty.

• LSR[7] will show if any FIFO data errors occurred.

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Dual UART with 16-byte transmit and receive FIFOs

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7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO

trigger levels, and select the DMA mode.

7.3.1 DMA mode

Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or

receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will

go to a logic 0 whenever an empty transmit space is available in the Transmit Holding

Register (THR). Receive Ready (RXRDY) at the MF pin will go to a logic 0 whenever

the Receive Holding Register (RHR) is loaded with a character and the MF register is

set to the RXRDY mode.

Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The

transmit interrupt is set when the transmit FIFO has at least one empty location.

TXRDY remains a logic 0 as long as one empty FIFO location is available. The

receive interrupt is set when the receive FIFO ﬁlls to the programmed trigger level.

However, the FIFO continues to ﬁll regardless of the programmed level until the FIFO

is full. RXRDY at the MF pin remains a logic 0 as long as the FIFO ﬁll level is above

the programmed trigger level, and the MF register is set to the RXRDY mode.

7.3.2 FIFO mode

Table 8:

FIFO Control Register bits description

Bit

Symbol

Description

7-6

FCR[7]

(MSB),

FCR[6]

(LSB)

RCVR trigger. These bits are used to set the trigger level for the

receive FIFO interrupt.

An interrupt is generated when the number of characters in the

FIFO equals the programmed trigger level. However, the FIFO will

continue to be loaded until it is full. Refer to Table 9.

5-4

3

FCR[5-4]

FCR[3]

Not used; initialized to logic 0.

DMA mode select.

Logic 0 = Set DMA mode ‘0’ (normal default condition).

Logic 1 = Set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C2552 is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO

mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and

when there are no characters in the transmit FIFO or transmit

holding register, the TXRDY pin will be a logic 0. Once active, the

TXRDY pin will go to a logic 1 after the ﬁrst character is loaded into

the transmit holding register.

Receive operation in mode ‘0’: When the SC16C2552 is in

16C450 mode, or in the FIFO mode (FCR[0] = logic 1;

FCR[3] = logic 0) and there is at least one character in the receive

FIFO, the RXRDY signal at the MF pin will be a logic 0. Once

active, the RXRDY signal at the MF pin will go to a logic 1 when

there are no more characters in the receiver. NOTE: The AFR

register must be set to the RXRDY mode prior to any possible

reading of the RXRDY signal.

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Dual UART with 16-byte transmit and receive FIFOs

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Table 8:

FIFO Control Register bits description…continued

Bit

Symbol

Description

3

Transmit operation in mode ‘1’: When the SC16C2552 is in

FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin

will be a logic 1 when the transmit FIFO is completely full. It will be

a logic 0 if one or more FIFO locations are empty.

(continued)

Receive operation in mode ‘1’: When the SC16C2552 is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has

been reached, or a Receive Time-Out has occurred, the RXRDY

signal at the MF pin will go to a logic 0. Once activated, it will go to

a logic 1 after there are no more characters in the FIFO.

NOTE: The AFR register must be set to the RXRDY mode prior to

any possible reading of the RXRDY signal.

2

1

0

FCR[2]

FCR[1]

FCR[0]

XMIT FIFO reset.

Logic 0 = No FIFO transmit reset (normal default condition).

Logic 1 = Clears the contents of the transmit FIFO and resets

the FIFO counter logic (the transmit shift register is not cleared

or altered). This bit will return to a logic 0 after clearing the FIFO.

RCVR FIFO reset.

Logic 0 = No FIFO receive reset (normal default condition).

Logic 1 = Clears the contents of the receive FIFO and resets the

FIFO counter logic (the receive shift register is not cleared or

altered). This bit will return to a logic 0 after clearing the FIFO.

FIFOs enabled.

Logic 0 = Disable the transmit and receive FIFO (normal default

condition).

Logic 1 = Enable the transmit and receive FIFO. This bit must

be a ‘1’ when other FCR bits are written to, or they will not

be programmed.

Table 9:

RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level

0

1

0

1

0

1

01

04

08

14

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Dual UART with 16-byte transmit and receive FIFOs

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7.4 Interrupt Status Register (ISR)

The SC16C2552 provides four levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with four

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged

until the pending interrupt is serviced. Whenever the interrupt status register is read,

the interrupt status is cleared. However, it should be noted that only the current

pending interrupt is cleared by the read. A lower level interrupt may be seen after

re-reading the interrupt status bits. Table 10 “Interrupt source” shows the data values

(bits 0-3) for the four prioritized interrupt levels and the interrupt sources associated

with each of these interrupt levels.

Table 10: Interrupt source

Priority ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

2

3

4

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status Register)

RXRDY (Received Data Ready)

RXRDY (Receive Data time-out)

TXRDY (Transmitter Holding Register Empty)

MSR (Modem Status Register)

Table 11: Interrupt Status Register bits description

Bit

Symbol

Description

7-6

ISR[7-6]

FIFOs enabled. These bits are set to a logic 0 when the FIFOs are

not being used in the 16C450 mode. They are set to a logic 1

when the FIFOs are enabled in the SC16C2552 mode.

Logic 0 or cleared = default condition.

Not used; initialized to a logic 0.

5-4

3-1

ISR[5-4]

ISR[3-1]

Logic 0 or cleared = default condition.

INT priority bits 2-0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 10).

Logic 0 or cleared = default condition.

INT status.

0

ISR[0]

Logic 0 = An interrupt is pending and the ISR contents may be

used as a pointer to the appropriate interrupt service routine.

Logic 1 = No interrupt pending (normal default condition).

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Dual UART with 16-byte transmit and receive FIFOs

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7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by

writing the appropriate bits in this register.

Table 12: Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and

Enhance Feature mode enable.

Logic 0 = Divisor latch disabled (normal default condition).

Logic 1 = Divisor latch enabled.

6

LCR[6]

Set break. When enabled, the Break control bit causes a break

condition to be transmitted (the TX output is forced to a logic 0

state). This condition exists until disabled by setting LCR[6] to a

logic 0.

Logic 0 = no TX break condition (normal default condition)

Logic 1 = forces the transmitter output (TX) to a logic 0 for

alerting the remote receiver to a line break condition.

5-3

2

LCR[5-3]

LCR[2]

Programs the parity conditions (see Table 13).

Stop bits. The length of stop bit is speciﬁed by this bit in

conjunction with the programmed word length (see Table 14).

Logic 0 or cleared = default condition.

1-0

LCR[1-0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 15).

Logic 0 or cleared = default condition.

Table 13: LCR[5] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

X

0

1

X

0

1

0

1

0

1

ODD parity

EVEN parity

force parity ‘1’

forced parity ‘0’

Table 14: LCR[2] stop bit length

LCR[2]

Word length

5, 6, 7, 8

5

Stop bit length (bit times)

0

1

1-¹⁄₂

6, 7, 8

2

Table 15: LCR[1-0] word length

LCR[1]

LCR[0]

Word length

0

1

0

1

0

1

5

6

7

8

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Dual UART with 16-byte transmit and receive FIFOs

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7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 16: Modem Control Register bits description

Bit

7-5

4

Symbol

MCR[7-5]

MCR[4]

Description

Not used; initialized to a logic 0.

Loop-back. Enable the local loop-back mode (diagnostics). In this

mode the transmitter output TX and the receiver input RX, CTS, DSR,

CD, and RI are disconnected from the SC16C2552 I/O pins.

Internally the modem data and control pins are connected into a

loop-back data conﬁguration (see Figure 4). In this mode, the receiver

and transmitter interrupts remain fully operational. The Modem

Control Interrupts are also operational, but the interrupts’ sources are

switched to the lower four bits of the Modem Control. Interrupts

continue to be controlled by the IER register.

Logic 0 = Disable loop-back mode (normal default condition).

Logic 1 = Enable local loop-back mode (diagnostics).

3

MCR[3]

OP2, INTA/INTB enable. Used to control the modem CD signal in the

loop-back mode.

Logic 0 = Forces INT (A-B) outputs to the 3-State mode and sets

OP2 to a logic 1 (normal default condition). In the loop-back mode,

sets CD internally to a logic 1.

Logic 1 = Forces the INT (A-B outputs to the active mode and sets

OP2 to a logic 0. In the loop-back mode, sets CD internally to a

logic 0.

2

1

MCR[2]

MCR[1]

OP1. This bit is used in the Loop-back mode only. In the loop-back

mode, this bit is used to write the state of the modem RI interface

signal.

RTS

Logic 0 = Force RTS output to a logic 1 (normal default condition).

Logic 1 = Force RTS output to a logic 0.

DTR

0

MCR[0]

Logic 0 = Force DTR output to a logic 1 (normal default condition).

Logic 1 = Force DTR output to a logic 0.

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Dual UART with 16-byte transmit and receive FIFOs

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7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C2552 and

the CPU.

Table 17: Line Status Register bits description

Bit

Symbol

Description

7

LSR[7]

FIFO data error.

Logic 0 = No error (normal default condition).

Logic 1 = At least one parity error, framing error or break indication is in

the current FIFO data. This bit is cleared when LSR register is read.

6

5

LSR[6]

LSR[5]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is

set to a logic 1 whenever the transmit holding register and the transmit

shift register are both empty. It is reset to logic 0 whenever either the THR

or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’

whenever the transmit FIFO and transmit shift register are both empty.

THR empty. This bit is the Transmit Holding Register Empty indicator.

This bit indicates that the UART is ready to accept a new character for

transmission. In addition, this bit causes the UART to issue an interrupt to

CPU when the THR interrupt enable is set. The THR bit is set to a logic 1

when a character is transferred from the transmit holding register into the

transmitter shift register. The bit is reset to a logic 0 concurrently with the

loading of the transmitter holding register by the CPU. In the FIFO mode,

this bit is set when the transmit FIFO is empty; it is cleared when at least

1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

Logic 0 = No break condition (normal default condition).

Logic 1 = The receiver received a break signal (RX was a logic 0 for

one character frame time). In the FIFO mode, only one break character

is loaded into the FIFO.

Framing error.

Logic 0 = No framing error (normal default condition).

Logic 1 = Framing error. The receive character did not have a valid stop

bit(s). In the FIFO mode, this error is associated with the character at

the top of the FIFO.

Parity error.

Logic 0 = No parity error (normal default condition).

Logic 1 = Parity error. The receive character does not have correct

parity information and is suspect. In the FIFO mode, this error is

associated with the character at the top of the FIFO.

Overrun error.

Logic 0 = No overrun error (normal default condition).

Logic 1 = Overrun error. A data overrun error occurred in the receive

shift register. This happens when additional data arrives while the FIFO

is full. In this case, the previous data in the shift register is overwritten.

Note that under this condition, the data byte in the receive shift register

is not transferred into the FIFO, therefore the data in the FIFO is not

corrupted by the error.

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Dual UART with 16-byte transmit and receive FIFOs

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Table 17: Line Status Register bits description…continued

Bit

Symbol

Description

0

LSR[0]

Receive data ready.

Logic 0 = No data in receive holding register or FIFO (normal default

condition).

Logic 1 = Data has been received and is saved in the receive holding

register or FIFO.

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the

modem, or other peripheral device to which the SC16C2552 is connected. Four bits

of this register are used to indicate the changed information. These bits are set to a

logic 1 whenever a control input from the modem changes state. These bits are set to

a logic 0 whenever the CPU reads this register.

Table 18: Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

Carrier Detect, CD. During normal operation, this bit is the complement

of the CD input. Reading this bit in the loop-back mode produces the

state of MCR[3] (OPA/OPB).

6

5

4

3

MSR[6]

MSR[5]

MSR[4]

MSR[3]

Ring Indicator, RI. During normal operation, this bit is the complement of

the RI input. Reading this bit in the loop-back mode produces the state of

MCR[2] (OP1).

Data Set Ready, DSR. During normal operation, this bit is the

complement of the DSR input. During the loop-back mode, this bit is

equivalent to MCR[0] (DTR).

Clear To Send, CTS. During normal operation, this bit is the complement

of the CTS input. During the loop-back mode, this bit is equivalent to

MCR[1] (RTS).

∆CD ^[1]

Logic 0 = No CD change (normal default condition).

Logic 1 = The CD input to the SC16C2552 has changed state since

the last time it was read. A modem Status Interrupt will be generated.

2

1

0

MSR[2]

MSR[1]

MSR[0]

∆RI ^[1]

Logic 0 = No RI change (normal default condition).

Logic 1 = The RI input to the SC16C2552 has changed from a logic 0

to a logic 1. A modem Status Interrupt will be generated.

∆DSR ^[1]

Logic 0 = No DSR change (normal default condition).

Logic 1 = The DSR input to the SC16C2552 has changed state since

the last time it was read. A modem Status Interrupt will be generated.

∆CTS ^[1]

Logic 0 = No CTS change (normal default condition).

Logic 1 = The CTS input to the SC16C2552 has changed state since

the last time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.

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Dual UART with 16-byte transmit and receive FIFOs

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7.9 Scratchpad Register (SPR)

The SC16C2552 provides a temporary data register to store 8 bits of user

information.

7.10 Alternate Function Register (AFR)

This is a read/write register used to select speciﬁc modes of MF operation and to

allow both UART register’s sets to be written concurrently.

Table 19: Alternate Function Register bits description

Bit

7-3

2-1

Symbol

AFR[7-3]

AFR[2-1]

Description

Not used. All are initialized to logic 0.

Selects a signal function for output on the MFA, MFB pins. These

signal functions are described as: OP2 (interrupt enable),

BAUDOUT, or TXRDY. Only one signal function can be selected

at a time. See Table 20.

0

AFR[0]

When this bit is set, CPU can write concurrently to the same

register in both UARTs. This function is intended to reduce the

dual UART initialization time. It can be used by CPU when both

channels are initialized to the same state. The external CPU can

set or clear this bit by accessing either register set. When this bit

is set, the Channel Select pin still selects the channel to be

accessed during read operation. Setting or clearing this bit has no

effect on read operations. The user should ensure that LCR[7] of

both channels are in the same state before executing a

concurrent write to the registers at address 0, 1, or 2.

Logic 0 = No concurrent write (normal default condition).

Logic 1 = Register set A and B are written concurrently with a

single external CPU I/O write operation.

Table 20: MFA, MFB function selection

AFR[2]

AFR[1]

MF function

OP2

0

1

0

1

0

1

BAUDOUT

RXRDY

reserved

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Dual UART with 16-byte transmit and receive FIFOs

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7.11 SC16C2552 external reset conditions

Table 21: Reset state for registers

Register

IER

Reset state

IER[7-0] = 0

ISR

ISR[7-1] = 0; ISR[0] = 1

LCR[7-0] = 0

LCR

MCR

LSR

MCR[7-0] = 0

LSR[7] = 0; LSR[6-5] = 1; LSR[4-0] = 0

MSR[7-4] = input signals; MSR[3-0] = 0

FCR[7-0] = 0

MSR

FCR

AFR

AFR[7-0] = 0

Table 22: Reset state for outputs

Output

Reset state

HIGH

TXA, TXB

OP2A, OP2B

RTSA, RTSB

DTRA, DTRB

INTA, INTB

HIGH

LOW

TXRDYA, TXRDYB

LOW

8. Limiting values

Table 23: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

Max

Unit

V

supply voltage

-

7

V_n

voltage at any pin

operating temperature

storage temperature

GND − 0.3 V_CC+ 0.3

V

T_amb

−40

−65

-

+85

°C

mW

T_stg

+150

500

P_tot(pack)

total power dissipation per

package

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Dual UART with 16-byte transmit and receive FIFOs

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9. Static characteristics

Table 24: DC electrical characteristics

T_amb= −40 °C to +85 °C; V_CC= 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise speciﬁed.

Symbol Parameter

Conditions

2.5 V

Max

3.3 V

Max

5.0 V

Max

Unit

Min

−0.3

1.8

Min

−0.3

2.4

Min

−0.5

3.0

V_IL(CK)

V_IH(CK)

V_IL

LOW-level clock input voltage

0.45

V_CC

0.65

0.6

V_CC

0.8

0.6

V_CC

0.8

V

HIGH-level clock input voltage

LOW-level input voltage

(except X1 clock)

−0.3

−0.5

V_IH

HIGH-level input voltage

(except X1 clock)

1.6

-

2.0

-

2.2

-

V

µA

V_OL

LOW-level output voltage

on all outputs^[1]

I_OL= 5 mA

(databus)

-

0.4

I

_OL= 4 mA

(other outputs)

_OL= 2 mA

(databus)

_OL= 1.6 mA

-

0.4

-

I

-

0.4

-

I

-

0.4

-

(other outputs)

V_OH

HIGH-level output voltage

I_OH= −5 mA

(databus)

-

2.4

-

I

_OH= −1 mA

(other outputs)

_OH= −800 µA

(data bus)

_OH= −400 µA

-

2.0

-

I

1.85

-

I

-

(other outputs)

I_LIL

LOW-level input leakage

current

±10

I_CL

I_CC

C_i

clock leakage

-

±30

3.5

5

-

±30

4.5

5

-

±30

4.5

5

µA

mA

pF

supply current

input capacitance

f = 5 MHz

[1] Except x₂, V_OL= 1 V typical.

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10. Dynamic characteristics

Table 25: AC electrical characteristics

T_amb= −40 °C to +85 °C; V_CC= 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise speciﬁed.

Symbol Parameter

Conditions

2.5 V

Max

3.3 V

Max

5.0 V

Unit

Min

10

-

Min

6

Min Max

t_1w, t_2w

t_3w

clock pulse duration

-

6

-

ns

MHz

ns

[1]

oscillator/clock frequency

address set-up time

address hold time

48

-

80

-

80

-

t_6s

0

t_6h

0

-

0

-

0

-

t_7d

IOR delay from chip select

IOR strobe width

10

77

0

-

10

26

0

-

10

23

0

-

t_7w

25 pF load

-

t_7h

chip select hold time from IOR

read cycle delay

-

t_9d

25 pF load

20

-

20

-

20

-

t_12d

t_12h

t_13d

t_13w

t_13h

t_15d

t_16s

t_16h

t_17d

t_18d

delay from IOR to data

data disable time

77

15

-

26

15

-

23

15

-

IOW delay from chip select

IOW strobe width

10

20

0

10

20

0

10

15

0

[2]

-

chip select hold time from IOW

write cycle delay

-

[3]

25

20

15

-

25

20

5

-

20

15

5

-

data set-up time

-

data hold time

-

delay from IOW to output

25 pF load

100

-

33

24

-

29

23

delay to set interrupt from Modem 25 pF load

input

-

t_19d

t_20d

t_21d

t_22d

t_23d

t_24d

t_25d

t_26d

t_27d

t_28d

t_RESET

N

delay to reset interrupt from IOR

delay from stop to set interrupt

delay from IOR to reset interrupt

delay from start to set interrupt

delay from IOW to transmit start

delay from IOW to reset interrupt

delay from stop to set RXRDY

delay from IOR to reset RXRDY

delay from IOW to set TXRDY

delay from start to reset TXRDY

Reset pulse width

25 pF load

-

100

1

-

24

1

-

23

1

ns

-

R_clk

ns

25 pF load

-

100

24

-

29

45

24

45

1

-

28

40

24

40

1

-

ns

8

-

8

-

R_clk

ns

-

100

1

-

R_clk

ns

-

100

8

-

45

8

-

40

8

-

ns

-

R_clk

200

1

-

40

1

-

40

1

-

ns

baud rate divisor

2¹⁶− 1

2¹⁶− 1 R_clk

[1] Applies to external clock, crystal oscillator max 24 MHz.

1

[2] IOWstrobe_max

=

--------------------------------------

2(Baudrate_max

)

= 333 ns (for Baudrate_max= 1.5 Mbits/s)

= 1 µs (for Baudrate_max= 460.8 kbits/s)

= 4 µs (for Baudrate_max= 115.2 kbits/s)

[3] When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x₁, clock cycle.

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10.1 Timing diagrams

t

6h

VALID

ADDRESS

A0–A2

CHSEL

t

6s

t

13h

ACTIVE

CS

t

13d

t

15d

t

13w

IOW

ACTIVE

t

16h

t

16s

D0–D7

DATA

002aaa128

Fig 5. General write timing.

t

6h

VALID

ADDRESS

A0–A2

CHSEL

t

6s

t

7h

ACTIVE

CS

t

7d

t

9d

t

7w

IOR

ACTIVE

t

12h

t

12d

D0–D7

DATA

002aaa127

Fig 6. General read timing.

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IOW

ACTIVE

t

17d

RTS

DTR

CHANGE OF STATE

CD

CTS

DSR

CHANGE OF STATE

t

18d

INT

ACTIVE

t

19d

IOR

ACTIVE

t

18d

RI

CHANGE OF STATE

002aaa352

Fig 7. Modem input/output timing.

t

1w

2w

EXTERNAL

CLOCK

002aaa112

t

3w

Fig 8. External clock timing.

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START

BIT

PARITY STOP START

BIT

DATA BITS (5-8)

RX

D0

D1

D2

D3

D4

D5

D6

D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

t

20d

ACTIVE

INT

t

21d

ACTIVE

IOR

16 BAUD RATE CLOCK

002aaa113

Fig 9. Receive timing.

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START

BIT

PARITY STOP START

BIT

DATA BITS (5–8)

RX

D0

D1

D2

D3

D4

D5

D6

D7

t

25d

ACTIVE

DATA

READY

RXRDY

t

26d

ACTIVE

IOR

002aaa114

Fig 10. Receive ready timing in non-FIFO mode.

START

BIT

PARITY STOP

BIT BIT

DATA BITS (5–8)

RX

D0

D1

D2

D3

D4

D5

D6

D7

FIRST BYTE THAT

REACHES THE

TRIGGER LEVEL

t

25d

ACTIVE

DATA

READY

RXRDY

t

26d

ACTIVE

IOR

002aaa115

Fig 11. Receive ready timing in FIFO mode.

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START

BIT

PARITY STOP START

BIT

DATA BITS (5–8)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

ACTIVE TX READY

INT

t

22d

t

24d

t

23d

ACTIVE

IOW

16 BAUD RATE CLOCK

002aaa116

Fig 12. Transmit timing.

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Fig 13. Transmit ready timing in non-FIFO mode.

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START

BIT

PARITY STOP

BIT

DATA BITS (5-8)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 DATA BITS

6 DATA BITS

7 DATA BITS

ACTIVE

IOW

D0–D7

TXRDY

t

28d

BYTE #16

t

27d

FIFO FULL

002aaa346

Fig 14. Transmit ready timing in FIFO mode (DMA mode ‘1’).

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11. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

e

D

E

y

X

A

39

29

b

p

Z

E

28

40

b

1

w

M

44

1

H

E

pin 1 index

A

1

A

4

e

(A )

3

6

18

β

L

p

k

detail X

7

17

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

A

Z

E

4

1

(1)

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

3

1

D

E

D

E

p

max.

min.

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22 1.44

14.99 14.99 17.40 17.40 1.07 1.02

0.53

0.33

0.51 0.25 3.05

0.02 0.01 0.12

1.27

0.05

0.18 0.18

0.1

2.16 2.16

o

45

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.63 0.63 0.695 0.695 0.048 0.057

0.59 0.59 0.685 0.685 0.042 0.040

0.021

0.013

inches

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

01-11-14

SOT187-2

112E10

MS-018

EDR-7319

Fig 15. PLCC44 package outline (SOT187-2).

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12. Soldering

12.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering can still

be used for certain surface mount ICs, but it is not suitable for ﬁne pitch SMDs. In

these situations reﬂow soldering is recommended. In these situations reﬂow

soldering is recommended.

12.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder

paste material. The top-surface temperature of the packages should preferably be

kept:

• below 220 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA and SSOP-T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all

times.

12.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

• Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

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• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in

most applications.

12.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

12.5 Package related soldering information

Table 26: Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, LBGA, LFBGA, SQFP, SSOP-T^[3],

TFBGA, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSQFP,

HSOP, HTQFP, HTSSOP, HVQFN, HVSON,

SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^[5][6]

not recommended^[7]

SSOP, TSSOP, VSO, VSSOP

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

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[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow

soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow

oven. The package body peak temperature must be kept as low as possible.

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

13. Revision history

Table 27: Revision history

Rev Date

CPCN

-

Description

03 20030620

Product data (9397 750 11636). ECN 853-2375 30034 of 16 June 2003.

Modiﬁcations:

• Figure 3 “Crystal oscillator connection.” on page 9: changed capacitors’ values and

added connection with oscillator.

02 20030313

01 20020910

-

Product data (9397 750 11205). ECN 853-2375 29620 of 07 March 2003.

Product data (9397 750 08936). ECN 853-2375 28891 of 10 September 2002.

9397 750 11636

Product data

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14. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

15. Deﬁnitions

16. Disclaimers

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

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Product data

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SC16C2552

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Philips Semiconductors

Contents

1

2

3

4

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 23

Static characteristics . . . . . . . . . . . . . . . . . . . 24

Dynamic characteristics. . . . . . . . . . . . . . . . . 25

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 26

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33

9

10

10.1

11

12

12.1

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Introduction to soldering surface mount

packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 34

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 34

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 35

Package related soldering information. . . . . . 35

6

Functional description . . . . . . . . . . . . . . . . . . . 6

UART A-B functions . . . . . . . . . . . . . . . . . . . . . 6

Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 7

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 8

Time-out interrupts . . . . . . . . . . . . . . . . . . . . . . 8

Programmable baud rate generator . . . . . . . . . 8

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 10

Loop-back mode. . . . . . . . . . . . . . . . . . . . . . . 10

12.2

12.3

12.4

12.5

6.1

6.2

6.3

6.4

6.5

6.6

6.7

13

14

15

16

Revision history . . . . . . . . . . . . . . . . . . . . . . . 36

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 37

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 12

Transmit (THR) and Receive (RHR)

Holding Registers . . . . . . . . . . . . . . . . . . . . . 13

Interrupt Enable Register (IER) . . . . . . . . . . . 13

IER versus Transmit/Receive FIFO interrupt

mode operation . . . . . . . . . . . . . . . . . . . . . . . 14

IER versus Receive/Transmit FIFO polled

7.2

7.2.1

7.2.2

mode operation . . . . . . . . . . . . . . . . . . . . . . . 14

FIFO Control Register (FCR) . . . . . . . . . . . . . 15

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Interrupt Status Register (ISR) . . . . . . . . . . . . 17

Line Control Register (LCR) . . . . . . . . . . . . . . 18

Modem Control Register (MCR) . . . . . . . . . . . 19

Line Status Register (LSR). . . . . . . . . . . . . . . 20

Modem Status Register (MSR). . . . . . . . . . . . 21

Scratchpad Register (SPR) . . . . . . . . . . . . . . 22

Alternate Function Register (AFR) . . . . . . . . . 22

SC16C2552 external reset conditions . . . . . . 23

7.3

7.3.1

7.3.2

7.4

7.5

7.6

7.7

7.8

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Printed in the U.S.A

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 20 June 2003

Document order number: 9397 750 11636


型号：	SC16C2552IA44
厂家：	NXP
描述：	Dual UART with 16-byte transmit and receive FIFOs 双UART，具有16字节的发送和接收FIFO 先进先出芯片
文件：	总38页 (文件大小：530K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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