SC16C652BIB48,157_技术文档

SC16C652B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte

FIFOs and infrared (IrDA) encoder/decoder

Rev. 04 — 1 September 2005

Product data sheet

1. General description

The SC16C652B is a 2 channel Universal Asynchronous Receiver and Transmitter

(UART) used for serial data communications. Its principal function is to convert parallel

data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.

The SC16C652B is pin compatible with the SC16C2550. It will power-up to be functionally

equivalent to the 16C2450. The SC16C652B provides enhanced UART functions with

32-byte FIFOs, modem control interface, DMA mode data transfer, and IrDA

encoder/decoder. The DMA mode data transfer is controlled by the FIFO trigger levels

and the TXRDY and RXRDY signals. On-board status registers provide the user with error

indications and operational status. System interrupts and modem control features may be

tailored by software to meet speciﬁc user requirements. An internal loop-back capability

allows on-board diagnostics. Independent programmable baud rate generators are

provided to select transmit and receive baud rates.

The SC16C652B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,

and is available in plastic LQFP48 and very small (Micro-UART) HVQFN32 packages.

2. Features

■ 2 channel UART

■ 5 V, 3.3 V and 2.5 V operation

■ 5 V tolerant inputs

■ Industrial temperature range (−40 °C to +85 °C)

■ Pin and functionally compatible to 16C2450 in LQFP48 package, and software

compatible with industry standard 16C450, 16C550, and SC16C650

■ Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V

■ 32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

■ 32-byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the

external CPU

■ Independent transmit and receive UART control

■ Four selectable Receive and Transmit FIFO interrupt trigger levels

■ Automatic software (Xon/Xoff) and hardware (RTS/CTS) ﬂow control

■ Programmable Xon/Xoff characters

■ Software selectable baud rate generator

■ Standard modem interface or infrared IrDA encoder/decoder interface

■ Supports IrDA version 1.0 (up to 115.2 kbit/s)

■ Sleep mode

■ Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

■ Transmit, Receive, Line Status, and Data Set interrupts independently controlled

■ Fully programmable character formatting:

◆ 5-bit, 6-bit, 7-bit, or 8-bit characters

◆ Even, odd, or no-parity formats

◆ 1, 1¹⁄₂, or 2-stop bit

◆ Baud generation (DC to 5 Mbit/s)

■ False start-bit detection

■ Complete status reporting capabilities

■ 3-state output TTL drive capabilities for bi-directional data bus and control bus

■ Line break generation and detection

■ Internal diagnostic capabilities:

◆ Loop-back controls for communications link fault isolation

■ Prioritized interrupt system controls

■ Modem control functions (CTS, RTS, DSR, DTR, RI, CD)

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

SC16C652BIB48

SC16C652BIBS

LQFP48

plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm

SOT313-2

SOT617-1

HVQFN32 plastic thermal enhanced very thin quad ﬂat package; no leads;

32 terminals; body 5 × 5 × 0.85 mm

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

2 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

4. Block diagram

SC16C652B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTER

D0 to D7

IOR

DATA BUS

AND

IOW

RESET

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RXA, RXB

REGISTER

FLOW

CONTROL

LOGIC

A0 to A2

CSA

IR

DECODER

REGISTER

SELECT

LOGIC

CSB

DTRA, DTRB

RTSA, RTSB

OP2A, OP2B

MODEM

CONTROL

LOGIC

CTSA, CTSB

RIA, RIB

CDA, CDB

DSRA, DSRB

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

002aaa592

XTAL1

XTAL2

Fig 1. Block diagram of SC16C652B

SC16C652B_4

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SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

5. Pinning information

5.1 Pinning

1

2

36

35

34

33

32

31

30

29

28

27

26

25

D5

D6

RESET

DTRB

DTRA

RTSA

OP2A

RXRDYA

INTA

INTB

A0

3

D7

4

RXB

RXA

TXRDYB

TXA

5

6

SC16C652BIB48

7

8

TXB

9

OP2B

CSA

CSB

n.c.

10

11

12

A1

A2

n.c.

002aaa593

Fig 2. Pin conﬁguration for LQFP48

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

D6

D7

RESET

RTSA

OP2A

INTA

INTB

A0

RXB

RXA

TXA

TXB

OP2B

CSA

SC16C652BIBS

A1

A2

002aaa865

Transparent top view

Fig 3. Pin conﬁguration for HVQFN32

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

4 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

5.2 Pin description

Table 2:

Symbol

Pin description

Type Description

LQFP48 HVQFN32

A0

28

27

26

40

16

19

18

17

-

I

Address 0 select bit. Internal register address selection.

Address 1 select bit. Internal register address selection.

A1

A2

Address 2 select bit. Internal register address selection.

CDA

CDB

Carrier Detect (active LOW). These inputs are associated with individual UART

channels A through B. A logic 0 on this pin indicates that a carrier has been

detected by the modem for that channel.

-

CSA

CSB

10

11

8

9

I

Chip Select A, B (active LOW). This function is associated with individual

channels, A through B. These pins enable data transfers between the user CPU

and the SC16C652B for the channel(s) addressed. Individual UART sections (A, B)

are addressed by providing a logic 0 on the respective CSA, CSB pin.

CTSA

CTSB

38

23

25

16

Clear to Send (active LOW). These inputs are associated with individual UART

channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is

ready to accept transmit data from the SC16C652B. Status can be tested by

reading MSR[4]. This pin has no effect on the UART’s transmit or receive

operation.

DSRA

DSRB

39

20

-

I

Data Set Ready (active LOW). These inputs are associated with individual UART

channels, A through B. A logic 0 on this pin indicates the modem or data set is

powered-on and is ready for data exchange with the UART. This pin has no effect

on the UART’s transmit or receive operation.

DTRA

DTRB

34

35

-

O

Data Terminal Ready (active LOW). These outputs are associated with individual

UART channels, A through B. A logic 0 on this pin indicates that the SC16C652B is

powered-on and ready. This pin can be controlled via the modem control register.

Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem.

This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. This pin

has no effect on the UART’s transmit or receive operation.

D0

44

45

46

47

48

1

27

28

29

30

31

32

1

I/O

Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least signiﬁcant bit

and the ﬁrst data bit in a transmit or receive serial data stream.

D1

D2

D3

D4

D5

D6

2

D7

3

2

GND

INTA

INTB

17

30

29

13

21

20

I

Signal and power ground.

O

Interrupt A, B (3-state). This function is associated with individual channel

interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1,

interrupts are enabled in the Interrupt Enable Register (IER), and is active when an

interrupt condition exists. Interrupt conditions include: receiver errors, available

receiver buffer data, transmit buffer empty, or when a modem status ﬂag is

detected.

IOR

19

14

I

Read strobe (active LOW strobe). A logic 0 transition on this pin will load the

contents of an internal register deﬁned by address bits A0 to A2 onto the

SC16C652B data bus (D0 to D7) for access by external CPU.

SC16C652B_4

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SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 2:

Symbol

Pin description …continued

Type Description

LQFP48 HVQFN32

IOW

15

12

I

Write strobe (active LOW strobe). A logic 0 transition on this pin will transfer the

contents of the data bus (D0 to D7) from the external CPU to an internal register

that is deﬁned by address bits A0 to A2.

OP2A

OP2B

32

9

22

7

O

Output 2 (user-deﬁned). This function is associated with individual channels, A

through B. The state at these pin(s) are deﬁned by the user and through MCR

register bit 3. INTA, INTB are set to the active mode and OP2 to logic 0 when

MCR[3] is set to a logic 1. INTA, INTB are set to the 3-state mode and OP2 to a

logic 1 when MCR[3] is set to a logic 0 (see Table 20 “Modem Control Register bits

description”, bit 3). Since these bits control both the INTA, INTB operation and

OP2 outputs, only one function should be used at one time, INT or OP2.

RESET

36

24

I

Reset (active HIGH). A logic 1 on this pin will reset the internal registers and all

the outputs. The UART transmitter output and the receiver input will be disabled

during reset time. (See Section 7.11 “SC16C652B external reset condition” for

initialization details.)

RIA

RIB

41

21

-

I

Ring Indicator (active LOW). These inputs are associated with individual UART

channels, A through B. A logic 0 on this pin indicates the modem has received a

ringing signal from the telephone line. A logic 1 transition on this input pin will

generate an interrupt.

RTSA

RTSB

33

22

23

15

O

Request to Send (active LOW). These outputs are associated with individual

UART channels, A through B. A logic 0 on the RTS pin indicates the transmitter

has data ready and waiting to send. Writing a logic 1 in the modem control register

MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this

pin will be set to a logic 1. This pin has no effect on the UART’s transmit or receive

operation.

RXA

RXB

5

4

3

I

Receive data A, B. These inputs are associated with individual serial channel data

to the SC16C652B receive input circuits, A through B. The RX signal will be a

logic 1 during reset, idle (no data), or when the transmitter is disabled. During the

local loop-back mode, the RX input pin is disabled and TX data is connected to the

UART RX input, internally.

RXRDYA 31

RXRDYB 18

-

O

Receive Ready A, B (active LOW). This function provides the RX FIFO/RHR

status for individual receive channels (A to B). RXRDYn is primarily intended for

monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0 indicates

there is a receive data to read/upload, that is, receive ready status with one or

more RX characters available in the FIFO/RHR. This pin is a logic 1 when the

FIFO/RHR is empty or when the programmed trigger level has not been reached.

This signal can also be used for single mode transfers (DMA mode 0).

TXA

TXB

7

8

5

6

O

Transmit data A, B. These outputs are associated with individual serial transmit

channel data from the SC16C652B. The TX signal will be a logic 1 during reset,

idle (no data), or when the transmitter is disabled. During the local loop-back

mode, the TX output pin is disabled and TX data is internally connected to the

UART RX input.

TXRDYA 43

-

Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR

status for individual transmit channels (A to B). TXRDYn is primarily intended for

monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual

channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is, at

lease one location is empty and available in the FIFO or THR. This pin goes to a

logic 1 (DMA mode 1) when there are no more empty locations in the FIFO or

THR. This signal can also be used for single mode transfers (DMA mode 0).

TXRDYB

6

SC16C652B_4

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SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 2:

Symbol

Pin description …continued

Type Description

LQFP48 HVQFN32

V_CC

42

13

26

10

I

Power supply input.

XTAL1

Crystal or external clock input. Functions as a crystal input or as an external

clock input. A crystal can be connected between this pin and XTAL2 to form an

internal oscillator circuit. This conﬁguration requires an external 1 MΩ resistor

between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be

connected to this pin to provide custom data rates (see Section 6.8

“Programmable baud rate generator”). See Figure 4.

XTAL2

14

11

O

Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal

oscillator output or buffered clock output. Should be left open if an external clock is

connected to XTAL1. For extended frequency operation, this pin should be tied to

V_CCvia a 2 kΩ resistor.

6. Functional description

The SC16C652B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is insured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex, especially

when manufactured on a single integrated silicon chip. The SC16C652B represents such

an integration with greatly enhanced features. The SC16C652B is fabricated with an

advanced CMOS process.

The SC16C652B is an upward solution that provides a dual UART capability with 32 bytes

of transmit and receive FIFO memory, instead of 16 bytes for the 16C2550 and none in

the 16C2450. The SC16C652B is designed to work with high speed modems and shared

network environments that require fast data processing time. Increased performance is

realized in the SC16C652B by the transmit and receive FIFOs. This allows the external

processor to handle more networking tasks within a given time. In addition, the four

selectable receive and transmit FIFO trigger interrupt levels are uniquely provided for

maximum data throughput performance especially when operating in a multi-channel

environment. The FIFO memory greatly reduces the bandwidth requirement of the

external controlling CPU, increases performance, and reduces power consumption.

The SC16C652B is capable of operation up to 5 Mbit/s with a 80 MHz clock. With a crystal

or external clock input of 7.3728 MHz, the user can select data rates up to 460.8 kbit/s.

The rich feature set of the SC16C652B is available through internal registers. Selectable

receive and transmit FIFO trigger levels, selectable TX and RX baud rates, and modem

interface controls are all standard features. Following a power-on reset or an external

reset, the SC16C652B is software compatible with the previous generation, SC16C2550

and ST16C2450.

SC16C652B_4

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SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

6.1 UART A-B functions

The UART provides the user with the capability to bi-directionally transfer information

between an external CPU, the SC16C652B package, and an external serial device. A

logic 0 on chip select pins CSA and/or CSB allows the user to conﬁgure, send data,

and/or receive data via UART channels A-B. Individual channel select functions are shown

in Table 3.

Table 3:

Serial port selection

Chip Select

CSA-CSB = 1

CSA = 0

Function

none

UART channel A

UART channel B

CSB = 0

6.2 Internal registers

The SC16C652B provides two sets of internal registers (A and B) consisting of

17 registers each for monitoring and controlling the functions of each channel of the

UART. These registers are shown in Table 4. The UART registers function as data holding

registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control

Register (FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a

user accessible Scratchpad Register (SPR).

Table 4:

A2

Internal registers decoding

A0 Read mode

A1

Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

LSB of Divisor Latch

MSB of Divisor Latch

0

1

MSB of Divisor Latch

Enhanced register set (EFR, Xon1/Xon2, Xoff1/Xoff2)^[3]

0

1

0

1

0

1

0

1

Enhanced Feature Register

Xon1 word

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

[3] Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when the LCR is set to ‘BFh’.

SC16C652B_4

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SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

6.3 FIFO operation

The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register

bit 0 (FCR[0]). With 16C2550 devices, the user can set the receive trigger level, but not

the transmit trigger level. The SC16C652B provides independent trigger levels for both

receiver and transmitter. To remain compatible with SC16C2550, the transmit interrupt

trigger level is set to 16 following a reset. It should be noted that the user can set the

transmit trigger levels by writing to the FCR, but activation will not take place until EFR[4]

is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is

delivered to the external CPU. An interrupt is generated whenever the Receive Holding

Register (RHR) has not been read following the loading of a character or the receive

trigger level has not been reached.

Table 5:

Flow control mechanism

Selected trigger level

(characters)

INT pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

RX

8

TX

16

8

0

16

24

28

16

24

28

16

24

28

7

24

30

15

23

6.4 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C652B monitors the CTS pin

for a remote buffer overﬂow indication and controls the RTS pin for local buffer overﬂows.

Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to

a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a ﬂow control request,

ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C652B will suspend

TX transmissions as soon as the stop bit of the character in process is shifted out.

Transmission is resumed after the CTS input returns to a logic 0, indicating more data may

be sent.

With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS

off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return

to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the

programmed trigger level. However, under the above described conditions, the

SC16C652B will continue to accept data until the receive FIFO is full.

6.5 Software ﬂow control

When software ﬂow control is enabled, the SC16C652B compares one or two sequential

receive data characters with the programmed Xon or Xoff character value(s). If received

character(s) match the programmed Xoff values, the SC16C652B will halt transmission

(TX) as soon as the current character(s) has completed transmission. When a match

occurs, the receive ready (if enabled via Xoff IER[5]) ﬂags will be set and the interrupt

output pin (if receive interrupt is enabled) will be activated. Following a suspension due to

a match of the Xoff characters’ values, the SC16C652B will monitor the receive data

stream for a match to the Xon1/Xon2 character value(s). If a match is found, the

SC16C652B will resume operation and clear the ﬂags (ISR[4]).

SC16C652B_4

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SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow control.

Different conditions can be set to detect Xon/Xoff characters and suspend/resume

transmissions. When double 8-bit Xon/Xoff characters are selected, the SC16C652B

compares two consecutive receive characters with two software ﬂow control 8-bit values

(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above

described ﬂow control mechanisms, ﬂow control characters are not placed (stacked) in the

user accessible RX data buffer or FIFO. When using a software ﬂow control the Xon/Xoff

characters cannot be used for data transfer.

In the event that the receive buffer is overﬁlling and ﬂow control needs to be executed, the

SC16C652B automatically sends an Xoff message (when enabled) via the serial TX

output to the remote modem. The SC16C652B sends the Xoff1/Xoff2 characters as soon

as received data passes the programmed trigger level. To clear this condition, the

SC16C652B will transmit the programmed Xon1/Xon2 characters as soon as receive data

drops below the programmed trigger level.

6.6 Special feature software ﬂow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit

character is detected, it will be placed on the user-accessible data stack along with normal

incoming RX data. This condition is selected in conjunction with EFR[3:0]. Note that

software ﬂow control should be turned off when using this special mode by setting

EFR[3:0] to a logic 0.

The SC16C652B compares each incoming receive character with Xoff2 data. If a match

exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate

detection of a special character. Although Table 9 “SC16C652B internal registers” shows

each X-Register with eight bits of character information, the actual number of bits is

dependent on the programmed word length. Line Control Register bits LCR[1:0] deﬁne the

number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length

selected by LCR[1:0] also determine the number of bits that will be used for the special

character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive

character.

6.7 Hardware/software and time-out interrupts

The interrupts are enabled by IER[3:0]. Care must be taken when handling these

interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C652B

will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to

continuing operations. The ISR provides the current singular highest priority interrupt only.

It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition

can exist where a higher priority interrupt may mask the lower priority CTS/RTS

interrupt(s). Only after servicing the higher pending interrupt will the lower priority

CTS/RTS interrupt(s) be reﬂected in the status register. Servicing the interrupt without

investigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt

priority (when enabled by IER[0]). The receiver issues an interrupt after the number of

characters have reached the programmed trigger level. In this case, the SC16C652B

FIFO may hold more characters than the programmed trigger level. Following the removal

of a data byte, the user should re-check LSR[0] for additional characters. A Receive

SC16C652B_4

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SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Time Out will not occur if the receive FIFO is empty. The time-out counter is reset at the

center of each stop bit received or each time the Receive Holding Register (RHR) is read.

The actual time-out value is 4 character time, including data information length, start bit,

parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times.

6.8 Programmable baud rate generator

The SC16C652B supports high speed modem technologies that have increased input

data rates by employing data compression schemes. For example, a 33.6 kbit/s modem

that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s

ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.

The SC16C652B can support a standard data rate of 921.6 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing

independent TX/RX channel control. The programmable Baud Rate Generator is capable

of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is

necessary to use full rail swing on the clock input. The SC16C652B can be conﬁgured for

internal or external clock operation. For internal clock oscillator operation, an industry

standard microprocessor crystal is connected externally between the XTAL1 and XTAL2

pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the

internal baud rate generator for standard or custom rates (see Table 6).

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). The

SC16C652B divides the basic external clock by 16. The basic 16× clock provides table

rates to support standard and custom applications using the same system design. The

rate table is conﬁgured via the DLL and DLM internal register functions. Customized baud

rates can be achieved by selecting the proper divisor values for the MSB and LSB

sections of baud rate generator.

Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a

user capability for selecting the desired ﬁnal baud rate. The example in Table 6 shows the

selectable baud rate table available when using a 1.8432 MHz external clock input.

XTAL1

XTAL2

XTAL1

XTAL2

1.5 kΩ

X1

1.8432 MHz

C1

22 pF

C2

33 pF

C1

22 pF

C2

47 pF

002aaa870

Fig 4. Crystal oscillator connection

SC16C652B_4

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SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 6:

Baud rate generator programming table using a 1.8432 MHz clock

Output

baud rate

(bit/s)

Output

16× clock divisor

(decimal)

Output

16× clock divisor

(HEX)

DLM

program value

(HEX)

DLL

program value

(HEX)

50

2304

1536

1047

768

384

192

96

900

600

417

300

180

C0

60

09

06

04

03

01

00

17

00

80

C0

60

30

20

18

10

0C

06

03

02

01

75

110

150

300

600

1200

2400

3600

4800

7200

9600

19.2 k

38.4 k

57.6 k

115.2 k

48

30

32

20

24

18

16

10

12

0C

06

6

3

03

2

02

1

01

6.9 DMA operation

The SC16C652B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. The user can optionally operate the transmit and receive FIFOs in the

DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output

pins. Table 7 and Table 8 show this.

Table 7:

Effect of DMA mode on state of RXRDY pin

Non-DMA mode

DMA mode

1 = FIFO empty

0-to-1 transition when FIFO empties

1-to-0 transition when FIFO reaches trigger level, or time-out occurs

0 = at least 1 byte in FIFO

Table 8:

Effect of DMA mode on state of TXRDY pin

Non-DMA mode

1 = at least 1 byte in FIFO

0 = FIFO empty

DMA mode

0-to-1 transition when FIFO becomes full

1-to-0 transition when FIFO goes below trigger level

6.10 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the

normal modem interface pins are disconnected and reconﬁgured for loop-back internally

(see Figure 5). MCR[3:0] register bits are used for controlling loop-back diagnostic testing.

In the loop-back mode, the transmitter output (TX) and the receiver input (RX) are

disconnected from their associated interface pins, and instead are connected together

internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control

inputs pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and

SC16C652B_4

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SC16C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

MCR[2] (OP1). Loop-back test data is entered into the transmit holding register via the

user data bus interface, D[7:0]. The transmit UART serializes the data and passes the

serial data to the receive UART via the internal loop-back connection. The receive UART

converts the serial data back into parallel data that is then made available at the user data

interface D[7:0]. The user optionally compares the received data to the initial transmitted

data for verifying error-free operation of the UART TX/RX circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The modem

control interrupts are also operational.

SC16C652B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTERS

REGISTER

DATA BUS

AND

D0 to D7

IOR

IOW

RESET

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

REGISTERS

RECEIVE

SHIFT

REGISTER

RXA, RXB

FLOW

CONTROL

LOGIC

IR

DECODER

A0 to A2

CSA

REGISTER

SELECT

LOGIC

CSB

RTSA, RTSB

CTSA, CTSB

DTRA, DTRB

MODEM

CONTROL

LOGIC

DSRA, DSRB

(OP1A, OP1B)

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

RIA, RIB

(OP2A, OP2B)

CDA, CDB

002aaa594

XTAL1 XTAL2

Fig 5. Internal loop-back mode diagram

SC16C652B_4

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SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

6.11 Sleep mode

Sleep mode is an enhanced feature of the SC16C652B UART. It is enabled when EFR[4],

the enhanced functions bit, is set and when IER[4] of both channels are set. Sleep mode

is entered when:

• Modem input pins are not toggling.

• The serial data input line, RX, is idle (logic HIGH).

• The TX FIFO and TX shift register are empty.

• There are no interrupts pending.

Remark: Sleep mode will not be entered if there is data in the RX FIFO.

In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are

clocked using these clocks, the power consumption is greatly reduced.

Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be

done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]

before writing to DLL or DLH.

SC16C652B resumes normal operation by any of the following:

• Receives a start bit on RXA/RXB pin.

• Data is loaded into transmit FIFO.

• A change of state on any of the modem input pins

If the device is awakened by one of the conditions described above, it will return to the

Sleep mode automatically after the last character is transmitted or read by the user. The

device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a

logic 0.

SC16C652B_4

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SC16C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7. Register descriptions

Table 9 details the assigned bit functions for the SC16C652B internal registers. The

assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.11.

Table 9:

SC16C652B internal registers

A2 A1 A0 Register Default^[1]Bit 7

General Register Set^[3]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

CTS

bit 6

RTS

bit 5

Xoff

bit 4

bit 3

bit 2

bit 1

bit 0

bit 4

Sleep

modem receive

status line

interrupt status

transmit receive

holding

register

interrupt interrupt interrupt mode^[2]

holding

register

[2]

Rx

interrupt interrupt

0

1

0

1

FCR

ISR

00

01

00

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

TX

trigger

(MSB)^[2]

TX trigger DMA

XMIT

FIFO

reset

RCVR

FIFO

reset

FIFOs

enable

(LSB)^[2]

mode

select

FIFOs

INT

priority

bit 1

INT

priority

bit 0

INT

status

enabled enabled priority

bit 4

priority

bit 3

priority

bit 2

LCR

divisor

latch

enable

set break set parity even

parity

stop bits word

length

word

length

bit 0

parity

enable

bit 1

1

0

1

MCR

LSR

00

60

clock

IRDA

0

loop back OP2/INT (OP1)

enable

RTS

DTR

select^[2]enable

FIFO

data

error

THR and THR

TSR

empty

break

framing parity

overrun receive

error

empty

interrupt error

error

data

ready

1

0

1

MSR

SPR

X0

FF

CD

RI

DSR

bit 5

CTS

bit 4

∆CD

∆RI

∆DSR

∆CTS

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

Special Register Set^[4]

0

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

0

1

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

Enhanced Register Set^[5]

0

1

0

EFR

00

Auto

CTS

Auto RTS special

Enable

Cont-3

Cont-2

Tx, Rx

Control

Cont-1

Tx, Rx

Control

Cont-0

Tx, Rx

Control

character IER[7:4], Tx, Rx

select

ISR[5:4], Control

FCR[5:4],

MCR[7:5]

1

0

1

0

1

0

1

Xon-1

Xon-2

Xoff-1

Xoff-2

00

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 1

bit 9

bit 0

bit 8

bit 0

bit 8

bit 15

bit 7

bit 14

bit 6

bit 13

bit 5

bit 12

bit 4

bit 11

bit 3

bit 10

bit 2

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

[1] The value shown in represents the register’s initialized HEX value; X = not applicable.

[2] This bit is only accessible when EFR[4] is set.

[3] Accessible only when LCR[7] is logic 0.

[4] Baud rate registers accessible only when LCR[7] is logic 1.

[5] Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’.

SC16C652B_4

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SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the

TSR and UART via the THR, providing that the THR is empty. The THR empty ﬂag in the

LSR will be set to a logic 1 when the transmitter is empty or when data is transferred to the

TSR. Note that a write operation can be performed when the THR empty ﬂag is set

(logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a

Receive Serial Shift Register (RSR). Receive data is removed from the SC16C652B and

receive FIFO by reading the RHR. The receive section provides a mechanism to prevent

false starts. On the falling edge of a start or false start bit, an internal receiver counter

starts counting clocks at the 16× clock rate. After 7¹⁄₂clocks, the start bit time should be

shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a

logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from

assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INTA, INTB output pins.

Table 10: Interrupt Enable Register bits description

Bit

Symbol Description

7

IER[7]

IER[6]

IER[5]

CTS interrupt.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC16C652B issues an interrupt when

the CTS pin transitions from a logic 0 to a logic 1.

6

5

RTS interrupt.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC16C652B issues an interrupt when

the RTS pin transitions from a logic 0 to a logic 1.

Xoff interrupt.

logic 0 = disable the software ﬂow control, receive Xoff interrupt (normal

default condition)

logic 1 = enable the software ﬂow control, receive Xoff interrupt.

Sleep mode.

4

3

IER[4]

IER[3]

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode

Modem Status Interrupt. This interrupt will be issued whenever there is a modem

status change as reﬂected in MSR[3:0].

logic 0 = disable the modem status register interrupt (normal default condition)

logic 1 = enable the modem status register interrupt

2

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a receive

data error condition exists as reﬂected in LSR[4:1].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

SC16C652B_4

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SC16C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 10: Interrupt Enable Register bits description …continued

Bit

Symbol Description

1

IER[1]

Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will be

issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO

modes, this interrupt will be issued whenever the FIFO is empty.

logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt

(normal default condition)

logic 1 = enable the TXRDY (ISR level 3) interrupt

0

IER[0]

Receive Holding Register. In the 16C450 mode, this interrupt will be issued when

the RHR has data, or is cleared when the RHR is empty. In the FIFO mode, this

interrupt will be issued when the FIFO has reached the programmed trigger level

or is cleared when the FIFO drops below the trigger level.

logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal

default condition)

logic 1 = enable the RXRDY (ISR level 2) interrupt

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by the TSR and UART for

transmission via the transmission media. The interrupt is cleared either by reading the

ISR, or by loading the THR with new data characters.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C652B in the FIFO polled

mode of operation. In this mode, interrupts are not generated and the user must poll the

LSR register for TX and/or RX data status. Since the receiver and transmitter have

separate bits in the LSR either or both can be used in the polled mode by selecting

respective transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will show if any FIFO data errors occurred.

SC16C652B_4

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SC16C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels, and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation, and is similar to

the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR,

if FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the

Receive Holding Register (RHR) is loaded with a character.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO is below the programmed trigger level. The receive interrupt is set when

the receive FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll

regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long

as the FIFO ﬁll level is above the programmed trigger level.

7.3.2 FIFO mode

Table 11: FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive FIFO

interrupt.

An interrupt is generated when the number of characters in the FIFO equals

the programmed trigger level. However, the FIFO will continue to be loaded

until it is full. Refer to Table 12.

5:4

3

FCR[5:4] Logic 0 or cleared is the default condition; TX trigger level = 16.

These bits are used to set the trigger level for the transmit FIFO interrupt.

The SC16C652B will issue a transmit empty interrupt when the number of

characters in FIFO drops below the selected trigger level. Refer to Table 13.

FCR[3]

DMA mode select.

logic 0 = set DMA mode ‘0’ (normal default condition)

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C652B is in the 16C450

mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs

enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no

characters in the transmit FIFO or transmit holding register, the TXRDY pin

will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the ﬁrst

character is loaded into the transmit holding register.

Receive operation in mode ‘0’: When the SC16C652B is in 16C450 mode,

or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least

one character in the receive FIFO, the RXRDY pin will be a logic 0. Once

active, the RXRDY pin will go to a logic 1 when there are no more characters

in the receiver.

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 11: FIFO Control Register bits description …continued

Bit

Symbol

Description

3

Transmit operation in mode ‘1’: When the SC16C652B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the

transmit FIFO is completely full. It will be a logic 0 when the trigger level has

been reached.

(cont.)

Receive operation in mode ‘1’: When the SC16C652B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,

or a Receive Time-Out has occurred, the RXRDY pin will go to a logic 0.

Once activated, it will go to a logic 1 after there are no more characters in the

FIFO.

2

1

0

FCR[2]

FCR[1]

FCR[0]

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’

when other FCR bits are written to, or they will not be programmed.

Table 12: RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level (bytes)

0

1

0

1

0

1

8

16

24

28

Table 13: TX FIFO trigger levels

FCR[5]

FCR[4]

TX FIFO trigger level (bytes)

0

1

0

1

0

1

16

8

24

30

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SC16C652B

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.4 Interrupt Status Register (ISR)

The SC16C652B provides six levels of prioritized interrupts to minimize external software

interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status

bits. Performing a read cycle on the ISR will provide the user with the highest pending

interrupt level to be serviced. No other interrupts are acknowledged until the pending

interrupt is serviced. A lower level interrupt may be seen after servicing the higher level

interrupt and re-reading the interrupt status bits. Table 14 “Interrupt source” shows the

data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources

associated with each of these interrupt levels.

Table 14: Interrupt source

Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

0

1

0

LSR (Receiver Line Status

Register)

2

3

0

1

0

1

0

1

0

RXRDY (Received Data Ready)

RXRDY (Receive Data time-out)

TXRDY (Transmitter Holding

Register Empty)

4

5

0

1

0

MSR (Modem Status Register)

RXRDY (Received Xoff signal)/

Special character

6

1

0

CTS, RTS change of state

Table 15: Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being

used in the 16C450 mode. They are set to a logic 1 when the FIFOs are

enabled in the SC16C652B mode.

logic 0 or cleared = default condition

5:4

ISR[5:4]

INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.

ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]

indicates that CTS, RTS have been generated. Note that once set to a

logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.

logic 0 or cleared = default condition

3:1

0

ISR[3:1]

ISR[0]

INT priority bits 2:0. These bits indicate the source for a pending interrupt at

interrupt priority levels 1, 2, and 3 (see Table 14).

logic 0 or cleared = default condition

INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as a

pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 16: Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6

LCR[6]

Set break. When enabled, the Break control bit causes a break condition to

be transmitted (the TX output is forced to a logic 0 state). This condition

exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

5:3

2

LCR[5:3]

LCR[2]

Programs the parity conditions (see Table 17).

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with the

programmed word length (see Table 18).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 19).

logic 0 or cleared = default condition

Table 17: LCR[5:3] parity selection

LCR[5] LCR[4] LCR[3] Parity selection

X

0

1

X

0

1

0

1

0

1

no parity

odd parity

even parity

forced parity ‘1’

forced parity ‘0’

Table 18: LCR[2] stop bit length

LCR[2]

Word length (bits) Stop bit length (bit times)

0

1

5, 6, 7, 8

5

1

1¹⁄₂

6, 7, 8

2

Table 19: LCR[1:0] word length

LCR[1]

LCR[0]

Word length (bits)

0

1

0

1

0

1

5

6

7

8

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Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 20: Modem Control Register bits description

Bit

Symbol

Description

7

MCR[7]

Clock select

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

IR enable (see Figure 17).

6

MCR[6]

logic 0 = enable the standard modem receive and transmit input/output

interface (normal default condition)

logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While

in this mode, the TX/RX output/inputs are routed to the infrared

encoder/decoder. The data input and output levels will conform to the

IrDA infrared interface requirement. As such, while in this mode, the

infrared TX output will be a logic 0 during idle data conditions.

5

4

MCR[5]

MCR[4]

Reserved; set to ‘0’.

Loop-back. Enable the local loop-back mode (diagnostics). In this mode the

transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI

are disconnected from the SC16C652B I/O pins. Internally the modem data

and control pins are connected into a loop-back data conﬁguration (see

Figure 5). In this mode, the receiver and transmitter interrupts remain fully

operational. The Modem Control Interrupts are also operational, but the

interrupts’ sources are switched to the lower four bits of the Modem Control.

Interrupts continue to be controlled by the IER register.

logic 0 = disable Loop-back mode (normal default condition)

logic 1 = enable local Loop-back mode (diagnostics)

OP2/INT enable

3

2

MCR[3]

MCR[2]

logic 0 = forces INT (A, B) outputs to the 3-state mode and sets OP2 to a

logic 1 (normal default condition)

logic 1 = forces the INT (A, B) outputs to the active mode and sets OP2 to

a logic 0

(OP1). OP1A/OP1B are not available as an external signal in the

SC16C652B. This bit is instead used in the Loop-back mode only. In the

Loop-back mode, this bit is used to write the state of the modem RI interface

signal.

1

0

MCR[1]

MCR[0]

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

22 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C652B and the CPU.

Table 21: Line Status Register bits description

Bit

Symbol Description

7

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when there are no remaining error ﬂags

associated with the remaining data in the FIFO.

6

5

LSR[6]

LSR[5]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the transmit holding register and the transmit shift register are

both empty. It is reset to logic 0 whenever either the THR or TSR contains a data

character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and

transmit shift register are both empty.

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the transmit holding register into the transmitter shift register.

The bit is reset to a logic 0 concurrently with the loading of the transmitter

holding register by the CPU. In the FIFO mode, this bit is set when the transmit

FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s). In

the FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error.

logic 0 = no parity error (normal default condition

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with the

character at the top of the FIFO.

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the Receive Shift

Register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the Receive Shift Register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

0

LSR[0]

Receive data ready.

logic 0 = no data in Receive Holding Register or FIFO (normal default

condition)

logic 1 = data has been received and is saved in the Receive Holding Register

or FIFO

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

23 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or

other peripheral device to which the SC16C652B is connected. Four bits of this register

are used to indicate the changed information. These bits are set to a logic 1 whenever a

control input from the modem changes state. These bits are set to a logic 0 whenever the

CPU reads this register.

Table 22: Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

CD. During normal operation, this bit is the complement of the CD input.

Reading this bit in the loop-back mode produces the state of MCR[3] (OP2).

6

5

4

3

MSR[6]

MSR[5]

MSR[4]

MSR[3]

RI. During normal operation, this bit is the complement of the RI input.

Reading this bit in the loop-back mode produces the state of MCR[2] (OP1).

DSR. During normal operation, this bit is the complement of the DSR input.

During the loop-back mode, this bit is equivalent to MCR[0] (DTR).

CTS. During normal operation, this bit is the complement of the CTS input.

During the loop-back mode, this bit is equivalent to MCR[1] (RTS).

[1]

∆CD

logic 0 = no CD change (normal default condition)

logic 1 = the CD input to the SC16C652B has changed state since the

last time it was read. A modem Status Interrupt will be generated.

[1]

2

1

0

MSR[2]

MSR[1]

MSR[0]

∆RI

logic 0 = no RI change (normal default condition)

logic 1 = the RI input to the SC16C652B has changed from a logic 0 to a

logic 1. A modem Status Interrupt will be generated.

[1]

∆DSR

logic 0 = no DSR change (normal default condition)

logic 1 = the DSR input to the SC16C652B has changed state since the

last time it was read. A modem Status Interrupt will be generated.

[1]

∆CTS

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C652B has changed state since the

last time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.

7.9 Scratchpad Register (SPR)

The SC16C652B provides a temporary data register to store 8 bits of user information.

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

24 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection. When the

Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are

concatenated into two sequential numbers.

Table 23: Enhanced Feature Register bits description

Bit

Symbol Description

7

EFR[7]

Automatic CTS ﬂow control.

logic 0 = automatic CTS ﬂow control is disabled (normal default condition)

logic 1 = enable automatic CTS ﬂow control. Transmission will stop when

CTS goes to a logical 1. Transmission will resume when the CTS pin returns

to a logical 0.

6

EFR[6]

Automatic RTS ﬂow control. Automatic RTS may be used for hardware ﬂow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be

generated when the receive FIFO is ﬁlled to the programmed trigger level and

RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when

data is unloaded below the next lower trigger level (programmed trigger level 1).

The state of this register bit changes with the status of the hardware ﬂow

control. RTS functions normally when hardware ﬂow control is disabled.

logic

0 = automatic RTS ﬂow control is disabled (normal default condition)

logic 1 = enable automatic RTS ﬂow control

Special Character Detect.

5

EFR[5]

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. The SC16C652B compares each

incoming receive character with Xoff2 data. If a match exists, the received

data will be transferred to FIFO and ISR[4] will be set to indicate detection of

special character. Bit-0 in the X-registers corresponds with the LSB bit for the

receive character. When this feature is enabled, the normal software ﬂow

control must be disabled (EFR[3:0] must be set to a logic 0).

4

EFR[4]

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and

MCR[7:5] can be modiﬁed and latched. After modifying any bits in the enhanced

registers, EFR[4] can be set to a logic 0 to latch the new values. This feature

prevents existing software from altering or overwriting the SC16C652B

enhanced functions.

logic 0 = disable/latch enhanced features. IER[7:4], ISR[5:4], FCR[5:4], and

MCR[7:5] are saved to retain the user settings, then IER[7:4] ISR[5:4],

FCR[5:4], and MCR[7:5] are set to a logic 0 to be compatible with SC16C554

mode. (Normal default condition.)

logic 1 = enables the enhanced functions. When this bit is set to a logic 1, all

enhanced features of the SC16C652B are enabled and user settings stored

during a reset will be restored.

3:0

EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming these

bits. See Table 24.

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

25 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 24: Software ﬂow control functions^[1]

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software ﬂow controls

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

X

0

1

No transmit ﬂow control

Transmit Xon1/Xoff1

Transmit Xon2/Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

No receive ﬂow control

Receiver compares Xon1/Xoff1

Receiver compares Xon2/Xoff2

Transmit Xon1/Xoff1

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Transmit Xon2/Xoff2

0

1

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

Receiver compares Xon1 and Xon2/Xoff1 and Xoff2

[1] When using a software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

7.11 SC16C652B external reset condition

Table 25: Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

FCR

ISR

FCR[7:0] = 0

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

LSR

MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

SFR[7:0] = 1

MSR

SPR

DLL

DLL[7:0] = X

DLM

DLM[7:0] = X

Table 26: Reset state for outputs

Output

Reset state

logic 1

TXA, TXB

OP2A, OP2B

RTSA, RTSB

DTRA, DTRB

INTA, INTB

logic 1

3-state condition

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

26 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

8. Limiting values

Table 27: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

Max

7

Unit

V

supply voltage

-

V_n

voltage at any pin

GND − 0.3

V_CC+ 0.3

+85

V

T_amb

ambient temperature

storage temperature

total power dissipation per package

operating in free air

−40

−65

-

°C

mW

T_stg

+150

500

P_tot(pack)

9. Static characteristics

Table 28: Static characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC= ± 10 %; unless otherwise speciﬁed.

Symbol Parameter Conditions V_CC= 2.5 V

Min Max

−0.3 0.45

V_CC= 3.3 V

V_CC= 5.0 V

Min Max

−0.5 0.6

Unit

Min

−0.3

Max

0.6

V_IL(CK)

V_IH(CK)

V_IL

LOW-level clock input voltage

V

HIGH-level clock input voltage

1.8

V_CC

2.4

V_CC

0.8

3.0

V_CC

0.8

LOW-level input voltage

(except X1 clock)

−0.3

0.65

−0.3

−0.5

V_IH

HIGH-level input voltage

(except X1 clock)

1.6

-

2.0

-

2.2

-

V

V_OL

LOW-level output voltage on all I_OL= 5 mA

outputs^[1]

-

0.4

(databus)

I_OL= 4 mA

(other outputs)

-

0.4

-

I_OL= 2 mA

(databus)

-

0.4

-

I_OL= 1.6 mA

(other outputs)

-

0.4

-

V_OH

HIGH-level output voltage

I_OH= −5 mA

(databus)

-

2.4

I_OH= −1 mA

(other outputs)

-

2.0

-

I_OH= −800 µA

(data bus)

1.85

-

I_OH= −400 µA

(other outputs)

I_LIL

LOW-level input leakage current

clock leakage current

supply current

-

±10

±30

3.5

50

-

±10

±30

4.5

50

-

±10

±30

4.5

50

µA

mA

µA

pF

I_CL

I_CC

f = 5 MHz

[2]

I_CCsleep

C_i

sleep current

input capacitance

5

[1] Except XTAL2, V_OL= 1 V typical.

[2] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode.

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

27 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

10. Dynamic characteristics

Table 29: Dynamic characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC= ± 10 %; unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

Min Max

V_CC= 3.3 V

Min Max

V_CC= 5.0 V

Min Max

Unit

t_1w, t_2w

f_XTAL

t_6s

clock pulse duration

10

-

6

-

6

-

ns

[1] [2]

oscillator/clock frequency

address set-up time

address hold time

48

-

80

-

80

-

MHz

ns

0

t_6h

0

-

0

-

0

-

ns

t_7d

IOR delay from chip select

IOR strobe width

10

77

0

-

10

26

0

-

10

23

0

-

ns

t_7w

25 pF load

-

ns

t_7h

chip select hold time from

IOR

-

ns

t_9d

read cycle delay

25 pF load

20

-

20

-

20

-

ns

t_12d

t_12h

t_13d

t_13w

t_13h

delay from IOR to data

data disable time

77

15

-

26

15

-

23

15

-

IOW delay from chip select

IOW strobe width

10

20

0

10

20

0

10

15

0

-

chip select hold time from

IOW

-

t_15d

t_16s

t_16h

t_17d

t_18d

write cycle delay

data set-up time

25

20

15

-

25

20

5

-

20

15

5

-

ns

-

data hold time

-

delay from IOW to output

25 pF load

100

-

33

24

-

29

23

delay to set interrupt from

Modem input

-

t_19d

t_20d

t_21d

t_22d

t_23d

t_24d

t_25d

t_26d

t_27d

delay to reset interrupt from 25 pF load

IOR

-

100

-

24

-

23

ns

s

[3]

delay from stop to set

interrupt

1T_RCLK

100

1T_RCLK

29

1T_RCLK

28

delay from IOR to reset

interrupt

25 pF load

ns

s

delay from start to set

interrupt

100

45

40

[3]

delay from IOW to transmit

start

8T_RCLK24T_RCLK8T_RCLK24T_RCLK8T_RCLK24T_RCLK

delay from IOW to reset

interrupt

-

100

-

45

-

40

ns

s

delay from stop to set

RXRDY

1T_RCLK

100

1T_RCLK

45

1T_RCLK

40

delay from IOR to reset

RXRDY

ns

delay from IOW to set

TXRDY

100

45

40

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

28 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Table 29: Dynamic characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC= ± 10 %; unless otherwise speciﬁed.

Symbol Parameter Conditions V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

[3]

t_28d

delay from start to reset

-

8T_RCLK

-

8T_RCLK

-

8T_RCLK

s

TXRDY

t_RESET

N

RESET pulse width

baud rate divisor

200

1

-

40

-

40

-

ns

(2¹⁶− 1) 1

(2¹⁶− 1)

[1] Applies to external clock, crystal oscillator max 24 MHz.

1

t_3w

[2] Maximum frequency =

-------

[3] RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.

10.1 Timing diagrams

t

6h

valid

address

A0 to A2

t

13h

6s

active

CSx

t

13d

15d

t

13w

IOW

active

t

16h

t

16s

D0 to D7

data

002aaa109

Fig 6. General write timing

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

29 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

t

6h

7h

valid

address

A0 to A2

t

6s

active

CSx

IOR

t

7d

9d

t

7w

active

t

12h

12d

D0 to D7

data

002aaa110

Fig 7. General read timing

active

IOW

t

17d

RTS

DTR

change of state

CD

CTS

DSR

change of state

t

18d

INT

active

t

19d

active

IOR

t

18d

change of state

RI

002aaa352

Fig 8. Modem input/output timing

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

30 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

t

2w

1w

EXTERNAL

CLOCK

002aaa112

t

3w

1

t_3w

f _XTAL

=

-------

Fig 9. External clock timing

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

RX

D0

D1

D2

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

20d

active

INT

t

21d

active

IOR

16 baud rate clock

002aaa113

Fig 10. Receive timing

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

31 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RX

t

25d

active data

ready

RXRDY

IOR

t

26d

active

002aab063

Fig 11. Receive ready timing in non-FIFO mode

start

bit

parity stop

bit bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RX

first byte that

reaches the

trigger level

t

25d

active data

ready

RXRDY

IOR

t

26d

active

002aab064

Fig 12. Receive ready timing in FIFO mode

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

32 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

start

bit

parity stop start

bit

data bits (0 to 7)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

active

INT

transmitter ready

t

22d

t

24d

t

23d

active

IOW

active

16 baud rate clock

002aaa116

Fig 13. Transmit timing

start

bit

parity stop start

bit bit

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TX

IOW

active

t

28d

D0 to D7

byte #1

t

27d

active transmitter

ready

TXRDY

transmitter

not ready

002aab062

Fig 14. Transmit ready timing in non-FIFO mode

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

33 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

start

bit

parity stop

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TX

5 data bits

6 data bits

7 data bits

IOW

active

t

28d

D0 to D7

byte #32

t

27d

TXRDY

FIFO full

002aab065

Fig 15. Transmit ready timing in FIFO mode (DMA mode ‘1’)

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

34 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

UART frame

start

0

data bits

stop

1

0

1

0

1

0

TX data

IrDA TX data

1

/

bit time

2

bit

time

3

/

bit time

16

002aaa212

Fig 16. Infrared transmit timing

IrDA RX data

bit

time

0 to 1 16× clock delay

0

1

0

1

0

1

0

1

RX data

start

data bits

stop

UART frame

002aaa213

Fig 17. Infrared receive timing

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

35 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

11. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 18. Package outline SOT313-2 (LQFP48)

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

36 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w

9

16

L

17

8

e

E

h

2

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 19. Package outline SOT617-1 (HVQFN32)

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

37 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

12. Soldering

12.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

12.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

12.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

38 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

12.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

12.5 Package related soldering information

Table 30: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

39 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

13. Abbreviations

Table 31: Abbreviations

Acronym

FIFO

Description

First In, First Out

UART

CPU

Universal Asynchronous Receiver/Transmitter

Central Processing Unit

ISDN

Integrated Service Digital Network

Direct Memory Access

DMA

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

40 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

14. Revision history

Table 32: Revision history

Document ID

SC16C652B_4

Modiﬁcations:

Release date Data sheet status

20050901 Product data sheet

Change notice Doc. number

Supersedes

-

SC16C652B-03

• The format of this data sheet has be redesigned to comply with the new presentation and

information standard of Philips Semiconductors.

• Table 4 “Internal registers decoding” on page 8, Table note 3: changed “BF(HEX)” to “BFh”

• Section 6.8 “Programmable baud rate generator” on page 11, 3rd paragraph: changed from

“... from 1 to 2¹⁶− 1.” to “... from 1 to (2¹⁶− 1).”

• Table 6 on page 12: added “(bit/s)” to ﬁrst column heading

• Add new Section 6.11 “Sleep mode” on page 14

• Table 9 “SC16C652B internal registers” on page 15: removed shading, added (new) Table note 2

and references to it in previously shaded table cells

• Table 18 “LCR[2] stop bit length” on page 21: added “(bits)” to column heading “Word length”

• Table 19 “LCR[1:0] word length” on page 21: added “(bits)” to column heading “Word length”

• Table 28 “Static characteristics” on page 27:

–

added row I_CCsleepand new Table note 2

–

Table note 1: changed “x₂” to “XTAL2”

• Table 29 “Dynamic characteristics” on page 28:

–

changed symbol “t_3w” to “f_XTAL” and added (new) Table note 2

–

presentation of values for t_20d, t_23d, t_25d, t_28dchanged: “T_RCLK” appended to multiplier; Unit

changed from “R_clk” to “s”; Table note 3 added and referenced at these 4 timing

measurements

–

Unit “R_clk” deleted from row for symbol “N” (N is a number)

• added equation to Figure 9 “External clock timing” on page 31

• signal TXRDY modiﬁed in Figure 14 “Transmit ready timing in non-FIFO mode” on page 33

• Figure 15 “Transmit ready timing in FIFO mode (DMA mode ‘1’)” on page 34: changed

“BYTE #1” to “byte #32”

• added Section 13 “Abbreviations”

SC16C652B-03

Modiﬁcations:

20041210

Product data

-

9397 750 14452 SC16C652B-02

• There is no modiﬁcation to the data sheet. However, reader is advised to refer to

AN10333 (Rev. 01) “SC16CXXXB baud rate deviation tolerance” (9397 750 14411) that was

released together with this revision.

SC16C652B-02

SC16C652B-01

20040617

20040326

Product data

-

9397 750 13123 SC16C652B-01

9397 750 11972

-

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

41 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

15. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

16. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

18. Trademarks

Notice — All referenced brands, product names, service names and

17. Disclaimers

trademarks are the property of their respective owners.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

19. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

SC16C652B_4

Product data sheet

Rev. 04 — 1 September 2005

42 of 43

SC16C652B

Philips Semiconductors

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

20. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

12.1

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 38

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 38

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 39

Package related soldering information. . . . . . 39

12.2

12.3

12.4

12.5

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

13

14

15

16

17

18

19

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . 41

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 42

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Contact information . . . . . . . . . . . . . . . . . . . . 42

6

Functional description . . . . . . . . . . . . . . . . . . . 7

UART A-B functions . . . . . . . . . . . . . . . . . . . . . 8

Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 8

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hardware ﬂow control. . . . . . . . . . . . . . . . . . . . 9

Software ﬂow control . . . . . . . . . . . . . . . . . . . . 9

Special feature software ﬂow control . . . . . . . 10

Hardware/software and time-out interrupts. . . 10

Programmable baud rate generator . . . . . . . . 11

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 12

Loop-back mode. . . . . . . . . . . . . . . . . . . . . . . 12

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 15

Transmit (THR) and Receive (RHR) Holding

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Interrupt Enable Register (IER) . . . . . . . . . . . 16

IER versus Transmit/Receive FIFO interrupt

7.2

7.2.1

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 17

IER versus Receive/Transmit FIFO polled

7.2.2

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 17

FIFO Control Register (FCR) . . . . . . . . . . . . . 18

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Mode 0 (FCR bit 3 = 0). . . . . . . . . . . . . . . . . . 18

Mode 1 (FCR bit 3 = 1). . . . . . . . . . . . . . . . . . 18

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Interrupt Status Register (ISR) . . . . . . . . . . . . 20

Line Control Register (LCR) . . . . . . . . . . . . . . 21

Modem Control Register (MCR) . . . . . . . . . . . 22

Line Status Register (LSR). . . . . . . . . . . . . . . 23

Modem Status Register (MSR). . . . . . . . . . . . 24

Scratchpad Register (SPR) . . . . . . . . . . . . . . 24

Enhanced Feature Register (EFR) . . . . . . . . . 25

SC16C652B external reset condition . . . . . . . 26

7.3

7.3.1

7.3.1.1

7.3.1.2

7.3.2

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27

Static characteristics. . . . . . . . . . . . . . . . . . . . 27

Dynamic characteristics . . . . . . . . . . . . . . . . . 28

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 29

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 36

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9

10

10.1

11

12

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 1 September 2005

Document number: SC16C652B_4

Published in The Netherlands


型号：	SC16C652BIB48,157
厂家：	NXP
描述：	SC16C652B - 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoder QFP 48-Pin 通信时钟数据传输先进先出芯片外围集成电路
文件：	总43页 (文件大小：204K)
中文：	中文翻译
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