SC16C654BIBM_技术文档

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte

FIFOs and infrared (IrDA) encoder/decoder

Rev. 02 — 20 June 2005

Product data sheet

1. General description

The SC16C654B/654DB is a Quad Universal Asynchronous Receiver and Transmitter

(QUART) used for serial data communications. Its principal function is to convert parallel

data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.

It comes with an Intel or Motorola interface.

The SC16C654B/654DB is pin compatible with the ST16C654 and TL16C754 and it will

power-up to be functionally equivalent to the 16C454. Programming of control registers

enables the added features of the SC16C654B/654DB. Some of these added features are

the 64-byte receive and transmit FIFOs, automatic hardware or software ﬂow control and

infrared encoding/decoding. The selectable auto-ﬂow control feature signiﬁcantly reduces

software overload and increases system efﬁciency while in FIFO mode by automatically

controlling serial data ﬂow using RTS output and CTS input signals. The

SC16C654B/654DB also provides DMA mode data transfers through FIFO trigger levels

and the TXRDY and RXRDY signals. (TXRDY and RXRDY signals are not available in the

HVQFN48 package.) On-board status registers provide the user with error indications,

operational status, and modem interface control. System interrupts may be tailored to

meet user requirements. An internal loop-back capability allows on-board diagnostics.

The SC16C654B/654DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature

range, and is available in plastic PLCC68, LQFP64, HVQFN48 and LFBGA64 packages.

On the HVQFN48 package, only channel C has all the modem pins. Channel A and

channel B have only RTS and CTS pins, and channel D does not have any modem pin.

2. Features

■ 4 channel UART

■ 5 V, 3.3 V and 2.5 V operation

■ Industrial temperature range (−40 °C to +85 °C)

■ SC16C654B is pin and software compatible with the industry-standard

ST16C454/554, ST16C654, ST68C454/554, TL16C554

■ SC16C654DB is pin and software compatible with ST16C654D, and software

compatible with ST16C454/554, ST68C454/554, TL16C554

■ Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5 V

■ 5 V tolerant inputs

■ 64-byte transmit FIFO

■ 64-byte receive FIFO with error ﬂags

■ Automatic software (Xon/Xoff)/hardware (RTS/CTS) ﬂow control

■ Programmable Xon/Xoff characters

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

■ Software selectable baud rate generator

■ Four selectable Receive and Transmit FIFO interrupt trigger levels

■ Standard modem interface or infrared (IrDA) encoder/decoder interface

■ Sleep mode

■ Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

■ Transmit, Receive, Line Status, and Data Set interrupts independently controlled

■ Fully programmable character formatting:

◆ 5, 6, 7, or 8-bit characters

◆ Even, Odd, or No Parity formats

◆ 1, 1¹⁄₂, or 2-stop bit

◆ Baud generation (DC to 5 Mbit/s)

■ False start-bit detection

■ Complete status reporting capabilities

■ 3-state output TTL drive capabilities for bi-directional data bus and control bus

■ Line break generation and detection

■ Internal diagnostic capabilities:

◆ Loop-back controls for communications link fault isolation

■ Prioritized interrupt system controls

■ Modem control functions (CTS, RTS, DSR, DTR, RI, CD).

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

SC16C654BIA68

SC16C654BIB64

SC16C654BIBM

SC16C654BIBS

PLCC68

LQFP64

plastic leaded chip carrier; 68 leads

SOT188-2

SOT314-2

SOT414-1

SOT778-3

plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm

plastic low proﬁle quad ﬂat package; 64 leads; body 7 × 7 × 1.4 mm

HVQFN48 plastic thermal enhanced very thin quad ﬂat package; no leads;

48 terminals; body 6 × 6 × 0.85 mm

SC16C654BIEC

LFBGA64

plastic low proﬁle ﬁne-pitch ball grid array package; 64 balls;

body 6 × 6 × 1.05 mm

SOT686-1

SOT314-2

SC16C654DBIB64 LQFP64

plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

2 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

4. Block diagram

SC16C654B/654DB

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA to TXD

REGISTERS

REGISTER

D0 to D7

IOR

DATA BUS

AND

IOW

RESET

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RXA to RXD

REGISTERS

REGISTER

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0 to A2

CSA to CSD

16/68

DTRA to DTRD

RTSA to RTSD

MODEM

CONTROL

LOGIC

INTA to INTD

TXRDY

CTSA to CTSD

RIA to RID

CDA to CDD

DSRA to DSRD

RXRDY

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

INTSEL

002aaa871

XTAL1 XTAL2

CLKSEL

Fig 1. Block diagram of SC16C654B/654DB (16 mode)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

3 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

SC16C654B/654DB

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA to TXD

REGISTERS

REGISTER

DATA BUS

D0 to D7

AND

R/W

CONTROL

RESET

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RXA to RXD

REGISTERS

REGISTER

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

A0 to A4

SELECT

CS

LOGIC

16/68

DTRA to DTRD

RTSA to RTSD

MODEM

CONTROL

LOGIC

CTSA to CTSD

RIA to RID

CDA to CDD

DSRA to DSRD

IRQ

TXRDY

RXRDY

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

002aaa872

XTAL1 XTAL2

CLKSEL

Fig 2. Block diagram of SC16C654B/654DB (68 mode)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

4 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

5. Pinning information

5.1 Pinning

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

DSRA

DSRD

CTSD

DTRD

GND

RTSD

INTD

CSD

CTSA

DTRA

V

CC

RTSA

INTA

CSA

TXA

TXD

IOW

SC16C654BIA68

16 mode

IOR

TXB

TXC

CSB

CSC

INTB

RTSB

GND

DTRB

CTSB

DSRB

INTC

RTSC

V

CC

DTRC

CTSC

DSRC

002aaa873

Fig 3. Pin conﬁguration for PLCC68 (16 mode)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

5 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

DSRA

CTSA

DTRA

DSRD

CTSD

DTRD

GND

RTSD

n.c.

V

CC

RTSA

IRQ

CS

n.c.

TXA

R/W

TXB

A3

TXD

n.c.

SC16C654BIA68

68 mode

TXC

A4

n.c.

RTSB

GND

DTRB

CTSB

DSRB

RTSC

V

CC

DTRC

CTSC

DSRC

002aaa874

Fig 4. Pin conﬁguration for PLCC68 (68 mode)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

6 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DSRA

CTSA

DTRA

DSRD

CTSD

DTRD

GND

RTSD

INTD

CSD

3

4

V

CC

5

RTSA

INTA

CSA

6

7

SC16C654BIB64

SC16C654BIBM

SC16C654DBIB64

8

TXA

TXD

9

IOW

IOR

10

11

12

13

14

15

16

TXB

TXC

CSB

CSC

INTB

RTSB

GND

DTRB

CTSB

INTC

RTSC

V

CC

DTRC

CTSC

002aaa875

Fig 5. Pin conﬁguration for LQFP64

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

7 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

terminal 1

index area

1

2

36

35

34

33

32

31

30

29

28

27

26

25

CTSA

INTD

CSD

TXD

IOR

V

CC

3

RTSA

INTA

CSA

TXA

4

5

TXC

CSC

INTC

RTSC

6

SC16C654BIBS

16 mode

7

IOW

8

TXB

9

CSB

INTB

RTSB

CTSB

V

CC

10

11

12

DTRC

CTSC

DSRC

002aab568

Transparent top view

Fig 6. Pin conﬁguration for HVQFN48 (16 mode)

terminal 1

index area

1

2

36

35

34

33

32

31

30

29

28

27

26

25

CTSA

n.c.

V

CC

CSD

TXD

IOR

TXC

A4

3

RTSA

IRQ

4

5

CS

6

TXA

R/W

TXB

A3

SC16C654BIBS

68 mode

7

n.c.

8

RTSC

9

V

CC

10

11

12

n.c.

DTRC

CTSC

DSRC

RTSB

CTSB

002aab565

Transparent top view

Fig 7. Pin conﬁguration for HVQFN48 (68 mode)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

8 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

ball A1

index area

SC16C654BIEC

1 2 3 4 5 6 7 8 9 10

A

B

C

D

E

F

G

H

J

K

002aab566

Transparent top view

Fig 8. Pin conﬁguration for LFBGA64

1

2

3

4

5

6

7

8

9

10

A

B

C

D

E

F

CDA

DSRA

RIA

RXA

GND

D7

D6

D5

D4

D3

D2

D1

D0

V

RID

CDD

CTSD

RTSD

INTD

TXD

CC

V

RXD

DSRD

DTRD

GND

CSD

IOR

CC

RTSA

INTA

TXA

CTSA

DTRA

CSA

IOW

CSB

GND

TXB

TXC

INTB

RTSB

CTSB

CDB

CSC

RTSC

CDC

DSRC

INTC

G

H

J

V

CC

RIB

V

A1

A0

XTAL1 RESET

XTAL2 GND

RXC

RIC

DTRC

DTRB

DSRB

CC

RXB

A2

CTSC

K

002aab567

Fig 9. Ball mapping for LFBGA64

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

9 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

5.2 Pin description

Table 2:

Pin description

Symbol Pin

Type Description

PLCC68 LQFP64 HVQFN48 LFBGA6

4

16/68

31

-

14

-

I

16/68 Interface type select (input with internal pull-up).

This input provides the 16 (Intel) or 68 (Motorola) bus

interface type select. The functions of IOR, IOW,

INTA to INTD, and CSA to CSD are re-assigned with the

logical state of this pin. When this pin is a logic 1, the

16 mode interface (16C654) is selected. When this pin is a

logic 0, the 68 mode interface (68C654) is selected. When

this pin is a logic 0, IOW is re-assigned to R/W, RESET is

re-assigned to RESET, IOR is not used, and INTA to INTD

are connected in a wire-OR conﬁguration. The wire-OR

outputs are connected internally to the open-drain IRQ

signal output. This pin is not available on 64-pin packages

which operate in the 16 mode only.

A0

A1

A2

34

33

32

24

23

22

17

16

15

K5

J5

I

Address 0 select bit. Internal registers address selection in

16 and 68 modes.

Address 1 select bit. Internal registers address selection in

16 and 68 modes.

K4

Address 2 select bit. Internal registers address selection in

16 and 68 modes.

A3

A4

20

50

-

9

-

Address 3, Address 4 select bits. When the 68 mode is

selected, these pins are used to address or select individual

UARTs (providing CS is a logic 0). In the 16 mode, these

pins are re-assigned as chip selects, see CSB and CSC.

These pins are not available on 64-pin packages which

operate in the 16 mode only.

31

CDA

CDB

CDC

CDD

9

64

18

31

49

-

A1

K2

J9

A10

-

I

Carrier Detect (active LOW). These inputs are associated

with individual UART channels A through D. A logic 0 on this

pin indicates that a carrier has been detected by the modem

for that channel.

27

43

61

-

24

-

CLKSEL 30

-

Clock Select. The 1× or 4× pre-scalable clock is selected by

this pin. The 1× clock is selected when CLKSEL is a logic 1

(connected to V_CC) or the 4× is selected when CLKSEL is a

logic 0 (connected to GND). MCR[7] can override the state

of this pin following reset or initialization (see MCR[7]). This

pin is not available on 64-pin packages which provide

MCR[7] selection only.

CS

16

-

5

-

I

Chip Select (active LOW). In the 68 mode, this pin

functions as a multiple channel chip enable. In this case, all

four UARTs (A to D) are enabled when the CS pin is a

logic 0. An individual UART channel is selected by the data

contents of address bits A[3:4]. when the 16 mode is

selected (68-pin devices), this pin functions as CSA (see

deﬁnition under CSA, CSB). This pin is not available on

64-pin packages which operate in the 16 mode only.

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

10 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Table 2:

Symbol Pin

PLCC68 LQFP64 HVQFN48 LFBGA6

Pin description …continued

Type Description

4

CSA

CSB

CSC

CSD

16

20

50

54

7

5

E1

G1

G9

E9

I

Chip Select A, B, C, D (active LOW). This function is

associated with the 16 mode only, and for individual

channels ‘A’ through ‘D’. When in 16 mode, these pins

enable data transfers between the user CPU and the

SC16C654B/654DB for the channel(s) addressed. Individual

UART sections (A, B, C, D) are addressed by providing a

logic 0 on the respective CSA to CSD pin. When the

68 mode is selected, the functions of these pins are

re-assigned. 68 mode functions are described under their

respective name/pin headings.

11

38

42

9

31

35

CTSA

CTSB

CTSC

CTSD

11

25

45

59

2

1

C1

I

Clear to Send (active LOW). These inputs are associated

with individual UART channels A through D. A logic 0 on the

CTS pin indicates the modem or data set is ready to accept

transmit data from the SC16C654B/654DB. Status can be

tested by reading MSR[4]. This pin only affects the transmit

or receive operations when Auto CTS function is enabled via

the Enhanced Feature Register EFR[7] for hardware ﬂow

control operation.

16

33

47

12

26

-

J2

K10

B10

D0 to D2, 66 to 68 53 to 55, 39 to 41, B7, A7,

I/O

I

Data bus (bi-directional). These pins are the 8-bit, 3-state

data bus for transferring information to or from the controlling

CPU. D0 is the least signiﬁcant bit and the ﬁrst data bit in a

transmit or receive serial data stream.

D3 to D7 , 1 to 5 56 to 60 42 to 46

B6, A6,

B5, A5,

B4, A4

DSRA

DSRB

DSRC

DSRD

DTRA

DTRB

DTRC

DTRD

10

26

44

60

12

24

46

58

1

-

B1

K1

K9

B9

D1

J1

Data Set Ready (active LOW). These inputs are associated

with individual UART channels, A through D. A logic 0 on this

pin indicates the modem or data set is powered-on and is

ready for data exchange with the UART. This pin has no

effect on the UART’s transmit or receive operation.

17

32

48

3

-

25

-

O

Data Terminal Ready (active LOW). These outputs are

associated with individual UART channels, A through D. A

logic 0 on this pin indicates that the SC16C654B/654DB is

powered-on and ready. This pin can be controlled via the

modem control register. Writing a logic 1 to MCR[0] will set

the DTR output to logic 0, enabling the modem. This pin will

be a logic 1 after writing a logic 0 to MCR[0], or after a reset.

This pin has no effect on the UART’s transmit or receive

operation.

15

34

46

-

27

-

J10

C9

GND

6, 23,

40, 57

14, 28,

45, 61

21, 37, 47 B3, K7,

H1, D9

I

Signal and power ground.

INTA

INTB

INTC

INTD

15

21

49

55

6

4

D2

O

Interrupt A, B, C, D (active HIGH). This function is

associated with the 16 mode only. These pins provide

individual channel interrupts INTA to INTD. INTA to INTD are

enabled when MCR[3] is set to a logic 1, interrupts are

enabled in the interrupt enable register (IER), and when an

interrupt condition exists. Interrupt conditions include:

receiver errors, available receiver buffer data, transmit buffer

empty, or when a modem status ﬂag is detected. When the

68 mode is selected, the functions of these pins are

re-assigned. 68 mode functions are described under their

respective name/pin headings.

12

37

43

10

30

36

G2

G10

D10

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

11 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Table 2:

Symbol Pin

PLCC68 LQFP64 HVQFN48 LFBGA6

Pin description …continued

Type Description

4

INTSEL 65

-

I

Interrupt Select (active HIGH, with internal pull-down).

This function is associated with the 16 mode only. When the

16 mode is selected, this pin can be used in conjunction with

MCR[3] to enable or disable the 3-state interrupts,

INTA to INTD, or override MCR[3] and force continuous

interrupts. Interrupt outputs are enabled continuously by

making this pin a logic 1. Making this pin a logic 0 allows

MCR[3] to control the 3-state interrupt output. In this mode,

MCR[3] is set to a logic 1 to enable the 3-state outputs. This

pin is disabled in the 68 mode. Due to pin limitations on the

64-pin packages, this pin is not available. To cover this

limitation, the SC16C654DBIB64 version operates in the

continuous interrupt enable mode by bonding this pin to V_CC

internally. The SC16C654BIB64 operates with MCR[3]

control by bonding this pin to GND.

IOR

52

18

40

33

F9

F1

I

Input/Output Read strobe (active LOW). This function is

associated with the 16 mode only. A logic 0 transition on this

pin will load the contents of an internal register deﬁned by

address bits A[0:2] onto the SC16C654B/654DB data bus

(D[0:7]) for access by external CPU. This pin is disabled in

the 68 mode.

IOW

9

7

Input/Output Write strobe (active LOW). This function is

associated with the 16 mode only. A logic 0 transition on this

pin will transfer the contents of the data bus (D[0:7]) from the

external CPU to an internal register that is deﬁned by

address bits A[0:2]. When the 68 mode is selected

(PLCC68), this pin functions as R/W (see deﬁnition under

R/W).

IRQ

15

-

4

-

O

Interrupt Request or Interrupt ‘A’. This function is

associated with the 68 mode only. In the 68 mode, interrupts

from UART channels A-D are wire-ORed internally to

function as a single IRQ interrupt. This pin transitions to a

logic 0 (if enabled by the interrupt enable register) whenever

a UART channel(s) requires service. Individual channel

interrupt status can be determined by addressing each

channel through its associated internal register, using CS

and A[3:4]. In the 68 mode, and external pull-up resistor

must be connected between this pin and V_CC. The function

of this pin changes to INTA when operating in the 16 mode

(see deﬁnition under INTA).

n.c.

21, 49,

52, 54,

55, 65

-

I

not connected

RESET, 37

RESET

27

20

J7

Reset. In the 16 mode, a logic 1 on this pin will reset the

internal registers and all the outputs. The UART transmitter

output and the receiver input will be disabled during reset

time. (See Section 7.11 “SC16C654B/654DB external reset

conditions” for initialization details.) When 16/68 is a logic 0

(68 mode), this pin functions similarly, but as an inverted

reset interface signal, RESET.

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

12 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Table 2:

Symbol Pin

PLCC68 LQFP64 HVQFN48 LFBGA6

Pin description …continued

Type Description

4

RIA

8

63

19

30

50

5

-

A2

J3

I

Ring Indicator (active LOW). These inputs are associated

with individual UART channels, A through D. A logic 0 on this

pin indicates the modem has received a ringing signal from

the telephone line. A logic 1 transition on this input pin will

generate an interrupt.

RIB

28

42

62

14

22

48

56

-

RIC

23

-

K8

A9

C2

H2

H9

C10

RID

RTSA

RTSB

RTSC

RTSD

3

O

Request to Send (active LOW). These outputs are

associated with individual UART channels, A through D. A

logic 0 on the RTS pin indicates the transmitter has data

ready and waiting to send. Writing a logic 1 in the modem

control register MCR[1] will set this pin to a logic 0,

indicating data is available. After a reset this pin will be set to

a logic 1. This pin only affects the transmit and receive

operations when Auto RTS function is enabled via the

Enhanced Feature Register (EFR[6]) for hardware ﬂow

control operation.

13

36

44

11

29

-

R/W

18

-

7

-

I

Read/Write strobe. This function is associated with the

68 mode only. This pin provides the combined functions for

Read or Write strobes.

Logic 1 = Read from UART register selected by CS and

A[0:4].

Logic 0 = Write to UART register selected by CS and A[0:4].

RXA

RXB

RXC

RXD

7

62

20

29

51

48

13

22

38

A3

K3

J8

Receive data input RXA-RXD. These inputs are associated

with individual serial channel data to the

29

41

63

SC16C654B/654DB. The RX signal will be a logic 1 during

reset, idle (no data), or when the transmitter is disabled.

During the local loop-back mode, the RX input pin is

disabled and TX data is connected to the UART RX input

internally.

B8

RXRDY

38

-

O

Receive Ready (active LOW). This function is associated

with 68-pin package only. RXRDY contains the wire-ORed

status of all four receive channel FIFOs, RXRDYA-RXRDYD.

A logic 0 indicates receive data ready status, that is, the

RHR is full, or the FIFO has one or more RX characters

available for unloading. This pin goes to a logic 1 when the

FIFO/RHR is empty, or when there are no more characters

available in either the FIFO or RHR. Individual channel RX

status is read by examining individual internal registers via

CS and A[0:4] pin functions.

TXA

TXB

TXC

TXD

17

19

51

53

8

6

E2

O

Transmit data A, B, C, D. These outputs are associated

with individual serial transmit channel data from the

SC16C654B/654DB. The TX signal will be a logic 1 during

reset, idle (no data), or when the transmitter is disabled.

During the local loop-back mode, the TX output pin is

disabled and TX data is internally connected to the UART

RX input.

10

39

41

8

F2

32

34

F10

E10

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Table 2:

Symbol Pin

PLCC68 LQFP64 HVQFN48 LFBGA6

Pin description …continued

Type Description

4

TXRDY

39

-

O

Transmit Ready (active LOW). This function is associated

with the 68-pin package only. TXRDY contains the

wire-ORed status of all four transmit channel FIFOs,

TXRDYA-TXRDYD. A logic 0 indicates a buffer ready status,

that is, at least one location is empty and available in one of

the TX channels (A to D). This pin goes to a logic 1 when all

four channels have no more empty locations in the TX FIFO

or THR. Individual channel TX status can be read by

examining individual internal registers via CS and A[0:4] pin

functions.

V_CC

13, 47, 4, 21,

2, 28

18

A8, B2,

J4, H10

I

Power supply inputs.

64

35, 52

XTAL1

35

25

J6

Crystal or external clock input. Functions as a crystal

input or as an external clock input. A crystal can be

connected between this pin and XTAL2 to form an internal

oscillator circuit; see Figure 10. Alternatively, an external

clock can be connected to this pin to provide custom data

rates; see Section 6.9 “Programmable baud rate generator”.

XTAL2

36

26

19

K6

O

Output of the crystal oscillator or buffered clock. (See

also XTAL1.) Crystal oscillator output or buffered clock

output.

6. Functional description

The SC16C654B/654DB provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character. Data integrity is insured by attaching a parity bit to the data character. The

parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry

to provide all these functions is fairly complex, especially when manufactured on a single

integrated silicon chip. The SC16C654B/654DB represents such an integration with

greatly enhanced features. The SC16C654B/654DB is fabricated with an advanced

CMOS process to achieve low drain power and high speed requirements.

The SC16C654B/654DB is an upward solution that provides 64 bytes of transmit and

receive FIFO memory, instead of 16 bytes provided in the 16C554, or none in the 16C454.

The SC16C654B/654DB is designed to work with high speed modems and shared

network environments that require fast data processing time. Increased performance is

realized in the SC16C654B/654DB by the larger transmit and receive FIFOs. This allows

the external processor to handle more networking tasks within a given time. For example,

the SC16C554 with a 16-byte FIFO unloads 16 bytes of receive data in 1.53 ms. (This

example uses a character length of 11 bits, including start/stop bits at 115.2 kbit/s.) This

means the external CPU will have to service the receive FIFO at 1.53 ms intervals.

However, with the 64-byte FIFO in the SC16C654B/654DB, the data buffer will not require

unloading/loading for 6.1 ms. This increases the service interval, giving the external CPU

additional time for other applications and reducing the overall UART interrupt servicing

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time. In addition, the four selectable levels of FIFO trigger interrupt and automatic

hardware/software ﬂow control is uniquely provided for maximum data throughput

performance, especially when operating in a multi-channel environment. The combination

of the above greatly reduces the bandwidth requirement of the external controlling CPU,

increases performance, and reduces power consumption.

The SC16C654B/654DB combines the package interface modes of the 16C454/554 and

68C454/554 series on a single integrated chip. The 16 mode interface is designed to

operate with the Intel-type of microprocessor bus, while the 68 mode is intended to

operate with Motorola and other popular microprocessors. Following a reset, the

SC16C654B/654DB is downward compatible with the 16C454/554 or the 68C454/554,

dependent on the state of the interface mode selection pin, 16/68.

The SC16C654B/654DB is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and

up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the max speed is

3 Mbit/s). With a crystal of 14.7464 MHz, and through a software option, the user can

select data rates up to 460.8 kbit/s or 921.6 kbit/s, 8 times faster than the 16C554.

The rich feature set of the SC16C654B/654DB is available through internal registers.

Automatic hardware/software ﬂow control, selectable transmit and receive FIFO trigger

levels, selectable TX and RX baud rates, infrared encoder/decoder interface, modem

interface controls, and a sleep mode are all standard features. MCR[5] provides a facility

for turning off (Xon) software ﬂow control with any incoming (RX) character. In the

16 mode, INTSEL and MCR[3] can be conﬁgured to provide a software controlled or

continuous interrupt capability. Due to pin limitations of the 64-pin package, this feature is

offered by two different LQFP64 packages. The SC16C654DB operates in the continuous

interrupt enable mode by bonding INTSEL to V_CCinternally. The SC16C654B operates in

conjunction with MCR[3] by bonding INTSEL to GND internally.

The PLCC68 SC16C654B package offers a clock select pin to allow system/board

designers to preset the default baud rate table. The CLKSEL pin selects the 1× or 4×

pre-scalable baud rate generator table during initialization, but can be overridden following

initialization by MCR[7].

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6.1 Interface options

Two user interface modes are selectable for the PLCC68 package. These interface modes

are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature corresponds to the

early 16C454/554 and 68C454/554 package interfaces respectively.

6.1.1 The 16 mode interface

The 16 mode conﬁgures the package interface pins for connection as a standard

16 series (Intel) device and operates similar to the standard CPU interface available on

the 16C454/554. In the 16 mode (pin 16/68 = logic 1), each UART is selected with

individual chip select (CSx) pins, as shown in Table 3.

Table 3:

Serial port channel selection, 16 mode interface

CSA

CSB

CSC

CSD

UART channel

1

0

1

0

1

0

1

0

none

A

B

C

D

6.1.2 The 68 mode interface

The 68 mode conﬁgures the package interface pins for connection with Motorola, and

other popular microprocessor bus types. The interface operates similar to the

68C454/554. In this mode, the SC16C654B/654DB decodes two additional addresses,

A3-A4, to select one of the four UART ports. The A[3:4] address decode function is used

only when in the 68 mode (16/68 = logic 0), and is shown in Table 4.

Table 4:

Serial port channel selection, 68 mode interface

CS

1

A4

n/a

0

A3

n/a

0

UART channel

none

A

0

1

B

0

1

0

C

0

1

D

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6.2 Internal registers

The SC16C654B/654DB provides 17 internal registers for monitoring and control. These

registers are shown in Table 5. Twelve registers are similar to those already available in

the standard 16C554. These registers function as data holding registers (THR/RHR),

interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status

and control registers (LCR/LSR), modem status and control registers (MCR/MSR),

programmable data rate (clock) control registers (DLL/DLM), and a user accessible

scratchpad register (SPR). Beyond the general 16C554 features and capabilities, the

SC16C654B/654DB offers an enhanced feature register set (EFR, Xon/Xoff1-2) that

provides on-board hardware/software ﬂow control. Register functions are more fully

described in the following paragraphs.

Table 5:

A2

Internal registers decoding

A0 Read mode

A1

Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

LSB of Divisor Latch

MSB of Divisor Latch

0

1

MSB of Divisor Latch

Enhanced register set (EFR, Xon/off 1-2)^[3]

0

1

0

1

0

1

0

1

Enhanced Feature Register

Xon1 word

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

[3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to ‘BFh’.

6.3 FIFO operation

The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register

(FCR) bit 0. With SC16C554 devices, the user can set the receive trigger level, but not the

transmit trigger level. The SC16C654B/654DB provides independent trigger levels for both

receiver and transmitter. To remain compatible with SC16C554, the transmit interrupt

trigger level is set to 8 following a reset. It should be noted that the user can set the

transmit trigger levels by writing to the FCR register, but activation will not take place until

EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure

data is delivered to the external CPU. An interrupt is generated whenever the Receive

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Holding Register (RHR) has not been read following the loading of a character or the

receive trigger level has not been reached. (For a description of this timing, see Section

6.4 “Hardware ﬂow control”.)

Table 6:

RX trigger levels

Selected trigger level

(characters)

INT pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

(characters)

8

16

56

60

0

16

56

60

16

56

60

8

16

56

6.4 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C654B/654DB monitors the

CTS pin for a remote buffer overﬂow indication and controls the RTS pin for local buffer

overﬂows. Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and

EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a ﬂow

control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the

SC16C654B/654DB will suspend TX transmissions as soon as the stop bit of the

character in process is shifted out. Transmission is resumed after the CTS input returns to

a logic 0, indicating more data may be sent.

With the Auto RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTS pin will not be forced to a logic 1

(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin will

return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below

the programmed trigger. However, under the above described conditions, the

SC16C654B/654DB will continue to accept data until the receive FIFO is full.

Remark: Hardware ﬂow control is not supported on channel D in the HVQFN48 package.

6.5 Software ﬂow control

When software ﬂow control is enabled, the SC16C654B/654DB compares one or two

sequential receive data characters with the programmed Xon/Xoff or Xoff1,2 character

value(s). If received character(s) match the programmed values, the SC16C654B/654DB

will halt transmission (TX) as soon as the current character(s) has completed

transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5]) ﬂags

will be set and the interrupt output pin (if receive interrupt is enabled) will be activated.

Following a suspension due to a match of the Xoff characters’ values, the

SC16C654B/654DB will monitor the receive data stream for a match to the Xon1,2

character value(s). If a match is found, the SC16C654B/654DB will resume operation and

clear the ﬂags (ISR[4]). The SC16C654B/654DB offers a special Xon mode via MCR[5].

The initialized default setting of MCR[5] is a logic 0. In this state, Xoff and Xon will operate

as deﬁned above. Setting MCR[5] to a logic 1 sets a special operational mode for the Xon

function. In this case, Xoff operates normally, however, transmission (Xon) will resume

with the next character received, that is, a match is declared simply by the receipt of an

incoming (RX) character.

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5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow control.

Different conditions can be set to detect Xon/Xoff characters and suspend/resume

transmissions. When double 8-bit Xon/Xoff characters are selected, the

SC16C654B/654DB compares two consecutive receive characters with two software ﬂow

control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly.

Under the above described ﬂow control mechanisms, ﬂow control characters are not

placed (stacked) in the user accessible RX data buffer or FIFO.

In the event that the receive buffer is overﬁlling and ﬂow control needs to be executed, the

SC16C654B/654DB automatically sends an Xoff message (when enabled) via the serial

TX output to the remote modem. The SC16C654B/654DB sends the Xoff1,2 characters

as soon as received data passes the programmed trigger level. To clear this condition, the

SC16C654B/654DB will transmit the programmed Xon1,2 characters as soon as receive

data drops below the programmed trigger level.

6.6 Special feature software ﬂow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit

character is detected, it will be placed on the user-accessible data stack along with normal

incoming RX data. This condition is selected in conjunction with EFR[0:3]. Note that

software ﬂow control should be turned off when using this special mode by setting

EFR[0:3] to a logic 0.

The SC16C654B/654DB compares each incoming receive character with Xoff2 data. If a

match exists, the received data will be transferred to the FIFO, and ISR[4] will be set to

indicate detection of a special character. Although the Internal Register Table (Table 8)

shows each X-Register with eight bits of character information, the actual number of bits is

dependent on the programmed word length. Line Control Register bits LCR[0:1] deﬁne the

number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length

selected by LCR[0:1] also determine the number of bits that will be used for the special

character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive

character.

6.7 Xon any feature

A special feature is provided to return the Xoff ﬂow control to the inactive state following its

activation. In this mode, any RX character received will return the Xoff ﬂow control to the

inactive state so that transmissions may be resumed with a remote buffer. This feature is

more fully deﬁned in Section 6.5 “Software ﬂow control”.

6.8 Hardware/software and time-out interrupts

Three special interrupts have been added to monitor the hardware and software ﬂow

control. The interrupts are enabled by IER[5:7]. Care must be taken when handling these

interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C654B/654DB

will issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt

must be serviced prior to continuing operations. The LSR register provides the current

singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have

lowest interrupt priority. A condition can exist where a higher priority interrupt may mask

the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt

will the lower priority CTS/TRS interrupt(s) be reﬂected in the status register. Servicing the

interrupt without investigating further interrupt conditions can result in data errors.

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When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt

priority (when enabled by IER[0]). The receiver issues an interrupt after the number of

characters have reached the programmed trigger level. In this case, the

SC16C654B/654DB FIFO may hold more characters than the programmed trigger level.

Following the removal of a data byte, the user should re-check LSR[0] for additional

characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out

counter is reset at the center of each stop bit received or each time the receive holding

register (RHR) is read. The actual time-out value is 4 character time.

In the 16 mode for the PLCC68 package, the system/board designer can optionally

provide software controlled 3-state interrupt operation. This is accomplished by INTSEL

and MCR[3]. When INTSEL interface pin is left open or made a logic 0, MCR[3] controls

the 3-state interrupt outputs, INTA to INTD. When INTSEL is a logic 1, MCR[3] has no

effect on the INTA to INTD outputs, and the package operates with interrupt outputs

enabled continuously.

6.9 Programmable baud rate generator

The SC16C654B/654DB supports high speed modem technologies that have increased

input data rates by employing data compression schemes. For example, a 33.6 kbit/s

modem that employs data compression may require a 115.2 kbit/s input data rate.

A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate

of 460.8 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing

independent TX/RX channel control. The programmable Baud Rate Generator is capable

of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as required for

supporting a 5 Mbit/s data rate. The SC16C654B/654DB can be conﬁgured for internal or

external clock operation. For internal clock oscillator operation, an industry standard

microprocessor crystal (parallel resonant/22 pF to 33 pF load) is connected externally

between the XTAL1 and XTAL2 pins; see Figure 10. Alternatively, an external clock can be

connected to the XTAL1 pin to clock the internal baud rate generator for standard or

custom rates; see Table 7.

XTAL1

XTAL2

XTAL1

XTAL2

1.5 kΩ

X1

1.8432 MHz

C1

22 pF

C2

33 pF

C1

22 pF

C2

47 pF

002aaa870

Fig 10. Crystal oscillator connection

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). The

SC16C654B/654DB divides the basic external clock by 16. Further division of this 16×

clock provides two table rates to support low and high data rate applications using the

same system design. After a hardware reset and during initialization, the

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SC16C654B/654DB sets the default baud rate table according to the state of the CLKSEL

pin. A logic 1 on CLKSEL will set the 1× clock default, whereas logic 0 will set the 4× clock

default table. Following the default clock rate selection during initialization, the rate tables

can be changed by the internal register MCR[7]. Setting MCR[7] to a logic 1 when

CLKSEL is a logic 1 provides an additional divide-by-4, whereas setting MCR[7] to a

logic 0 only divides by 1; see Table 7 and Figure 11. Customized baud rates can be

achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate

generator.

Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a

user capability for selecting the desired ﬁnal baud rate. The example in Table 7 shows the

two selectable baud rate tables available when using a 7.3728 MHz crystal.

Table 7:

Baud rate generator programming table using a 7.3728 MHz clock

Output baud rate

User

DLM

DLL

16× clock divisor

program value program value

(HEX)

MCR[7] = 1

50

MCR[7] = 0

Decimal

HEX

200

2304

384

192

96

48

24

12

6

900

180

C0

60

09

01

00

80

C0

60

30

18

0C

06

03

02

01

300

1200

600

2400

1200

4800

2400

9600

30

4800

19.2 k

38.4 k

76.8 k

153.6 k

230.4 k

460.8 k

18

9600

0C

06

19.2 k

38.4 k

57.6 k

115.2 k

3

03

2

02

1

01

MCR[7] = 0

DIVIDE-BY-1

LOGIC

XTAL1

XTAL2

CLOCK

OSCILLATOR

LOGIC

BAUD RATE

GENERATOR

LOGIC

BAUDOUT

DIVIDE-BY-4

LOGIC

MCR[7] = 1

002aaa208

Fig 11. Baud rate generator circuitry

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6.10 DMA operation

The SC16C654B/654DB FIFO trigger level provides additional ﬂexibility to the user for

block mode operation. LSR[5:6] provide an indication when the transmitter is empty or has

an empty location(s). The user can optionally operate the transmit and receive FIFOs in

the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA

mode is de-activated (DMA Mode 0), the SC16C654B/654DB activates the interrupt

output pin for each data transmit or receive operation. When DMA mode is activated

(DMA Mode 1), the user takes the advantage of block mode operation by loading or

unloading the FIFO in a block sequence determined by the preset trigger level. In this

mode, the SC16C654B/654DB sets the interrupt output pin when characters in the

transmit FIFOs are below the transmit trigger level, or the characters in the receive FIFOs

are above the receive trigger level.

Remark: DMA operation is not supported in the HVQFN48 package option.

6.11 Sleep mode

The SC16C654B/654DB is designed to operate with low power consumption. A special

sleep mode is included to further reduce power consumption when the chip is not being

used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C654B/654DB enters

the sleep mode, but resumes normal operation when a start bit is detected, a change of

state on any of the modem input pins RX, RI, CTS, DSR, CD, or a transmit data is

provided by the user. If the sleep mode is enabled and the SC16C654B/654DB is

awakened by one of the conditions described above, it will return to the sleep mode

automatically after the last character is transmitted or read by the user. In any case, the

sleep mode will not be entered while an interrupt(s) is pending. The SC16C654B/654DB

will stay in the sleep mode of operation until it is disabled by setting IER[4] to a logic 0.

6.12 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the

normal modem interface pins are disconnected and reconﬁgured for loop-back internally.

MCR[0:3] register bits are used for controlling loop-back diagnostic testing. In the

loop-back mode, OP1 and OP2 in the MCR register (bits 2:3) control the modem RI and

CD inputs, respectively. MCR signals DTR and RTS (bits 0:1) are used to control the

modem DSR and CTS inputs, respectively. The transmitter output (TX) and the receiver

input (RX) are disconnected from their associated interface pins, and instead are

connected together internally; see Figure 12. The CTS, DSR, CD, and RI are

disconnected from their normal modem control input pins, and instead are connected

internally to RTS, DTR, OP2 and OP1. Loop-back test data is entered into the transmit

holding register via the user data bus interface, D[0:7]. The transmit UART serializes the

data and passes the serial data to the receive UART via the internal loop-back connection.

The receive UART converts the serial data back into parallel data that is then made

available at the user data interface D[0:7]. The user optionally compares the received data

to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem

Control Interrupts are also operational. However, the interrupts can only be read using

lower four bits of the Modem Status Register (MSR[0:3]) instead of the four Modem Status

Register bits 4:7. The interrupts are still controlled by the IER.

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SC16C654B/654DB

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA to TXD

REGISTERS

REGISTER

D0 to D7

IOR

DATA BUS

AND

IOW

RESET

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

REGISTERS

RECEIVE

SHIFT

REGISTER

RXA to RXD

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0 to A2

CSA to CSD

RTSA to RTSD

CTSA to CTSD

DTRA to DTRD

MODEM

CONTROL

LOGIC

DSRA to DSRD

OP1A to OP1D

INTA to INTD

TXRDY

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

RIA to RID

RXRDY

OP2A to OP2D

CDA to CDD

002aaa876

XTAL1 XTAL2

Fig 12. Internal loop-back mode diagram

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5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7. Register descriptions

Table 8 details the assigned bit functions for the SC16C654B/654DB internal registers.

The assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.11.

Table 8:

SC16C654B/654DB internal registers

A2 A1 A0 Register Default^[1]Bit 7

General Register Set^[2]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

CTS

bit 6

RTS

bit 5

Xoff

bit 4

bit 3

bit 2

bit 1

bit 0

bit 4

bit 2

Sleep

modem

status

interrupt

receive

transmit receive

interrupt interrupt interrupt mode^[3]

line status holding holding

interrupt

[3]

register register

0

1

0

1

FCR

ISR

00

01

00

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

TX

trigger

(MSB)^[3]

TXtrigger DMA

(LSB)^[3]mode

select ^[4]

XMIT

FIFO reset FIFO

reset

RCVR

FIFO

enable

FIFOs

INT

priority

bit 1

INT

priority

bit 0

INT

status

enabled enabled priority

bit 4

priority

bit 3

priority

bit 2

LCR

divisor

latch

enable

set

break

set parity even

parity

enable

stop bits

word

length

bit 1

word

length

bit 0

1

0

1

MCR

LSR

00

60

Clock

IR

Xon

loop back OP2, INTx OP1

enable

RTS

DTR

select^[3]enable^[3]Any^[3]

FIFO

data

error

trans.

empty

trans.

holding

empty

break

framing

parity

error

overrun receive

error

interrupt error

data

ready

1

0

1

MSR

SPR

X0

FF

CD

RI

DSR

bit 5

CTS

bit 4

∆CD

∆RI

∆DSR

∆CTS

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

Special Register Set^[5]

0

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

0

1

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

Enhanced Register Set^[6]

0

1

0

EFR

00

Auto

CTS

Auto

RTS

Special Enable

Cont-3 Tx, Cont-2 Tx, Cont-1

Cont-0

Tx, Rx

char.

IER[4:7], Rx Control Rx Control Tx, Rx

select

ISR[4:5],

FCR[4:5],

MCR[5:7]

Control Control

1

0

1

0

1

0

1

Xon-1

Xon-2

Xoff-1

Xoff-2

00

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 1

bit 9

bit 0

bit 8

bit 0

bit 8

bit 15

bit 7

bit 14

bit 6

bit 13

bit 5

bit 12

bit 4

bit 11

bit 3

bit 10

bit 2

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

[1] The value shown represents the register’s initialized HEX value; X = not applicable.

[2] These registers are accessible only when LCR[7] = 0.

[3] These bits are only accessible when EFR[4] is set.

[4] This function is not supported in the HVQFN48 package; TXRDY and RXRDY are removed.

[5] The Special Register set is accessible only when LCR[7] is set to a logic 1.

[6] Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’.

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7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the

THR, providing that the THR or TSR is empty. The THR empty ﬂag in the LSR register will

be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.

Note that a write operation can be performed when the THR empty ﬂag is set

(logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).

Receive data is removed from the SC16C654B/654DB and receive FIFO by reading the

RHR register. The receive section provides a mechanism to prevent false starts. On the

falling edge of a start or false start bit, an internal receiver counter starts counting clocks

at the 16× clock rate. After 7¹⁄₂clocks, the start bit time should be shifted to the center of

the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.

Evaluating the start bit in this manner prevents the receiver from assembling a false

character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INTA to INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the

68 mode.

Table 9:

Interrupt Enable Register bits description

Description

Bit

Symbol

IER[7]

7

CTS interrupt.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC16C654B/654DB issues an

interrupt when the CTS pin transitions from a logic 0 to a logic 1.

6

5

IER[6]

IER[5]

RTS interrupt.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC16C654B/654DB issues an

interrupt when the RTS pin transitions from a logic 0 to a logic 1.

Xoff interrupt.

logic 0 = disable the software ﬂow control, receive Xoff interrupt (normal

default condition)

logic 1 = enable the software ﬂow control, receive Xoff interrupt. See Section

6.5 “Software ﬂow control” for details.

4

3

IER[4]

IER[3]

Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See Section 6.11 “Sleep mode” for details.

Modem Status Interrupt.

logic 0 = disable the modem status register interrupt (normal default

condition)

logic 1 = enable the modem status register interrupt

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5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Table 9:

Bit

Interrupt Enable Register bits description …continued

Symbol

IER[2]

Description

2

Receive Line Status interrupt.

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

1

IER[1]

IER[0]

Transmit Holding Register interrupt. This interrupt will be issued whenever the

THR is empty, and is associated with LSR[1].

logic 0 = disable the transmitter empty interrupt (normal default condition)

logic 1 = enable the transmitter empty interrupt

0

Receive Holding Register interrupt. This interrupt will be issued when the FIFO

has reached the programmed trigger level, or is cleared when the FIFO drops

below the trigger level in the FIFO mode of operation.

logic 0 = disable the receiver ready interrupt (normal default condition)

logic 1 = enable the receiver ready interrupt

7.2.1 IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive data available interrupts are issued to the external CPU when the FIFO

has reached the programmed trigger level. It will be cleared when the FIFO drops

below the programmed trigger level.

• FIFO status will also be reﬂected in the user accessible ISR register when the FIFO

trigger level is reached. Both the ISR register status bit and the interrupt will be cleared

when the FIFO drops below the trigger level.

• The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift

register to the receive FIFO. It is reset when the FIFO is empty.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C654B/654DB in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the

LSR, either or both can be used in the polled mode by selecting respective transmit or

receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[1:4] will provide the type of errors encountered, if any.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will indicate any FIFO data errors.

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7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO

trigger levels, and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation, and is similar to

the 16C454 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty

transmit space is available in the Transmit Holding Register (THR). Receive Ready

(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with

a character.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO is below the programmed trigger level. TXRDY remains a logic 0 as long

as one empty FIFO location is available. The receive interrupt is set when the receive

FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll regardless

of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the

FIFO ﬁll level is above the programmed trigger level.

7.3.2 FIFO mode

Table 10: FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7] (MSB), RCVR trigger. These bits are used to set the trigger level for the receive

FCR[6] (LSB) FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to

be loaded until it is full. Refer to Table 11.

5:4

FCR[5] (MSB), TX trigger.

FCR[4] (LSB)

These bits are used to set the trigger level for the transmit FIFO

interrupt. The SC16C654B/654DB will issue a transmit empty interrupt

when the number of characters in FIFO drops below the selected trigger

level. Refer to Table 12.

3

FCR[3]

DMA mode select.

logic 0 = set DMA mode ‘0’ (normal default condition)

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C654B/654DB is in

the 16C454 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO

mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when

there are no characters in the transmit FIFO or transmit holding register,

the TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a

logic 1 after the ﬁrst character is loaded into the transmit holding

register.

Receive operation in mode ‘0’: When the SC16C654B/654DB is in

mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1;

FCR[3] = logic 0) and there is at least one character in the receive FIFO,

the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a

logic 1 when there are no more characters in the receiver.

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Table 10: FIFO Control Register bits description …continued

Bit

Symbol

Description

3

FCR[3]

Transmit operation in mode ‘1’: When the SC16C654B/654DB is in

FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a

logic 1 when the transmit FIFO is completely full. It will be a logic 0 when

the trigger level has been reached.

(cont.) (continued)

Receive operation in mode ‘1’: When the SC16C654B/654DB is in

FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has

been reached, or a Receive Time-Out has occurred, the RXRDY pin will

go to a logic 0. Once activated, it will go to a logic 1 after there are no

more characters in the FIFO.

2

1

0

FCR[2]

FCR[1]

FCR[0]

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default

condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’

when other FCR bits are written to, or they will not be

programmed.

Table 11: RX trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level

0

1

0

1

0

1

08

16

56

60

Table 12: TX trigger levels

FCR[5]

FCR[4]

TX FIFO trigger level (# of characters)

0

1

0

1

0

1

08

16

32

56

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7.4 Interrupt Status Register (ISR)

The SC16C654B/654DB provides six levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with six

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged until

the pending interrupt is serviced. Whenever the interrupt status register is read, the

interrupt status is cleared. However, it should be noted that only the current pending

interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the

interrupt status bits. Table 13 “Interrupt source” shows the data values (bits 0:5) for the six

prioritized interrupt levels and the interrupt sources associated with each of these interrupt

levels.

Table 13: Interrupt source

Priority

level

ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

1

2

3

4

5

6

0

1

0

1

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status

Register)

RXRDY (Receive Data

Ready)

RXRDY (Receive Data

time-out)

TXRDY (Transmitter Holding

Register Empty)

MSR (Modem Status

Register)

RXRDY (Received Xoff

signal)/Special character

CTS, RTS change of state

Table 14: Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is not

being used. They are set to a logic 1 when the FIFOs are enabled.

logic 0 or cleared = default condition

5:4

ISR[5:4]

INT priority bits 4:3. These bits are enabled when EFR[4] is set to a

logic 1. ISR[4] indicates that matching Xoff character(s) have been

detected. ISR[5] indicates that CTS, RTS have been generated. Note

that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon

character(s) are received.

logic 0 or cleared = default condition

3:1

0

ISR[3:1]

ISR[0]

INT priority bits 2:0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3; see Table 13.

Logic 0 or cleared = default condition.

INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as

a pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

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7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 15: Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhance

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch and enhanced feature register enabled

6

5

LCR[6]

LCR[5]

Set break. When enabled, the Break control bit causes a break

condition to be transmitted (the TX output is forced to a logic 0 state).

This condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

Set parity. If the parity bit is enabled, LCR[5] selects the forced parity

format. Programs the parity conditions; see Table 16.

logic 0 = parity is not forced (normal default condition)

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1

for the transmit and receive data

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0

for the transmit and receive data

4

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,

LCR[4] selects the even or odd parity format.

logic 0 = odd parity is generated by forcing an odd number of logic 1s

in the transmitted data. The receiver must be programmed to check

the same format (normal default condition).

logic 1 = even parity is generated by forcing an even number of

logic 1s in the transmitted data. The receiver must be programmed to

check the same format.

3

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.

logic 0 = no parity (normal default condition)

logic 1 = a parity bit is generated during the transmission, receiver

checks the data and parity for transmission errors

2

LCR[2]

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with

the programmed word length; see Table 17.

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received; see Table 18.

logic 0 or cleared = default condition

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Table 16: LCR[5] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

X

0

1

X

0

1

0

1

0

1

odd parity

even parity

forced parity ‘1’

forced parity ‘0’

Table 17: LCR[2] stop bit length

LCR[2]

Word length

5, 6, 7, 8

5

Stop bit length (bit times)

0

1

1¹⁄₂

6, 7, 8

2

Table 18: LCR[1:0] word length

LCR[1]

LCR[0]

Word length

0

1

0

1

0

1

5

6

7

8

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 19: Modem Control Register bits description

Bit

Symbol

Description

7

MCR[7]

Clock select.

logic 0 = divide-by-1. The input clock (crystal or external) is divided by 16

and then presented to the Programmable Baud Rate Generator (BGR)

without further modiﬁcation, that is, divide-by-1. (normal default condition).

logic 1 = divide-by-4. The divide-by-1 clock described in MCR[7] = a logic 0,

if further divided by four. Also see Section 6.9 “Programmable baud rate

generator”.

6

MCR[6]

IR enable.

logic 0 = enable the standard modem receive and transmit input/output

interface (normal default condition)

logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in

this mode, the TX/RX output/inputs are routed to the infrared

encoder/decoder. The data input and output levels will conform to the IrDA

infrared interface requirement. As such, while in this mode, the infrared TX

output will be a logic 0 during idle data conditions.

5

MCR[5]

Xon Any.

logic 0 = disable Xon Any function (for 16C554 compatibility) (normal default

condition)

logic 1 = enable Xon Any function. In this mode, any RX character received

will enable Xon

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Table 19: Modem Control Register bits description …continued

Bit

Symbol

MCR[4]

Description

4

Loop-back. Enable the local loop-back mode (diagnostics). In this mode the

transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are

disconnected from the SC16C654B/654DB I/O pins. Internally the modem

data and control pins are connected into a loop-back data conﬁguration; see

Figure 12. In this mode, the receiver and transmitter interrupts remain fully

operational. The Modem Control Interrupts are also operational, but the

interrupts’ sources are switched to the lower four bits of the Modem Control.

Interrupts continue to be controlled by the IER register.

logic 0 = disable loop-back mode (normal default condition)

logic 1 = enable local loop-back mode (diagnostics)

3

MCR[3]

OP2, INTx enable. Used to control the modem CD signal in the loop-back

mode.

logic 0 = forces INTA-INTD outputs to the 3-state mode during the 16 mode

(normal default condition). In the loop-back mode, sets OP2 (CD) internally

to a logic 1.

logic 1 = forces the INTA-INTD outputs to the active mode during the

16 mode. In the loop-back mode, sets OP2 (CD) internally to a logic 0.

2

1

MCR[2]

MCR[1]

OP1. This bit is used in the Loop-back mode only. In the loop-back mode, this

bit is used to write the state of the modem RI interface signal via OP1.

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

Automatic RTS may be used for hardware ﬂow control by enabling EFR[6].

See Table 22.

0

MCR[0]

DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

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7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C654B/654DB and

the CPU.

Table 20: Line Status Register bits description

Bit Symbol Description

7

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when LSR register is read.

6

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the transmit holding register and the transmit shift register are

both empty. It is reset to logic 0 whenever either the THR or TSR contains a data

character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and

transmit shift register are both empty.

5

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the transmit holding register into the transmitter shift register.

The bit is reset to a logic 0 concurrently with the loading of the transmitter

holding register by the CPU. In the FIFO mode, this bit is set when the transmit

FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s). In

the FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with the

character at the top of the FIFO.

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the receive shift

register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

0

LSR[0]

Receive data ready.

logic 0 = no data in receive holding register or FIFO (normal default condition)

logic 1 = data has been received and is saved in the receive holding register or

FIFO

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

33 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or

other peripheral device to which the SC16C654B/654DB is connected. Four bits of this

register are used to indicate the changed information. These bits are set to a logic 1

whenever a control input from the modem changes state. These bits are set to a logic 0

whenever the CPU reads this register.

Table 21: Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

CD (active HIGH, logical 1). Normally this bit is the complement of the CD

input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR

register.

6

5

MSR[6]

MSR[5]

RI (active HIGH, logical 1). Normally this bit is the complement of the RI input.

In the loop-back mode this bit is equivalent to the OP1 bit in the MCR register.

DSR (active HIGH, logical 1). Normally this bit is the complement of the DSR

input. In loop-back mode this bit is equivalent to the DTR bit in the MCR

register.

4

MSR[4]

CTS. CTS functions as hardware ﬂow control signal input if it is enabled via

EFR[7]. The transmit holding register ﬂow control is enabled/disabled by

MSR[4]. Flow control (when enabled) allows starting and stopping the

transmissions based on the external modem CTS signal. A logic 1 at the CTS

pin will stop SC16C654B/654DB transmissions as soon as current character

has ﬁnished transmission. Normally MSR[4] is the complement of the CTS

input. However, in the loop-back mode, this bit is equivalent to the RTS bit in

the MCR register.

[1]

3

2

1

0

MSR[3]

MSR[2]

MSR[1]

MSR[0]

∆CD

logic 0 = no CD change (normal default condition)

logic 1 = the CD input to the SC16C654B/654DB has changed state since

the last time it was read. A modem Status Interrupt will be generated.

[1]

∆RI

logic 0 = no RI change (normal default condition)

logic 1 = the RI input to the SC16C654B/654DB has changed from a logic 0

to a logic 1. A modem Status Interrupt will be generated.

[1]

∆DSR

logic 0 = no DSR change (normal default condition)

logic 1 = the DSR input to the SC16C654B/654DB has changed state since

the last time it was read. A Modem Status Interrupt will be generated.

[1]

∆CTS

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C654B/654DB has changed state since

the last time it was read. A Modem Status Interrupt will be generated.

[1] Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated.

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

34 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.9 Scratchpad Register (SPR)

The SC16C654B/654DB provides a temporary data register to store 8 bits of user

information.

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection. When the

Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are

concatenated into two sequential numbers.

Table 22: Enhanced Feature Register bits description

Bit

Symbol

Description

7

EFR[7]

Auto CTS. Automatic CTS Flow Control.

logic 0 = automatic CTS ﬂow control is disabled (normal default condition)

logic 1 = enable Automatic CTS ﬂow control. Transmission will stop when

CTS goes to a logical 1. Transmission will resume when the CTS pin

returns to a logical 0.

6

EFR[6]

EFR[5]

EFR[4]

Auto RTS. Automatic RTS may be used for hardware ﬂow control by enabling

EFR[6]. When Auto RTS is selected, an interrupt will be generated when the

receive FIFO is ﬁlled to the programmed trigger level and RTS will go to a

logic 1 at the next trigger level. RTS will return to a logic 0 when data is

unloaded below the next lower trigger level. The state of this register bit

changes with the status of the hardware ﬂow control. RTS functions normally

when hardware ﬂow control is disabled.

logic 0 = automatic RTS ﬂow control is disabled (normal default condition)

logic 1 = enable Automatic RTS ﬂow control

5

Special Character Detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. The SC16C654B/654DB

compares each incoming receive character with Xoff2 data. If a match

exists, the received data will be transferred to FIFO and ISR[4] will be set to

indicate detection of special character. Bit-0 in the X-registers corresponds

with the LSB bit for the receive character. When this feature is enabled, the

normal software ﬂow control must be disabled (EFR[3:0] must be set to a

logic 0).

4

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4],

and MCR[7:5] can be modiﬁed and latched. After modifying any bits in the

enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.

This feature prevents existing software from altering or overwriting the

SC16C654B/654DB enhanced functions.

logic 0 = disable (normal default condition)

logic 1 = enable

3:0

EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming these

bits. See Table 23.

9397 750 14965

Product data sheet

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35 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Table 23: Software ﬂow control functions^[1]

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software ﬂow controls

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

X

0

1

no transmit ﬂow control

transmit Xon1/Xoff1

transmit Xon2/Xoff2

transmit Xon1 and Xon2/Xoff1 and Xoff2

no receive ﬂow control

receiver compares Xon1/Xoff1

receiver compares Xon2/Xoff2

transmit Xon1/Xoff1

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

transmit Xon2/Xoff2

0

1

receiver compares Xon1 and Xon2/Xoff1 and Xoff2

transmit Xon1 and Xon2/Xoff1 and Xoff2

receiver compares Xon1 and Xon2/Xoff1 and Xoff2

[1] When using software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

7.11 SC16C654B/654DB external reset conditions

Table 24: Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

ISR

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

LSR

MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

FCR[7:0] = 0

MSR

FCR

EFR

EFR[7:0] = 0

Table 25: Reset state for outputs

Output

Reset state

HIGH

TXA, TXB, TXC, TXD

RTSA, RTSB, RTSC, RTSD

DTRA, DTRB, DTRC, DTRD

RXRDY

HIGH

TXRDY

LOW

9397 750 14965

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SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

8. Limiting values

Table 26: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

Max

Unit

V

supply voltage

-

7

V_n

voltage at any pin

ambient temperature

storage temperature

GND − 0.3 V_CC+ 0.3

V

T_amb

−40

−65

-

+85

°C

mW

T_stg

+150

500

P_tot(pack)

total power dissipation per

package

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

37 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

10. Dynamic characteristics

Table 28: Dynamic characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC= ± 10 %, unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

Min Max

V_CC= 3.3 V

Min Max

V_CC= 5.0 V

Min Max

Unit

t_1w, t_2w

f_XTAL

t_6s

clock pulse duration

10

-

6

-

6

-

ns

[1] [2]

oscillator/clock frequency

address setup time

48

-

80

-

80

-

MHz

ns

0

t_6h

address hold time

0

-

0

-

0

-

ns

t_7d

IOR delay from chip select

IOR strobe width

10

77

0

-

10

26

0

-

10

23

0

-

ns

t_7w

25 pF load

-

ns

t_7h

chip select hold time from

IOR

-

ns

t_9d

read cycle delay

25 pF load

20

-

20

-

20

-

ns

t_12d

t_12h

t_13d

t_13w

t_13h

delay from IOR to data

data disable time

77

15

-

26

15

-

23

15

-

IOW delay from chip select

IOW strobe width

10

20

0

10

20

0

10

15

0

-

chip select hold time from

IOW

-

t_15d

t_16s

t_16h

t_17d

t_18d

write cycle delay

data setup time

data hold time

25

20

15

-

25

20

5

-

20

15

5

-

ns

-

delay from IOW to output 25 pF load

100

-

33

24

-

29

23

delay to set interrupt from 25 pF load

Modem input

-

t_19d

t_20d

t_21d

t_22d

t_23d

t_24d

t_25d

t_26d

t_27d

delay to reset interrupt

from IOR

25 pF load

-

100

-

24

-

23

ns

delay from stop to

set interrupt

1T_RCLK

[3]

1T_RCLK

[3]

1T_RCLK

[3]

delay from IOR to

reset interrupt

25 pF load

100

29

45

28

40

delay from start to set

interrupt

delay from IOW to transmit

start

8T_RCLK24T_RCLK8T_RCLK24T_RCLK8T_RCLK24T_RCLKns

[3]

delay from IOW to

reset interrupt

-

100

-

45

-

40

ns

delay from stop to

set RXRDY

-

1T_RCLK

[3]

-

1T_RCLK

[3]

-

1T_RCLK

[3]

delay from IOR to

reset RXRDY

100

45

40

delay from IOW to

set TXRDY

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

39 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Table 28: Dynamic characteristics …continued

T_amb= −40 °C to +85 °C; tolerance of V_CC= ± 10 %, unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

t_28d

delay from start to reset

TXRDY

-

8T_RCLK

[3]

-

8T_RCLK

[3]

-

8T_RCLK

[3]

ns

t_30s

t_30w

t_30h

t_30d

t_31d

t_31h

t_32s

t_32h

t_32d

t_33s

t_33h

t_RESET

N

address setup time

chip select strobe width

address hold time

read cycle delay

delay from CS to data

data disable time

write strobe setup time

write strobe hold time

write cycle delay

data setup time

10

90

15

20

-

10

26

15

20

-

10

23

15

20

-

ns

[1]

25 pF load

-

25 pF load

-

90

26

23

-

15

-

15

-

15

10

25

20

15

200

1

-

10

25

15

5

-

10

20

15

5

-

data hold time

-

RESET pulse width

baud rate divisor

-

40

1

-

40

1

-

(2¹⁶− 1)

[1] Applies to external clock, crystal oscillator max 24 MHz.

1

t_3w

[2] Maximum frequency =

-------

[3] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

40 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

10.1 Timing diagrams

A0 to A4

t

30h

t

30w

30s

t

30d

CS

t

31h

32s

R/W

t

31d

D0 to D7

002aaa210

Fig 13. General read timing in 68 mode

A0 to A4

t

30h

30s

30w

CS

R/W

t

32d

32s

32h

t

33h

t

33s

D0 to D7

002aaa211

Fig 14. General write timing in 68 mode

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

41 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

t

6h

valid

address

A0 to A2

t

13h

6s

active

CS

IOW

t

13d

15d

t

13w

active

t

16h

t

16s

D0 to D7

data

002aaa171

Fig 15. General write timing in 16 mode

t

6h

7h

valid

address

A0 to A2

t

6s

active

CS

t

7d

9d

t

7w

IOR

active

t

12h

12d

D0 to D7

data

002aaa172

Fig 16. General read timing in 16 mode

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

42 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

active

IOW

t

17d

RTS

DTR

change of state

CD

CTS

DSR

change of state

t

18d

INT

active

t

19d

active

IOR

t

18d

change of state

RI

002aaa352

Fig 17. Modem input/output timing

t

1w

2w

EXTERNAL

CLOCK

002aaa112

t

3w

1

f _XTAL

=

-------

t_3w

Fig 18. External clock timing

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

43 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

RX

D0

D1

D2

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

20d

active

INT

t

21d

active

IOR

16 baud rate clock

002aaa113

Fig 19. Receive timing

start

bit

parity stop start

bit bit

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RX

t

25d

active data

ready

RXRDY

IOR

t

26d

active

002aab063

Fig 20. Receive ready timing in non-FIFO mode

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

44 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

start

bit

parity stop

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RX

first byte that

reaches the

trigger level

t

25d

active data

ready

RXRDY

IOR

t

26d

active

002aab064

Fig 21. Receive ready timing in FIFO mode

start

bit

parity stop start

bit bit

bit

data bits (0 to 7)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

active

INT

transmitter ready

t

22d

t

24d

t

23d

active

IOW

16 baud rate clock

002aaa116

Fig 22. Transmit timing

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

45 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TX

IOW

active

t

28d

D0 to D7

byte #1

t

27d

active transmitter

ready

TXRDY

transmitter

not ready

002aab062

Fig 23. Transmit ready timing in non-FIFO mode

start

bit

parity stop

bit bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TX

5 data bits

6 data bits

7 data bits

IOW

active

t

28d

D0 to D7

byte #16

t

27d

TXRDY

FIFO full

002aab061

Fig 24. Transmit ready timing in FIFO mode (DMA mode ‘1’)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

46 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

UART frame

start

0

data bits

stop

1

0

1

0

1

0

TX data

IrDA TX data

1

/

bit time

2

bit

time

3

/

bit time

16

002aaa212

Fig 25. Infrared transmit timing

IrDA RX data

bit

time

0 to 1 16× clock delay

0

1

0

1

0

1

0

1

RX data

start

data bits

stop

UART frame

002aaa213

Fig 26. Infrared receive timing

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

47 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

11. Package outline

PLCC68: plastic leaded chip carrier; 68 leads

SOT188-2

e

E

D

y

X

A

60

44

Z

E

43

61

b

p

b

1

w

M

68

1

H

E

pin 1 index

A

e

A

1

A

4

(A )

3

L

p

9

k

27

β

detail X

10

26

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

A

Z

E

4

1

(1)

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

3

1

D

E

D

E

p

max.

min.

max. max.

4.57

4.19

0.81 24.33 24.33

0.66 24.13 24.13

23.62 23.62 25.27 25.27 1.22 1.44

22.61 22.61 25.02 25.02 1.07 1.02

0.53

0.33

0.51 0.25

3.3

1.27

0.05

0.18 0.18

0.1

2.16 2.16

o

45

0.180

0.165

0.032 0.958 0.958

0.026 0.950 0.950

0.93 0.93 0.995 0.995 0.048 0.057

0.89 0.89 0.985 0.985 0.042 0.040

0.021

0.013

inches

0.02 0.01 0.13

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

01-11-14

SOT188-2

112E10

MS-018

EDR-7319

Fig 27. Package outline SOT188-2 (PLCC68)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

48 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v M

D

A

e

w M

b

p

D

B

H

v M

B

D

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 28. Package outline SOT314-2 (LQFP64)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

49 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm

SOT414-1

y

X

A

48

33

49

32

Z

E

e

A

2

A

H

E

(A )

3

A

1

w M

p

θ

b

pin 1 index

L

p

L

64

17

detail X

1

16

Z

v M

A

D

e

w M

b

p

D

B

H

v M

B

D

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

θ

1

2

3

p

E

p

D

E

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.23 0.20 7.1

0.13 0.09 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.64 0.64

0.36 0.36

1.6

mm

0.25

0.4

1

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-20

SOT414-1

136E06

MS-026

Fig 29. Package outline SOT414-1 (LQFP64)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

50 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 6 x 6 x 0.85 mm

SOT778-3

D

B

A

terminal 1

index area

E

A

1

c

detail X

C

e

1

y

C

1

y

M

v

C

A

B

b

e

1/2 e

w

13

24

L

25

12

e

2

E

h

1/2 e

1

36

terminal 1

index area

48

37

X

D

h

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

D

E

e

L

v

w

y

1

h

1

2

max

0.05 0.25

0.00 0.15

6.1

5.9

3.95

3.65

6.1

5.9

3.95

3.65

0.5

0.3

1

mm

0.2

0.4

4.4

0.1

0.05 0.05

0.1

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

04-06-16

04-06-23

SOT778-3

- - -

Fig 30. Package outline SOT778-3 (HVQFN48)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

51 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

LFBGA64: plastic low profile fine-pitch ball grid array package; 64 balls; body 6 x 6 x 1.05 mm

SOT686-1

D

A

B

ball A1

index area

A

2

A

E

A

1

detail X

e

1

C

e

y

1/2 e

v

M

b

C

A

B

C

1

w M

K

J

e

H

G

F

e

2

E

D

C

B

A

1/2 e

ball A1

1

2

3

4

5

6

7

8

9

10

index area

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

y

D

E

e

v

w

y

1

2

1

2

max.

0.3

0.2

1.20 0.35

0.95 0.25

6.1

5.9

6.1

5.9

mm

1.5

4.5

0.08

0.1

0.5

0.15 0.05

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

SOT686-1

- - -

02-03-11

Fig 31. Package outline SOT686-1 (LFBGA64)

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

52 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

12. Soldering

12.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

12.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

12.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

53 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

12.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

12.5 Package related soldering information

Table 29: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

54 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

13. Abbreviations

Table 30: Abbreviations

Acronym

BRG

Description

Baud Rate Generator

CPU

Central Processing Unit

DMA

Direct Memory Access

FIFO

First-In, First-Out

ISDN

LSB

Integrated Service Digital Network

Least Signiﬁcant Bit

MSB

Most Signiﬁcant Bit

QUART

UART

4-channel (Quad) Universal Asynchronous Receiver and Transmitter

Universal Asynchronous Receiver and Transmitter

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

55 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

14. Revision history

Table 31: Revision history

Document ID

Release date Data sheet status

Change

notice

Doc. number

Supersedes

SC16C654B_654DB_2 20050620

Product data sheet

-

9397 750 14965 SC16C654B_654DB_1

Modiﬁcations:

• Section 1 “General description”:

–

2nd paragraph: added 6th sentence.

–

3rd paragraph: added HVQFN48 and LFBGA64 package options, and added second

sentence.

• Table 1 “Ordering information”: added HVQFN48, LFBGA64, and LQFP64 (SOT414-1)

package options.

• Figure 5 “Pin conﬁguration for LQFP64”: added SC16C654BIBM option

• Added Figure 6 “Pin conﬁguration for HVQFN48 (16 mode)”, Figure 7 “Pin conﬁguration for

HVQFN48 (68 mode)”, Figure 8 “Pin conﬁguration for LFBGA64” and Figure 9 “Ball mapping

for LFBGA64”.

• Table 2 “Pin description”: added columns for HVQFN48 and LFBGA64 package types

• moved Section 6.1.1 “The 16 mode interface” (was Section 6.2) and Section 6.1.2 “The

68 mode interface” (was Section 6.3) to be sub-sections of Section 6.1 “Interface options”

• Section 6.4 “Hardware ﬂow control”: added ‘Remark’ following second paragraph.

• Section 6.10 “DMA operation”: added ‘Remark’ following ﬁrst paragraph.

• Table 8 “SC16C654B/654DB internal registers”: added (new) Table note 4 and its reference

at FCR[3].

• Table 27 “Static characteristics”:

–

descriptive line following title: changed ‘V_CC= 2.5 V, 3.3 V or 5.0 V ± 10 %,’ to ‘tolerance

of V_CC± 10 %;’

–

added ‘V_CC= ‘ to the limits’ column headings

• Table 28 “Dynamic characteristics”:

–

descriptive line following title: changed ‘V_CC= 2.5 V, 3.3 V or 5.0 V ± 10 %,’ to ‘tolerance

of V_CC± 10 %;’

–

added ‘V_CC= ‘ to the limits’ column headings

baud rate divisor Max. columns: changed ‘2¹⁶− 1 T_RCLK’ to ‘(2¹⁶− 1)’; deleted ‘ns’ from

Unit column (N is a number).

• Section 11 “Package outline”: added Figure 29 “Package outline SOT414-1 (LQFP64)”,

Figure 30 “Package outline SOT778-3 (HVQFN48)”, and Figure 31 “Package outline

SOT686-1 (LFBGA64)”.

• Added Section 13 “Abbreviations” on page 55

• Section 18 “Trademarks” re-written.

SC16C654B_654DB_1 20050209

Product data sheet

-

9397 750 13115

-

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

56 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

15. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

16. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

18. Trademarks

Notice — All referenced brands, product names, service names and

17. Disclaimers

trademarks are the property of their respective owners.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

19. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 14965

Product data sheet

Rev. 02 — 20 June 2005

57 of 58

SC16C654B/654DB

Philips Semiconductors

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

20. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

10.1

11

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 41

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 48

12

12.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 53

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 53

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 54

Package related soldering information. . . . . . 54

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10

12.2

12.3

12.4

12.5

6

6.1

6.1.1

6.1.2

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

6.12

Functional description . . . . . . . . . . . . . . . . . . 14

Interface options . . . . . . . . . . . . . . . . . . . . . . . 16

The 16 mode interface . . . . . . . . . . . . . . . . . . 16

The 68 mode interface . . . . . . . . . . . . . . . . . . 16

Internal registers. . . . . . . . . . . . . . . . . . . . . . . 17

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 17

Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 18

Software ﬂow control . . . . . . . . . . . . . . . . . . . 18

Special feature software ﬂow control . . . . . . . 19

Xon any feature . . . . . . . . . . . . . . . . . . . . . . . 19

Hardware/software and time-out interrupts. . . 19

Programmable baud rate generator . . . . . . . . 20

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 22

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Loop-back mode. . . . . . . . . . . . . . . . . . . . . . . 22

13

14

15

16

17

18

19

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 55

Revision history . . . . . . . . . . . . . . . . . . . . . . . 56

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 57

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Contact information . . . . . . . . . . . . . . . . . . . . 57

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 24

Transmit (THR) and Receive (RHR) Holding

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Interrupt Enable Register (IER) . . . . . . . . . . . 25

IER versus Receive FIFO interrupt mode

7.2

7.2.1

operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

IER versus Receive/Transmit FIFO polled mode

operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

FIFO Control Register (FCR) . . . . . . . . . . . . . 27

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Mode 0 (FCR bit 3 = 0). . . . . . . . . . . . . . . . . . 27

Mode 1 (FCR bit 3 = 1). . . . . . . . . . . . . . . . . . 27

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Interrupt Status Register (ISR) . . . . . . . . . . . . 29

Line Control Register (LCR) . . . . . . . . . . . . . . 30

Modem Control Register (MCR) . . . . . . . . . . . 31

Line Status Register (LSR). . . . . . . . . . . . . . . 33

Modem Status Register (MSR). . . . . . . . . . . . 34

Scratchpad Register (SPR) . . . . . . . . . . . . . . 35

Enhanced Feature Register (EFR) . . . . . . . . . 35

SC16C654B/654DB external reset conditions 36

7.2.2

7.3

7.3.1

7.3.1.1

7.3.1.2

7.3.2

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 37

Static characteristics. . . . . . . . . . . . . . . . . . . . 38

Dynamic characteristics . . . . . . . . . . . . . . . . . 39

9

10

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 20 June 2005

Document number: 9397 750 14965

Published in The Netherlands


型号：	SC16C654BIBM
厂家：	NXP
描述：	5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder 5 V ， 3.3 V和2.5 V四UART ， 5兆比特/秒（最大），具有64字节FIFO和红外线（ IrDA）编码器/解码器解码器微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片编码器数据传输时钟
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中文：	中文翻译
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