SC16C750BIA44,529_技术文档

SC16C750B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Rev. 05 — 17 October 2008

Product data sheet

1. General description

The SC16C750B is a Universal Asynchronous Receiver and Transmitter (UART) used for

serial data communications. Its principal function is to convert parallel data into serial

data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.

The SC16C750B is pin compatible with the TL16C750 and it will power-up to be

functionally equivalent to the 16C450. Programming of control registers enables the

added features of the SC16C750B. Some of these added features are the 64-byte receive

and transmit FIFOs, automatic hardware ﬂow control. The selectable auto-ﬂow control

feature signiﬁcantly reduces software overload and increases system efﬁciency while in

FIFO mode by automatically controlling serial data ﬂow using RTS output and CTS input

signals. The SC16C750B also provides DMA mode data transfers through FIFO trigger

levels and the TXRDY and RXRDY signals. On-board status registers provide the user

with error indications, operational status, and modem interface control. System interrupts

may be tailored to meet user requirements. An internal loopback capability allows

on-board diagnostics.

The SC16C750B operates at 5 V, 3.3 V and 2.5 V, the industrial temperature range and is

available in plastic PLCC44, LQFP64, and HVQFN32 packages.

2. Features

I Single channel

I 5 V, 3.3 V and 2.5 V operation

I 5 V tolerant on input only pins¹

I Industrial temperature range (−40 °C to +85 °C)

I After reset, all registers are identical to the typical 16C450 register set

I Capable of running with all existing generic 16C450 software

I Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,

PC16C450/550. Software compatible with SC16C750 and TL16C750

I Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V

I 64-byte transmit FIFO

I 64-byte receive FIFO with error ﬂags

I Programmable auto-RTS and auto-CTS

N In auto-CTS mode, CTS controls transmitter

N In auto-RTS mode, receive FIFO contents and threshold control RTS

I Automatic hardware ﬂow control

I Software selectable baud rate generator

1. For data bus pins D7 to D0, see Table 24 “Limiting values”.

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

I Four selectable Receive interrupt trigger levels

I Standard modem interface

I Sleep mode

I Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

I Independent receiver clock input

I Transmit, Receive, Line Status, and data set interrupts independently controlled

I Fully programmable character formatting:

N 5-bit, 6-bit, 7-bit, or 8-bit characters

N Even, odd, or no-parity formats

N 1, 1¹⁄₂, or 2-stop bit

N Baud generation (DC to 3 Mbit/s)

I False start-bit detection

I Complete status reporting capabilities

I 3-state output TTL drive capabilities for bidirectional data bus and control bus

I Line break generation and detection

I Internal diagnostic capabilities:

N Loopback controls for communications link fault isolation

I Prioritized interrupt system controls

I Modem control functions (CTS, RTS, DSR, DTR, RI, DCD)

3. Ordering information

Table 1.

Ordering information

Industrial: V_CC= 2.5 V, 3.3 V or 5 V ± 10 %; T_amb= −40 °C to +85 °C.

Type number

Package

Name

Description

Version

SC16C750BIA44

SC16C750BIB64

SC16C750BIBS

PLCC44

LQFP64

plastic leaded chip carrier; 44 leads

plastic low proﬁle quad ﬂat package; 64 leads; 10 × 10 × 1.4 mm

SOT187-2

SOT314-2

SOT617-1

HVQFN32 plastic thermal enhanced very thin quad ﬂat package; no leads;

32 terminals; body 5 × 5 × 0.85 mm

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

2 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

4. Block diagram

SC16C750B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTERS

REGISTER

D0 to D7

IOR, IOR

IOW, IOW

RESET

DATA BUS

AND

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

RECEIVE

FIFO

RECEIVE

SHIFT

RX

REGISTERS

REGISTER

FLOW

CONTROL

LOGIC

A0 to A2

CS0, CS1, CS2

AS

REGISTER

SELECT

LOGIC

DDIS

DTR

RTS

OUT1, OUT2

MODEM

CONTROL

LOGIC

CTS

RI

DCD

DSR

INT

TXRDY

RXRDY

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

002aaa588

XTAL1

RCLK

XTAL2

BAUDOUT

Shown for PLCC44 and LQFP64 pin assignments.

Fig 1. Block diagram of SC16C750B

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

3 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

5. Pinning information

5.1 Pinning

7

39

38

37

36

35

34

33

32

31

30

29

D5

D6

RESET

OUT1

DTR

RTS

OUT2

n.c.

8

9

D7

10

11

12

13

14

15

16

17

RCLK

RX

n.c.

SC16C750BIA44

TX

INT

CS0

RXRDY

A0

CS1

CS2

A1

BAUDOUT

A2

002aaa589

Fig 2. Pin conﬁguration for PLCC44

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

D5

D6

RESET

OUT

DTR

RTS

INT

D7

RCLK

RX

SC16C750BIBS

TX

RXRDY

A0

CS

BAUDOUT

A1

002aaa949

Transparent top view

Fig 3. Pin conﬁguration for HVQFN32

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

4 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

XTAL1

XTAL2

n.c.

D4

n.c.

D3

D2

n.c.

D1

D0

n.c.

3

4

IOW

n.c.

5

6

IOW

n.c.

7

8

GND

IOR

SC16C750BIB64

9

V

CC

10

11

12

13

14

15

16

IOR

n.c.

RI

n.c.

DDIS

TXRDY

n.c.

DCD

DSR

n.c.

CTS

AS

n.c.

002aaa590

Fig 4. Pin conﬁguration for LQFP64

5.2 Pin description

Table 2.

Symbol

Pin description

Type Description

PLCC44 LQFP64

HVQFN32

A2, A1, A0 29, 30, 17, 18, 20 16, 17, 18

31

I

Register select. A0 to A2 are used during read and write

operations to select the UART register to read from or write to.

Refer to Table 3 for register addresses and refer to AS description.

AS

28

15

64

-

Address strobe. When AS is active (LOW), A0, A1, and A2 and

CS0, CS1, and CS2 drive the internal select logic directly; when AS

is HIGH, the register select and chip select signals are held at the

logic levels they were in when the LOW-to-HIGH transition of AS

occurred.

BAUDOUT 17

8

O

Baud out. BAUDOUT is a 16× clock signal for the transmitter

section of the UART. The clock rate is established by the reference

oscillator frequency divided by a divisor speciﬁed in the baud rate

generator divisor latches. BAUDOUT may also be used for the

receiver section by tying this output to RCLK.

CS0, CS1, 14, 15, 59, 61, 62

-

I

Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these

three inputs select the UART. When any of these inputs are inactive,

the UART remains inactive (refer to AS description).

CS2

16

CS

-

7

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

5 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 2.

Symbol

Pin description …continued

Type Description

PLCC44 LQFP64

HVQFN32

CTS

40

33

25

I

Clear to send. CTS is a modem status signal. Its condition can be

checked by reading bit 4 (CTS) of the Modem Status Register

(MSR). MSR[3] (∆CTS) indicates that CTS has changed states

since the last read from the MSR. If the modem status interrupt is

enabled when CTS changes levels and the auto-CTS mode is not

enabled, an interrupt is generated. CTS is also used in the

auto-CTS mode to control the transmitter.

D7 to D0

DCD

9, 8, 7, 52, 51, 50, 3, 2, 1, 32, I/O

6, 5, 4, 48, 46, 45, 31, 30,

Data bus. Eight data lines with 3-state outputs provide a

bidirectional path for data, control and status information between

the UART and the CPU.

3, 2

43, 42

29, 28

42

36

-

I

Data carrier detect. DCD is a modem status signal. Its condition

can be checked by reading bit 7 (DCD) of the Modem Status

Register (MSR). MSR[3] (∆DCD) indicates that DCD has changed

states since the last read from the MSR. If the modem status

interrupt is enabled when DCD changes levels, an interrupt is

generated.

DDIS

DSR

26

41

12

35

-

O

I

Driver disable. DDIS is active (LOW) when the CPU is reading

data. When inactive (HIGH), DDIS can disable an external

transceiver.

26

Data set ready. DSR is a modem status signal. Its condition can be

checked by reading bit 5 (DSR) of the Modem Status Register. Bit 1

(DDSR) of the MSR indicates DSR has changed levels since the

last read from the MSR. If the modem status interrupt is enabled

when DSR changes levels, an interrupt is generated.

DTR

INT

37

33

28

23

22

20

O

Data terminal ready. When active (LOW), DTR informs a modem

or data set that the UART is ready to establish communication. DTR

is placed in the active level by setting the DTR bit of the Modem

Control Register. DTR is placed in the inactive level either as a

result of a Master Reset, during Loopback mode operation, or

clearing the DTR bit.

Interrupt. When active (HIGH), INT informs the CPU that the UART

has an interrupt to be serviced. Four conditions that cause an

interrupt to be issued are: a receiver error, received data that is

available or timed out (FIFO mode only), an empty transmitter

holding register or an enabled modem status interrupt. INT is reset

(deactivated) either when the interrupt is serviced or as a result of a

Master Reset.

n.c.

34

3, 5, 7, 11, 12

14, 16, 19,

22, 24, 27,

29, 31, 34,

37, 39, 41,

44, 47, 49,

53, 56, 57,

60, 63

-

not connected

OUT1,

OUT2

38, 35

-

30, 25

-

O

Outputs 1 and 2. These are user-designated output terminals that

are set to the active (LOW) level by setting respective Modem

Control Register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2

are set to inactive the (HIGH) level as a result of Master Reset,

during Loopback mode operations, or by clearing bit 2 (OUT1) or

bit 3 (OUT2) of the MCR.

OUT

-

23

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

6 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 2.

Symbol

Pin description …continued

Type Description

PLCC44 LQFP64

HVQFN32

RCLK

10

54

4

I

Receiver clock. RCLK is the 16× baud rate clock for the receiver

section of the UART.

RESET

39

32

24

Master Reset. When active (HIGH), RESET clears most UART

registers and sets the levels of various output signals.

IOR

25

24

10

9

-

I

Read inputs. When either IOR or IOR is active (LOW or HIGH,

respectively) while the UART is selected, the CPU is allowed to

read status information or data from a selected UART register. Only

one of these inputs is required for the transfer of data during a read

operation; the other input should be tied to its inactive level (that is,

IOR tied LOW or IOR tied HIGH).

14

RI

43

36

38

26

-

I

Ring indicator. RI is a modem status signal. Its condition can be

checked by reading bit 6 (RI) of the Modem Status Register. Bit 2

(∆RI) of the MSR indicates that RI has changed from a LOW to a

HIGH level since the last read from the MSR. If the modem status

interrupt is enabled when this transition occurs, an interrupt is

generated.

RTS

21

O

Request to send. When active, RTS informs the modem or data

set that the UART is ready to receive data. RTS is set to the active

level by setting the RTS Modem Control Register bit and is set to

the inactive (HIGH) level either as a result of a Master Reset or

during Loopback mode operations or by clearing bit 1 (RTS) of the

MCR. In the auto-RTS mode, RTS is set to the inactive level by the

receiver threshold control logic.

RXRDY

32

21

19

O

Receiver ready. Receiver Direct Memory Access (DMA) signaling

is available with RXRDY. When operating in the FIFO mode, one of

two types of DMA signaling can be selected using the FIFO Control

Register bit 3 (FCR[3]). When operating in the 16C450 mode, only

DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in

which a transfer is made between CPU bus cycles. Mode 1

supports multi-transfer DMA in which multiple transfers are made

continuously until the receiver FIFO has been emptied. In DMA

mode 0 (FCR[0] = 0 or FCR[0] = 1, FCR[3] = 0), when there is at

least one character in the receiver FIFO or receiver holding register,

RXRDY is active (LOW). When RXRDY has been active but there

are no characters in the FIFO or holding register, RXRDY goes

inactive (HIGH). In DMA mode 1 (FCR[0] = 1, FCR[3] = 1), when

the trigger level or the time-out has been reached, RXRDY goes

active (LOW); when it has been active but there are no more

characters in the FIFO or holding register, it goes inactive (HIGH).

RX

TX

11

13

55

58

5

6

I

Serial data input. RX is serial data input from a connected

communications device.

O

Serial data output. TX is composite serial data output to a

connected communication device. TX is set to the marking (HIGH)

level as a result of Master Reset.

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

7 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 2.

Symbol

Pin description …continued

Type Description

PLCC44 LQFP64

HVQFN32

TXRDY

27

13

15

O

Transmitter ready. Transmitter DMA signaling is available with

TXRDY. When operating in the FIFO mode, one of two types of

DMA signaling can be selected using FCR[3]. When operating in

the 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports

single-transfer DMA in which a transfer is made between CPU bus

cycles. Mode 1 supports multi-transfer DMA in which multiple

transfers are made continuously until the transmit FIFO has been

ﬁlled.

V_CC

44

22

21

20

40

8

27

13

-

Power 2.5 V, 3 V or 5 V supply voltage.

Power Ground voltage.

GND

IOW

6

I

Write inputs. When either IOW or IOW is active (LOW or HIGH,

respectively) and while the UART is selected, the CPU is allowed to

write control words or data into a selected UART register. Only one

of these inputs is required to transfer data during a write operation;

the other input should be tied to its inactive level (that is, IOW tied

LOW or IOW tied HIGH).

4

11

XTAL1

XTAL2^[1]

18

19

1

2

9

I

Crystal connection or External clock input.

10

O

Crystal connection or the inversion of XTAL1 if XTAL1 is

driven.

[1] In Sleep mode, XTAL2 is left ﬂoating.

6. Functional description

The SC16C750B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is insured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The SC16C750B is fabricated with an advanced CMOS process to achieve low

drain power and high speed requirements.

The SC16C750B is an upward solution that provides 64 bytes of transmit and receive

FIFO memory, instead of none in the 16C450, or 16 bytes in the 16C550. The

SC16C750B is designed to work with high speed modems and shared network

environments that require fast data processing time. Increased performance is realized in

the SC16C750B by the larger transmit and receive FIFOs. This allows the external

processor to handle more networking tasks within a given time. In addition, the four

selectable levels of FIFO trigger interrupt and automatic hardware ﬂow control is uniquely

provided for maximum data throughput performance, especially when operating in a

multi-channel environment. The combination of the above greatly reduces the bandwidth

requirement of the external controlling CPU, increases performance, and reduces power

consumption.

The SC16C750B is capable of operation up to 3 Mbit/s with a 48 MHz external clock input

(at 5 V).

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

8 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

The rich feature set of the SC16C750B is available through internal registers. Automatic

hardware ﬂow control, selectable transmit and receive FIFO trigger level, selectable TX

and RX baud rates, modem interface controls, and a sleep mode are some of these

features.

6.1 Internal registers

The SC16C750B provides 12 internal registers for monitoring and control. These registers

are shown in Table 3. These twelve registers are similar to those already available in the

standard 16C550. These registers function as data holding registers (THR/RHR), interrupt

status and control registers (IER/ISR), a FIFO Control Register (FCR), line status and

control registers (LCR/LSR), modem status and control registers (MCR/MSR),

programmable data rate (clock) control registers (DLL/DLM), and a user accessible

Scratchpad Register (SPR). Register functions are more fully described in the following

paragraphs.

Table 3.

A2

Internal registers decoding

A0 READ mode

A1

WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

1

LSB of Divisor Latch

MSB of Divisor Latch

LSB of Divisor Latch

MSB of Divisor Latch

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

9 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

6.2 FIFO operation

The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register

bit 0 (FCR[0]). The receiver FIFO section includes a time-out function to ensure data is

delivered to the external CPU. An interrupt is generated whenever the Receive Holding

Register (RHR) has not been read following the loading of a character or the receive

trigger level has not been reached.

Table 4.

Flow control mechanism

Selected trigger level

(characters)

INT pin activation

Negate RTS

Assert RTS

16-byte FIFO

1

0

4

8

14

64-byte FIFO

1

0

16

32

56

16

32

56

16

32

56

6.3 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C750B monitors the CTS pin

for a remote buffer overﬂow indication and controls the RTS pin for local buffer overﬂows.

Automatic hardware ﬂow control is selected by setting MCR[5] (RTS) and MCR[1] (CTS)

to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a ﬂow control request,

the SC16C750B will suspend TX transmissions as soon as the stop bit of the character in

process is shifted out. Transmission is resumed after the CTS input returns to a logic 0,

indicating more data may be sent.

With the auto-RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS

off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return

to a logic 0 after the data buffer (FIFO) is emptied. However, under the above described

conditions, the SC16C750B will continue to accept data until the receive FIFO is full.

6.4 Time-out interrupts

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt

priority (when enabled by IER[0]). The receiver issues an interrupt after the number of

characters have reached the programmed trigger level. In this case, the SC16C750B

FIFO may hold more characters than the programmed trigger level. Following the removal

of a data byte, the user should re-check LSR[0] for additional characters. A Receive

Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the

center of each stop bit received or each time the receive holding register (RHR) is read.

The actual time-out value is 4 character time.

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

10 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

6.5 Programmable baud rate generator

The SC16C750B supports high speed modem technologies that have increased input

data rates by employing data compression schemes. For example, a 33.6 kbit/s modem

that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s

ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing

independent TX/RX channel control. The programmable baud rate generator is capable of

accepting an input clock up to 48 MHz, as required for supporting a 3 Mbit/s data rate.

The SC16C750B can be conﬁgured for internal or external clock operation. For internal

clock oscillator operation, an industry standard microprocessor crystal (parallel resonant,

22 pF to 33 pF load) is connected externally between the XTAL1 and XTAL2 pins (see

Figure 5). Alternatively, an external clock can be connected to the XTAL1 pin to clock the

internal baud rate generator for standard or custom rates (see Table 5).

XTAL1

XTAL2

XTAL1

XTAL2

1.5 kΩ

X1

1.8432 MHz

C1

22 pF

C2

33 pF

C1

22 pF

C2

47 pF

002aaa870

Fig 5. Crystal oscillator connection

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). The

SC16C750B divides the basic crystal or external clock by 16. The frequency of the

BAUDOUT output pin is exactly 16× (16 times) of the selected baud rate

(BAUDOUT = 16 Baud Rate). Customized baud rates can be achieved by selecting the

proper divisor values for the MSB and LSB sections of baud rate generator.

Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a

user capability for selecting the desired ﬁnal baud rate. The example in Table 5 shows

selectable baud rates when using a 1.8432 MHz crystal.

For custom baud rates, the divisor value can be calculated using Equation 1:

XTAL1 clock frequency

serial data rate × 16

divisor (in decimal) =

(1)

----------------------------------------------------------------

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

11 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 5.

Baud rates using 1.8432 MHz or 3.072 MHz crystal

Using 3.072 MHz crystal

Using 1.8432 MHz crystal

Desired

baud rate

Divisor for

16× clock

Baud rate

error

Desired

baud rate

Divisor for

16× clock

Baud rate

error

50

2304

1536

1047

857

768

384

192

96

50

3840

2560

1745

1428

1280

640

320

160

107

96

75

110

0.026

0.058

110

0.026

0.034

134.5

150

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

64

0.312

58

0.69

48

80

32

53

0.628

1.23

24

40

16

27

12

20

6

10

3

5

2

2.86

6.6 DMA operation

The SC16C750B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. The user can optionally operate the transmit and receive FIFOs in the

DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output

pins. Table 6 and Table 7 show this.

Table 6.

Effect of DMA mode on state of RXRDY pin

Non-DMA mode

DMA mode

1 = FIFO empty

0-to-1 transition when FIFO empties

0 = at least 1 byte in FIFO

1-to-0 transition when FIFO reaches trigger level,

or time-out occurs

Table 7.

Effect of DMA mode on state of TXRDY pin

Non-DMA mode

1 = at least 1 byte in FIFO

0 = FIFO empty

DMA mode

0-to-1 transition when FIFO becomes full

1-to-0 transition when FIFO becomes empty

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

12 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

6.7 Sleep mode

The SC16C750B is designed to operate with low power consumption. A special Sleep

mode is included to further reduce power consumption (the internal oscillator driver is

disabled) when the chip is not being used. With IER[4] enabled (set to a logic 1), the

SC16C750B enters the Sleep mode, but resumes normal operation when a start bit is

detected, a change of state of RX or on any of the modem input pins RI, CTS, DSR, DCD,

or a transmit data is provided by the user. If the Sleep mode is enabled and the

SC16C750B is awakened by one of the conditions described above, it will return to the

Sleep mode automatically after the last character is transmitted or read by the user. In any

case, the Sleep mode will not be entered while an interrupt(s) is pending. The

SC16C750B will stay in the Sleep mode of operation until it is disabled by setting IER[4] to

a logic 0.

6.8 Low power mode

In Low power mode the oscillator is still running and only the clock to the UART core is

cut off. This helps to reduce the operating current to about ¹⁄₃. The UART wakes up under

the same conditions as in Sleep mode.

6.9 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally.

MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the

Loopback mode, OUT1 and OUT2 in the MCR register (bit 2 and bit 3) control the modem

RI and DCD inputs, respectively. MCR signals DTR and RTS (bit 0 and bit 1) are used to

control the modem DSR and CTS inputs, respectively. The transmitter output (TX) and the

receiver input (RX) are disconnected from their associated interface pins, and instead are

connected together internally (see Figure 6). The CTS, DSR, DCD, and RI are

disconnected from their normal modem control input pins, and instead are connected

internally to RTS, DTR, OUT2 and OUT1. Loopback test data is entered into the Transmit

Holding Register via the user data bus interface, D0 to D7. The transmit UART serializes

the data and passes the serial data to the receive UART via the internal loopback

connection. The receive UART converts the serial data back into parallel data that is then

made available at the user data interface D0 to D7. The user optionally compares the

received data to the initial transmitted data for verifying error-free operation of the UART

TX/RX circuits.

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

13 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

SC16C750B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTERS

REGISTER

D0 to D7

IOR, IOR

IOW, IOW

RESET

DATA BUS

AND

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

MCR[4] = 1

RECEIVE

FIFO

REGISTERS

RECEIVE

SHIFT

REGISTER

RX

FLOW

CONTROL

LOGIC

A0 to A2

CS0, CS1, CS2

AS

REGISTER

SELECT

LOGIC

RTS

DDIS

CTS

DTR

DSR

MODEM

CONTROL

LOGIC

OUT1

INT

TXRDY

RXRDY

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

RI

OUT2

DCD

002aaa591

XTAL1

RCLK

XTAL2

BAUDOUT

Shown for PLCC44 and LQFP64 pin assignments.

Fig 6. Internal Loopback mode diagram

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

14 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7. Register descriptions

Table 8 details the assigned bit functions for the ﬁfteen SC16C750B internal registers. The

assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.10.

Table 8.

SC16C750B internal registers

A2 A1 A0 Register Default^[1]Bit 7

General Register Set^[2]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

0

bit 6

0

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Low

power

mode

Sleep

mode

modem receive

status line

interrupt status

interrupt

transmit receive

holding holding

register register

0

1

0

1

0

1

FCR

ISR

00

01

00

60

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

64-byte reserved DMA

XMIT

FIFO

reset

RCVR

FIFO

reset

FIFO

enable

FIFO

enable

mode

select

FIFOs

64-byte

0

INT

priority

bit 1

INT

priority

bit 0

INT

status

enabled enabled FIFO

enable

priority

bit 2

LCR

MCR

LSR

divisor

latch

enable

set break set

parity

even

parity

stop bits word

length

word

length

bit 0

parity

enable

bit 1

0

ﬂow

loopback OUT2

OUT1

RTS

DTR

control

enable

FIFO

data

error

trans.

empty

trans.

break

framing parity

overrun receive

error

holding interrupt error

empty

error

data

ready

1

0

1

MSR

SPR

X0

FF

DCD

bit 7

RI

DSR

bit 5

CTS

bit 4

∆DCD

∆RI

∆DSR

∆CTS

bit 6

bit 3

bit 2

bit 1

bit 0

Special Register Set^[3]

0

1

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

[1] The value shown represents the register’s initialized HEX value; X = n/a.

[2] These registers are accessible only when LCR[7] = 0.

[3] The Special Register set is accessible only when LCR[7] is set to a logic 1.

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

15 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the

THR, providing that the THR or TSR is empty. The THR empty ﬂag in the LSR register will

be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.

Note that a write operation can be performed when the THR empty ﬂag is set

(logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).

Receive data is removed from the SC16C750B and receive FIFO by reading the RHR

register. The receive section provides a mechanism to prevent false starts. On the falling

edge of a start or false start bit, an internal receiver counter starts counting clocks at the

16× clock rate. After 7¹⁄₂clocks, the start bit time should be shifted to the center of the

start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.

Evaluating the start bit in this manner prevents the receiver from assembling a false

character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INT output pin.

Table 9.

Interrupt Enable Register bits description

Description

Bit

7:6

5

Symbol

IER[7:6]

Not used.

IER[5]

IER[4]

IER[3]

Low power mode.

logic 0 = disable Low power mode (normal default condition)

logic 1 = enable Low power mode

Sleep mode.

4

3

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See Section 6.7 “Sleep mode” for details.

Modem Status Interrupt.

logic 0 = disable the modem status register interrupt (normal default

condition)

logic 1 = enable the modem status register interrupt

2

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a fully

assembled receive character is transferred from RSR to the RHR/FIFO, i.e.,

data ready, LSR[0].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

16 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 9.

Interrupt Enable Register bits description …continued

Bit

Symbol

Description

1

IER[1]

Transmit Holding Register interrupt. This interrupt will be issued whenever the

THR is empty, and is associated with LSR[1].

logic 0 = disable the transmitter empty interrupt (normal default condition)

logic 1 = enable the transmitter empty interrupt

0

IER[0]

Receive Holding Register interrupt. This interrupt will be issued when the FIFO

has reached the programmed trigger level, or is cleared when the FIFO drops

below the trigger level in the FIFO mode of operation.

logic 0 = disable the receiver ready interrupt (normal default condition)

logic 1 = enable the receiver ready interrupt

7.2.1 IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive data available interrupts are issued to the external CPU when the FIFO

has reached the programmed trigger level. It will be cleared when the FIFO drops

below the programmed trigger level.

• FIFO status will also be reﬂected in the user accessible ISR register when the FIFO

trigger level is reached. Both the ISR register status bit and the interrupt will be

cleared when the FIFO drops below the trigger level.

• The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift

register to the receive FIFO. It is reset when the FIFO is empty.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C750B in the FIFO polled

mode of operation. Since the receiver and transmitter have separate bits in the LSR,

either or both can be used in the polled mode by selecting respective transmit or receive

control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of errors encountered, if any.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will indicate any FIFO data errors.

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

17 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels, and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation, and is similar to

the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty

transmit space is available in the Transmit Holding Register (THR). Receive Ready

(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with

a character.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO is below the programmed trigger level. The receive interrupt is set when

the receive FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll

regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long

as the FIFO ﬁll level is above the programmed trigger level.

7.3.2 FIFO mode

Table 10. FIFO Control Register bits description

Bit Symbol

Description

7:6 FCR[7]

(MSB),

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

FCR[6] (LSB)

An interrupt is generated when the number of characters in the FIFO equals

the programmed trigger level. However, the FIFO will continue to be loaded

until it is full. Refer to Table 11.

5

FCR[5]

64-byte FIFO enable.

logic 0 = 16-byte mode (normal default condition)

logic 1 = 64-byte mode

4

3

FCR[4]

FCR[3]

reserved

DMA mode select.

logic 0 = set DMA mode ‘0’ (normal default condition).

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C750B is in the 16C450

mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs

enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no

characters in the transmit FIFO or transmit holding register, the TXRDY pin

will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the

ﬁrst character is loaded into the transmit holding register.

Receive operation in mode ‘0’: When the SC16C750B is in 16C450

mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is

at least one character in the receive FIFO, the RXRDY pin will be a logic 0.

Once active, the RXRDY pin will go to a logic 1 when there are no more

characters in the receiver.

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

18 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 10. FIFO Control Register bits description …continued

Bit Symbol Description

FCR[3]

(continued)

Transmit operation in mode ‘1’: When the SC16C750B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when

the transmit FIFO is completely full. It will be a logic 0 when the FIFO is

emptied.

Receive operation in mode ‘1’: When the SC16C750B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,

or a Receive Time-Out has occurred, the RXRDY pin will go to a logic 0.

Once activated, it will go to a logic 1 after there are no more characters in

the FIFO.

2

1

0

FCR[2]

FCR[1]

FCR[0]

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO

Table 11. RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level (bytes)

16-byte operation

64-byte operation

0

1

0

1

0

1

4

16

32

56

8

14

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

19 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.4 Interrupt Status Register (ISR)

The SC16C750B provides four levels of prioritized interrupts to minimize external software

interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status

bits. Performing a read cycle on the ISR will provide the user with the highest pending

interrupt level to be serviced. No other interrupts are acknowledged until the pending

interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is

cleared. However, it should be noted that only the current pending interrupt is cleared by

the read. A lower level interrupt may be seen after re-reading the interrupt status bits.

Table 12 “Interrupt source” shows the data values (bit 0 to bit 4) for the four prioritized

interrupt levels and the interrupt sources associated with each of these interrupt levels.

Table 12. Interrupt source

Priority

level

ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

1

2

3

4

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status Register)

RXRDY (Received Data Ready)

RXRDY (Receive Data time-out)

TXRDY (Transmitter Holding Register Empty)

MSR (Modem Status Register)

Table 13. Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is not

being used. They are set to a logic 1 when the FIFOs are enabled.

logic 0 or cleared = default condition

64-byte FIFO enable.

5

ISR[5]

logic 0 = 16-byte operation

logic 1 = 64-byte operation

not used

4

ISR[4]

3:1

ISR[3:1]

INT priority bit 2 to bit 0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 12).

logic 0 or cleared = default condition

INT status.

0

ISR[0]

logic 0 = an interrupt is pending and the ISR contents may be used

as a pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

20 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 14. Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch and enhanced feature register enabled

6

5

LCR[6]

LCR[5]

Set break. When enabled, the Break control bit causes a break condition to

be transmitted (the TX output is forced to a logic 0 state). This condition exists

until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format.

Programs the parity conditions (see Table 15).

logic 0 = parity is not forced (normal default condition)

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for the

transmit and receive data

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for the

transmit and receive data

4

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4]

selects the even or odd parity format.

logic 0 = odd parity is generated by forcing an odd number of logic 1s in the

transmitted data. The receiver must be programmed to check the same

format (normal default condition).

logic 1 = even parity is generated by forcing an even number of logic 1s in

the transmitted data. The receiver must be programmed to check the same

format.

3

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.

logic 0 = no parity (normal default condition)

logic 1 = a parity bit is generated during the transmission, receiver checks

the data and parity for transmission errors

2

LCR[2]

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with the

programmed word length (see Table 16).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bit 1, bit 0. These two bits specify the word length to be

transmitted or received (see Table 17).

logic 0 or cleared = default condition

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

21 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 15. LCR[5] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

X

0

1

X

0

1

0

1

0

1

no parity

odd parity

even parity

force parity ‘1’

forced parity ‘0’

Table 16. LCR[2] stop bit length

LCR[2]

Word length (bits)

Stop bit length (bit times)

0

1

5, 6, 7, 8

5

1

1¹⁄₂

6, 7, 8

2

Table 17. LCR[1:0] word length

LCR[1]

LCR[0]

Word length (bits)

0

1

0

1

0

1

5

6

7

8

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

22 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 18. Modem Control Register bits description

Bit

7

Symbol

MCR[7]

MCR[6]

MCR[5]

Description

reserved; set to 0

6

5

AFE. This bit is the auto ﬂow control enable. When this bit is set, the auto

ﬂow control is enabled.

4

MCR[4]

Loopback. Enable the local Loopback mode (diagnostics). In this mode the

transmitter output (TX) and the receiver input (RX), CTS, DSR, DCD, and RI

are disconnected from the SC16C750B I/O pins. Internally the modem data

and control pins are connected into a loopback data conﬁguration (see

Figure 6). In this mode, the receiver and transmitter interrupts remain fully

operational. The Modem Control Interrupts are also operational, but the

interrupts’ sources are switched to the lower four bits of the Modem Control.

Interrupts continue to be controlled by the IER register.

logic 0 = disable Loopback mode (normal default condition)

logic 1 = enable local Loopback mode (diagnostics)

3

MCR[3]

OUT2, INT enable. Used to control the modem DCD signal in the Loopback

mode.

logic 0 = set OUT2 to HIGH. In the Loopback mode, sets OUT2 (DCD)

internally to a logic 1.

logic 1 = set OUT2 to LOW. In the Loopback mode, sets OUT2 (DCD)

internally to a logic 0.

2

1

MCR[2]

MCR[1]

OUT1. This bit is used in the Loopback mode only. In the Loopback mode,

this bit is used to write the state of the modem RI interface signal via OUT1.

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

0

MCR[0]

DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

The ﬂow control can be conﬁgured by programming MCR[1] and MCR[5] as shown in

Table 19.

Table 19. Flow control conﬁguration

MCR[5] (AFE)

MCR[1] (RTS)

Flow conﬁguration

1

0

1

0

X

auto RTS and CTS enabled

auto CTS only enabled

auto RTS and CTS disabled

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

23 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C750B and the CPU.

Table 20. Line Status Register bits description

Bit

Symbol Description

7

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when LSR register is read.

6

5

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the transmit holding register and the transmit shift register are

both empty. It is reset to logic 0 whenever either the THR or TSR contains a data

character. In the FIFO mode, this bit is set to logic 1 whenever the transmit FIFO

and transmit shift register are both empty.

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the transmit holding register into the transmitter shift register.

The bit is reset to a logic 0 concurrently with the loading of the transmitter

holding register by the CPU. In the FIFO mode, this bit is set when the transmit

FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s). In

the FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with the

character at the top of the FIFO.

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the receive shift

register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

0

LSR[0]

Receive data ready.

logic 0 = no data in receive holding register or FIFO (normal default condition)

logic 1 = data has been received and is saved in the receive holding register or

FIFO

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

24 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or

other peripheral device to which the SC16C750B is connected. Four bits of this register

are used to indicate the changed information. These bits are set to a logic 1 whenever a

control input from the modem changes state. These bits are set to a logic 0 whenever the

CPU reads this register.

Table 21. Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

Data Carrier Detect. DCD (active HIGH, logic 1). Normally this bit is the

complement of the DCD input. In the Loopback mode this bit is equivalent to

the OUT2 bit in the MCR register.

6

5

4

MSR[6]

MSR[5]

MSR[4]

Ring Indicator. RI (active HIGH, logic 1). Normally this bit is the complement

of the RI input. In the Loopback mode this bit is equivalent to the OUT1 bit in

the MCR register.

Data Set Ready. DSR (active HIGH, logic 1). Normally this bit is the

complement of the DSR input. In Loopback mode this bit is equivalent to the

DTR bit in the MCR register.

Clear To Send. CTS. CTS functions as hardware ﬂow control signal input if it

is enabled via MCR[5]. Flow control (when enabled) allows starting and

stopping the transmissions based on the external modem CTS signal. A

logic 1 at the CTS pin will stop SC16C750B transmissions as soon as current

character has ﬁnished transmission. Normally MSR[4] is the complement of

the CTS input. However, in the Loopback mode, this bit is equivalent to the

RTS bit in the MCR register.

3

2

1

0

MSR[3]

MSR[2]

MSR[1]

MSR[0]

∆DCD ^[1]

logic 0 = no DCD change (normal default condition)

logic 1 = the DCD input to the SC16C750B has changed state since the last

time it was read. A modem Status Interrupt will be generated.

∆RI ^[1]

logic 0 = no RI change (normal default condition)

logic 1 = the RI input to the SC16C750B has changed from a logic 0 to a

logic 1. A modem Status Interrupt will be generated.

∆DSR ^[1]

logic 0 = no DSR change (normal default condition)

logic 1 = the DSR input to the SC16C750B has changed state since the last

time it was read. A modem Status Interrupt will be generated.

∆CTS ^[1]

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C750B has changed state since the last

time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR[0:3] is set to logic 1, a Modem Status Interrupt will be generated.

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

25 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.9 Scratchpad Register (SPR)

The SC16C750B provides a temporary data register to store 8 bits of user information.

7.10 SC16C750B external reset conditions

Table 22. Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

ISR

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

LSR

MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

FCR[7:0] = 0

MSR

FCR

Table 23. Reset state for outputs

Output

TX

Reset state

HIGH

RTS

HIGH

DTR

HIGH

RXRDY

TXRDY

INT

HIGH (STD mode)

LOW (STD mode)

8. Limiting values

Table 24. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

7

Unit

V

V_CC

V_n

supply voltage

-

voltage on any other pin

at D7 to D0 pins

at input only pins

operating

GND − 0.3

V_CC+ 0.3

5.3

V

GND − 0.3

V

T_amb

T_stg

ambient temperature

storage temperature

−40

−65

-

+85

°C

mW

+150

500

P_tot/pack total power dissipation

per package

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

26 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

9. Static characteristics

Table 25. Static characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC= ± 10 %, unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V Unit

Min

−0.3

1.8

Max

0.45

V_CC

0.65

-

Min

−0.3

2.4

Max

0.6

V_CC

0.8

-

Min

−0.5

3.0

Max

0.6

V_IL(clk)

V_IH(clk)

V_IL

clock LOW-level input voltage

V

clock HIGH-level input voltage

LOW-level input voltage

HIGH-level input voltage

LOW-level output voltage

V_CC

0.8

−0.3

1.6

−0.3

2.0

−0.5

2.2

V_IH

V_CC

[1]

V_OL

on all outputs

I_OL= 5 mA

(data bus)

-

0.4

V

I_OL= 4 mA

(other outputs)

-

0.4

-

I_OL= 2 mA

(data bus)

-

0.4

-

I_OL= 1.6 mA

(other outputs)

-

0.4

-

V_OH

HIGH-level output voltage

I_OH= −5 mA

(data bus)

-

2.0

-

2.4

I_OH= −1 mA

(other outputs)

-

I_OH= −800 µA

(data bus)

1.85

I_OH= −400 µA

-

(other outputs)

I_LIL

LOW-level input leakage current

clock leakage current

-

±10

±30

3.5

50

1.0

5

-

±10

±30

4.5

50

1.5

5

-

±10 µA

±30 µA

4.5 mA

I_L(clk)

I_CC(AV)

-

average supply current

-

[2]

I_CC(sleep)sleep mode supply current

-

50

µA

I_CC(lp)

C_i

low-power mode supply current

input capacitance

-

1.5 mA

5

-

pF

R_pu(int)

internal pull-up resistance

500

-

500

-

500

kΩ

[1] Except for XTAL2, V_OL= 1 V typically.

[2] Sleep current might be higher if there is activity on the UART data bus during Sleep mode.

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

27 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

10. Dynamic characteristics

Table 26. Dynamic characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC= ± 10 %, unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

t_w1

clock pulse duration

15

-

13

-

10

-

ns

MHz

ns

t_w2

clock pulse duration

frequency on pin XTAL1

address strobe width

address set-up time

address hold time

-

[1]

f_XTAL1

t_4w

16

32

-

48

-

45

5

-

35

5

25

1

t_5s

-

t_5h

5

-

5

-

5

-

t_6s

chip select set-up time to AS

address hold time

10

0

-

5

-

0

-

t_6h

-

0

-

0

-

[2]

t_6s'

address set-up time

chip select hold time

IOR delay from chip select

IOR strobe width

10

0

-

10

0

-

5

-

t_6h

-

0

-

t_7d

10

77

0

-

10

26

0

-

10

23

0

-

t_7w

25 pF load

-

t_7h

chip select hold time from IOR

address hold time

-

[2]

t_7h'

t_8d

5

-

5

-

5

-

IOR delay from address

read cycle delay

10

20

-

10

20

-

10

20

-

t_9d

25 pF load

-

t_11d

t_12d

t_12h

t_13d

t_13w

t_13h

t_14d

t_15d

t_16s

t_16h

t_17d

t_18d

IOR to DDIS delay

100

35

26

15

-

30

23

15

-

delay from IOR to data

data disable time

-

77

-

15

-

IOW delay from chip select

IOW strobe width

10

20

0

-

10

20

0

10

15

0

-

chip select hold time from IOW

IOW delay from address

write cycle delay

-

10

25

20

15

-

10

25

20

5

-

10

20

15

5

-

data set-up time

-

data hold time

-

delay from IOW to output

25 pF load

100

-

33

24

-

29

23

delay to set interrupt from

Modem input

-

t_19d

delay to reset interrupt from

IOR

25 pF load

-

100

-

24

-

23

ns

[3]

t_20d

t_21d

delay from stop to set interrupt

-

1T_RCLK

100

-

1T_RCLK

29

-

1T_RCLK

28

s

delay from IOR to reset

interrupt

ns

t_22d

t_23d

delay from start to set interrupt

-

100

-

45

-

40

ns

s

delay from IOW to transmit

start

8T_RCLK24T_RCLK8T_RCLK24T_RCLK8T_RCLK24T_RCLK

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

28 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 26. Dynamic characteristics …continued

T_amb= −40 °C to +85 °C; tolerance of V_CC= ± 10 %, unless otherwise speciﬁed.

Symbol Parameter Conditions V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

t_24d

delay from IOW to reset

-

100

-

45

-

40

ns

interrupt

[3]

t_25d

t_26d

delay from stop to set RXRDY

-

1T_RCLK

100

-

1T_RCLK

45

-

1T_RCLK

40

s

delay from IOR to reset

RXRDY

ns

t_27d

t_28d

delay from IOW to set TXRDY

-

100

-

45

-

40

ns

s

[3]

[4]

delay from start to reset

TXRDY

8T_RCLK

t_RESET

N

Reset pulse width

baud rate divisor

100

1

-

40

1

-

40

1

-

ns

2¹⁶− 1

[1] Applies to external clock, crystal oscillator max 24 MHz.

[2] Applicable only when AS is tied LOW.

[3] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

[4] Reset pulse must happen when these signals are inactive: CS, CS2, CS1, CS0, IOR, IOR, IOW, IOW.

10.1 Timing diagrams

t

4w

AS

t

5h

5s

valid

address

A0 to A2

t

6s

6h

CS2

CS1, CS0

valid

t

7h

7d

t

7w

t

9d

8d

active

IOR, IOR

t

11d

t

11h

active

DDIS

t

12h

12d

D0 to D7

data

002aaa331

Fig 7. General read timing when using AS signal

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

29 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

t

4w

AS

t

5h

5s

valid

address

A0 to A2

t

6s

6h

CS2

CS1, CS0

valid

t

13d

13h

t

13w

t

15d

14d

active

IOW, IOW

D0 to D7

t

16h

16s

data

002aaa332

Fig 8. General write timing when using AS signal

valid

A0 to A2

address

t

7h'

t

6s'

7h'

7w

CS

active

t

9d

7w

active

IOR

t

12h

t

12h

12d

D0 to D7

data

002aaa333

Fig 9. General read timing when AS is tied to GND

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

30 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

valid

address

valid

address

A0 to A2

t

7h'

t

6s'

7h'

active

CS

IOW

t

13w

15d

active

t

16h

t

16h

16s

data

D0 to D7

002aaa334

Fig 10. General write timing when AS is tied to GND

active

IOW

t

17d

RTS

DTR

change of state

DCD

CTS

DSR

change of state

t

18d

INT

active

t

19d

active

IOR

t

18d

change of state

RI

002aaa111

Fig 11. Modem input/output timing

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

31 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

t

w1

w2

EXTERNAL

CLOCK

002aaa112

t

w3

1

t_w3

f _XTAL1

=

-------

Fig 12. External clock timing

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

RX

D0

D1

D2

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

20d

active

INT

t

21d

active

IOR

16 baud rate clock

002aaa113

Fig 13. Receive timing

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

32 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RX

t

25d

active data

ready

RXRDY

IOR

t

26d

active

002aaa114

Fig 14. Receive ready timing in non-FIFO mode

start

bit

parity stop

bit bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RX

first byte that

reaches the

trigger level

t

25d

active data

ready

RXRDY

IOR

t

26d

active

002aaa115

Fig 15. Receive ready timing in FIFO mode

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

33 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

start

bit

parity stop start

bit

data bits (0 to 7)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

active

INT

transmitter ready

t

22d

t

24d

t

23d

active

IOW

active

16 baud rate clock

002aaa116

Fig 16. Transmit timing

start

bit

parity stop start

bit bit

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TX

IOW

active

transmitter ready

D0 to D7

byte #1

t

28d

t

27d

TXRDY

active

transmitter

not ready

002aaa129

Fig 17. Transmit ready timing in non-FIFO mode

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

34 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

start

bit

parity stop

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TX

5 data bits

6 data bits

7 data bits

IOW

active

t

28d

byte #16

or byte #64

D0 to D7

t

27d

TXRDY

FIFO full

002aaa118

Fig 18. Transmit ready timing in FIFO mode (DMA mode ‘1’)

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

35 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

11. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

e

D

E

y

X

A

39

29

b

p

Z

E

28

40

b

1

w

M

44

1

H

E

pin 1 index

A

1

A

4

e

(A )

3

6

18

β

L

p

k

detail X

7

17

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

A

Z

E

4

1

(1)

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

3

1

D

E

D

E

p

max.

min.

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22 1.44

14.99 14.99 17.40 17.40 1.07 1.02

0.53

0.33

0.51 0.25 3.05

0.02 0.01 0.12

1.27

0.05

0.18 0.18

0.1

2.16 2.16

o

45

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.63 0.63 0.695 0.695 0.048 0.057

0.59 0.59 0.685 0.685 0.042 0.040

0.021

0.013

inches

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

01-11-14

SOT187-2

112E10

MS-018

EDR-7319

Fig 19. Package outline SOT187-2 (PLCC44)

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

36 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w

9

16

L

17

8

e

E

h

2

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 20. Package outline SOT617-1 (HVQFN32)

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

37 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 21. Package outline SOT314-2 (LQFP64)

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

38 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

39 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 22) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 27 and 28

Table 27. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 28. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 22.

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

40 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 22. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

13. Abbreviations

Table 29. Abbreviations

Acronym

CMOS

CPU

Description

Complementary Metal Oxide Semiconductor

Central Processing Unit

DLL

Divisor Latch LSB

DLM

Divisor Latch MSB

DMA

FIFO

ISDN

LSB

Direct Memory Access

First In, First Out

Integrated Service Digital Network

Least Signiﬁcant Bit

MSB

Most Signiﬁcant Bit

TTL

Transistor-Transistor Logic

Universal Asynchronous Receiver and Transmitter

UART

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

41 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

14. Revision history

Table 30. Revision history

Document ID

SC16C750B_5

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20081017

Product data sheet

-

SC16C750B_4

• The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 2 “Features”, 3^rdbullet item re-written; added Footnote 1

• Figure 3 “Pin conﬁguration for HVQFN32”: corrected pin 7 signal name from “CS2” to “CS”

• Table 2 “Pin description”, description of RI: changed from “... has transitioned from a LOW to a

HIGH ...” to “... has changed from a LOW to a HIGH ...”

• Table 24 “Limiting values”:

–

symbol V_nsplit to show 2 separate conditions: “at D7 to D0 pins” and “at input only pins”

• Table 25 “Static characteristics”:

–

Symbol/parameter changed from “V_IL(CK), LOW-level clock input voltage” to “V_IL(clk), clock

LOW-level input voltage”

Symbol/parameter changed from “V_IH(CK), HIGH-level clock input voltage” to “V_IH(clk), clock

HIGH-level input voltage”

–

Symbol changed from “I_CL” to “I_L(clk)

”

Table note [1]: changed from “Except for x₂, ...” to “Except for XTAL2, ...”

• Table 26 “Dynamic characteristics”:

–

Symbol “t_w2, t_2w” changed to 2 separate symbols, “t_w1” and “t_w2

”

–

Table note [4]: added “CS” to list of signals which must be inactive when reset pulse happens

• Updated soldering information

SC16C750B_4

20060825

Product data sheet

-

SC16C750B-03

SC16C750B-02

SC16C750B-03

(9397 750 14453)

20041213

Product data

SC16C750B-02

(9397 750 13318)

20040527

20040329

-

SC16C750B-01

-

SC16C750B-01

(9397 750 11969)

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

42 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

SC16C750B_5

Product data sheet

Rev. 05 — 17 October 2008

43 of 44

SC16C750B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

12.4

13

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 40

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41

Revision history . . . . . . . . . . . . . . . . . . . . . . . 42

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

14

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 43

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43

15.1

15.2

15.3

15.4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6

Functional description . . . . . . . . . . . . . . . . . . . 8

Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 9

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 10

Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 10

Time-out interrupts . . . . . . . . . . . . . . . . . . . . . 10

Programmable baud rate generator . . . . . . . . 11

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 12

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Low power mode . . . . . . . . . . . . . . . . . . . . . . 13

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 13

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 43

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 15

Transmit Holding Register (THR) and

Receive Holding Register (RHR) . . . . . . . . . . 16

Interrupt Enable Register (IER) . . . . . . . . . . . 16

IER versus Receive FIFO interrupt mode

7.2

7.2.1

operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

IER versus Receive/Transmit FIFO polled

7.2.2

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 17

FIFO Control Register (FCR) . . . . . . . . . . . . . 18

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Mode 0 (FCR bit 3 = 0). . . . . . . . . . . . . . . . . . 18

Mode 1 (FCR bit 3 = 1). . . . . . . . . . . . . . . . . . 18

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Interrupt Status Register (ISR) . . . . . . . . . . . . 20

Line Control Register (LCR) . . . . . . . . . . . . . . 21

Modem Control Register (MCR) . . . . . . . . . . . 23

Line Status Register (LSR). . . . . . . . . . . . . . . 24

Modem Status Register (MSR). . . . . . . . . . . . 25

Scratchpad Register (SPR) . . . . . . . . . . . . . . 26

SC16C750B external reset conditions . . . . . . 26

7.3

7.3.1

7.3.1.1

7.3.1.2

7.3.2

7.4

7.5

7.6

7.7

7.8

7.9

7.10

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26

Static characteristics. . . . . . . . . . . . . . . . . . . . 27

Dynamic characteristics . . . . . . . . . . . . . . . . . 28

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 29

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 36

9

10

10.1

11

12

Soldering of SMD packages . . . . . . . . . . . . . . 39

Introduction to soldering . . . . . . . . . . . . . . . . . 39

Wave and reﬂow soldering . . . . . . . . . . . . . . . 39

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1

12.2

12.3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 17 October 2008

Document identifier: SC16C750B_5


型号：	SC16C750BIA44,529
厂家：	NXP
描述：	SC16C750B - 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs LCC 44-Pin 先进先出芯片
文件：	总44页 (文件大小：212K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC16C750BIA44,529 [NXP]

相关型号：

SC16C750BIA44-S

SC16C750BIA44-T

SC16C750BIB64

SC16C750BIB64,128

SC16C750BIB64,151

SC16C750BIB64-F

SC16C750BIB64-S

SC16C750BIBS

SC16C750BIBS,118

SC16C750BIBS,128

SC16C750BIBS,157

SC16C750BIBS-F