SC16C850IET-S_技术文档

SC16C850

2.5 V to 3.3 V UART, 5 Mbit/s (max.) with 128-byte FIFOs,

infrared (IrDA), and 16 mode or 68 mode parallel bus interface

Rev. 01 — 10 January 2008

Product data sheet

1. General description

The SC16C850 is a 2.5 V to 3.3 V, low power, single channel Universal Asynchronous

Receiver and Transmitter (UART) used for serial data communications. Its principal

function is to convert parallel data into serial data and vice versa. The UART can handle

serial data rates up to 5 Mbit/s. The SC16C850 is functionally (software) compatible with

the SC16C650B. SC16C850 can be programmed to operate in extended mode (see

Section 6.2) where additional advanced UART features are available. The SC16C850

UART provides enhanced UART functions with 128-byte FIFOs, modem control interface,

and IrDA encoder/decoder. On-board status registers provide the user with error

indications and operational status. System interrupts and modem control features may be

tailored by software to meet speciﬁc user requirements. An internal loopback capability

allows on-board diagnostics.

The SC16C850IBS with Intel (16 mode) or Motorola (68 mode) bus host interface

operates at 2.5 V to 3.3 V and is available in a very small (Micro-UART) HVQFN32

package.

The SC16C850IET with Intel (16 mode) bus host interface operates at 2.5 V to 3.3 V and

is available in a very small TFBGA36 package.

2. Features

I Single channel high performance UART

I Intel or Motorola bus interface selectable using 16/68 pin

I 2.5 V to 3.3 V operation

I Up to 5 Mbit/s data rate

I 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

I 128-byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the

external CPU

I 128 programmable Receive and Transmit FIFO interrupt trigger levels

I 128 Receive and Transmit FIFO reporting levels (level counters)

I Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) ﬂow control

I Industrial temperature range (−40 °C to +85 °C)

I 128 hardware and software trigger levels

I Automatic 9-bit mode (RS-485) address detection

I Automatic RS-485 driver turn-around with programmable delay

I UART software reset

I High resolution clock prescaler, from 0 to 15 with granularity of ¹⁄₁₆to allow

non-standard UART clock to be used

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

I Programmable Xon/Xoff characters

I Software selectable baud rate generator

I Support IrDA version 1.0 (up to 115.2 kbit/s)

I Standard modem interface or infrared IrDA encoder/decoder interface

I Enhanced Sleep mode and low power feature

I Modem control functions (CTS, RTS, DSR, DTR, RI, CD)

I Independent transmitter and receiver enable/disable

I Pb-free, RoHS compliant package offered

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

SC16C850IBS

SC16C850IET

HVQFN32 plastic thermal enhanced very thin quad ﬂat package; SOT617-1

no leads; 32 terminals; body 5 × 5 × 0.85 mm

TFBGA36 plastic thin ﬁne-pitch ball grid array package; 36 balls; SOT912-1

body 3.5 × 3.5 × 0.8 mm

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

2 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

4. Block diagram

SC16C850

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTER

D0 to D7

IOR

DATA BUS

AND

IOW

RESET

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RX

REGISTER

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0 to A2

CS

POWER-DOWN

CONTROL

LOWPWR

DTR

RTS

MODEM

CONTROL

LOGIC

CTS

RI

CD

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

INT

DSR

002aad020

XTAL1

XTAL2

Fig 1. Block diagram of SC16C850 (16 mode)

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

3 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

SC16C850

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTER

DATA BUS

AND

D0 to D7

R/W

RESET

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RX

REGISTER

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0 to A2

CS

POWER-DOWN

CONTROL

LOWPWR

DTR

RTS

MODEM

CONTROL

LOGIC

CTS

RI

CD

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

IRQ

DSR

002aad021

XTAL1

XTAL2

Fig 2. Block diagram of SC16C850 (68 mode)

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

4 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

5. Pinning information

5.1 Pinning

ball A1

index area

SC16C850IET

1

2

3

4

5

6

A

B

C

D

E

F

002aad022

Transparent top view

Fig 3. Pin conﬁguration for TFBGA36

1

2

3

4

5

6

A

B

C

D

E

F

V

n.c.

IOR

n.c.

XTAL2

XTAL1

DD

A2

n.c.

A1

IOW

LOWPWR

CS

RX

D6

D5

A0

INT

V

TX

D7

D3

D2

SS

DD

RTS

n.c.

CTS

CD

RI

V

DTR

D1

D0

RESET

DSR

D4

002aad023

Transparent top view.

Fig 4. Ball mapping for TFBGA36

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

5 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

terminal 1

index area

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

D4

16

CTS

RESET

DTR

RTS

INT

D4

68

CTS

RESET

DTR

RTS

IRQ

A0

D5

D6

D7

RX

TX

CS

D5

D6

D7

RX

TX

CS

SC16C850IBS

(16 mode)

(68 mode)

A0

A1

A2

002aad024

002aad025

Transparent top view

a. 16 mode

Fig 5. Pin conﬁguration for HVQFN32

b. 68 mode

5.2 Pin description

Table 2.

Symbol

Pin description

Type Description

TFBGA36 HVQFN32

16/68

-

2

I

Bus select. Intel or Motorola bus select.

When 16/68 pin is at logic 1 or left unconnected (internally pulled-up) the

device will operate in Intel bus (16 mode) type of interface.

When 16/68 pin is at logic 0, the device will operate in Motorola bus (68 mode)

type of interface.

A0

A1

A2

CD

C1

C3

B1

E3

19

18

17

26

I

Address 0 select bit. Internal register address selection.

Address 1 select bit. Internal register address selection.

Address 2 select bit. Internal register address selection.

Carrier Detect (active LOW). A logic 0 on this pin indicates that a carrier has

been detected by the modem. Status can be tested by reading MSR[7].

CS

B6

D3

8

I

Chip Select (active LOW). In 16 mode or 68 mode, this input is chip select for

the UART.

CTS

24

Clear to Send (active LOW). A logic 0 on the CTS pin indicates the modem

or data set is ready to accept transmit data from the SC16C850. Status can be

tested by reading MSR[4].

DSR

DTR

F2

E1

25

22

I

Data Set Ready (active LOW). A logic 0 on this pin indicates the modem or

data set is powered-on and is ready for data exchange with the UART. Status

can be tested by reading MSR[5].

O

Data Terminal Ready (active LOW). A logic 0 on this pin indicates that the

SC16C850 is powered-on and ready. This pin can be controlled via the

modem control register. Writing a logic 1 to MCR[0] will set the DTR output to

logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to

MCR[0], or after a reset.

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

6 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Table 2.

Symbol

Pin description …continued

Type Description

TFBGA36 HVQFN32

D0

F4

E4

F5

E5

F6

E6

D6

D5

-

29

30

31

32

1

I/O

O

Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least

signiﬁcant bit and the ﬁrst data bit in a transmit or receive serial data stream.

D1

D2

D3

D4

D5

3

D6

4

D7

5

INT

(IRQ)

20

When 16/68 pin is at logic 1 or unconnected, this output becomes active HIGH

interrupt output. The output state is deﬁned by the user through the software

setting of MCR[5]. INT is set to the active mode when MCR[5] is set to a

logic 1. INT is set to the open-source mode when MCR[5] is set to a logic 0.

When 16/68 pin is at logic 0, this output becomes device interrupt output

(active LOW, open-drain). An external pull-up resistor to V_DDis required.

INT

D1

-

O

I

Interrupt output (active HIGH). The output state is deﬁned by the user

through the software setting of MCR[5]. INT is set to the active mode when

MCR[5] is set to a logic 1. INT is set to the open-source mode when MCR[5] is

set to a logic 0.

IOR

14

When 16/68 pin is at logic 1, this input becomes the read strobe (active LOW).

When 16/68 pin is at logic 0, this input pin is not used and should be

(V_DD

)

connected to V_DD

.

IOR

A3

-

I

Read strobe (active LOW).

IOW

12

When 16/68 pin is at logic 1 or unconnected, this input becomes the write

strobe (active LOW).

(R/W)

When 16/68 pin is at logic 0, this input becomes read strobe when it is at logic

HIGH, and write strobe when it is at logic LOW.

IOW

B4

-

I

Write strobe (active LOW).

LOWPWR B5

9

Low Power. When asserted (active HIGH), the device immediately goes into

low power mode. The oscillator is shut-off and some host interface pins are

isolated from the host’s bus to reduce power consumption. The device only

returns to normal mode when the LOWPWR pin is de-asserted. On the

negative edge of a de-asserting LOWPWR signal, the device is automatically

reset and all registers return to their default reset states. This pin has an

internal pull-down resistor, therefore, it can be left unconnected (refer to

Section 6.12 “Low power feature”).

RESET

-

23

I

Master Reset. When 16/68 pin is at logic 1 or unconnected, this input

becomes the RESET pin (active HIGH).

(RESET)

When 16/68 pin is at logic LOW, this input pin becomes RESET (active LOW).

(See Section 7.23 “SC16C850 external reset condition and software reset” for

initialization details.)

RESET

RI

F1

F3

-

I

Reset input (active HIGH). See Section 7.23 “SC16C850 external reset

condition and software reset” for initialization details.

27

Ring Indicator (active LOW). A logic 0 on this pin indicates the modem has

received a ringing signal from the telephone line. A logic 1 transition on this

input pin will generate an interrupt if modem status interrupt is enabled. Status

can be tested by reading MCR[6].

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

7 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Table 2.

Symbol

Pin description …continued

Type Description

TFBGA36 HVQFN32

RTS

RX

D2

C6

C5

21

6

O

I

Request to Send (active LOW). A logic 0 on the RTS pin indicates the

transmitter has data ready and waiting to send. Writing a logic 1 in the modem

control register MCR[1] will set this pin to a logic 0, indicating data is available.

After a reset this pin will be set to a logic 1.

UART receive data. The RX signal will be a logic 1 during reset, idle (no

data), or when not receiving data. During the local loopback mode, the RX

input pin is disabled and TX data is connected to the UART RX input,

internally.

TX

7

O

UART transmit data. The TX signal will be a logic 1 during reset, idle (no

data), or when the transmitter is disabled. During the local loopback mode, the

TX output pin is disabled and TX data is internally connected to the UART RX

input.

V_DD

A1, D4

C2, C4

A6

28

13^[1]

I

Power supply input.

V_SS

Signal and power ground.

XTAL1

10

Crystal or external clock input. Functions as a crystal input or as an

external clock input. A crystal can be connected between this pin and XTAL2

to form an internal oscillator circuit. Alternatively, an external clock can be

connected to this pin to provide custom data rates (see Section 6.9

“Programmable baud rate generator”). See Figure 8.

XTAL2

A5

11

O

Output of the crystal oscillator or buffered clock. (See also XTAL1.)

Crystal oscillator output or buffered clock output. Should be left open if an

external clock is connected to XTAL1.

[1] HVQFN package die supply ground is connected to both V_SSpin and exposed center pad. V_SSpin must be connected to supply ground

for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to

the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be

incorporated in the PCB in the thermal pad region.

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

8 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

6. Functional description

The SC16C850 provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is ensured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex, especially

when manufactured on a single integrated silicon chip. The SC16C850 represents such

an integration with greatly enhanced features. The SC16C850 is fabricated with an

advanced CMOS process.

The SC16C850 is an upward solution to the SC16C650B that provides a single UART

capability with 128 bytes of transmit and receive FIFO memory, instead of 32 bytes for the

SC16C650B and 16 bytes in the SC16C550B. The SC16C850 is designed to work with

high speed modems and shared network environments that require fast data processing

time. Increased performance is realized in the SC16C850 by the transmit and receive

FIFOs. This allows the external processor to handle more networking tasks within a given

time. In addition, the four selectable receive and transmit FIFO trigger interrupt levels are

provided in 16C650 mode, or 128 programmable levels are provided in the extended

mode for maximum data throughput performance especially when operating in a

multi-channel environment (see Section 6.2 “Extended mode (128-byte FIFO)”). The FIFO

memory greatly reduces the bandwidth requirement of the external controlling CPU and

increases performance. A low power pin (LOWPWR) is provided to further reduce power

consumption by isolating the host bus interface.

The SC16C850 is capable of operation up to 5 Mbit/s with an external 80 MHz clock. With

a crystal, the SC16C850 is capable of operation up to 1.5 Mbit/s.

The rich feature set of the SC16C850 is available through internal registers. These

features are: selectable and programmable receive and transmit FIFO trigger levels,

selectable TX and RX baud rates, and modem interface controls, and are all standard

features. Following a power-on reset, an external reset, or a software reset, the

SC16C850 is software compatible with the previous generation, SC16C550B, and

SC16C650B.

6.1 UART selection

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC16C850 package, and an external serial device. A

logic 0 (LOW) on chip select pin CS allows the user to conﬁgure, send data, and/or

receive data via the UART. Refer to Table 3 and Table 4.

Table 3.

Serial port selection (Intel interface)

H = HIGH; L = LOW.

Chip Select

CS = H

Function

none

CS = L

UART select

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

9 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Table 4.

Serial port selection (Motorola interface)

H = HIGH; L = LOW.

Chip Select

CS = H

Function

none

CS = L

UART select

6.2 Extended mode (128-byte FIFO)

The device is in the extended mode when any of these four registers contains any value

other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL.

6.3 Internal registers

The SC16C850 provides a set of 25 internal registers for monitoring and controlling the

functions of the UART. These registers are shown in Table 5.

Table 5.

A2 A1 A0 Read mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, EFCR, SPR)^[1]

Internal registers decoding

Write mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

Extra Feature Control Register (EFCR)

n/a

Modem Status Register

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

LSB of Divisor Latch

MSB of Divisor Latch

0

1

MSB of Divisor Latch

Second special register set (TXLVLCNT/RXLVLCNT)^[3]

0

1

Transmit FIFO Level Count

n/a

1

0

Receive FIFO Level Count

Enhanced feature register set (EFR, Xon1/Xon2, Xoff1/Xoff2)^[4]

0

1

0

1

0

1

0

1

Enhanced Feature Register

Xon1 word

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)^[5]

0

1

0

1

0

1

Transmit FIFO Interrupt Level

Receive FIFO Interrupt Level

Flow Control Count High

Flow Control Count Low

Transmit FIFO Interrupt Level

Receive FIFO Interrupt Level

Flow Control Count High

Flow Control Count Low

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

10 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Table 5.

Internal registers decoding …continued

A2 A1 A0 Read mode

Write mode

Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1)^[6]

0

1

0

1

0

1

Clock Prescaler

RS-485 turn-around Timer

Additional Feature Control Register 2 Additional Feature Control Register 2

Additional Feature Control Register 1 Additional Feature Control Register 1

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

[3] Second Special registers are accessible only when EFCR[0] = 1.

[4] Enhanced Feature Registers are only accessible when LCR = 0xBF.

[5] First Extra Feature Registers are only accessible when EFCR[2:1] = 01b.

[6] Second Extra Feature Registers are only accessible when EFCR[2:1] = 10b.

6.4 FIFO operation

6.4.1 32-byte FIFO mode

When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the

‘ﬁrst extra feature register set’ are empty (0x00) the transmit and receive trigger levels are

set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward

compatible to the SC16C650B (see Table 6), and the FIFO sizes are 32 entries. The

transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]).

It should be noted that the user can set the transmit trigger levels by writing to the FCR,

but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section

includes a time-out function to ensure data is delivered to the external CPU (see

Section 6.8). Please refer to Table 11 and Table 12 for the setting of FCR[7:4].

Table 6.

Interrupt trigger level and ﬂow control mechanism

FCR[7:6] FCR[5:4] INT pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

RX

8

TX

16

8

00

01

10

11

00

01

10

11

8

0

16

24

28

16

24

28

7

24

30

15

23

6.4.2 128-byte FIFO mode

When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘ﬁrst extra feature

register set’ contains any value other than 0x00, the transmit and receive trigger levels are

set by TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the

transmit FIFO, and the transmit trigger levels can be set to any value between 1 and 128

with granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive

trigger levels can be set to any value between 1 and 128 with granularity of 1.

When the effective FIFO size changes (that is, when FCR[0] toggles or when the

combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between

equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will

be lost).

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

11 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

6.5 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C850 monitors the CTS pin

for a remote buffer overﬂow indication and controls the RTS pin for local buffer overﬂows.

Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to

a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a ﬂow control request,

ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C850 will suspend TX

transmissions as soon as the stop bit of the character in process is shifted out.

Transmission is resumed after the CTS input returns to a logic 0, indicating more data may

be sent.

When AFCR1[2] is set to logic 1 then the function of CTS pin is mapped to the DSR pin,

and the function of RTS is mapped to DTR pin. DSR and DTR pins will behave as

described above for CTS and RTS.

With the automatic hardware ﬂow control function enabled, an interrupt is generated when

the receive FIFO reaches the programmed trigger level. The RTS (or DTR) pin will not be

forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level.

However, the RTS (or DTR) pin will return to a logic 0 after the receive buffer (FIFO) is

unloaded to the next trigger level below the programmed trigger level. Under the above

described conditions, the SC16C850 will continue to accept data until the receive FIFO is

full.

When the TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the ‘ﬁrst extra feature

register set’ are all zeroes, the hardware and software ﬂow control trigger levels are set by

FCR[7:4]; see Table 6.

When the TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘ﬁrst extra feature

register set’ contain any value other than 0x00, the hardware and software ﬂow control

trigger levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines

how many bytes are in the receive FIFO before RTS (or DTR) is de-asserted or Xoff is

sent. The content in FLWCNTL determines how many bytes are in the receive FIFO

before RTS (or DTR) is asserted, or Xon is sent.

In 128-byte FIFO mode, hardware and software ﬂow control trigger levels can be set to

any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always

be greater than FLWCNTL. The UART does not check for this condition automatically, and

if this condition is not met, spurious operation of the device might occur. When using

FLWCNTH and FLWCNTL, these registers must be initialized to proper values before

hardware or software ﬂow control is enabled via the EFR register.

6.6 Software ﬂow control

When software ﬂow control is enabled, the SC16C850 compares one or two sequentially

received data characters with the programmed Xon or Xoff character value(s). If the

received character(s) match the programmed Xoff values, the SC16C850 will halt

transmission (TX) as soon as the current character(s) has completed transmission. When

a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if

receive interrupt is enabled) will be activated. Following a suspension due to a match of

the Xoff characters’ values, the SC16C850 will monitor the receive data stream for a

match to the Xon1/Xon2 character value(s). If a match is found, the SC16C850 will

resume operation and clear the ﬂags (ISR[4]).

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

12 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow control.

Different conditions can be set to detect Xon/Xoff characters and suspend/resume

transmissions (see Table 24). When double 8-bit Xon/Xoff characters are selected, the

SC16C850 compares two consecutive receive characters with two software ﬂow control

8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under

the above described ﬂow control mechanisms, ﬂow control characters are not placed

(stacked) in the receive FIFO. When using software ﬂow control, the Xon/Xoff characters

cannot be used for data transfer.

In the event that the receive buffer is overﬁlling, the SC16C850 automatically sends an

Xoff character (when enabled) via the serial TX output to the remote UART. The

SC16C850 sends the Xoff1/Xoff2 characters as soon as the number of received data in

the receive FIFO passes the programmed trigger level. To clear this condition, the

SC16C850 will transmit the programmed Xon1/Xon2 characters as soon as the number of

characters in the receive FIFO drops below the programmed trigger level.

6.7 Special character detect

A special character detect feature is provided to detect an 8-bit character when EFR[5] is

set. When an 8-bit character is detected, it will be placed on the user-accessible data

stack along with normal incoming RX data. This condition is selected in conjunction with

EFR[3:0] (see Table 24). Note that software ﬂow control should be turned off when using

this special mode by setting EFR[3:0] to all zeroes.

The SC16C850 compares each incoming receive character with Xoff2 data. If a match

occurs, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate

detection of a special character. Although Table 8 “SC16C850 internal registers” shows

Xon1, Xon2, Xoff1, Xoff2 with eight bits of character information, the actual number of bits

is dependent on the programmed word length. Line Control Register bits LCR[1:0] deﬁne

the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length

selected by LCR[1:0] also determines the number of bits that will be used for the special

character comparison. Bit 0 in Xon1, Xon2, Xoff1, Xoff2 corresponds with the LSB bit for

the received character.

6.8 Interrupt priority and time-out interrupts

The interrupts are enabled by IER[7:0]. Care must be taken when handling these

interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C850

will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to

continuing operations. The ISR indicates the current singular highest priority interrupt

only. A condition can exist where a higher priority interrupt masks the lower priority

interrupt(s) (see Table 13). Only after servicing the higher pending interrupt will the lower

priority interrupt(s) be reﬂected in the status register. Servicing the interrupt without

investigating further interrupt conditions can result in data errors.

Receive Data Ready and Receive Time-Out have the same interrupt priority (when

enabled by IER[0]), and it is important to serve these interrupts correctly. The receiver

issues an interrupt after the number of characters have reached the programmed trigger

level. In this case, the SC16C850 FIFO may hold more characters than the programmed

trigger level. Following the removal of a data byte, the user should re-check LSR[0] to see

if there are any additional characters. A Receive Time-Out will not occur if the receive

FIFO is empty. The time-out counter is reset at the center of each stop bit received or

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each time the Receive Holding Register (RHR) is read. The actual time-out value is

4 character time, including data information length, start bit, parity bit, and the size of stop

bit, that is, 1×, 1.5×, or 2× bit times.

6.9 Programmable baud rate generator

The SC16C850 UART contains a programmable rational baud rate generator that takes

any clock input and divides it by a divisor in the range between 1 and (2¹⁶− 1). The

SC16C850 offers the capability of dividing the input frequency by rational divisor. The

fractional part of the divisor is controlled by the CLKPRES register in the ‘ﬁrst extra feature

register set’.

f _XTAL1

baud rate =

(1)

-------------------------------------------------------------------

M

MCR[7] × 16 × N +

-----

16

where:

N is the integer part of the divisor in DLL and DLM registers;

M is the fractional part of the divisor in CLKPRES register;

f_XTAL1is the clock frequency at XTAL1 pin.

Prescaler = 1 when MCR[7] is set to 0.

Prescaler = 4 when MCR[7] is set to 1.

CLKPRES

[3:0]

DIVIDE-BY-1

DIVIDE-BY-4

MCR[7] = 0

MCR[7] = 1

XTAL1

XTAL2

BAUD RATE

GENERATOR

(DLL, DLM)

transmitter and

receiver clock

OSCILLATOR

002aac645

Fig 6. Prescalers and baud rate generator block diagram

A single baud rate generator is provided for the transmitter and receiver. The

programmable Baud Rate Generator is capable of operating with a frequency of up to

80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock

input. The SC16C850 can be conﬁgured for internal or external clock operation. For

internal clock operation, an industry standard crystal is connected externally between the

XTAL1 and XTAL2 pins (see Figure 7). Alternatively, an external clock can be connected

to the XTAL1 pin (see Figure 8) to clock the internal baud rate generator for standard or

custom rates (see Table 7).

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). The

SC16C850 divides the basic external clock by 16. The baud rate is conﬁgured via the

CLKPRES, DLL and DLM internal register functions. Customized baud rates can be

achieved by selecting the proper divisor values for the MSB and LSB sections of the baud

rate generator.

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Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB)

provides a user capability for selecting the desired ﬁnal baud rate. The example in Table 7

shows the selectable baud rate table available when using a 1.8432 MHz external clock

input when MCR[7] = 0, and CLKPRES = 0x00.

XTAL1

XTAL2

XTAL1

XTAL2

1.5 kΩ

X1

1.8432 MHz

C1

22 pF

C2

33 pF

C1

22 pF

C2

47 pF

002aaa870

Fig 7. Crystal oscillator connection

XTAL1

XTAL2

100 pF

f

XTAL1

002aac630

If f_XTAL1frequency is greater than 50 MHz, then a DC blocking capacitor is required.

XTAL2 pin should be left unconnected when an external clock is used.

Fig 8. External clock connection

Table 7.

Baud rate generator programming table using a 1.8432 MHz clock when

MCR[7] = 0 and CLKPRES[3:0] = 0

Output

baud rate

(bit/s)

Output

16× clock divisor

(decimal)

Output

16× clock divisor

(hexadecimal)

DLM

program value

(hexadecimal)

DLL

program value

(hexadecimal)

50

2304

1536

1047

768

384

192

96

900

600

417

300

180

C0

60

09

06

04

03

01

00

17

00

80

C0

60

30

20

18

10

0C

06

75

110

150

300

600

1.2 k

2.4 k

3.6 k

4.8 k

7.2 k

9.6 k

19.2 k

48

30

32

20

24

18

16

10

12

0C

06

6

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Table 7.

Baud rate generator programming table using a 1.8432 MHz clock when

MCR[7] = 0 and CLKPRES[3:0] = 0 …continued

Output

baud rate

(bit/s)

Output

16× clock divisor

(decimal)

Output

16× clock divisor

(hexadecimal)

DLM

program value

(hexadecimal)

DLL

program value

(hexadecimal)

38.4 k

57.6 k

115.2 k

3

2

1

03

02

01

00

03

02

01

6.10 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally

(see Figure 9). MCR[3:0] register bits are used for controlling loopback diagnostic testing.

In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are

disconnected from their associated interface pins, and instead are connected together

internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control

input pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2]

(OP1). Loopback test data is entered into the transmit holding register via the user data

bus interface, D[7:0]. The transmit UART serializes the data and passes the serial data to

the receive UART via the internal loopback connection. The receive UART converts the

serial data back into parallel data that is then made available at the user data interface

D[7:0]. The user optionally compares the received data to the initial transmitted data for

verifying error-free operation of the UART TX/RX circuits.

In this mode, the interrupt pin is 3-stated, therefore, the software must use the polling

method (see Section 7.2.2) to send and receive data.

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SC16C850

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTERS

REGISTER

DATA BUS

D0 to D7

IOR

IOW

RESET

AND

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

REGISTERS

RECEIVE

SHIFT

REGISTER

RX

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

A0 to A2

CS

RTS

CTS

DTR

POWER-

DOWN

CONTROL

LOWPWR

MODEM

CONTROL

LOGIC

DSR

RI

OP1

OP2

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

INT

(IRQ)

CD

002aad026

XTAL1 XTAL2

Fig 9. Internal Loopback mode diagram

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6.11 Sleep mode

Sleep mode is an enhanced feature of the SC16C850 UART. It is enabled when EFR[4],

the enhanced functions bit, is set and when IER[4] bit is set.

6.11.1 Conditions to enter Sleep mode

Sleep mode is entered when:

• Modem input pins are not toggling.

• The serial data input line, RX, is idle for 4 character time (logic HIGH) and AFCR1[4]

is logic 0. When AFCR1[4] is logic 1 the device will go to sleep regardless of the state

of the RX pin (see Section 7.21 for the description of AFCR1 bit 4).

• The TX FIFO and TX shift register are empty.

• There are no interrupts pending.

• The RX FIFO is empty.

In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are

clocked using these clocks, the power consumption is greatly reduced.

Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be

done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]

before writing to DLL or DLM.

6.11.2 Conditions to resume normal operation

SC16C850 resumes normal operation by any of the following:

• Receives a start bit on RX pin.

• Data is loaded into transmit FIFO.

• A change of state on any of the modem input pins

If the device is awakened by one of the conditions described above, it will return to the

Sleep mode automatically after all the conditions described in Section 6.11.1 are met. The

device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a

logic 0.

When the SC16C850 is in Sleep mode and the host data bus (D[7:0], A[2:0], IOW, IOR,

CS) remains in steady state, either HIGH or LOW, the Sleep mode supply current will be

in the µA range as speciﬁed in Table 36 “Static characteristics”. If any of these signals is

toggling or ﬂoating then the sleep current will be higher.

6.12 Low power feature

A low power feature is provided by the SC16C850 to prevent the switching of the host data

bus from inﬂuencing the sleep current. When the pin LOWPWR is activated (logic HIGH),

the device immediately and unconditionally goes into Low power mode. All clocks are

stopped and most host interface pins are isolated to reduce power consumption. The

device only returns to normal mode when the LOWPWR pin is de-asserted. The pin can

be left unconnected because it has an internal pull-down resistor.

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6.13 RS-485 features

6.13.1 Auto RS-485 RTS control

Normally the RTS pin is controlled by MCR[1], or if hardware ﬂow control is enabled, the

logic state of the RTS pin is controlled by the hardware ﬂow control circuitry. AFCR2[4] will

take the precedence over the other two modes; once this bit is set, the transmitter will

control the state of the RTS pin. The transmitter automatically asserts the RTS pin

(logic 0) once the host writes data to the transmit FIFO, and de-asserts RTS pin (logic 1)

once the last bit of the data has been transmitted.

To use the auto RS-485 RTS mode the software would have to disable the hardware

ﬂow control function.

6.13.2 RS-485 RTS inversion

AFCR2[5] reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.

When the transmitter has data to be sent it will de-asserts the RTS pin (logic 1), and when

the last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).

6.13.3 Auto 9-bit mode (RS-485)

AFCR2[0] is used to enable the 9-bit mode (Multi-drop or RS-485 mode). In this mode of

operation, a ‘master’ station transmits an address character followed by data characters

for the addressed ‘slave’ stations. The slave stations examine the received data and

interrupt the controller if the received character is an address character (parity bit = 1).

To use the automatic 9-bit mode, the software would have to disable the hardware and

software ﬂow control functions.

6.13.3.1 Normal Multi-drop mode

The 9-bit Mode in AFCR2[0] is enabled, but not Special Character Detect (EFR[5]). The

receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an

address byte is received (parity bit = 1). This address byte will cause the UART to set the

parity error. The UART will generate a line status interrupt (IER[2] must be set to ‘1’ at this

time), and at the same time puts this address byte in the RX FIFO. After the controller

examines the byte it must make a decision whether or not to enable the receiver; it should

enable the receiver if the address byte addresses its ID address, and must not enable the

receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until

being disabled by the controller after the controller has received a complete message from

the ‘master’ station. If the controller does not disable the receiver after receiving a

message from the ‘master’ station, the receiver will generate a parity error upon receiving

another address byte. The controller then determines if the address byte addresses its ID

address, if it is not, the controller then can disable the receiver. If the address byte

addresses the ‘slave’ ID address, the controller takes no further action, and the receiver

will receive the subsequent data.

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6.13.3.2 Auto address detection

If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the

address byte) the receiver will try to detect an address byte that matches the programmed

character in the Xoff2 register. If the received byte is a data byte or an address byte that

does not match the programmed character in the Xoff2 register, the receiver will discard

these data. Upon receiving an address byte that matches the Xoff2 character, the receiver

will be automatically enabled if not already enabled, and the address character is pushed

into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also

generates a line status interrupt (IER[2] must be set to ‘1’ at this time). The receiver will

then receive the subsequent data from the ‘master’ station until being disabled by the

controller after having received a message from the ‘master’ station.

If another address byte is received and this address byte does not match the Xoff2

character, the receiver will be automatically disabled and the address byte is ignored. If

the address byte matches the Xoff2 character, the receiver will put this byte in the RX

FIFO along with the parity bit in the parity error bit (LSR bit 2).

7. Register descriptions

Table 8 details the assigned bit functions for the SC16C850 internal registers. The

assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.23.

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7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the

transmit FIFO. The THR empty ﬂag in the LSR will be set to a logic 1 when the transmit

FIFO is empty or when data is transferred to the TSR.

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a

Receive Serial Shift Register (RSR). Receive data is removed from the SC16C850

receive FIFO by reading the RHR. The receive section provides a mechanism to prevent

false starts. On the falling edge of a start or false start bit, an internal receiver counter

starts counting clocks at the 16× clock rate. After 7¹⁄₂clocks, the start bit time should be

shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a

logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from

assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INT output pin.

Table 9.

Interrupt Enable Register bits description

Bit

Symbol Description

7

IER[7]

IER[6]

IER[5]

CTS interrupt.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC16C850 issues an interrupt when

the CTS pin transitions from a logic 0 to a logic 1.

6

5

RTS interrupt.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC16C850 issues an interrupt when

the RTS pin transitions from a logic 0 to a logic 1.

Xoff interrupt.

logic 0 = disable the software ﬂow control, receive Xoff interrupt (normal

default condition)

logic 1 = enable the receive Xoff interrupt

Sleep mode.

4

3

IER[4]

IER[3]

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode

Modem Status Interrupt. This interrupt will be issued whenever there is a modem

status change as reﬂected in MSR[3:0].

logic 0 = disable the modem status register interrupt (normal default condition)

logic 1 = enable the modem status register interrupt

2

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a receive

data error condition exists as reﬂected in LSR[4:1].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

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Table 9.

Interrupt Enable Register bits description …continued

Bit

Symbol Description

1

IER[1]

Transmit Holding Register interrupt. In the non-FIFO mode, this interrupt will be

issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO

modes, this interrupt will be issued whenever the FIFO is empty.

logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt

(normal default condition)

logic 1 = enable the TXRDY (ISR level 3) interrupt

0

IER[0]

Receive Holding Register interrupt. In the non-FIFO mode, this interrupt will be

issued when the RHR has data, or is cleared when the RHR is empty. In the FIFO

mode, this interrupt will be issued when the FIFO has reached the programmed

trigger level or is cleared when the FIFO drops below the trigger level.

logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal

default condition)

logic 1 = enable the RXRDY (ISR level 2) interrupt

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts

(IER[0] = logic 1) are enabled, the receive interrupts and register status will reﬂect the

following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by the TSR and UART for

transmission via the transmission media. The interrupt is cleared either by reading the

ISR, or by loading the THR with new data characters.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, setting IER[3:0] puts the SC16C850 in the FIFO polled mode of

operation. In this mode, interrupts are not generated and the user must poll the LSR

register for TX and/or RX data status. Since the receiver and transmitter have separate

bits in the LSR either or both can be used in the polled mode by selecting respective

transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will show if any FIFO data errors occurred.

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7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO

trigger levels.

7.3.1 FIFO mode

Table 10. FIFO Control Register bits description

Bit

Symbol Description

7:6

FCR[7:6] Receive trigger level in 32-byte FIFO mode^[1].

These bits are used to set the trigger levels for receive FIFO interrupt and ﬂow

control. The SC16C850 will issue a receive ready interrupt when the number of

characters in the receive FIFO reaches the selected trigger level. Refer to

Table 11.

5:4

FCR[5:4] Transmit trigger level in 32-byte FIFO mode^[2].

These bits are used to set the trigger level for the transmit FIFO interrupt and

ﬂow control. The SC16C850 will issue a transmit empty interrupt when the

number of characters in FIFO drops below the selected trigger level. Refer to

Table 12.

3

2

FCR[3]

FCR[2]

reserved

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic. This bit will return to a logic 0 after clearing the FIFO.

1

0

FCR[1]

FCR[0]

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO counter

logic. This bit will return to a logic 0 after clearing the FIFO.

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO

[1] For 128-byte FIFO mode, refer to Section 7.16, Section 7.17, Section 7.18.

[2] For 128-byte FIFO mode, refer to Section 7.15, Section 7.17, Section 7.18.

Table 11. RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level (bytes) in 32-byte FIFO mode^[1]

0

1

0

1

0

1

8

16

24

28

[1] When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and

transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”).

SC16C850_1

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Table 12. TX FIFO trigger levels

FCR[5]

FCR[4]

TX FIFO trigger level (bytes) in 32-byte FIFO mode^[1]

0

1

0

1

0

1

16

8

24

30

[1] When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and

transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”).

7.4 Interrupt Status Register (ISR)

The SC16C850 provides six levels of prioritized interrupts to minimize external software

interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status

bits. Performing a read cycle on the ISR will provide the user with the highest pending

interrupt level to be serviced. No other interrupts are acknowledged until the pending

interrupt is serviced. A lower level interrupt may be seen after servicing the higher level

interrupt and re-reading the interrupt status bits. Table 13 “Interrupt source” shows the

data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources

associated with each of these interrupt levels.

Table 13. Interrupt source

Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

0

1

0

LSR (Receiver Line Status

Register)

2

3

0

1

0

1

0

1

0

RXRDY (Received Data Ready)

RXRDY (Receive Data time-out)

TXRDY (Transmitter Holding

Register Empty)

4

5

0

1

0

MSR (Modem Status Register)

RXRDY (Received Xoff signal)/

Special character

6

1

0

CTS, RTS change of state

Table 14. Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being

used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are

enabled in the SC16C850 mode.

logic 0 or cleared = default condition

5:4

3:1

ISR[5:4]

ISR[3:1]

INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.

ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]

indicates that CTS, RTS have been generated. Note that once set to a

logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.

logic 0 or cleared = default condition

INT priority bits 2:0. These bits indicate the source for a pending interrupt at

interrupt priority levels 1, 2, and 3 (see Table 13).

logic 0 or cleared = default condition

SC16C850_1

Product data sheet

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26 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Table 14. Interrupt Status Register bits description …continued

Bit

Symbol

Description

0

ISR[0]

INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as a

pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 15. Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6

LCR[6]

Set break. When enabled, the Break control bit causes a break condition to

be transmitted (the TX output is forced to a logic 0 state). This condition

exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

5:3

2

LCR[5:3]

LCR[2]

Programs the parity conditions (see Table 16).

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with the

programmed word length (see Table 17).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 18).

logic 0 or cleared = default condition

Table 16. LCR[5:3] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

X

0

1

X

0

1

0

1

0

1

odd parity

even parity

forced parity ‘1’

forced parity ‘0’

Table 17. LCR[2] stop bit length

LCR[2]

Word length (bits)

Stop bit length (bit times)

0

1

5, 6, 7, 8

5

1

1¹⁄₂

6, 7, 8

2

SC16C850_1

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Table 18. LCR[1:0] word length

LCR[1]

LCR[0]

Word length (bits)

0

1

0

1

0

1

5

6

7

8

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 19. Modem Control Register bits description

Bit

Symbol

Description

7

MCR[7]

Clock select

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

IR enable (see Figure 22).

6

MCR[6]

logic 0 = enable the standard modem receive and transmit input/output

interface (normal default condition)

logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While

in this mode, the TX/RX output/inputs are routed to the infrared

encoder/decoder. The data input and output levels will conform to the

IrDA infrared interface requirement. As such, while in this mode, the

infrared TX output will be a logic 0 during idle data conditions.

5

4

MCR[5]

MCR[4]

Interrupt type (Intel mode only). In Intel mode (16/68 = 1), this pin

determines the interrupt output pin conﬁguration.

logic 0 = CMOS output

logic 1 = open-source. A 300 Ω to 500 Ω pull-down resistor is required.

In Motorola mode (16/68 = 0), the output is always open-drain.

Loopback. Enable the local loopback mode (diagnostics). In this mode the

transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI

are disconnected from the SC16C850 I/O pins. Internally the modem data

and control pins are connected into a loopback data conﬁguration (see

Figure 9). In this mode, the receiver and transmitter interrupts remain fully

operational. The Modem Control Interrupts are also operational, but the

interrupts’ sources are switched to the lower four bits of the Modem Control.

Interrupts continue to be controlled by the IER register.

logic 0 = disable Loopback mode (normal default condition)

logic 1 = enable local Loopback mode (diagnostics)

3

2

1

MCR[3]

MCR[2]

MCR[1]

OP2. This bit is used for internal Loopback mode only. In Loopback mode,

this bit is used to write the state of the modem CD interface signal.

OP1. This bit is used for internal Loopback mode only. In Loopback mode,

this bit is used to write the state of the modem RI interface signal.

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

0

MCR[0]

DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

SC16C850_1

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C850 and the CPU.

Table 20. Line Status Register bits description

Bit

Symbol Description

7

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when there are no remaining error ﬂags

associated with the remaining data in the FIFO.

6

5

LSR[6]

LSR[5]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the transmit holding register and the transmit shift register are

both empty. It is reset to logic 0 whenever either the THR or TSR contains a data

character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and

transmit shift register are both empty.

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the transmit holding register into the transmitter shift register.

The bit is reset to a logic 0 concurrently with the loading of the transmitter

holding register by the CPU. In the FIFO mode, this bit is set when the transmit

FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s). In

the FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with the

character at the top of the FIFO.

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the Receive Shift

Register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the Receive Shift Register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

0

LSR[0]

Receive data ready.

logic 0 = no data in Receive Holding Register or FIFO (normal default

condition)

logic 1 = data has been received and is saved in the Receive Holding Register

or FIFO

SC16C850_1

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.8 Modem Status Register (MSR)

This register shares the same address as EFCR register. This is a read-only register and

it provides the current state of the control interface signals from the modem, or other

peripheral device to which the SC16C850 is connected. Four bits of this register are used

to indicate the changed information. These bits are set to a logic 1 whenever a control

input from the modem changes state. These bits are set to a logic 0 whenever the CPU

reads this register.

When write, the data will be written to EFCR register.

Table 21. Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

CD. During normal operation, this bit is the complement of the CD input.

Reading this bit in the loopback mode produces the state of MCR[3] (OP2).

6

5

4

3

MSR[6]

MSR[5]

MSR[4]

MSR[3]

RI. During normal operation, this bit is the complement of the RI input.

Reading this bit in the loopback mode produces the state of MCR[2] (OP1).

DSR. During normal operation, this bit is the complement of the DSR input.

During the loopback mode, this bit is equivalent to MCR[0] (DTR).

CTS. During normal operation, this bit is the complement of the CTS input.

During the loopback mode, this bit is equivalent to MCR[1] (RTS).

∆CD ^[1]

logic 0 = no CD change (normal default condition)

logic 1 = the CD input to the SC16C850 has changed state since the last

time it was read. A modem Status Interrupt will be generated.

2

1

0

MSR[2]

MSR[1]

MSR[0]

∆RI ^[1]

logic 0 = no RI change (normal default condition)

logic 1 = the RI input to the SC16C850 has changed from a logic 0 to a

logic 1. A modem Status Interrupt will be generated.

∆DSR ^[1]

logic 0 = no DSR change (normal default condition)

logic 1 = the DSR input to the SC16C850 has changed state since the

last time it was read. A modem Status Interrupt will be generated.

∆CTS ^[1]

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C850 has changed state since the

last time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.

SC16C850_1

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.9 Extra Feature Control Register (EFCR)

This is a write-only register, and it allows the software access to these registers: ‘ﬁrst extra

feature register set’, ‘second extra feature register set’, Transmit FIFO Level Counter

(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).

Table 22. Extra Feature Control Register bits description

Bit

7:3

2:1

Symbol

Description

EFCR[7:3]

EFCR[2:1]

reserved

Enable Extra Feature Control bits

00 = General register set is accessible

01 = First extra feature register set is accessible

10 = Second extra feature register set is accessible

11 = reserved

0

EFCR[0]

Enable TXLVLCNT and RXLVLCNT access

0 = TXLVLCNT and RXLVLCNT are disabled

1 = TXLVLCNT and RXLVLCNT are enabled and can be read.

Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can

only be accessed if EFCR[2:1] are zeroes.

7.10 Scratchpad Register (SPR)

The SC16C850 provides a temporary data register to store 8 bits of user information.

7.11 Divisor Latch (DLL and DLM)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock

in the baud rate generator. DLM, stores the most signiﬁcant part of the divisor. DLL stores

the least signiﬁcant part of the divisor.

7.12 Transmit FIFO Level Count (TXLVLCNT)

This register is a read-only register. It reports the number of spaces available in the

transmit FIFO.

7.13 Receive FIFO Level Count (RXLVLCNT)

This register is a read-only register. It reports the ﬁll level of the receive FIFO (the number

of characters in the RX FIFO).

SC16C850_1

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.14 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection. When the

Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are

concatenated into two sequential numbers.

Table 23. Enhanced Feature Register bits description

Bit

Symbol Description

7

EFR[7]

Automatic CTS ﬂow control.

logic 0 = automatic CTS ﬂow control is disabled (normal default condition)

logic 1 = enable automatic CTS ﬂow control. Transmission will stop when

CTS goes to a logical 1. Transmission will resume when the CTS pin returns

to a logical 0.

6

EFR[6]

Automatic RTS ﬂow control. Automatic RTS may be used for hardware ﬂow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be

generated when the receive FIFO is ﬁlled to the programmed trigger level and

RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when

data is unloaded below the next lower trigger level (programmed trigger level 1).

The state of this register bit changes with the status of the hardware ﬂow

control. RTS functions normally when hardware ﬂow control is disabled.

logic 0 = automatic RTS ﬂow control is disabled (normal default condition)

logic 1 = enable automatic RTS ﬂow control

5

EFR[5]

Special Character Detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. The SC16C850 compares each

incoming receive character with Xoff2 data. If a match exists, the received

data will be transferred to FIFO and ISR[4] will be set to indicate detection of

special character. Bit 0 in the X-registers corresponds with the LSB bit for the

receive character. When this feature is enabled, the normal software ﬂow

control must be disabled (EFR[3:0] must be set to a logic 0).

4

EFR[4]

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and

MCR[7:5] can be modiﬁed and latched. After modifying any bits in the enhanced

registers, EFR[4] can be set to a logic 0 to latch the new values. This feature

prevents existing software from altering or overwriting the SC16C850 enhanced

functions.

logic 0 = disable/latch enhanced features^[1]. (Normal default condition.)

logic 1 = enables the enhanced functions^[1].

3:0

EFR[3:0] Cont-3:0 TX, RX control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming these

bits. See Table 24.

[1] Enhanced function control bits IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5].

SC16C850_1

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Table 24. Software ﬂow control functions^[1]

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software ﬂow controls

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

X

0

1

No transmit ﬂow control

Transmit Xon1/Xoff1

Transmit Xon2/Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

No receive ﬂow control

Receiver compares Xon1/Xoff1

Receiver compares Xon2/Xoff2

Transmit Xon1/Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon2/Xoff2

0

1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

[1] When using a software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

7.15 Transmit Interrupt Level Register (TXINTLVL)

This 8-bit register is used to store the transmit FIFO trigger levels used for interrupt

generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.

Table 25 shows the TXINTLVL register bit settings.

Table 25. TXINTLVL register bits description

Bit

Symbol

Description

7:0

TXINTLVL[7:0]

This register stores the programmable transmit interrupt trigger levels

for 128-byte FIFO mode^[1].

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.16 Receive Interrupt Level Register (RXINTLVL)

This 8-bit register is used store the receive FIFO trigger levels used for interrupt

generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.

Table 26 shows the RXINTLVL register bit settings.

Table 26. RXINTLVL register bits description

Bit

Symbol

Description

7:0

RXINTLVL[7:0] This register stores the programmable receive interrupt trigger levels

for 128-byte FIFO mode^[1].

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

SC16C850_1

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.17 Flow Control Trigger Level High (FLWCNTH)

This 8-bit register is used to store the receive FIFO high threshold levels to start/stop

transmission during hardware/software ﬂow control. Table 27 shows the FLWCNTH

register bit settings; see Section 6.5.

Table 27. FLWCNTH register bits description

Bit

Symbol

Description

7:0

FLWCNTH[7:0]

This register stores the programmable HIGH threshold level for

hardware and software ﬂow control for 128-byte FIFO mode^[1].

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.18 Flow Control Trigger Level Low (FLWCNTL)

This 8-bit register is used to store the receive FIFO low threshold levels to start/stop

transmission during hardware/software ﬂow control. Table 28 shows the FLWCNTL

register bit settings; see Section 6.5.

Table 28. FLWCNTL register bits description

Bit

Symbol

Description

7:0

FLWCNTL[7:0]

This register stores the programmable LOW threshold level for

hardware and software ﬂow control for 128-byte FIFO mode^[1].

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.19 Clock Prescaler (CLKPRES)

This register hold values for the clock prescaler.

Table 29. Clock Prescaler register bits description

Bit

7:4

3:0

Symbol

Description

CLKPRES[7:4]

CLKPRES[3:0]

reserved

Clock Prescaler value. Reset to 0.

SC16C850_1

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.20 RS-485 Turn-around time delay (RS485TIME)

The value in this register controls the turn-around time of the external line transceiver in

bit time. In automatic 9-bit mode RTS or DTR pin is used to control the direction of the line

driver, after the last bit of data has been shifted out of the transmit shift register the UART

will count down the value in this register. When the count value reaches zero, the UART

will assert RTS or DTR pin (logic 0) to turn the external RS-485 transceiver around for

receiving.

Table 30. RS-485 programmable turn-around time register bits description

Bit

Symbol

Description

7:0

RS485TIME[7:0] External RS-485 transceiver turn-around time delay. The value

represents the bit time at the programmed baud rate.

7.21 Advanced Feature Control Register 2 (AFCR2)

Table 31. Advanced Feature Control Register 2 register bits description

Bit

7:6

5

Symbol

Description

AFCR2[7:6]

AFCR2[5]

reserved

RTSInvert. Invert RTS or DTR signal in automatic 9-bit mode.

logic 0 = RTS or DTR is set to 0 by the UART during transmission,

and to 1 during reception

logic 1 = RTS or DTR is set to 1 by the UART during transmission,

and to 0 during reception

4

3

AFCR2[4]

AFCR2[3]

RTSCon. Enable the transmitter to control RTS or DTR pin in

automatic 9-bit mode.

logic 0 = transmitter does not control RTS or DTR pin

logic 1 = transmitter controls RTS or DTR pin

RS485 RTS/DTR. Select RTS or DTR pin to control the external

transceiver.

logic 0 = RTS pin is used to control the external transceiver

logic 1 = DTR pin is used to control the external transceiver

TXDisable. Disable transmitter

2

1

0

AFCR2[2]

AFCR2[1]

AFCR2[0]

logic 0 = transmitter is enabled

logic 1 = transmitter is disabled

RXDisable. Disable receiver

logic 0 = receiver is enabled

logic 1 = receiver is disabled

9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode

logic 0 = normal RS-232 mode

logic 1 = enable 9-bit mode

SC16C850_1

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SC16C850

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2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.22 Advanced Feature Control Register 1 (AFCR1)

Table 32. Advanced Feature Control Register 1 register bits description

Bit

7:5

4

Symbol

Description

AFCR1[7:5] reserved

AFCR1[4]

Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.

logic 0 = RX input is level-sensitive. If RX pin is LOW, the UART will not

go to sleep. Once the UART is in Sleep mode, it will wake up if RX pin

goes LOW.

logic 1 = RX input is edge-sensitive. UART will go to sleep even if RX

pin is LOW, and will wake up when RX pin toggles.

3

2

AFCR1[3]

AFCR1[2]

reserved

RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to

DTR/DSR.

logic 0 = RTS and CTS signals are used for hardware ﬂow control.

logic 1 = DTR and DSR signals are used for hardware ﬂow control.

RTS and CTS retain their functionality.

1

0

AFCR1[1]

AFCR1[0]

SReset. Software Reset. A write to this bit will reset the UART. Once the

UART is reset this bit is automatically set to 0.^[1]

TSR Interrupt. Select TSR interrupt mode

logic 0 = transmit empty interrupt occurs when transmit FIFO falls

below the trigger level or becomes empty.

logic 1 = transmit empty interrupt occurs when transmit FIFO falls

below the trigger level, or becomes empty and the last stop bit has

been shifted out of the Transmit Shift Register.

[1] It takes 4 XTAL1 clocks to reset the device.

SC16C850_1

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.23 SC16C850 external reset condition and software reset

These two reset methods are identical and will reset the internal registers as indicated in

Table 33.

Table 33. Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

FCR

FCR[7:0] = 0

ISR

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

MCR[7:0] = 0

LSR

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

EFCR[7:0] = 0

MSR

EFCR

SPR

SPR[7:0] = 1

DLL

undeﬁned

DLM

undeﬁned

TXLVLCNT

RXLVLCNT

EFR

TXLVLCNT[7:0] = 0

RXLVLCNT[7:0] = 0

EFR[7:0] = 0

Xon1

undeﬁned

Xon2

undeﬁned

Xoff1

undeﬁned

Xoff2

undeﬁned

TXINTLVL

RXINTLVL

FLWCNTH

FLWCNTL

CLKPRES

RS485TIME

AFCR2

AFCR1

TXINTLVL[7:0] = 0

RXINTLVL[7:0] = 0

FLWCNTH[7:0] = 0

FLWCNTL[7:0] = 0

CLKPRES[7:0] = 0

RS485TIME[7:0] = 0

AFCR2[7:0] = 0

AFCR1[7:0] = 0

Table 34. Reset state for outputs

Output

TX

Reset state

logic 1

RTS

DTR

INT

logic 1

logic 0

IRQ

open-drain

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

8. Limiting values

Table 35. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

Max

Unit

V

supply voltage

-

7

V_n

voltage on any other pin

ambient temperature

storage temperature

V

_SS− 0.3 V_DD+ 0.3

V

T_amb

operating in free air

−40

−65

-

+85

°C

mW

T_stg

+150

500

P_tot/pack

total power dissipation per

package

9. Static characteristics

Table 36. Static characteristics

T_amb= −40 °C to +85 °C; tolerance of V_DD± 10 %; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

V_DD= 2.5 V

V_DD= 3.3 V

Unit

Min

Max

Min

Max

0.6

V_DD

0.8

-

V_IL(clk)

V_IH(clk)

V_IL

clock LOW-level input voltage

clock HIGH-level input voltage

LOW-level input voltage

−0.3

0.45

V_DD

0.65

-

−0.3

V

1.8

2.4

V

except XTAL1 clock

I_OL= 4 mA

−0.3

V

V_IH

HIGH-level input voltage

LOW-level output voltage

1.6

2.0

V

[1]

V_OL

-

0.4

-

V

I_OL= 2 mA

-

0.4

-

V

V_OH

HIGH-level output voltage

I_OH= −4 mA

-

2.0

-

V

I_OH= −800 µA

1.85

-

V

I_LIL

LOW-level input leakage current

HIGH-level input leakage current

clock leakage current

-

10

30

2

10

30

2

µA

mA

µA

pF

I_LIH

I_L(clk)

LOW-level

HIGH-level

f = 5 MHz

I_DD

supply current

[2]

[3]

I_DD(sleep)

I_DD(lp)

C_i

sleep mode supply current

low-power mode supply current

input capacitance

50

5

50

5

[1] Except XTAL2; XTAL2 V_OLis 1 V typical.

[2] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode.

[3] Activated by LOWPWR pin.

SC16C850_1

Product data sheet

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SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

10. Dynamic characteristics

Table 37. Dynamic characteristics - Intel or 16 mode

T_amb= −40 °C to +85 °C; tolerance of V_DD± 10 %; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

V_DD= 2.5 V

Min Max

V_DD= 3.3 V

Min Max

Unit

t_WH

pulse width HIGH

6

-

6

-

ns

MHz

ns

t_WL

pulse width LOW

6

12.5

-

6

12.5

-

t_w(clk)

clock pulse width

[1][2]

f_XTAL1

t_su(A)

frequency on pin XTAL1

address set-up time

80

-

80

-

10

35

0

5

t_h(A)

address hold time

-

5

-

t_d(CS-IOR)

t_w(IOR)

t_h(IOR-CS)

t_d(IOR)

t_d(IOR-Q)

t_dis(IOR-QZ)

delay time from CS to IOR

IOR pulse width time

hold time from IOR to chip select

IOR delay time

-

5

-

26

0

-

10

-

10

-

delay time from IOR to data output

25 pF load

35

17

26

15

disable time from IOR to

high-impedance data output^[3]

-

t_d(CSL-IOWL)delay time from CS LOW to IOW LOW

10

15

0

-

5

20

0

-

ns

t_w(IOW)

IOW pulse width time

hold time from IOW to CS

IOW delay time

t_h(IOW-CS)

t_d(IOW)

15

10

20

5

t_su(D-IOWH)

set-up time from data input to

IOW HIGH

t_h(IOWH-D)

t_d(IOW-Q)

data input hold time after IOW HIGH

delay time from IOW to data output

10

-

40

5

-

33

ns

s

25 pF load

t_d(modem-INT)delay time from modem to INT

-

35

-

24

t_d(IOR-INTL)

t_d(stop-INT)

t_d(start-INT)

t_d(IOW-TX)

t_d(IOW-INTL)

t_w(RESET)

N

delay time from IOR to INT LOW

delay time from stop to INT

delay time from start to INT

delay time from IOW to TX

delay time from IOW to INT LOW

pulse width on pin RESET

baud rate divisor

-

35

-

24

[4]

-

1T_RCLK

-

1T_RCLK

-

s

8T_RCLK24T_RCLK8T_RCLK24T_RCLK

s

-

55

-

45

ns

10

1

-

10

1

-

(2¹⁶− 1)

[1] Applies to external clock, crystal oscillator max 24 MHz.

1

[2] Maximum frequency =

--------------

t_w(clk)

[3] 10 % of the data bus output voltage level.

[4] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

SC16C850_1

Product data sheet

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39 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

Table 38. Dynamic characteristics - Motorola or 68 mode

T_amb= −40 °C to +85 °C; tolerance of V_DD± 10 %; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

V_DD= 2.5 V

Min Max

V_DD= 3.3 V

Min Max

Unit

t_WH

pulse width HIGH

6

-

6

-

ns

MHz

ns

t_WL

pulse width LOW

6

12.5

-

6

12.5

-

t_w(clk)

clock pulse width

[1][2]

f_XTAL1

frequency on pin XTAL1

address set-up time

80

-

80

-

t_su(A)

10

15

10

50

20

-

10

15

10

20

10

-

t_h(A)

address hold time

-

t_su(RWL-CSL)

t_su(RWH-CSL)

t_w(CS)

set-up time from R/W LOW to CS LOW

set-up time from R/W HIGH to CS LOW

CS pulse width

-

25 pF load

-

t_d(CS)

CS delay time

-

t_d(CS-Q)

t_dis(CS-QZ)

delay time from CS to data output

50

20

disable time from CS to

-

high-impedance data output

t_h(CS-RWH)

t_d(RW)

t_su(D-CSH)

t_h(CSH-D)

hold time from CS to R/W HIGH

R/W delay time

10

15

-

10

15

-

ns

s

-

set-up time from data input to CS HIGH

data input hold time after CS HIGH

-

[3]

t_{d(modem-IRQL)}delay time from modem to IRQ LOW

40

30

t_d(CS-IRQH)R

t_d(stop-IRQL)

t_d(CS-TX)W

t_{d(start-IRQL)}

t_d(CS-IRQH)W

t_d(CS-Q)W

t_{w(RESET_N)}

N

read delay time from CS to IRQ HIGH

delay time from stop to IRQ LOW

write delay time from CS to TX

delay time from start to IRQ LOW

write delay time from CS to IRQ HIGH

write delay time from CS to data output

pulse width on pin RESET

-

40

-

30

[4]

-

1T_RCLK

-

1T_RCLK

[4]

8T_RCLK24T_RCLK8T_RCLK24T_RCLK

s

[3][4]

[3]

-

1T_RCLK

-

1T_RCLK

s

55

45

ns

-

40

-

33

10

1

-

10

1

-

baud rate divisor

(2¹⁶− 1)

[1] Applies to external clock, crystal oscillator max 24 MHz.

1

[2] Maximum frequency =

--------------

t_w(clk)

[3] 1 kΩ pull-up resistor on IRQ pin.

[4] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

SC16C850_1

Product data sheet

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40 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

10.1 Timing diagrams

t

h(A)

valid

address

A0 to A2

t

h(IOW-CS)

su(A)

active

CS

IOW

t

d(IOW)

d(CSL-IOWL)

w(IOW)

active

t

h(IOWH-D)

t

su(D-IOWH)

D0 to D7

data

002aac690

Fig 10. General write timing (16 mode)

A0 to A4

t

h(A)

su(A)

t

w(CS)

CS

R/W

t

su(RWL-CSL)

t

d(RW)

t

h(CS-RWH)

t

h(CSH-D)

t

su(D-CSH)

D0 to D7

002aac408

Fig 11. General write timing (68 mode)

SC16C850_1

Product data sheet

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41 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

t

h(A)

valid

address

A0 to A2

t

h(IOR-CS)

su(A)

active

CS

IOR

t

d(IOR)

d(CS-IOR)

w(IOR)

active

t

d(IOR-Q)

t

dis(IOR-QZ)

D0 to D7

data

002aac691

Fig 12. General read timing (16 mode)

t

h(A)

A0 to A4

t

su(A)

t

d(CS)

w(CS)

CS

R/W

t

su(RWH-CSL)

t

dis(CS-QZ)

t

d(CS-Q)

D0 to D7

002aac407

Fig 13. General read timing (68 mode)

t

WH

WL

external clock

t

w(clk)

002aac357

1

f _XTAL

=

--------------

t_w(clk)

Fig 14. External clock timing

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

42 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

active

IOW

RTS

t

d(IOW-Q)

change of state

DTR

CD

CTS

DSR

change of state

t

d(modem-INT)

active

INT

active

t

d(IOR-INTL)

active

IOR

t

d(modem-INT)

change of state

002aac409

RI

Fig 15. Modem input/output timing (16 mode)

(1)

active

CS (write)

t

d(CS-Q)W

RTS

DTR

change of state

CD

CTS

DSR

change of state

t

d(modem-IRQL)

IRQ

active

t

d(CS-IRQH)R

(2)

CS (read)

active

t

d(modem-IRQL)

change of state

RI

002aac632

(1) CS timing during a write cycle. See Figure 11.

(2) CS timing during a read cycle. See Figure 13.

Fig 16. Modem input/output timing (68 mode)

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

43 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

next data

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

RX

D0

D1

D2

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

d(stop-INT)

(1)(2)

INT

active

t

d(IOR-INTL)

active

IOR

16 baud rate clock

002aac410

(1) INT is active when RX FIFO ﬁlls up to trigger level or a time-out condition happens (see Section 6.8).

(2) INT is cleared when RX FIFO drops below trigger level.

Fig 17. Receive timing in 16 mode

next data

start

bit

parity stop

bit bit

bit

data bits (0 to 7)

RX

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

d(stop-IRQL)

(1)(2)

active

IRQ

t

d(CS-IRQH)R

CS (read)

active

16 baud rate clock

002aac633

(1) IRQ is active when RX FIFO ﬁlls up to trigger level or time-out condition happens (see Section 6.8).

(2) IRQ is cleared when RX FIFO drops below trigger level.

Fig 18. Receive timing in 68 mode

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

44 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

next data

start

bit

start

bit

parity stop

bit bit

data bits (0 to 7)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

(1)(2)

INT

active

transmitter ready

t

d(start-INT)

t

d(IOW-INTL)

t

d(IOW-TX)

active

IOW

16 baud rate clock

002aac413

(1) INT is active when TX FIFO is empty or TX FIFO drops below trigger level.

(2) INT is cleared when ISR is read or TX FIFO ﬁlls up to trigger level.

Fig 19. Transmit timing in 16 mode

next data

start

bit

parity stop

bit bit

bit

data bits (0 to 7)

D0

D1

D2

D3

D4

D5

D6

D7

TX

5 data bits

6 data bits

7 data bits

active

TX ready

(1)(2)

IRQ

t

d(start-IRQL)

t

d(CS-IRQH)W

t

d(CS-TX)W

active

CS (write)

16 baud rate clock

002aac634

(1) IRQ is active when TX FIFO is empty or TX FIFO drops below trigger level.

(2) IRQ is cleared when ISR is read or TX FIFO ﬁlls up to trigger level.

Fig 20. Transmit timing in 68 mode

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

45 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

UART frame

start

0

data bits

stop

1

0

1

0

1

0

TX data

IrDA TX data

1

/

bit time

2

bit

time

3

/

bit time

16

002aaa212

Fig 21. Infrared transmit timing

IrDA RX data

bit

time

0 to 1 16× clock delay

0

1

0

1

0

1

0

1

RX data

start

data bits

stop

UART frame

002aaa213

Fig 22. Infrared receive timing

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

46 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

11. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w

9

16

L

17

8

e

E

h

2

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 23. Package outline SOT617-1 (HVQFN32)

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

47 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm

SOT912-1

D

B

A

E

ball A1

index area

A

2

A

1

detail X

e

1

1/2 e

e

C

M

v

C

A

B

b

y

w

C

1

F

E

D

C

B

A

e

2

1/2 e

ball A1

index area

1

2

3

4

5

6

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

2

v

w

y

1

max

0.25 0.90 0.35

0.15 0.75 0.25

3.6

3.4

3.6

3.4

mm

1.15

0.5

2.5

0.15 0.05 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

05-08-09

05-09-01

- - -

SOT912-1

Fig 24. Package outline SOT912-1 (TFBGA36)

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

48 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

12. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SC16C850_1

Product data sheet

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49 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 25) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 39 and 40

Table 39. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 40. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 25.

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

50 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 25. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

13. Abbreviations

Table 41. Abbreviations

Acronym

CPU

Description

Central Processing Unit

DLL

Divisor Latch LSB

DLM

Divisor Latch MSB

FIFO

IrDA

First In, First Out

Infrared Data Association

Integrated Service Digital Network

Least Signiﬁcant Bit

ISDN

LSB

MSB

PCB

Most Signiﬁcant Bit

Printed-Circuit Board

RoHS

UART

Restriction of Hazardous Substances directive

Universal Asynchronous Receiver/Transmitter

14. Revision history

Table 42. Revision history

Document ID

Release date

20080110

Data sheet status

Change notice

Supersedes

SC16C850_1

Product data sheet

-

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

51 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

16. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

SC16C850_1

Product data sheet

Rev. 01 — 10 January 2008

52 of 53

SC16C850

NXP Semiconductors

2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.11

7.12

Divisor Latch (DLL and DLM). . . . . . . . . . . . . 31

Transmit FIFO Level Count

(TXLVLCNT). . . . . . . . . . . . . . . . . . . . . . . . . . 31

Receive FIFO Level Count

(RXLVLCNT) . . . . . . . . . . . . . . . . . . . . . . . . . 31

Enhanced Feature Register

(EFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Transmit Interrupt Level Register

(TXINTLVL) . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Receive Interrupt Level Register

(RXINTLVL) . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Flow Control Trigger Level High

(FLWCNTH) . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Flow Control Trigger Level Low

(FLWCNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Clock Prescaler (CLKPRES) . . . . . . . . . . . . . 34

RS-485 Turn-around time delay

(RS485TIME) . . . . . . . . . . . . . . . . . . . . . . . . . 35

Advanced Feature Control Register 2

(AFCR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Advanced Feature Control Register 1

(AFCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SC16C850 external reset condition and

software reset. . . . . . . . . . . . . . . . . . . . . . . . . 37

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7.13

7.14

7.15

7.16

7.17

7.18

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6

6.1

6.2

6.3

Functional description . . . . . . . . . . . . . . . . . . . 9

UART selection. . . . . . . . . . . . . . . . . . . . . . . . . 9

Extended mode (128-byte FIFO) . . . . . . . . . . 10

Internal registers. . . . . . . . . . . . . . . . . . . . . . . 10

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11

32-byte FIFO mode. . . . . . . . . . . . . . . . . . . . . 11

128-byte FIFO mode. . . . . . . . . . . . . . . . . . . . 11

Hardware ﬂow control. . . . . . . . . . . . . . . . . . . 12

Software ﬂow control . . . . . . . . . . . . . . . . . . . 12

Special character detect . . . . . . . . . . . . . . . . . 13

Interrupt priority and time-out interrupts . . . . . 13

Programmable baud rate generator . . . . . . . . 14

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 16

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Conditions to enter Sleep mode . . . . . . . . . . . 18

Conditions to resume normal operation . . . . . 18

Low power feature . . . . . . . . . . . . . . . . . . . . . 18

RS-485 features . . . . . . . . . . . . . . . . . . . . . . . 19

Auto RS-485 RTS control . . . . . . . . . . . . . . . . 19

RS-485 RTS inversion . . . . . . . . . . . . . . . . . . 19

Auto 9-bit mode (RS-485). . . . . . . . . . . . . . . . 19

6.4

6.4.1

6.4.2

6.5

6.6

6.7

7.19

7.20

7.21

7.22

7.23

6.8

6.9

6.10

6.11

6.11.1

6.11.2

6.12

6.13

6.13.1

6.13.2

6.13.3

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38

Static characteristics . . . . . . . . . . . . . . . . . . . 38

Dynamic characteristics. . . . . . . . . . . . . . . . . 39

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 41

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 47

9

10

10.1

11

6.13.3.1 Normal Multi-drop mode. . . . . . . . . . . . . . . . . 19

6.13.3.2 Auto address detection. . . . . . . . . . . . . . . . . . 20

12

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Introduction to soldering. . . . . . . . . . . . . . . . . 49

Wave and reﬂow soldering . . . . . . . . . . . . . . . 49

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 49

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 50

12.1

12.2

12.3

12.4

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 20

Transmit (THR) and Receive (RHR)

Holding Registers . . . . . . . . . . . . . . . . . . . . . . 23

Interrupt Enable Register (IER) . . . . . . . . . . . 23

IER versus Transmit/Receive FIFO

7.2

7.2.1

13

14

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51

Revision history . . . . . . . . . . . . . . . . . . . . . . . 51

interrupt mode operation. . . . . . . . . . . . . . . . . 24

IER versus Receive/Transmit FIFO

7.2.2

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 52

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 52

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52

polled mode operation . . . . . . . . . . . . . . . . . . 24

FIFO Control Register (FCR) . . . . . . . . . . . . . 25

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Interrupt Status Register (ISR) . . . . . . . . . . . . 26

Line Control Register (LCR) . . . . . . . . . . . . . . 27

Modem Control Register (MCR) . . . . . . . . . . . 28

Line Status Register (LSR). . . . . . . . . . . . . . . 29

Modem Status Register (MSR). . . . . . . . . . . . 30

Extra Feature Control Register (EFCR) . . . . . 31

Scratchpad Register (SPR) . . . . . . . . . . . . . . 31

15.1

15.2

15.3

15.4

7.3

7.3.1

7.4

7.5

7.6

7.7

7.8

7.9

7.10

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 52

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 January 2008

Document identifier: SC16C850_1


型号：	SC16C850IET-S
厂家：	NXP
描述：	IC,UART,CMOS,BGA,36PIN,PLASTIC 先进先出芯片
文件：	总53页 (文件大小：254K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC16C850IET-S [NXP]

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