SC16C850SVIBS_技术文档

SC16C850SV

1.8 V single UART, 20 Mbit/s (max.) with 128-byte FIFOs,

infrared (IrDA), and XScale VLIO bus interface

Rev. 01 — 8 July 2008

Product data sheet

1. General description

The SC16C850SV is a 1.8 V, low power single channel Universal Asynchronous Receiver

and Transmitter (UART) used for serial data communications. Its principal function is to

convert parallel data into serial data and vice versa. The UART can handle serial data

rates up to 20 Mbit/s (4× sampling rate). SC16C850SV can be programmed to operate in

extended mode where additional advanced UART features are available (see

Section 6.2).The SC16C850SV family UART provides enhanced UART functions with

128-byte FIFOs, modem control interface and IrDA encoder/decoder. On-board status

registers provide the user with error indications and operational status. System interrupts

and modem control features may be tailored by software to meet speciﬁc user

requirements. An internal loopback capability allows on-board diagnostics. Independent

programmable baud rate generators are provided to select transmit and receive baud

rates.

The SC16C850SV with Intel XScale processor VLIO interface operates at 1.8 V and is

available in the HVQFN32 package.

2. Features

I Single channel high performance UART

I 1.8 V operation

I Advanced package: HVQFN32

I Up to 20 Mbit/s data rate at 1.8 V

I Programmable sampling rates: 16×, 8×, 4×

I 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

I 128-byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the

external CPU

I 128 programmable Receive and Transmit FIFO interrupt trigger levels

I 128 Receive and Transmit FIFO reporting levels (level counters)

I Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) ﬂow control

I Programmable Xon/Xoff characters

I 128 programmable hardware and software trigger levels

I Automatic 9-bit mode (RS-485) address detection

I Automatic RS-485 driver turn-around with programmable delay

I UART software reset

I High resolution clock prescaler, from 0 to 15 with granularity of ¹⁄₁₆to allow

non-standard UART clock to be used

I Industrial temperature range (−40 °C to +85 °C)

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

I Software compatible with industry standard SC16C650B

I Software selectable baud rate generator

I Supports IrDA version 1.0 (up to 115.2 kbit/s)

I Standard modem interface or infrared IrDA encoder/decoder interface

I Enhanced Sleep mode and low power feature

I Modem control functions (CTS, RTS, DSR, DTR, RI, CD)

I Independent transmitter and receiver enable/disable

I Pb-free, RoHS compliant package offered

3. Ordering information

Table 1.

Ordering information

Package

Name

Type number

Description

Version

SC16C850SVIBS HVQFN32 plastic thermal enhanced very thin quad ﬂat package; no leads; 32 terminals; SOT617-1

body 5 × 5 × 0.85 mm

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

2 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

4. Block diagram

SC16C850SV

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTER

AD0 to AD7

IOR

DATA BUS

AND

CONTROL

LOGIC

IOW

RESET

LLA

FLOW

CONTROL

LOGIC

IR

ENCODER

RECEIVE

FIFO

RECEIVE

SHIFT

RX

REGISTER

FLOW

CONTROL

LOGIC

IR

DECODER

REGISTER

SELECT

LOGIC

CS

LOWPWR

INT

POWER

DOWN

CONTROL

DTR

RTS

MODEM

CONTROL

LOGIC

CTS

RI

CD

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

DSR

002aad771

XTAL1

XTAL2

Fig 1. Block diagram of SC16C850SV

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

3 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

5. Pinning information

5.1 Pinning

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

AD4

n.c.

AD5

AD6

AD7

RX

CTS

RESET

DTR

RTS

INT

SC16C850SVIBS

LLA

TX

n.c.

CS

n.c.

002aad772

Transparent top view

Fig 2. Pin conﬁguration for HVQFN32

5.2 Pin description

Table 2.

Symbol

AD0

Pin description

29

30

31

32

1

Type Description

I/O

Address and Data bus (bidirectional). These pins are the 8-bit multiplexed data bus and

address bus for transferring information to or from the controlling CPU. AD0 is the least

signiﬁcant bit and is address A0 during the address cycle, and AD7 is the most signiﬁcant bit

and is address A7 during the address cycle.

AD1

AD2

AD3

AD4

AD5

3

AD6

4

AD7

5

CD

26

I

Carrier Detect (active LOW). A logic 0 on this pin indicates that a carrier has been detected

by the modem for that channel. Status can be tested by reading MSR[7].

CS

8

Chip Select (active LOW). This pin enables the data transfers between the host and the

SC16C850SV.

CTS

24

Clear to Send (active LOW). A logic 0 on the CTS pin indicates the modem or data set is

ready to accept transmit data from the SC16C850SV. Status can be tested by reading

MSR[4].

DSR

DTR

25

22

I

Data Set Ready (active LOW). A logic 0 on this pin indicates the modem or data set is

powered-on and is ready for data exchange with the UART. Status can be tested by reading

MSR[5].

O

Data Terminal Ready (active LOW). A logic 0 on this pin indicates that the SC16C850SV is

powered-on and ready. This pin can be controlled via the Modem Control Register. Writing a

logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a

logic 1 after writing a logic 0 to MCR[0], or after a reset.

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

4 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Table 2.

Symbol

INT

Pin description …continued

Type Description

20

O

Interrupt output. The output state is deﬁned by the user through the software setting of

MCR[5]. INT is set to the active mode when MCR[5] is set to a logic 0. INT is set to the

open-source mode when MCR[3] is set to a logic 1. See Table 19.

IOR

14

I

Read strobe (active LOW). A HIGH to LOW transition on this signal starts the read cycle.

The SC16C850SV reads a byte from the internal register and puts the byte on the data bus

for the host to retrieve.

IOW

LLA

12

19

I

Write strobe (active LOW). A HIGH to LOW transition on this signal starts the write cycle,

and a LOW to HIGH transition transfers the data on the data bus to the internal register.

Latch Lower Address (active LOW). A logic LOW on this pin puts the VLIO interface in the

address phase of the transaction, where the lower 8 bits of the VLIO (specifying the UART

register and the channel address) are loaded into the address latch of the device through

the AD7 to AD0 bus. A logic HIGH puts the VLIO interface in the data phase where data can

are transferred between the host and the UART.

LOWPWR 9

I

Low Power. When asserted (active HIGH), the device immediately goes into low-power

mode. The oscillator is shut-off and some host interface pins are isolated from the host’s bus

to reduce power consumption. The device only returns to normal mode when the LOWPWR

pin is de-asserted. On the negative edge of a de-asserting LOWPWR signal, the device is

automatically reset and all registers return to their default reset states. This pin has an

internal pull-down resistor, therefore, it can be left unconnected.

n.c.

2, 15, 16,

17, 18

-

I

not connected

RESET

23

Master reset (active LOW). A reset pulse will reset the internal registers and all the

outputs. The SC16C850SV transmitter outputs and receiver inputs will be disabled during

reset time. (See Section 7.24 “SC16C850SV external reset condition and software reset” for

initialization details.)

RI

27

21

6

I

Ring Indicator (active LOW). A logic 0 on this pin indicates the modem has received a

ringing signal from the telephone line. A logic 1 transition on this input pin will generate an

interrupt is modem status interrupt is enabled. Status can be tested by reading MCR[6].

RTS

RX

TX

O

I

Request to Send (active LOW). A logic 0 on the RTS pin indicates the transmitter has data

ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set

this pin to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1.

UART receive data. The RX signal will be a logic 1 during reset, idle (no data), or when not

receiving data. During the local Loopback mode, the RX input pin is disabled and TX data is

connected to the UART RX input internally.

7

O

UART transmit data. The TX signal will be a logic 1 during reset, idle (no data), or when the

transmitter is disabled. During the local Loopback mode, the TX output pin is disabled and

TX data is internally connected to the UART RX input.

V_DD

28

13^[1]

I

Power supply input.

V_SS

Signal and power ground.

XTAL1

10

Crystal or external clock input. Functions as a crystal input or as an external clock input.

A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit.

Alternatively, an external clock can be connected to this pin to provide custom data rates

(see Section 6.9 “Programmable baud rate generator”). See Figure 4.

XTAL2

11

O

Output of the crystal oscillator or buffered clock. Crystal oscillator output or buffered

clock output. Should be left open if an external clock is connected to XTAL1.

[1] HVQFN32 package die supply ground is connected to both V_SSpin and exposed center pad. V_SSpin must be connected to supply

ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

5 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

6. Functional description

The SC16C850SV provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is ensured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex, especially

when manufactured on a single integrated silicon chip. The SC16C850SV represents

such an integration with greatly enhanced features. The SC16C850SV is fabricated with

an advanced CMOS process.

The SC16C850SV is an upward solution to the SC16C650B with a VLIO interface that

provides a single UART capability with 128 bytes of transmit and receive FIFO memory,

instead of 32 bytes for the SC16C650B. The SC16C850SV is designed to work with high

speed modems and shared network environments that require fast data processing time.

Increased performance is realized in the SC16C850SV by the transmit and receive FIFOs.

This allows the external processor to handle more networking tasks within a given time. In

addition, the four selectable receive and transmit FIFO trigger interrupt levels are provided

in normal mode, or 128 programmable levels are provided in extended mode for maximum

data throughput performance especially when operating in a multi-channel environment

(see Section 6.2 “Extended mode (128-byte FIFO)”). The FIFO memory greatly reduces

the bandwidth requirement of the external controlling CPU, and increases performance.

A low power pin (LOWPWR) is provided to further reduce power consumption by isolating

the host interface bus.

The SC16C850SV is capable of operation up to 20 Mbit/s with an external 80 MHz clock.

With a 24 MHz crystal, the SC16C850SV is capable of operation up to 6 Mbit/s.

The rich feature set of the SC16C850SV is available through internal registers. These

features are: selectable and programmable receive and transmit FIFO trigger levels,

selectable TX and RX baud rates, and modem interface controls (all standard features).

Following a power-on reset an external reset or a software reset, the SC16C850SV is

software compatible with the previous generation SC16C650B.

6.1 UART selection

The UART provides the user with the capability to bidirectionally transfer information

between a CPU and an external serial device. The CS pin together with addresses A6 and

A7 determine if the UART is being accessed; see Table 3.

Table 3.

Serial port selection

H = HIGH; L = LOW; X = Don’t care.

Chip Select

Function

CS = H, A7 = X, A6 = X

CS = L, A7 = L, A6 = L

CS = L, A7 = L, A6 = H

CS = L, A7 = H, A6 = X

device not selected

UART selected

device not selected

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

6 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

6.2 Extended mode (128-byte FIFO)

The device is in the extended mode when any of these four registers contains any value

other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL.

6.3 Internal registers

The SC16C850SV provides a set of 25 internal registers for monitoring and controlling the

functions of the UART. These registers are shown in Table 4.

Table 4.

A3 A2 A1 Read mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)^[1]

Internal registers decoding

Write mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

Extra Feature Control Register (EFCR)

n/a

Modem Status Register

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

LSB of Divisor Latch

MSB of Divisor Latch

0

1

MSB of Divisor Latch

Second special register set (TXLVLCNT/RXLVLCNT)^[3]

0

1

Transmit FIFO Level Count

n/a

1

0

Receive FIFO Level Count

Enhanced register set (EFR, Xon1/Xon2, Xoff1/Xoff2)^[4]

0

1

0

1

0

1

0

1

Enhanced Feature Register

Xon1 word

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)^[5]

0

1

0

1

0

1

Transmit FIFO Interrupt Level

Receive FIFO Interrupt Level

Flow Control Count High

Flow Control Count Low

Transmit FIFO Interrupt Level

Receive FIFO Interrupt Level

Flow Control Count High

Flow Control Count Low

Second extra feature register set (CLKPRES, SAMPR, RS485TIME, AFCR2, AFCR1)^[6]

0

1

0

1

0

1

0

1

Clock Prescaler

Sampling Rate

RS-485 turn-around Timer

Advanced Feature Control Register 2

Advanced Feature Control Register 1

RS-485 turn-around Timer

Advanced Feature Control Register 2

Advanced Feature Control Register 1

[1] These registers are accessible only when LCR[7] is a logic 0.

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

7 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

[2] These registers are accessible only when LCR[7] is a logic 1.

[3] Second special registers are accessible only when EFCR[0] = 1.

[4] Enhanced feature registers are only accessible when LCR = 0xBF.

[5] First extra feature registers are only accessible when EFCR[2:1] = 01b.

[6] Second extra feature registers are only accessible when EFCR[2:1] = 10b.

6.4 FIFO operation

6.4.1 32-byte FIFO mode

When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the

First Extra Register Set are empty (0x00) the transmit and receive trigger levels are set by

FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to

the SC16C650B (see Table 5), and the FIFO sizes are 32 entries. The transmit and

receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). It should be

noted that the user can set the transmit trigger levels by writing to the FCR, but activation

will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a

time-out function to ensure data is delivered to the external CPU (see Section 6.8). Please

refer to Table 10 and Table 11 for the setting of FCR[7:4].

Table 5.

Interrupt trigger level and Flow control mechanism

FCR[7:6]

FCR[5:4]

INT pin activation

Negate RTS or Assert RTS

send Xoff

or send Xon

RX

8

TX

16

8

00

01

10

11

00

01

10

11

8

0

16

24

28

16

24

28

7

24

30

15

23

6.4.2 128-byte FIFO mode

When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register

Set contains any value other than 0x00, the transmit and receive trigger levels are set by

TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the transmit

FIFO, and the transmit trigger levels can be set to any value between 1 and 128 with

granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive trigger

levels can be set to any value between 1 and 128 with granularity of 1.

When the effective FIFO size changes (that is, when FCR[0] toggles or when the

combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between

equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will

be lost).

6.5 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C850SV monitors the CTS

pin for a remote buffer overﬂow indication and controls the RTS pin for local buffer

overﬂows. Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and

EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a ﬂow

control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the

SC16C850SV will suspend TX transmissions as soon as the stop bit of the character in

process is shifted out. Transmission is resumed after the CTS input returns to a logic 0,

indicating more data may be sent.

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

8 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

When AFCR1[2] is set to 1, then the function of CTS pin is mapped to the DSR pin, and

the function of RTS is mapped to DTR pin. DSR and DTR pins will behave as described

above for CTS and RTS.

With the automatic hardware ﬂow control function enabled, an interrupt is generated when

the receive FIFO reaches the programmed trigger level. The RTS (or DTR) pin will not be

forced to a logic 1 (RTS off) until the receive FIFO reaches the next trigger level. However,

the RTS (or DTR) pin will return to a logic 0 after the receive buffer (FIFO) is unloaded to

the next trigger level below the programmed trigger level. Under the above described

conditions, the SC16C850SV will continue to accept data until the receive FIFO is full.

When TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the First Extra Register Set

are all zeroes, the hardware and software ﬂow control trigger levels are set by FCR[7:4];

see Table 5.

When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register

Set contains any value other than 0x00, the hardware and software ﬂow control trigger

levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines how

many bytes are in the receive FIFO before RTS (or DTR) is de-asserted or Xoff is sent.

The content of FLWCNTL determines how many bytes are in the receive FIFO before RTS

(or DTR) is asserted, or Xon is sent.

In 128-byte FIFO mode, hardware and software ﬂow control trigger levels can be set to

any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always

be greater than FLWCNTL. The UART does not check for this condition automatically, and

if this condition is not met spurious operation of the device might occur. When using

FLWCNTH and FWLCNTL, these registers must be initialized to the proper values before

hardware or software ﬂow control is enabled via the EFR register.

6.6 Software ﬂow control

When software ﬂow control is enabled, the SC16C850SV compares one or two

sequentially received data characters with the programmed Xon or Xoff character

value(s). If the received character(s) match the programmed Xoff values, the

SC16C850SV will halt transmission (TX) as soon as the current character(s) has

completed transmission. When a match occurs, ISR bit 4 will be set (if enabled via IER[5])

and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a

suspension due to a match of the Xoff characters’ values, the SC16C850SV will monitor

the receive data stream for a match to the Xon1/Xon2 character value(s). If a match is

found, the SC16C850SV will resume operation and clear the ﬂags (ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow control.

Different conditions can be set to detect Xon/Xoff characters and suspend/resume

transmissions (see Table 24). When double 8-bit Xon/Xoff characters are selected, the

SC16C850SV compares two consecutive receive characters with two software ﬂow

control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly.

Under the above described ﬂow control mechanisms, ﬂow control characters are not

placed (stacked) in the receive FIFO. When using software ﬂow control, the Xon/Xoff

characters cannot be used for data transfer.

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

9 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

In the event that the receive buffer is overﬁlling, the SC16C850SV automatically sends an

Xoff character (when enabled) via the serial TX output to the remote UART. The

SC16C850SV sends the Xoff1/Xoff2 characters as soon as the number of received data

in the receive FIFO passes the programmed trigger level. To clear this condition, the

SC16C850SV will transmit the programmed Xon1/Xon2 characters as soon as the

number of characters in the receive FIFO drops below the programmed trigger level.

6.7 Special character detect

A special character detect feature is provided to detect an 8-bit character when EFR[5] is

set. When an 8-bit character is detected, it will be placed on the user-accessible data

stack along with normal incoming RX data. This condition is selected in conjunction with

EFR[3:0] (see Table 24). Note that software ﬂow control should be turned off when using

this special mode by setting EFR[3:0] to all zeroes.

The SC16C850SV compares each incoming receive character with Xoff2 data. If a match

occurs, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate

detection of a special character. Although Table 7 “SC16C850SV internal registers” shows

Xon1, Xon2, Xoff1, Xoff2 with eight bits of character information, the actual number of bits

is dependent on the programmed word length. Line Control Register bits LCR[1:0] deﬁne

the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length

selected by LCR[1:0] also determine the number of bits that will be used for the special

character comparison. Bit 0 in the Xon1, Xon2, Xoff1, Xoff2 registers corresponds with the

LSB bit for the received character.

6.8 Interrupt priority and time-out interrupts

The interrupts are enabled by IER[7:0]. Care must be taken when handling these

interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C850SV

will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to

continuing operations. The ISR indicates the current singular highest priority interrupt

only. A condition can exist where a higher priority interrupt masks the lower priority

interrupt(s) (see Table 12). Only after servicing the higher pending interrupt will the lower

priority interrupt(s) be reﬂected in the status register. Servicing the interrupt without

investigating further interrupt conditions can result in data errors.

Receive Data Ready and Receive Time Out have the same interrupt priority (when

enabled by IER[0]), and it is important to serve these interrupts correctly. The receiver

issues an interrupt after the number of characters have reached the programmed trigger

level. In this case, the SC16C850SV FIFO may hold more characters than the

programmed trigger level. Following the removal of a data byte, the user should re-check

LSR[0] to see if there are any additional characters. A Receive Time Out will not occur if

the receive FIFO is empty. The time-out counter is reset at the center of each stop bit

received or each time the Receive Holding Register (RHR) is read. The actual time-out

value is 4 character time, including data information length, start bit, parity bit, and the

size of stop bit, that is, 1×, 1.5×, or 2× bit times.

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

10 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

6.9 Programmable baud rate generator

The SC16C850SV UART contains a programmable rational baud rate generator that

takes any clock input and divides it by a divisor in the range between 1 and (2¹⁶− 1). The

SC16C850SV offers the capability of dividing the input frequency by rational divisor. The

fractional part of the divisor is controlled by the CLKPRES register in the First Extra

Register Set.

f _XTAL1

baud rate =

(1)

------------------------------------------------------------------------------------------------

M

MCR[7] × SAMPR × N +

-------------------

SAMPR

where:

N is the integer part of the divisor in DLL and DLM registers;

M is the fractional part of the divisor in CLKPRES register;

f_XTAL1is the clock frequency at XTAL1 pin;

SAMPR is the sampling rate in SAMPR register (16×, 8×, 4×); M / SAMPR should

always be less than 1.

Prescaler = 1 when MCR[7] is set to 0.

Prescaler = 4 when MCR[7] is set to 1.

CLKPRES

[3:0]

DIVIDE-BY-1

MCR[7] = 0

XTAL1

BAUD RATE

transmitter and

OSCILLATOR

GENERATOR

(DLL, DLM)

XTAL2

receiver clock

MCR[7] = 1

DIVIDE-BY-4

002aac645

Fig 3. Prescalers and baud rate generator block diagram

A single baud rate generator is provided for the transmitter and receiver. The

programmable Baud Rate Generator is capable of operating with a frequency of up to

80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock

input. The SC16C850SV can be conﬁgured for internal or external clock operation. For

internal clock operation, an industry standard crystal is connected externally between the

XTAL1 and XTAL2 pins (see Figure 4). Alternatively, an external clock can be connected

to the XTAL1 pin (see Figure 5) to clock the internal baud rate generator for standard or

custom rates (see Table 6).

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). The

SC16C850SV divides the basic external clock by 16. The baud rate is conﬁgured via the

CLKPRES, DLL and DLM internal register functions. Customized baud rates can be

achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate

generator. However, the user can also select 8×, 4× sampling rate to operate at four times,

or two times faster than the 16× sampling rate (see Section 7.20 “Sampling rate

(SAMPR)”).

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

11 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB)

provides a user capability for selecting the desired ﬁnal baud rate. The example in Table 6

shows the selectable baud rate table available when using a 1.8432 MHz external clock

input with MCR[7] is 0, SAMPR[1:0] = 00b, and CLKPRES = 0x00.

XTAL1

XTAL2

XTAL1

XTAL2

1.5 kΩ

X1

1.8432 MHz

C1

22 pF

C2

33 pF

C1

22 pF

C2

47 pF

002aaa870

Fig 4. Crystal oscillator connection

XTAL1

XTAL2

100 pF

f

XTAL1

002aac630

If f_XTAL1frequency is greater than 50 MHz, then a DC blocking capacitor is required.

XTAL2 pin should be left unconnected when an external clock is used.

Fig 5. External clock connection

Table 6.

Baud rate generator programming table using a 1.8432 MHz clock with

MCR[7] = 0, SAMPR[1:0] = 00b, and CLKPRE[3:0] = 0

Output

baud rate

(bit/s)

Output

16× clock divisor

(decimal)

Output

16× clock divisor

(hexadecimal)

DLM

program value

(hexadecimal)

DLL

program value

(hexadecimal)

50

2304

1536

1047

768

384

192

96

900

600

417

300

180

C0

60

09

06

04

03

01

00

17

00

80

C0

60

30

20

18

10

0C

06

75

110

150

300

600

1.2 k

2.4 k

3.6 k

4.8 k

7.2 k

9.6 k

19.2 k

48

30

32

20

24

18

16

10

12

0C

06

6

SC16C850SV_1

Product data sheet

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Table 6.

Baud rate generator programming table using a 1.8432 MHz clock with

MCR[7] = 0, SAMPR[1:0] = 00b, and CLKPRE[3:0] = 0 …continued

Output

baud rate

(bit/s)

Output

16× clock divisor

(decimal)

Output

16× clock divisor

(hexadecimal)

DLM

program value

(hexadecimal)

DLL

program value

(hexadecimal)

38.4 k

57.6 k

115.2 k

3

2

1

03

02

01

00

03

02

01

6.10 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally

(see Figure 6). MCR[3:0] register bits are used for controlling loopback diagnostic testing.

In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are

disconnected from their associated interface pins, and instead are connected together

internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control

inputs pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and

MCR[2] (OP1). Loopback test data is entered into the transmit holding register via the

user data bus interface, AD[7:0]. The transmit UART serializes the data and passes the

serial data to the receive UART via the internal loopback connection. The receive UART

converts the serial data back into parallel data that is then made available at the user data

interface AD[7:0]. The user optionally compares the received data to the initial transmitted

data for verifying error-free operation of the UART TX/RX circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The modem

control interrupts are also operational.

SC16C850SV_1

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

SC16C850SV

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTER

AD0 to AD7

IOR

DATA BUS

AND

CONTROL

LOGIC

IOW

RESET

LLA

IR

ENCODER

FLOW

CONTROL

LOGIC

MCR[4] = 1

RECEIVE

FIFO

REGISTER

RECEIVE

SHIFT

REGISTER

RX

IR

DECODER

FLOW

CONTROL

LOGIC

REGISTER

SELECT

LOGIC

CS

RTS

POWER

DOWN

CONTROL

CTS

DTR

LOWPWR

MODEM

CONTROL

LOGIC

DSR

RI

OP1

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

INT

OP2

CD

002aad773

XTAL1

XTAL2

Fig 6. Internal Loopback mode diagram

SC16C850SV_1

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

6.11 Sleep mode

Sleep mode is an enhanced feature of the SC16C850SV UART. It is enabled when

EFR[4], the enhanced functions bit, is set and when IER[4] bit is also set.

6.11.1 Conditions to enter Sleep mode

Sleep mode is entered when:

• Modem input pins are not toggling.

• The serial data input line, RX, is idle for 4 character time (logic HIGH) and AFCR1[4]

is 0. When AFCR1[4] is 1, the device will go to sleep regardless of the state of the RX

pin (see Section 7.22 for the description of AFCR1 bit 4).

• The TX FIFO and TX shift register are empty.

• There are no interrupts pending.

• The RX FIFO is empty.

In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are

clocked using these clocks, the power consumption is greatly reduced.

Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be

done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]

before writing to DLL or DLM.

6.11.2 Conditions to resume normal operation

SC16C850SV resumes normal operation by any of the following:

• Receives a start bit on RX pin.

• Data is loaded into transmit FIFO.

• A change of state on any of the modem input pins.

If the device is awakened by one of the conditions described above, it will return to the

Sleep mode automatically after all the conditions described in Section 6.11.1 are met. The

device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a

logic 0.

When the SC16C850SV is in Sleep mode and the host interface bus (AD7 to AD0, IOW,

IOR, CS) remains in steady state, either HIGH or LOW, the sleep current will be in the

microampere range as speciﬁed in Table 37 “Static characteristics”. If any of these signals

is toggling or ﬂoating then the sleep current will be higher.

6.12 Low power feature

A low power feature is provided by the SC16C850SV to prevent the switching of the host

data bus from inﬂuencing the sleep current. When the pin LOWPWR is activated (logic

HIGH), the device immediately and unconditionally goes into Low Power mode. All clocks

are stopped and most host interface pins are isolated to reduce power consumption. The

device only returns to normal mode when the LOWPWR pin is de-asserted. The pin can

be left unconnected because it has an internal pull-down resistor.

SC16C850SV_1

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

6.13 RS-485 Features

6.13.1 Auto RS-485 RTS control

Normally the RTS pin is controlled by MCR bit 1, or if hardware ﬂow control is enabled, the

logic state of the RTS pin is controlled by the hardware ﬂow control circuitry. EFCR2

register bit 4 will take the precedence over the other two modes; once this bit is set, the

transmitter will control the state of the RTS pin. The transmitter automatically asserts the

RTS pin (logic 0) once the host writes data to the transmit FIFO, and de-asserts the RTS

pin (logic 1) once the last bit of the data has been transmitted.

To use the auto RS-485 RTS mode, the software would have to disable the hardware ﬂow

control function.

6.13.2 RS-485 RTS inversion

EFCR2 bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.

When the transmitter has data to be sent, it will de-assert the RTS pin (logic 1), and when

the last bit of the data has been sent out, the transmitter asserts the RTS pin (logic 0).

6.13.3 Auto 9-bit mode (RS-485)

EFCR2 bit 0 is used to enable the 9-bit mode (Multi-drop or RS-485 mode). In this mode

of operation, a ‘master’ station transmits an address character followed by data characters

for the addressed ‘slave’ stations. The slave stations examine the received data and

interrupt the controller if the received character is an address character (parity bit = 1).

To use the auto 9-bit mode the software would have to disable the hardware and software

ﬂow control functions.

6.13.3.1 Normal Multi-drop mode

The 9-bit Mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5).

The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an

address byte is received (parity bit = 1). This address byte will cause the UART to set the

parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at

this time), and at the same time puts this address byte in the RX FIFO. After the controller

examines the byte it must make a decision whether or not to enable the receiver; it should

enable the receiver if the address byte addresses its ID address, and must not enable the

receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until

being disabled by the controller after the controller has received a complete message from

the ‘master’ station. If the controller does not disable the receiver after receiving a

message from the ‘master’ station, the receiver will generate a parity error upon receiving

another address byte. The controller then determines if the address byte addresses its ID

address, if it is not, the controller then can disable the receiver. If the address byte

addresses the ‘slave’ ID address, the controller take no further action, the receiver will

receive the subsequent data.

SC16C850SV_1

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SC16C850SV

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Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

6.13.3.2 Auto address detection

If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the

address byte), the receiver will try to detect an address byte that matches the

programmed character in the Xoff2 register. If the received byte is a data byte or an

address byte that does not match the programmed character in the Xoff2 register, the

receiver will discard these data. Upon receiving an address byte that matches the Xoff2

character, the receiver will be automatically enabled if not already enabled, and the

address character is pushed into the RX FIFO along with the parity bit (in place of the

parity error bit). The receiver also generates a line status interrupt (IER[2] must be set to

logic 1 at this time). The receiver will then receive the subsequent data from the ‘master’

station until being disabled by the controller after having received a message from the

‘master’ station.

If another address byte is received and this address byte does not match Xoff2 character,

the receiver will be automatically disabled and the address byte is ignored. If the address

byte matches Xoff2 character, the receiver will put this byte in the RX FIFO along with the

parity bit in the parity error bit (LSR bit 2).

7. Register descriptions

Table 7 details the assigned bit functions for the SC16C850SV internal registers. The

assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.24.

SC16C850SV_1

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

7.1 Transmit and Receive Holding Registers (THR and RHR)

The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (AD7 to AD0) to

the transmit FIFO. The THR empty ﬂag in the LSR will be set to a logic 1 when the

transmit FIFO is empty or when data is transferred to the TSR.

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a

Receive Serial Shift Register (RSR). Receive data is removed from the SC16C850SV

receive FIFO by reading the RHR. The receive section provides a mechanism to prevent

false starts. On the falling edge of a start or false start bit, an internal receiver counter

starts counting clocks at the sampling rate. After ^SAMPR⁄₂clocks (SAMPR is the sampling

rate of 16×, 8×, or 4×), the start bit time should be shifted to the center of the start bit. At

this time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start

bit in this manner prevents the receiver from assembling a false character. Receiver status

codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INT output pin.

Table 8.

Interrupt Enable Register bits description

Bit

Symbol Description

7

IER[7]

IER[6]

IER[5]

CTS interrupt.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC16C850SV issues an interrupt when

the CTS pin transitions from a logic 0 to a logic 1.

6

5

RTS interrupt.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC16C850SV issues an interrupt when

the RTS pin transitions from a logic 0 to a logic 1.

Xoff interrupt.

logic 0 = disable the software ﬂow control, receive Xoff interrupt (normal

default condition)

logic 1 = enable the receive Xoff interrupt

Sleep mode.

4

3

IER[4]

IER[3]

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode

Modem Status Interrupt. This interrupt will be issued whenever there is a modem

status change as reﬂected in MSR[3:0].

logic 0 = disable the modem status register interrupt (normal default condition)

logic 1 = enable the modem status register interrupt

2

IER[2]

Receive Line Status interrupt. This interrupt will be issued whenever a receive

data error condition exists as reﬂected in LSR[4:1].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

SC16C850SV_1

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Table 8.

Interrupt Enable Register bits description …continued

Bit

Symbol Description

1

IER[1]

Transmit Holding Register interrupt. In the non-FIFO mode, this interrupt will be

issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO

modes, this interrupt will be issued whenever the FIFO is empty.

logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt

(normal default condition)

logic 1 = enable the TXRDY (ISR level 3) interrupt

0

IER[0]

Receive Holding Register. In the non-FIFO mode, this interrupt will be issued

when the RHR has data, or is cleared when the RHR is empty. In the FIFO mode,

this interrupt will be issued when the FIFO has reached the programmed trigger

level or is cleared when the FIFO drops below the trigger level.

logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal

default condition)

logic 1 = enable the RXRDY (ISR level 2) interrupt

7.2.1 IER versus transmit/receive FIFO interrupt mode operation

When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts

(IER[0] = logic 1) are enabled, the receive interrupts and register status will reﬂect the

following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by the TSR and UART for

transmission via the transmission media. The interrupt is cleared either by reading the

ISR, or by loading the THR with new data characters.

7.2.2 IER versus receive/transmit FIFO polled mode operation

When FCR[0] = logic 1, setting IER[3:0] = zeroes puts the SC16C850SV in the FIFO

polled mode of operation. In this mode, interrupts are not generated and the user must

poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have

separate bits in the LSR either or both can be used in the polled mode by selecting

respective transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will show if any FIFO data errors occurred.

SC16C850SV_1

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger

levels.

7.3.1 FIFO mode

Table 9.

FIFO Control Register bits description

Bit Symbol Description

7:6 FCR[7:6] Receive trigger level in 32-byte FIFO mode.^[1]

These bits are used to set the trigger level for receive FIFO interrupt and ﬂow

control. The SC16C850SV will issue a receive ready interrupt when the number

of characters in the receive FIFO reaches the selected trigger level. Refer to

Table 10.

5:4 FCR[5:4] Transmit trigger level in 32-byte FIFO mode.^[2]

These bits are used to set the trigger level for the transmit FIFO interrupt and

ﬂow control. The SC16C850SV will issue a transmit empty interrupt when the

number of characters in FIFO drops below the selected trigger level. Refer to

Table 11.

3

2

FCR[3]

FCR[2]

reserved

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO counter

logic. This bit will return to a logic 0 after clearing the FIFO.

1

0

FCR[1]

FCR[0]

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO counter

logic. This bit will return to a logic 0 after clearing the FIFO.

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO

[1] For 128-byte FIFO mode, refer to Section 7.16, Section 7.17, Section 7.18.

[2] For 128-byte FIFO mode, refer to Section 7.15, Section 7.17, Section 7.18.

Table 10. RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level in 32-byte FIFO mode^[1]

0

1

0

1

0

1

8 bytes

16 bytes

24 bytes

28 bytes

[1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and

transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “FIFO operation”.

SC16C850SV_1

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SC16C850SV

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Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Table 11. TX FIFO trigger levels

FCR[5]

FCR[4]

TX FIFO trigger level in 32-byte FIFO mode^[1]

0

1

0

1

0

1

16 bytes

8 bytes

24 bytes

30 bytes

[1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and

transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “FIFO operation”.

7.4 Interrupt Status Register (ISR)

The SC16C850SV provides six levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with six

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged until

the pending interrupt is serviced. A lower level interrupt may be seen after servicing the

higher level interrupt and re-reading the interrupt status bits. Table 12 “Interrupt source”

shows the data values (bits 5:0) for the six prioritized interrupt levels and the interrupt

sources associated with each of these interrupt levels.

Table 12. Interrupt source

Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

2

3

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status Register)

RXRDY (Received Data Ready)

RXRDY (Receive Data time-out)

TXRDY (Transmitter Holding

Register Empty)

4

5

0

1

0

MSR (Modem Status Register)

RXRDY (Received Xoff signal)/

Special character

6

1

0

CTS, RTS change of state

Table 13. Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being

used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are

enabled in the SC16C850SV mode.

logic 0 or cleared = default condition

5:4

3:1

ISR[5:4]

ISR[3:1]

INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.

ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]

indicates that CTS, RTS have been generated. Note that once set to a

logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.

logic 0 or cleared = default condition

INT priority bits 2:0. These bits indicate the source for a pending interrupt at

interrupt priority levels 1, 2, and 3 (see Table 12).

logic 0 or cleared = default condition

SC16C850SV_1

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SC16C850SV

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Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Table 13. Interrupt Status Register bits description …continued

Bit

Symbol

Description

0

ISR[0]

INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as a

pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 14. Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6

LCR[6]

Set break. When enabled, the Break control bit causes a break condition to be

transmitted (the TX output is forced to a logic 0 state). This condition exists

until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

5:3

2

LCR[5:3]

LCR[2]

Programs the parity conditions (see Table 15).

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with the

programmed word length (see Table 16).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be transmitted

or received (see Table 17).

logic 0 or cleared = default condition

Table 15. LCR[5:3] parity selection

LCR[5] LCR[4] LCR[3] Parity selection

X

0

1

X

0

1

0

1

0

1

no parity

odd parity

even parity

forced parity ‘1’

forced parity ‘0’

Table 16. LCR[2] stop bit length

LCR[2]

Word length (bits) Stop bit length (bit times)

0

1

5, 6, 7, 8

5

1

1¹⁄₂

6, 7, 8

2

SC16C850SV_1

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SC16C850SV

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Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Table 17. LCR[1:0] word length

LCR[1]

LCR[0]

Word length (bits)

0

1

0

1

0

1

5

6

7

8

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 18. Modem Control Register bits description

Bit Symbol

Description

7

MCR[7]

Clock select

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

IR enable (see Figure 14).

6

MCR[6]

logic 0 = enable the standard modem receive and transmit input/output

interface (normal default condition)

logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this

mode, the TX/RX output/inputs are routed to the infrared encoder/decoder.

The data input and output levels will conform to the IrDA infrared interface

requirement. As such, while in this mode, the infrared TX output will be a

logic 0 during idle data conditions.

5

4

MCR[5]

MCR[4]

Interrupt type.

logic 0 = CMOS output

logic 1 = open-source. A 300 Ω to 500 Ω pull-down resistor is required.

Loopback. Enable the local Loopback mode (diagnostics). In this mode the

transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are

disconnected from the SC16C850SV I/O pins. Internally the modem data and

control pins are connected into a loopback data conﬁguration (see Figure 6). In

this mode, the receiver and transmitter interrupts remain fully operational. The

Modem Control Interrupts are also operational, but the interrupts’ sources are

switched to the lower four bits of the Modem Control. Interrupts continue to be

controlled by the IER register.

logic 0 = disable Loopback mode (normal default condition)

logic 1 = enable local Loopback mode (diagnostics)

3

2

1

MCR[3]

MCR[2]

MCR[1]

OP2. This bit is used for internal Loopback mode only. In Loopback mode, this

bit is used to write the state of the modem CD interface signal.

OP1. This bit is used for internal Loopback mode only. In Loopback mode, this

bit is used to write the state of the modem RI interface signal.

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

0

MCR[0]

DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

25 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Table 19. Interrupt output control

MCR[5]

INT output

active

0

1

open-source

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C850SV and

the CPU.

Table 20. Line Status Register bits description

Bit Symbol Description

7

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when there are no remaining error ﬂags

associated with the remaining data in the FIFO.

6

5

LSR[6]

LSR[5]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the transmit holding register and the transmit shift register are

both empty. It is reset to logic 0 whenever either the THR or TSR contains a data

character. In the FIFO mode, this bit is set to logic 1 whenever the transmit FIFO

and transmit shift register are both empty.

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the transmit holding register into the transmitter shift register. The

bit is reset to a logic 0 concurrently with the loading of the transmitter holding

register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is

empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

LSR[4]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

3

2

LSR[3]

LSR[2]

Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s). In

the FIFO mode, this error is associated with the character at the top of the FIFO.

Parity error.

logic 0 = no parity error (normal default condition

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with the

character at the top of the FIFO.

1

LSR[1]

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the Receive Shift

Register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the Receive Shift Register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

SC16C850SV_1

Product data sheet

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Table 20. Line Status Register bits description …continued

Bit Symbol Description

0

LSR[0]

Receive data ready.

logic 0 = no data in Receive Holding Register or FIFO (normal default condition)

logic 1 = data has been received and is saved in the Receive Holding Register

or FIFO

7.8 Modem Status Register (MSR)

This register shares the same address as EFCR register. This is a read-only register and

it provides the current state of the control interface signals from the modem, or other

peripheral device to which the SC16C850SV is connected. Four bits of this register are

used to indicate the changed information. These bits are set to a logic 1 whenever a

control input from the modem changes state. These bits are set to a logic 0 whenever the

CPU reads this register.

When write, the data will be written to EFCR register.

Table 21. Modem Status Register bits description

Bit

Symbol Description

7

MSR[7]

MSR[6]

MSR[5]

MSR[4]

MSR[3]

CD. During normal operation, this bit is the complement of the CD input.

Reading this bit in the loopback mode produces the state of MCR[3] (OP2).

6

5

4

3

RI. During normal operation, this bit is the complement of the RI input. Reading

this bit in the loopback mode produces the state of MCR[2] (OP1).

DSR. During normal operation, this bit is the complement of the DSR input.

During the loopback mode, this bit is equivalent to MCR[0] (DTR).

CTS. During normal operation, this bit is the complement of the CTS input.

During the loopback mode, this bit is equivalent to MCR[1] (RTS).

∆CD ^[1]

logic 0 = no CD change (normal default condition)

logic 1 = the CD input to the SC16C850SV has changed state since the last

time it was read. A modem Status Interrupt will be generated.

2

1

0

MSR[2]

MSR[1]

MSR[0]

∆RI ^[1]

logic 0 = no RI change (normal default condition)

logic 1 = the RI input to the SC16C850SV has changed from a logic 0 to a

logic 1. A modem Status Interrupt will be generated.

∆DSR ^[1]

logic 0 = no DSR change (normal default condition)

logic 1 = the DSR input to the SC16C850SV has changed state since the last

time it was read. A modem Status Interrupt will be generated.

∆CTS ^[1]

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C850SV has changed state since the last

time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

27 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

7.9 Extra Feature Control Register (EFCR)

This is a write-only register, and it allows the software access to these registers:

First Extra Register Set, Second Extra Register Set, Transmit FIFO Level Counter

(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).

Table 22. Extra Feature Control Register bits description

Bit

7:3

2:1

Symbol

Description

EFCR[7:3] reserved

EFCR[2:1] Enable Extra Feature Control bits

00 = General Register Set is accessible

01 = First Extra Register Set is accessible

10 = Second Extra Register Set is accessible

11 = reserved

0

EFCR[0]

Enable TXLVLCNT and RXLVLCNT access

0 = TXLVLCNT and RXLVLCNT are disabled

1 = TXLVLCNT and RXLVLCNT are enabled and can be read

Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can

only be accessed if EFCR[2:1] are zeroes.

7.10 Scratchpad Register (SPR)

The SC16C850SV provides a temporary data register to store 8 bits of user information.

7.11 Division Latch (DLL and DLM)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock

in the baud rate generator. DLM stores the most signiﬁcant part of the divisor. DLL stores

the least signiﬁcant part of the divisor.

7.12 Transmit FIFO Level Count (TXLVLCNT)

This register is a read-only register. It reports the number of spaces available in the

transmit FIFO.

7.13 Receive FIFO Level Count (RXLVLCNT)

This register is a read-only register. It reports the ﬁll level of the receive FIFO (the number

of characters in the RXFIFO).

SC16C850SV_1

Product data sheet

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

7.14 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bit 0 through bit 4 provide single or dual character software ﬂow control selection. When

the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words

are concatenated into two sequential numbers.

Table 23. Enhanced Feature Register bits description

Bit

Symbol Description

7

EFR[7]

Automatic CTS ﬂow control.

logic 0 = automatic CTS ﬂow control is disabled (normal default condition)

logic 1 = enable automatic CTS ﬂow control. Transmission will stop when

CTS goes to a logical 1. Transmission will resume when the CTS signal

returns to a logical 0.

6

EFR[6]

Automatic RTS ﬂow control. Automatic RTS may be used for hardware ﬂow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be

generated when the receive FIFO is ﬁlled to the programmed trigger level and

RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when

data is unloaded below the next lower trigger level (programmed trigger level 1).

The state of this register bit changes with the status of the hardware ﬂow

control. RTS functions normally when hardware ﬂow control is disabled.

logic 0 = automatic RTS ﬂow control is disabled (normal default condition)

logic 1 = enable automatic RTS ﬂow control

5

EFR[5]

Special Character Detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. The SC16C850SV compares each

incoming receive character with Xoff2 data. If a match exists, the received

data will be transferred to FIFO and ISR[4] will be set to indicate detection of

special character. Bit-0 in the X-registers corresponds with the LSB bit for the

receive character. When this feature is enabled, the normal software ﬂow

control must be disabled (EFR[3:0] must be set to a logic 0).

4

EFR[4]

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and

MCR[7:5] can be modiﬁed and latched. After modifying any bits in the enhanced

registers, EFR[4] can be set to a logic 0 to latch the new values. This feature

prevents existing software from altering or overwriting the SC16C850SV

enhanced functions.

logic 0 = disable/latch enhanced features^[1]

logic 1 = enables the enhanced functions^[1]. When this bit is set to a logic 1,

all enhanced features of the SC16C850SV are enabled and user settings

stored during a reset will be restored.

3:0

EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming these

bits. See Table 24.

[1] Enhanced function control bits: IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5].

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

29 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Table 24. Software ﬂow control functions^[1]

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software ﬂow controls

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

X

0

1

No transmit ﬂow control

Transmit Xon1/Xoff1

Transmit Xon2/Xoff2

Transmit Xon1 and Xon2/Xoff1 and Xoff2

No receive ﬂow control

Receiver compares Xon1/Xoff1

Receiver compares Xon2/Xoff2

Transmit Xon1/Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon2/Xoff2

0

1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

[1] When using a software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

7.15 Transmit Interrupt Level register (TXINTLVL)

This 8-bit register is used store the transmit FIFO trigger levels used for interrupt

generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.

Table 25 shows trigger level register bit settings.

Table 25. TXINTLVL register bits description

Bit

Symbol

Description

7:0

TXINTLVL[7:0] This register stores the programmable transmit interrupt trigger levels for

128-byte FIFO mode.^[1]

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.

7.16 Receive Interrupt Level register (RXINTLVL)

This 8-bit register is used store the receive FIFO trigger levels used for interrupt

generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.

Table 26 shows trigger level register bit settings.

Table 26. RXINTLVL register bits description

Bit

Symbol

Description

7:0

RXINTLVL[7:0] This register stores the programmable receive interrupt trigger levels for

128-byte FIFO mode.^[1]

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

30 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.

7.17 Flow Control Trigger Level High (FLWCNTH)

This 8-bit register is used to store the receive FIFO high threshold levels to start/stop

transmission during hardware/software ﬂow control. Table 27 shows transmission control

register bit settings; see Section 6.5.

Table 27. FLWCNTH register bits description

Bit

Symbol

Description

7:0

FLWCNTH[7:0]

This register stores the programmable HIGH threshold level for

hardware and software ﬂow control for 128-byte FIFO mode.^[1]

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.

7.18 Flow Control Trigger Level Low (FLWCNTL)

This 8-bit register is used to store the receive FIFO low threshold levels to start/stop

transmission during hardware/software ﬂow control. Table 28 shows transmission control

register bit settings; see Section 6.5.

Table 28. FLWCNTL register bits description

Bit

Symbol

Description

7:0

FLWCNTL[7:0] This register stores the programmable LOW threshold level for

hardware and software ﬂow control for 128-byte FIFO mode.^[1]

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.

7.19 Clock prescaler (CLKPRES)

This register hold values for the clock prescaler.

Table 29. Clock prescaler register description

Bit

7:4

3:0

Symbol

Description

CLKPRES[7:4] reserved

CLKPRES[3:0] clock prescaler value; reset to 0

SC16C850SV_1

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

7.20 Sampling rate (SAMPR)

Bit 1 and bit 0 of this register program the device’s sampling rate.

Table 30. Sampling rate register bits description

Bit

7:2

1:0

Symbol

Description

reserved

SAMPR[7:2]

SAMPR[1:0]

sampling rate

00 = 16×

01 = 8×

10 = 4×

11 = reserved

7.21 RS-485 turn-around time delay (RS485TIME)

The value in this register controls the turn-around time of the external line transceiver in

bit time. In automatic 9-bit mode, the RTS or DTR pin is used to control the direction of the

line driver, after the last bit of data has been shifted out of the transmit shift register the

UART will count down the value in this register. When the count value reaches zero, the

UART will assert the RTS or DTR pin (logic 0) to turn the external RS-485 transceiver

around for receiving.

Table 31. RS-485 programmable turn-around time register

Bit

Symbol

Description

7:0

RS485TIME[7:0] External RS-485 transceiver turn-around time delay. The value

represents the bit time at the programmed baud rate.

7.22 Advanced Feature Control Register 1 (AFCR1)

Table 32. Advanced Feature Control Register 1 bits description

Bit

7:5

4

Symbol

Description

AFCR1[7:5] reserved

AFCR1[4]

Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.

logic 0 = RX input is level sensitive. If RX pin is LOW, the UART will not

go to sleep. Once the UART is in Sleep mode, it will wake up if RX pin

goes LOW.

logic 1 = RX input is edge sensitive. UART will go to sleep even if RX pin

is LOW, and will wake up when RX pin toggles.

3

2

AFCR1[3]

AFCR1[2]

reserved

RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to

DTR/DSR.

logic 0 = RTS and CTS signals are used for hardware ﬂow control

logic 1 = DTR and DSR signals are used for hardware ﬂow control. RTS

and CTS retain their functionality.

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

Table 32. Advanced Feature Control Register 1 bits description …continued

Bit

Symbol

Description

1

AFCR1[1]

SReset. Software reset. A write to this bit will reset the UART. Once the

UART is reset this bit is automatically set to logic 0.^[1]

0

AFCR1[0]

TSR interrupt. Select TSR interrupt mode.

logic 0 = transmit empty interrupt occurs when transmit FIFO falls below

the trigger level or becomes empty.

logic 1 = transmit empty interrupt occurs when transmit FIFO fall below

the trigger level, or becomes empty and the last stop bit has been shift

out the transmit shift register.

[1] It takes 4 XTAL1 clocks to reset the device.

7.23 Advanced Feature Control Register 2 (AFCR2)

Table 33. Advanced Feature Control Register 2 bits description

Bit

7:6

5

Symbol

Description

AFCR2[7:6] reserved

AFCR2[5]

RTSInvert. Invert RTS or DTR signal in auto 9-bit mode.

logic 0 = RTS or DTR is set to 0 by the UART during transmission, and to

1 during reception

logic 1 = RTS or DTR is set to 1 by the UART during transmission, and to

0 during reception

4

3

AFCR2[4]

AFCR2[3]

RTSCon. Enable the transmitter to control RTS or DTR signal in auto 9-bit

mode.

logic 0 = transmitter does not control RTS or DTR signal

logic 1 = transmitter controls RTS or DTR signal

RS485 RTS/DTR. Select RTS or DTR pin to control the external

transceiver.

logic 0 = RTS pin is used to control the external transceiver

logic 1 = DTR pin is used to control the external transceiver

TXDisable. Disable transmitter.

2

1

0

AFCR2[2]

AFCR2[1]

AFCR2[0]

logic 0 = transmitter is enabled

logic 1 = transmitter is disabled

RXDisable. Disable receiver.

logic 0 = receiver is enabled

logic 1 = receiver is disabled

9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode.

logic 0 = normal RS-232 mode

logic 1 = enable 9-bit mode

SC16C850SV_1

Product data sheet

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

7.24 SC16C850SV external reset condition and software reset

These two reset methods are identical and will reset the internal registers as indicated in

Table 34.

Table 34. Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

FCR

FCR[7:0] = 0

ISR

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

MCR[7:0] = 0

LSR

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

EFCR[7:0] = 0

MSR

EFCR

SPR

SPR[7:0] = 1

DLL

undeﬁned

DLM

undeﬁned

TXLVLCNT

RXLVLCNT

EFR

TXLVLCNT[7:0] = 0

RXLVLCNT[7:0] = 0

EFR[7:0] = 0

Xon1

undeﬁned

Xon2

undeﬁned

Xoff1

undeﬁned

Xoff2

undeﬁned

TXINTLVL

RXINTLVL

FLWCNTH

FLWCNTL

CLKPRES

SAMPR

RS485TIME

AFCR2

AFCR1

TXINTLVL[7:0] = 0

RXINTLVL[7:0] = 0

FLWCNTH[7:0] = 0

FLWCNTL[7:0] = 0

CLKPRES[7:0] = 0

SAMPR[7:0] = 0

RS485TIME[7:0] = 0

AFCR2[7:0] = 0

AFCR1[7:0] = 0

Table 35. Reset state for outputs

Output

TX

Reset state

logic 1

RTS

DTR

INT

logic 1

3-state condition

SC16C850SV_1

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

8. Limiting values

Table 36. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V

V_DD

V_n

supply voltage

-

2.5

[1]

voltage on any other pin

ambient temperature

storage temperature

V_SS− 0.3 V_DD+ 0.3

V

T_amb

T_stg

operating in free air

−40

−65

-

+85

°C

mW

+150

500

P_tot/pack total power dissipation per

package

[1] V_nshould not exceed 2.5 V.

9. Static characteristics

Table 37. Static characteristics

T_amb= −40 °C to +85 °C; V_DD= 1.65 V to 1.95 V; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V

V_IL(clk)

V_IH(clk)

V_IL

clock LOW-level input voltage

-

0.25

clock HIGH-level input voltage

LOW-level input voltage

HIGH-level input voltage

LOW-level output voltage

HIGH-level output voltage

1.35

-

V

except XTAL1 clock

I_OL= 2 mA

-

0.45

V

V_IH

1.35

-

V

[1]

V_OL

-

0.35

V

V_OH

I_LIL

I_OH= −800 µA

1.45

-

V

LOW-level input leakage

current

1

µA

I_LIH

HIGH-level input leakage

current

-

1

µA

I_L(clk)

clock leakage current

LOW-level

HIGH-level

f = 5 MHz

-

30

2

µA

mA

µA

I_DD

supply current

[2]

[3]

I_DD(sleep)sleep mode supply current

5

I_DD(lp)

low-power mode supply

current

5

C_i

input capacitance

-

5

pF

[1] Except XTAL2.

[2] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode.

[3] Activate by LOWPWR pin.

SC16C850SV_1

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SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

10. Dynamic characteristics

Table 38. Dynamic characteristics

T_amb= −40 °C to +85 °C; V_DD= 1.65 V to 1.95 V; unless otherwise speciﬁed.

Symbol

f_XTAL1

Parameter

Conditions

Min

-

Typ

Max

Unit

MHz

ns

[1]

frequency on pin XTAL1

-

80

-

t_d(CS-LLAH)

t_su(A-LLAH)

t_w(LLA)

delay time from CS to LLA HIGH

set-up time from address to LLA HIGH

LLA pulse width time

10

5

-

ns

10

-

ns

t_h(LLAH-A)

t_d(IOW)

t_d(IOR-DV)

t_w(IOR)

t_d(LLAH-IORL)

t_w(IOW)

address hold time after LLA HIGH

IOW delay time

-

ns

-

ns

delay time from IOR to data valid

IOR pulse width time

25 pF load

40

-

ns

28

10

5

ns

delay time from LLA HIGH to IOR LOW

IOW pulse width time

-

ns

-

ns

t_h(IOWH-D)

t_d(LLAH-IOWL)

t_su(D-IOWH)

t_d(IOR)

data input hold time after IOW HIGH

delay time from LLA HIGH to IOW LOW

set-up time from data input to IOW HIGH

IOR delay time

-

ns

10

5

-

ns

-

ns

10

-

ns

t_dis(IOR-QZ)

disable time from IOR to high-impedance

data output^[2]

25 pF load

20

ns

t_d(IOW-Q)

t_d(modem-INT)

t_d(IOR-INTL)

t_WH

delay time from IOW to data output

delay time from modem to INT

delay time from IOR to INT LOW

pulse width HIGH

25 pF load

-

50

ns

s

-

50

-

50

6

-

t_WL

pulse width LOW

6

-

t_w(clk)

clock pulse width

12.5

-

[3]

t_d(stop-INT)

t_d(start-INT)

t_d(IOW-TX)

t_d(IOW-INTL)

t_{w(RESET_N)}

delay time from stop to INT

delay time from start to INT

delay time from IOW to TX

delay time from IOW to INT LOW

pulse width on pin RESET

25 pF load

-

1T_RCLK

24T_RCLK

50

-

s

8T_RCLK

s

25 pF load

-

ns

10

-

[1] External clock only; maximum crystal frequency is 24 MHz.

[2] 10 % of the data bus output voltage level.

[3] RCLK is an internal frequency and it is equal to 16 times the baud rate.

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

36 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

10.1 Timing diagrams

AD7 to AD0

upper address

lower address

su(A-LLAH)

data

t

h(LLAH-A)

CS

t

d(CS-LLAH)

t

h(IOWH-D)

t

w(LLA)

LLA

t

su(D-IOWH)

t

d(LLAH-IOWL)

t

d(IOW)

w(IOW)

IOW

002aac354

Fig 7. General write timing

AD7 to AD0

upper address

lower address

su(A-LLAH)

data

t

dis(IOR-QZ)

h(LLAH-A)

CS

t

d(CS-LLAH)

t

w(LLA)

LLA

t

d(IOR-DV)

t

d(IOR)

t

d(LLAH-IORL)

t

w(IOR)

IOR

002aac355

Fig 8. General read timing

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

37 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

active

IOW

RTS

t

d(IOW-Q)

change of state

DTR

CD

CTS

DSR

change of state

t

d(modem-INT)

active

INT

active

t

d(IOR-INTL)

active

IOR

t

d(modem-INT)

change of state

RI

002aac559

Fig 9. Modem input/output timing

t

WH

WL

external clock

t

w(clk)

002aac357

1

f _XTAL1

=

--------------

t_w(clk)

Fig 10. External clock timing

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

38 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

RX

D0

D1

D2

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

d(stop-INT)

active

INT

t

d(IOR-INTL)

active

IOR

16 baud rate clock

002aac560

Fig 11. Receive timing

start

bit

parity stop start

bit

data bits (0 to 7)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

active

INT

transmitter ready

t

d(start-INT)

t

d(IOW-INTL)

t

d(IOW-TX)

active

IOW

active

16 baud rate clock

002aac561

Fig 12. Transmit timing

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

39 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

UART frame

start

0

data bits

stop

1

0

1

0

1

0

TX data

IrDA TX data

1

/

bit time

2

bit

time

3

/

bit time

16

002aaa212

Fig 13. Infrared transmit timing

IrDA RX data

bit

time

0 to 1 16× clock delay

0

1

0

1

0

1

0

1

RX data

start

data bits

stop

UART frame

002aaa213

Fig 14. Infrared receive timing

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

40 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

11. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w

9

16

L

17

8

e

E

h

2

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 15. Package outline SOT617-1 (HVQFN32)

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

41 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

42 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 16) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 39 and 40

Table 39. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 40. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 16.

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

43 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 16. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

13. Abbreviations

Table 41. Abbreviations

Acronym

CMOS

CPU

Description

Complementary Metal-Oxide Semiconductor

Central Processing Unit

FIFO

IrDA

First In, First Out

Infrared Data Association

ISDN

LSB

Integrated Service Digital Network

Least Signiﬁcant Bit

MSB

Most Signiﬁcant Bit

PCB

Printed-Circuit Board

RoHS

UART

VLIO

Restriction of Hazardous Substances directive

Universal Asynchronous Receiver/Transmitter

Variable Latency Input/Output

14. Revision history

Table 42. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

SC16C850SV_1

20080708

Product data sheet

-

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

44 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

SC16C850SV_1

Product data sheet

Rev. 01 — 8 July 2008

45 of 46

SC16C850SV

NXP Semiconductors

Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.11

7.12

7.13

7.14

7.15

Division Latch (DLL and DLM) . . . . . . . . . . . . 28

Transmit FIFO Level Count (TXLVLCNT) . . . . 28

Receive FIFO Level Count (RXLVLCNT) . . . . 28

Enhanced Feature Register (EFR). . . . . . . . . 29

Transmit Interrupt Level register

(TXINTLVL) . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Receive Interrupt Level register

(RXINTLVL) . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Flow Control Trigger Level High

(FLWCNTH) . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Flow Control Trigger Level Low

(FLWCNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Clock prescaler (CLKPRES) . . . . . . . . . . . . . 31

Sampling rate (SAMPR). . . . . . . . . . . . . . . . . 32

RS-485 turn-around time delay

(RS485TIME) . . . . . . . . . . . . . . . . . . . . . . . . . 32

Advanced Feature Control Register 1

(AFCR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Advanced Feature Control Register 2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.16

7.17

7.18

6

6.1

6.2

6.3

Functional description . . . . . . . . . . . . . . . . . . . 6

UART selection. . . . . . . . . . . . . . . . . . . . . . . . . 6

Extended mode (128-byte FIFO) . . . . . . . . . . . 7

Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 7

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 8

32-byte FIFO mode. . . . . . . . . . . . . . . . . . . . . . 8

128-byte FIFO mode. . . . . . . . . . . . . . . . . . . . . 8

Hardware ﬂow control. . . . . . . . . . . . . . . . . . . . 8

Software ﬂow control . . . . . . . . . . . . . . . . . . . . 9

Special character detect . . . . . . . . . . . . . . . . . 10

Interrupt priority and time-out interrupts . . . . . 10

Programmable baud rate generator . . . . . . . . 11

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 13

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Conditions to enter Sleep mode . . . . . . . . . . . 15

Conditions to resume normal operation . . . . . 15

Low power feature . . . . . . . . . . . . . . . . . . . . . 15

RS-485 Features . . . . . . . . . . . . . . . . . . . . . . 16

Auto RS-485 RTS control . . . . . . . . . . . . . . . . 16

RS-485 RTS inversion . . . . . . . . . . . . . . . . . . 16

Auto 9-bit mode (RS-485). . . . . . . . . . . . . . . . 16

7.19

7.20

7.21

6.4

6.4.1

6.4.2

6.5

6.6

6.7

7.22

7.23

7.24

6.8

6.9

(AFCR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SC16C850SV external reset condition and

software reset. . . . . . . . . . . . . . . . . . . . . . . . . 34

6.10

6.11

6.11.1

6.11.2

6.12

6.13

6.13.1

6.13.2

6.13.3

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 35

Static characteristics . . . . . . . . . . . . . . . . . . . 35

Dynamic characteristics. . . . . . . . . . . . . . . . . 36

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 37

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 41

9

10

10.1

11

12

Soldering of SMD packages . . . . . . . . . . . . . . 42

Introduction to soldering. . . . . . . . . . . . . . . . . 42

Wave and reﬂow soldering . . . . . . . . . . . . . . . 42

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 42

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 43

6.13.3.1 Normal Multi-drop mode. . . . . . . . . . . . . . . . . 16

6.13.3.2 Auto address detection. . . . . . . . . . . . . . . . . . 17

12.1

12.2

12.3

12.4

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 17

Transmit and Receive Holding Registers

13

14

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44

Revision history . . . . . . . . . . . . . . . . . . . . . . . 44

(THR and RHR) . . . . . . . . . . . . . . . . . . . . . . . 20

Interrupt Enable Register (IER) . . . . . . . . . . . 20

IER versus transmit/receive FIFO interrupt

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 21

IER versus receive/transmit FIFO polled

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 21

FIFO Control Register (FCR) . . . . . . . . . . . . . 22

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Interrupt Status Register (ISR) . . . . . . . . . . . . 23

Line Control Register (LCR) . . . . . . . . . . . . . . 24

Modem Control Register (MCR) . . . . . . . . . . . 25

Line Status Register (LSR). . . . . . . . . . . . . . . 26

Modem Status Register (MSR). . . . . . . . . . . . 27

Extra Feature Control Register (EFCR) . . . . . 28

Scratchpad Register (SPR) . . . . . . . . . . . . . . 28

7.2

7.2.1

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 45

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 45

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45

15.1

15.2

15.3

15.4

7.2.2

7.3

7.3.1

7.4

7.5

7.6

7.7

7.8

7.9

7.10

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 45

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 July 2008

Document identifier: SC16C850SV_1


型号：	SC16C850SVIBS
厂家：	NXP
描述：	1.8 V single UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface 1.8 V单UART， 20兆位/秒（最大值）为128字节的FIFO ，红外（ IrDA）以及和XScale VLIO总线接口微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
文件：	总46页 (文件大小：217K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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