SC18IS602BIPW [NXP]
I2C-bus to SPI bridge; I2C总线以SPI桥
| 型号： | SC18IS602BIPW |
| 厂家： | 
NXP |
| 描述： | I2C-bus to SPI bridge |
| 文件： | 总25页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC18IS602/602B/603
I2C-bus to SPI bridge
Rev. 04 — 11 March 2008
Product data sheet
1. General description
The SC18IS602/602B and SC18IS603 are designed to serve as an interface between a
standard I2C-bus of a microcontroller and an SPI bus. This allows the microcontroller to
communicate directly with SPI devices through its I2C-bus. The SC18IS602/602B/603
operates as an I2C-bus slave-transmitter or slave-receiver and an SPI master. The
SC18IS602/602B/603 controls all the SPI bus-specific sequences, protocol, and timing.
The SC18IS602/602B has its own internal oscillator, while the SC18IS603 requires an
external clock source for operation. SC18IS602 and SC18IS603 do not support SS2
function as SPI slave select signal; this pin can only be used as GPIO2.
2. Features
I I2C-bus slave interface operating up to 400 kHz
I SPI master operating up to 1.8 Mbit/s (SC18IS602/602B) or 4 Mbit/s (SC18IS603)
I 200-byte data buffer
I Up to four slave select outputs
I Up to four programmable I/O pins
I Operating supply voltage: 2.4 V to 3.6 V
I Low power mode
I Internal oscillator option
I Active LOW interrupt output
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 that exceeds 100 mA
I Very small 16-pin TSSOP
3. Applications
I Converting I2C-bus to SPI
I Adding additional SPI bus controllers to an existing system
SC18IS602/602B/603
NXP Semiconductors
I2C-bus to SPI bridge
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
SC18IS602IPW
SC18IS602BIPW
SC18IS603IPW
TSSOP16
TSSOP16
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
SOT403-1
SOT403-1
5. Block diagram
MOSI
MISO
SPICLK
SS0
SCL
SDA
2
I C-BUS
BUFFER
SPI
SS1
(1)
SS2
SS3
CONTROL
REGISTER
SC18IS602
SC18IS602B
RESET
INT
INTERRUPT
CONTROL
LOGIC
INTERNAL
OSCILLATOR
002aac443
(1) Unused slave select outputs may be used for GPIO.
Fig 1. Block diagram of SC18IS602/602B
MOSI
MISO
SPICLK
SS0
SCL
2
I C-BUS
BUFFER
SDA
SPI
(1)
SS1
SS2
CONTROL
REGISTER
SC18IS603
RESET
INT
INTERRUPT
CONTROL
LOGIC
OSCILLATOR
CLKIN
002aac444
(1) Unused slave select outputs may be used for GPIO; SC18IS603 does not have SS3.
Fig 2. Block diagram of SC18IS603
SC18IS602_602B_603_4
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Product data sheet
Rev. 04 — 11 March 2008
2 of 25
SC18IS602/602B/603
NXP Semiconductors
I2C-bus to SPI bridge
6. Pinning information
6.1 Pinning
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SS0/GPIO0
SS1/GPIO1
RESET
A2
SS0/GPIO0
SS1/GPIO1
RESET
A2
A1
A1
A0
A0
V
SS3/GPIO3
V
CLKIN
SS
SS
SC18IS602IPW
SC18IS602BIPW
SC18IS603IPW
MISO
MOSI
SDA
V
MISO
MOSI
SDA
V
DD
DD
SPICLK
SS2/GPIO2
INT
SPICLK
SS2/GPIO2
INT
SCL
SCL
002aac441
002aac442
a. SC18IS602/602B
Fig 3. Pin configuration for TSSOP16
b. SC18IS603
6.2 Pin description
Table 2.
Symbol
Pin description
Pin
Type
Description
SC18IS602,
SC18IS602B
SC18IS603
SS0/GPIO0
SS1/GPIO1
RESET
VSS
1
1
I/O
SPI slave select output 0 (active LOW) or GPIO 0
SPI slave select output 1 (active LOW) or GPIO 1
reset input (active LOW)
ground supply
2
2
I/O
3
3
I
4
4
-
MISO
5
5
I
Master In, Slave Out
MOSI
6
6
O
I/O
I
Master Out, Slave In
I2C-bus data
I2C-bus clock
SDA
7
7
SCL
8
8
INT
9
9
O
I/O
O
-
interrupt output (active LOW)
SPI slave select output 2 (active LOW) or GPIO 2
SPI clock
SS2/GPIO2
SPICLK
VDD
10[1][2]
11
12
13
-
10[1]
11
12
-
supply voltage
SS3/GPIO3
CLKIN
A0
I/O
I
SPI slave select output 3 (active LOW) or GPIO 3
external clock input
13
14
15
16
14
15
16
I
address input 0
A1
I
address input 1
A2
I
address input 2
[1] SC18IS602IPW and SC18IS603IPW do not support SS2. This pin should be used as GPIO2 only.
[2] SC18IS602BIPW does support SS2/GPIO2 function. This pin can be used as SS2 or GPIO2.
SC18IS602_602B_603_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 11 March 2008
3 of 25
SC18IS602/602B/603
NXP Semiconductors
I2C-bus to SPI bridge
7. Functional description
The SC18IS602/602B/603 acts as a bridge between an I2C-bus and an SPI interface. It
allows an I2C-bus master device to communicate with any SPI-enabled device.
7.1 I2C-bus interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves
• Multi-master bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
• The I2C-bus may be used for test and diagnostic purposes
A typical I2C-bus configuration is shown in Figure 4. (Refer to NXP Semiconductors’
UM10204, “I2C-bus specification and user manual”, document order number
9398 393 40011.)
V
DD
R
PU
R
PU
SDA
SCL
2
I C-bus
2
2
I C-BUS
DEVICE
I C-BUS
SC18IS602/602B/603
DEVICE
002aac445
Fig 4. I2C-bus configuration
The SC18IS602/602B/603 device provides a byte-oriented I2C-bus interface that supports
data transfers up to 400 kHz. When the I2C-bus master is reading data from SC18IS60x,
the device will be a slave-transmitter. The SC18IS60x will be a slave-receiver when the
I2C-bus master is sending data. At no time does the SC18IS60x act as an I2C-bus master,
however, it does have the ability to hold the SCL line LOW between bytes to complete its
internal processes.
SC18IS602_602B_603_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 11 March 2008
4 of 25
SC18IS602/602B/603
NXP Semiconductors
I2C-bus to SPI bridge
7.1.1 Addressing
R/W
slave address
0
1
0
1
A2 A1 A0
programmable
X
fixed
002aac446
Fig 5. Slave address
The first seven bits of the first byte sent after a START condition defines the slave address
of the device being accessed on the bus. The eighth bit determines the direction of the
message. A ‘0’ in the least significant position of the first byte means that the master will
write information to a selected slave. A ‘1’ in this position means that the master will read
information from the slave. When an address is sent, each device in a system compares
the first seven bits after the START condition with its address. If they match, the device
considers itself addressed by the master as a slave-receiver or slave-transmitter,
depending on the R/W bit.
A slave address of the SC18IS602/602B/603 is comprised of a fixed and a programmable
part. The programmable part of the slave address enables the maximum possible number
of such devices to be connected to the I2C-bus. Since the SC18IS602/602B/603 have
three programmable address bits (defined by the A2, A1, and A0 pins), it is possible to
have eight of these devices on the same bus.
The state of the A2, A1, and A0 pins are latched at reset. Changes made after reset will
not alter the address.
7.1.2 Write to data buffer
All communications to or from the SC18IS602/602B/603 occur through the data buffer.
The data buffer is 200 bytes deep. A message begins with the SC18IS60x address,
followed by the Function ID. Depending upon the Function ID, zero to 200 data bytes can
follow.
The SC18IS60x will place the data received into a buffer and continue loading the buffer
until a STOP condition is received. After the STOP condition is detected, further
communications will not be acknowledged until the function designated by the Function ID
has been completed.
S
SLAVE ADDRESS
W
A
FUNCTION ID
A
0 TO 200 BYTES
A
P
002aac447
Fig 6. Write to data buffer
7.1.3 SPI read and write - Function ID 01h to 0Fh
Data in the buffer will be sent to the SPI port if the Function ID is 01h to 0Fh. The Function
ID contains the Slave Select (SS) to be used for the transmission on the SPI port. There
are four Slave Selects that can be used, with each SS being selected by one of the bits in
SC18IS602_602B_603_4
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Product data sheet
Rev. 04 — 11 March 2008
5 of 25
SC18IS602/602B/603
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I2C-bus to SPI bridge
the Function ID. There is no restriction on the number or combination of Slave Selects that
can be enabled for an SPI message. If more than one SSn pin is enabled at one time, the
user should be aware of possible contention on the data outputs of the SPI slave devices.
Table 3.
Function ID 01h to 0Fh
7
6
5
4
3
2
1
0
0
0
0
0
SS3[1]
SS2[2]
SS1
SS0
[1] SS3 does not exist in the SC18IS603.
[2] SS2 does not exist in the SC18IS602 and SC18IS603. Only SC18IS602B supports this function.
The data on the SPI port will contain the same information as the I2C-bus data, but without
the slave address and Function ID. For example, if the message shown in Figure 7 is
transmitted on the I2C-bus, the SPI bus will send the message shown in Figure 8.
write to buffer
SLAVE ADDRESS
FUNCTION
S
W
A
A
DATA 1
A
A
DATA n
A
P
ID
002aac448
Fig 7. I2C-bus message
SPI data
DATA 1
DATA n
002aac451
Fig 8. SPI message
The SC18IS602/602B/603 counts the number of data bytes sent to the I2C-bus port and
will automatically send this same number of bytes to the SPI bus. As the data is
transmitted from the MOSI pin, it is also read from the MISO pin and saved in the data
buffer. Therefore, the old data in the buffer is overwritten. The data in the buffer can then
be read back.
If the data from the SPI bus needs to be returned to the I2C-bus master, the process must
be completed by reading the data buffer. Section 8 gives an example of an SPI read.
7.1.4 Read from buffer
A read from the data buffer requires no Function ID. The slave address with the R/W bit
set to a ‘1’ will cause the SC18IS602/602B/603 to send the buffer contents to the I2C-bus
master. The buffer contents are not modified during the read process.
S
SLAVE ADDRESS
R
A
DATA 1
A
A
DATA n
NA
P
002aac449
Fig 9. Read from buffer
A typical write and read from an SPI EEPROM is shown in Section 8.
SC18IS602_602B_603_4
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Product data sheet
Rev. 04 — 11 March 2008
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SC18IS602/602B/603
NXP Semiconductors
I2C-bus to SPI bridge
7.1.5 Configure SPI Interface - Function ID F0h
The SPI hardware operating mode, data direction, and frequency can be changed by
sending a ‘Configure SPI Interface’ command to the I2C-bus.
S
SLAVE ADDRESS
W
A
F0h
A
DATA
A
P
002aac450
Fig 10. Configure SPI Interface
After the SC18IS602/602B/603 address is transmitted on the bus, the Configure SPI
Interface Function ID (F0h) is sent followed by a byte which will define the SPI
communications.
The Clock Phase bit (CPHA) allows the user to set the edges for sampling and changing
data. The Clock Polarity bit (CPOL) allows the user to set the clock polarity. Figure 20 and
Figure 21 show the different settings of Clock Phase bit CPHA.
Table 4.
Bit
Configure SPI Interface (F0h) bit allocation
7
X
X
6
X
X
5
ORDER
0
4
X
X
3
2
1
F1
0
0
F0
0
Symbol
Reset
MODE1 MODE0
0
0
Table 5.
Configure SPI Interface (F0h) bit description
Bit
7:6
5
Symbol
-
Description
reserved
ORDER
When logic 0, the MSB of the data word is transmitted first.
If logic 1, the LSB of the data word is transmitted first.
4
-
reserved
3:2
MODE1:MODE0 Mode selection
00 - SPICLK LOW when idle; data clocked in on leading edge
(CPOL = 0, CPHA = 0)
01 - SPICLK LOW when idle; data clocked in on trailing edge
(CPOL = 0, CPHA = 1)
10 - SPICLK HIGH when idle; data clocked in on trailing edge
(CPOL = 1, CPHA = 0)
11 - SPICLK HIGH when idle; data clocked in on leading edge
(CPOL = 1, CPHA = 1)
1:0
F1:F0
SPI clock rate
SC18IS602/602B:
00 - 1843 kHz
01 - 461 kHz
10 - 115 kHz
11 - 58 kHz
SC18IS603:
00 - fosc
01 - fosc
10 - fosc
11 - fosc
⁄
⁄
⁄
⁄
4
16
64
128
SC18IS602_602B_603_4
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Product data sheet
Rev. 04 — 11 March 2008
7 of 25
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I2C-bus to SPI bridge
7.1.6 Clear Interrupt - Function ID F1h
An interrupt is generated by the SC18IS602/602B/603 after any SPI transmission has
been completed. This interrupt can be cleared (INT pin HIGH) by sending a ‘Clear
Interrupt’ command. It is not necessary to clear the interrupt; when polling the device, this
function may be ignored.
S
SLAVE ADDRESS
W
A
F1h
A
P
002aac452
Fig 11. Clear Interrupt
7.1.7 Idle mode - Function ID F2h
A low-power mode may be entered by sending the ‘Idle Mode’ command.
S
SLAVE ADDRESS
W
A
F2h
A
P
002aac453
Fig 12. Idle mode
The Idle mode will be exited when its I2C-bus address is detected.
7.1.8 GPIO Write - Function ID F4h
The state of the pins defined as GPIO may be changed using the Port Write function.
S
SLAVE ADDRESS
W
A
F4h
A
DATA
A
P
002aac454
Fig 13. GPIO Write
The data byte following the F4h command will determine the state of SS3, SS2, SS1, and
SS0, if they are configured as GPIO. The Port Enable function will define if these pins are
used as SPI Slave Selects or if they are GPIO.
Table 6.
Bit
GPIO Write (F0h) bit allocation
7
X
X
6
X
X
5
X
X
4
X
X
3
SS3[1]
0
2
SS2
0
1
SS1
0
0
SS0
0
Symbol
Reset
[1] SS3 does not exist in the SC18IS603.
SC18IS602_602B_603_4
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Product data sheet
Rev. 04 — 11 March 2008
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SC18IS602/602B/603
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I2C-bus to SPI bridge
7.1.9 GPIO Read - Function ID F5h
The state of the pins defined as GPIO may be read into the SC18IS602/602B/603 data
buffer using the GPIO Read function.
S
SLAVE ADDRESS
W
A
F5h
A
DATA
A
P
002aac455
Fig 14. GPIO Read
Note that this function does not return the value of the GPIO. To receive the GPIO
contents, a one-byte Read Buffer command would be required. The value of the Read
Buffer command will return the following byte.
Table 7.
GPIO Read (F5h) bit allocation
7
6
5
4
3
2
1
0
X
X
X
X
SS3[1]
SS2
SS1
SS0
[1] SS3 does not exist in the SC18IS603.
Data for pins not defined as GPIO are undefined.
A GPIO Read is always performed to update the GPIO data in the buffer. The buffer is
undefined after the GPIO data is read back from the buffer. Therefore, reading data from
the GPIO always requires a two-message sequence (GPIO Read, followed by Read
Buffer).
7.1.10 GPIO Enable - Function ID F6h
At reset, the Slave Select pins (SS0, SS1, SS2 and SS3) are configured to be used as
slave select outputs. If these pins are not required for the SPI functions, they can be used
as GPIO after they are enabled as GPIO. Any combination of pins may be configured to
function as GPIO or Slave Selects.
After the GPIO Enable function is sent, the ports defined as GPIO will be configured as
quasi-bidirectional.
S
SLAVE ADDRESS
W
A
F6h
A
DATA
A
P
002aac456
Fig 15. GPIO Enable
The data byte following the F6h command byte will determine which pins can be used as
GPIO. A logic 1 will enable the pin as a GPIO, while a logic 0 will disable GPIO control.
Table 8.
GPIO Enable (F6h) bit allocation
7
6
5
4
3
2
1
0
X
X
X
X
SS3[1]
SS2
SS1
SS0
[1] SS3 does not exist in the SC18IS603.
SC18IS602_602B_603_4
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Product data sheet
Rev. 04 — 11 March 2008
9 of 25
SC18IS602/602B/603
NXP Semiconductors
I2C-bus to SPI bridge
7.1.11 GPIO Configuration - Function ID F7h
The pins defined as GPIO may be configured by software to one of four types on a
pin-by-pin basis. These are: quasi-bidirectional, push-pull, open-drain, and input-only.
Two bits select the output type for each port pin.
Table 9.
7
GPIO Configuration (F7h) bit allocation
6
5
4
3
2
1
0
SS3.1[1]
SS3.0[1]
SS2.1
SS2.0
SS1.1
SS1.0
SS0.1
SS0.0
[1] SS3.1 and SS3.0 do not exist in the SC18IS603.
Table 10. GPIO Configuration (F7h) bit description
Bit
7
Symbol
SS3.1[1]
SS3.0[1]
Description
SS3[1:0] = 00: quasi-bidirectional
SS3[1:0] = 01: push-pull
6
SS3[1:0] = 10: input-only (high-impedance)
SS3[1:0] = 11: open-drain
5
4
SS2.1
SS2.0
SS2[1:0] = 00: quasi-bidirectional
SS2[1:0] = 01: push-pull
SS2[1:0] = 10: input-only (high-impedance)
SS2[1:0] = 11: open-drain
3
2
SS1.1
SS1.0
SS1[1:0] = 00: quasi-bidirectional
SS1[1:0] = 01: push-pull
SS1[1:0] = 10: input-only (high-impedance)
SS1[1:0] = 11: open-drain
1
0
SS0.1
SS0.0
SS0[1:0] = 00: quasi-bidirectional
SS0[1:0] = 01: push-pull
SS0[1:0] = 10: input-only (high-impedance)
SS0[1:0] = 11: open-drain
[1] SS3.1 and SS3.0 do not exist in the SC18IS603.
The SSn pins defined as GPIO, for example SS0.0 and SS0.1, may be configured by
software to one of four types. These are: quasi-bidirectional, push-pull, open-drain, and
input-only. Two configuration bits in GPIO Configuration register for each pin select the
type for each pin. A pin has Schmitt-triggered input that also has a glitch suppression
circuit. For SC18IS603, the SS3 pin defined as GPIO is non-existent.
7.1.11.1 Quasi-bidirectional output configuration
Quasi-bidirectional outputs can be used both as an input and output without the need to
reconfigure the pin. This is possible because when the pin outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a large current. There are three pull-up
transistors in the quasi-bidirectional output that serve different purposes.
One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch
for the pin contains a logic 1. This very weak pull-up sources a very small current that will
pull the pin HIGH if it is left floating.
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Product data sheet
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I2C-bus to SPI bridge
A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin
contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the
primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is
pulled LOW by an external device, the weak pull-up turns off, and only the very weak
pull-up remains on. In order to pull the pin LOW under these conditions, the external
device has to sink enough current to overpower the weak pull-up and pull the pin below its
input threshold voltage.
The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up
LOW-to-HIGH transitions on a quasi-bidirectional pin when the port latch changes from a
logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks
quickly pulling the pin HIGH.
The quasi-bidirectional pin configuration is shown in Figure 16.
Although the SC18IS602/602B/603 is a 3 V device, most of the pins are 5 V tolerant. If 5 V
is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing
from the pin to VDD causing extra power consumption. Therefore, applying 5 V to pins
configured in quasi-bidirectional mode is discouraged.
A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression
circuit.
V
DD
2 SYSTEM
CLOCK
CYCLES
P
P
P
very
weak
strong
weak
GPIO pin
pin latch data
V
SS
input data
glitch rejection
002aac548
Fig 16. Quasi-bidirectional output configuration
7.1.11.2 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the pin when the port latch contains a logic 0. To be used as a logic output, a
pin configured in this manner must have an external pull-up, typically a resistor tied to
VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode.
The open-drain pin configuration is shown in Figure 17.
An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.
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Product data sheet
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SC18IS602/602B/603
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I2C-bus to SPI bridge
GPIO pin
pin latch data
V
SS
input data
glitch rejection
002aab883
Fig 17. Open-drain output configuration
7.1.11.3 Input-only configuration
The input-only pin configuration is shown in Figure 18. It is a Schmitt-triggered input that
also has a glitch suppression circuit.
input data
GPIO pin
002aab884
glitch rejection
Fig 18. Input-only configuration
7.1.11.4 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a pin output.
The push-pull pin configuration is shown in Figure 19.
A push-pull pin has a Schmitt-triggered input that also has a glitch suppression circuit.
V
DD
P
N
strong
GPIO pin
pin latch data
V
SS
input data
glitch rejection
002aab885
Fig 19. Push-pull output configuration
SC18IS602_602B_603_4
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Product data sheet
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I2C-bus to SPI bridge
7.2 External clock input (SC18IS603)
In this device, the processor clock is derived from an external source driving the CLKIN
pin. The rate may be from 0 Hz up to 18 MHz.
Using the external clock allows higher frequencies from the SPI interface, thus the
SPI Master operating can be up to 4 Mbit/s. The CLKIN frequency does not affect the
clock speed of the I2C-bus interface, however, it will have an effect on the low period
between bytes on the I2C-bus.
7.3 SPI interface
The SPI interface can support Mode 0 through Mode 3 of the SPI specification and can
operate up to 1.8 Mbit/s (SC18IS602/602B) or 4.0 Mbit/s (SC18IS603). The SPI interface
uses at least four pins: SPICLK, MOSI, MISO, and Slave Select (SSn).
SSn are the slave select pins. In a typical configuration, an SPI master selects one SPI
device as the current slave.
There are actually four SSn pins (SS0, SS1, SS2 and SS3) to allow the
SC18IS602/602B/603 to communicate with multiple SPI devices.
The SC18IS602/602B/603 generates the SPICLK (SPI clock) signal in order to send and
receive data. The SCLK, MOSI, and MISO are typically tied together between two or more
SPI devices. Data flows from the SC18IS602/602B/603 (master) to slave on the MOSI pin
(Pin 6) and the data flows from slave to SC18IS602/602B/603 (master) on the MISO pin
(Pin 5).
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
8. I2C-bus to SPI communications example
The following example describes a typical sequence of events required to read the
contents of an SPI-based EEPROM. This example assumes that the
SC18IS602/602B/603 is configured to respond to address 50h. A START condition is
shown as ‘ST’, while a STOP condition is ‘SP’. The data is presented in hexadecimal
format.
1. The first message is used to configure the SPI port for mode and frequency.
ST,50,F0,02,SP
SPI frequency 115 kHz using Mode 0
2. An SPI EEPROM first requires that a Write Enable command be sent before data can
be written.
ST,50,04,06,SP
06h
EEPROM write enable using SS2, assuming the Write Enable is
3. Clear the interrupt. This is not required if using a polling method rather than interrupts.
ST,50,F1,SP
Clear interrupt
4. Write the 8 data bytes. The first byte (Function ID) tells the SC18IS602/602B/603
which Slave Select output to use. This example uses SS2 (shown as 04h). The first
byte sent to the EEPROM is normally 02h for the EEPROM write command. The next
one or two bytes represent the subaddress in the EEPROM. In this example, a
two-byte subaddress is used. Bytes 00 and 30 would cause the EEPROM to write to
subaddress 0030h. The next eight bytes are the eight data bytes that will be written to
subaddresses 0030h through 0037h.
ST,50,04,02,00,30,01,02,03,04,05,06,07,08,SP
Write 8 bytes using SS2
5. When an interrupt occurs, do a Clear Interrupt or wait until the SC18IS602/602B/603
responds to its I2C-bus address.
ST,50,F1,SP
Clear interrupt
6. Read the 8 bytes from the EEPROM. Note that we are writing a command, even
though we are going to perform a read from the SPI port. The Function ID is again
04h, indicating that we are going to use SS2. The EEPROM requires that you send a
03h for a read, followed by the subaddress you would like to read. We are going to
read back the same data previously written, so this means that the subaddress should
be 0030h. We would like to read back 8 bytes so we can send eight bytes of FFh to
tell the SC18IS602/602B/603 to send eight more bytes on MOSI. While it is sending
these eight data bytes, it is also reading the MISO pin and saving the data in the
buffer.
ST,50,04,03,00,30,FF,FF,FF,FF,FF,FF,FF,FF,SP
Read 8 bytes using SS2
7. The interrupt can be cleared, if needed.
ST,50,F1,SP
Clear interrupt
8. Read back the data buffer. Note that we will actually need to read back 11 data bytes
since the first three bytes sent on the SPI port were the read code (03h) and the two
subaddress bytes.
ST,50,00,00,00,01,02,03,04,05,06,07,08,SP
Read the data buffer
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
You can see that on the I2C-bus the first four bytes do not contain the data from the
SPI bus. The first byte is the SC18IS60x address, followed by three dummy data
bytes. These dummy data bytes correspond to the three bytes sent to the EEPROM
before it actually places data on the bus (command 03h, subaddress 0030h).
9. Limiting values
Table 11. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1][2]
Symbol
Tamb(bias)
Tstg
Parameter
Conditions
Min
Max
+125
+150
+5.5
8
Unit
°C
bias ambient temperature
operating
−55
storage temperature
−65
°C
Vn
voltage on any other pin
referenced to VSS
−0.5
V
IOH(I/O)
IOL(I/O)
II/O(tot)(max)
Ptot/pack
HIGH-level output current per input/output pin
LOW-level output current per input/output pin
maximum total I/O current
-
-
-
-
mA
mA
mA
W
20
120
1.5
[3]
total power dissipation per package
[1] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
[2] Parameters are valid over the operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[3] Based on package heat transfer, not device power consumption.
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
10. Static characteristics
Table 12. Static characteristics
VDD = 2.4 V to 3.6 V; Tamb = −40 °C to +85 °C (industrial); unless otherwise specified.
Symbol
Parameter
Conditions
VDD = 3.6 V
f = 7.3728 MHz
f = 12 MHz
Min
Typ[1]
Max
Unit
IDD(oper)
operating supply current
-
-
-
5.6
7
6.7
13
16
mA
mA
mA
f = 18 MHz
11
IDD(idle)
Idle mode supply current
VDD = 3.6 V
f = 7.3728 MHz
f = 12 MHz
-
3.3
3.9
mA
mA
mA
V
-
3.6
4.8
f = 18 MHz
-
4
6
Vth(HL)
Vth(LH)
Vhys
HIGH-LOW threshold voltage Schmitt trigger input
LOW-HIGH threshold voltage Schmitt trigger input
hysteresis voltage
0.22VDD
0.4VDD
0.6VDD
0.2VDD
-
-
-
0.7VDD
-
V
V
VOL
LOW-level output voltage
all pins
IOL = 20 mA
-
-
-
0.6
0.3
0.2
1.0
0.5
0.3
V
V
V
IOL = 10 mA
IOL = 3.2 mA
VOH
HIGH-level output voltage
all pins
IOH = −8 mA;
push-pull mode
V
V
V
DD − 1
-
-
-
-
V
V
V
IOH = −3.2 mA;
push-pull mode
DD − 0.7
DD − 0.3
V
DD − 0.4
DD − 0.2
IOH = −20 µA;
V
quasi-bidirectional mode
[2]
[3]
Cig
IIL
input capacitance at gate
LOW-level input current
input leakage current
-
-
-
-
-
-
-
15
pF
µA
µA
µA
logical 0; VI = 0.4 V
−80
±10
−450
[4]
ILI
all ports; VI = VIL or VIH
[5][6]
ITHL
HIGH-LOW transition current all ports; logical 1-to-0;
VI = 2.0 V at VDD = 3.6 V
−30
RRESET_N(int) internal pull-up resistance on
pin RESET
10
-
30
kΩ
[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
[2] Pin capacitance is characterized but not tested.
[3] Measured with pins in quasi-bidirectional mode.
[4] Measured with pins in high-impedance mode.
[5] Pins in quasi-bidirectional mode with weak pull-up (applies to all pins with pull-ups).
[6] Pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is
highest when VI is approximately 2 V.
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
11. Dynamic characteristics
Table 13. Dynamic characteristics
VDD = 2.4 V to 3.6 V; Tamb = −40 °C to +85 °C (industrial); unless otherwise specified.
Symbol Parameter
Conditions
Variable clock
fosc = 12 MHz Unit
Min
Max
Min
Max
fosc(RC)
internal RC oscillator
frequency
nominal f = 7.3728 MHz;
trimmed to ±1 % at
7.189
7.557
-
-
MHz
T
amb = 25 °C
External clock input
[1]
fosc
oscillator frequency
0
55
22
22
-
18
-
-
-
-
MHz
ns
TCLCL
tCHCX
tCLCX
tCLCH
tCHCL
clock cycle time
clock HIGH time
clock LOW time
clock rise time
clock fall time
-
T
CLCL − tCLCX
22
22
-
-
ns
T
CLCL − tCHCX
-
ns
5
5
5
5
ns
-
-
ns
Glitch filter
tgr
glitch rejection time
RESET pin
-
125
-
50
-
-
125
-
50
-
ns
ns
ns
ns
any pin except RESET
RESET pin
tsa
signal acceptance time
15
-
15
-
any pin except RESET
50
50
SPI master interface
fosc
fSPI
SPI operating frequency
4.5 MHz
4.5 MHz
-
⁄
4
-
222
111
111
100
100
-
4.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
TSPICYC
tSPICLKH
tSPICLKL
tSPIDSU
tSPIDH
SPI cycle time
⁄
-
-
fosc
2
SPICLK HIGH time
SPICLK LOW time
SPI data set-up time
SPI data hold time
⁄
-
-
fosc
2
⁄
-
-
-
-
fosc
100
100
0
-
-
tSPIDV
SPI enable to output data 3.0 MHz
valid time
160
111
-
160
111
-
4.5 MHz
0
-
tSPIOH
tSPIR
SPI output data hold time
0
0
SPI rise time
SPI outputs
-
100
-
100
(SPICLK, MOSI, MISO)
SPI inputs
(SPICLK, MOSI, MISO, SSn)
-
-
-
2000
100
-
-
-
2000 ns
100 ns
2000 ns
tSPIF
SPI fall time
SPI outputs
(SPICLK, MOSI, MISO)
SPI inputs
2000
(SPICLK, MOSI, MISO, SSn)
[1] Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
T
CLCL
t
t
SPIR
SPIF
t
t
SPICLKL
SPICLKH
SPICLK
(CPOL = 0)
(output)
t
t
SPIR
SPIF
t
t
SPICLKL
SPICLKH
SPICLK
(CPOL = 1)
(output)
t
t
SPIDSU
SPIDH
MISO
(input)
MSB/LSB in
LSB/MSB in
t
t
t
t
SPIR
SPIDV
SPIOH
SPIDV
t
SPIF
MOSI
(output)
master MSB/LSB out
master LSB/MSB out
002aac457
Fig 20. SPI master timing (CPHA = 0)
T
CLCL
t
t
SPIF
SPIR
t
t
SPICLKH
SPICLKL
SPICLK
(CPOL = 0)
(output)
t
t
SPIR
SPIF
t
t
SPICLKL
SPICLKH
SPICLK
(CPOL = 1)
(output)
t
t
SPIDSU
SPIDH
MISO
(input)
MSB/LSB in
LSB/MSB in
t
t
t
t
t
SPIDV
SPIOH
SPIDV
SPIDV
SPIR
t
SPIF
MOSI
(output)
master MSB/LSB out
master LSB/MSB out
002aac458
Fig 21. SPI master timing (CPHA = 1)
V
DD
− 0.5 V
0.2V
+ 0.9 V
DD
0.2V
− 0.1 V
DD
0.45 V
t
CHCX
t
t
t
CLCH
CHCL
CLCX
T
CLCL
002aab886
Fig 22. External clock timing
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
12. Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 23. Package outline SOT403-1 (TSSOP16)
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Table 14. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 15. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 24.
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 16. Abbreviations
Acronym
CDM
CPU
Description
Charged Device Model
Central Processing Unit
Electrically Erasable Programmable Read-Only Memory
ElectroStatic Discharge
General Purpose Input/Output
Human Body Model
EEPROM
ESD
GPIO
HBM
I/O
Input/Output
I2C-bus
Inter-Integrated Circuit bus
Least Significant Bit
LSB
MM
Machine Model
MSB
Most Significant Bit
SPI
Serial Peripheral Interface
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
15. Revision history
Table 17. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SC18IS602_602B_603_4 20080311
Product data sheet
-
SC18IS602_603_3
Modifications:
• added Type number SC18IS602BIPW
• Section 1 “General description”, 2nd paragraph: added second sentence.
• Section 6 “Pinning information”:
–
added “SC18IS602BIPW” to Figure 3a
–
Table 2 “Pin description”: added Table note [1] and Table note [2] and their references at
pin 10
• Table 3 “Function ID 01h to 0Fh”: added Table note [2] and its reference at bit 2, SS2
• Section 7.1 “I2C-bus interface”, 2nd paragraph: updated title of referenced document
SC18IS602_603_3
SC18IS602_603_2
SC18IS602_603_1
20070813
20061213
20060926
Product data sheet
Product data sheet
Product data sheet
-
-
-
SC18IS602_603_2
SC18IS602_603_1
-
SC18IS602_602B_603_4
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
to result in personal injury, death or severe property or environmental
16.2 Definitions
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
I2C-bus — logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
SC18IS602_602B_603_4
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I2C-bus to SPI bridge
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
18
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
Functional description . . . . . . . . . . . . . . . . . . . 4
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . . 4
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write to data buffer . . . . . . . . . . . . . . . . . . . . . . 5
SPI read and write - Function ID 01h to 0Fh . . 5
Read from buffer. . . . . . . . . . . . . . . . . . . . . . . . 6
Configure SPI Interface - Function ID F0h . . . . 7
Clear Interrupt - Function ID F1h . . . . . . . . . . . 8
Idle mode - Function ID F2h . . . . . . . . . . . . . . . 8
GPIO Write - Function ID F4h . . . . . . . . . . . . . 8
GPIO Read - Function ID F5h . . . . . . . . . . . . . 9
GPIO Enable - Function ID F6h . . . . . . . . . . . . 9
GPIO Configuration - Function ID F7h . . . . . . 10
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.11.1 Quasi-bidirectional output configuration . . . . . 10
7.1.11.2 Open-drain output configuration . . . . . . . . . . . 11
7.1.11.3 Input-only configuration . . . . . . . . . . . . . . . . . 12
7.1.11.4 Push-pull output configuration . . . . . . . . . . . . 12
7.2
7.3
External clock input (SC18IS603). . . . . . . . . . 13
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
I2C-bus to SPI communications example . . . 14
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
Static characteristics. . . . . . . . . . . . . . . . . . . . 16
Dynamic characteristics . . . . . . . . . . . . . . . . . 17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
9
10
11
12
13
Soldering of SMD packages . . . . . . . . . . . . . . 20
Introduction to soldering . . . . . . . . . . . . . . . . . 20
Wave and reflow soldering . . . . . . . . . . . . . . . 20
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21
13.1
13.2
13.3
13.4
14
15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16.1
16.2
16.3
16.4
17
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 March 2008
Document identifier: SC18IS602_602B_603_4
相关型号：
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