SC4000 [NXP]
Universal Timeslot Interchange; 通用时隙交换
| 型号： | SC4000 |
| 厂家： | 
NXP |
| 描述： | Universal Timeslot Interchange |
| 文件： | 总52页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CURCUITS
DATA SHEET
SC4000
Universal Timeslot Interchange
Preliminary specification
2000 Sep 07
File under Integrated Curcuits
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Logic Pin Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
SC4000 100-Pin TQFP (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . .2
SC4000 Physical Dimensions (all dimensions in millimeters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................... . . . . . . . . . . . . . . . . . . . . . . . . . .4
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................... . . . . . . . . . . . . . . . . . . . . . . . .6
Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
PLL Timing and Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Interrupts Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
CLKFAIL Timing and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Message Channel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Operation Mode and Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Register Access Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... . . . . . . . . . . . . . . . .17
I/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Busy (D_0) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Read (D_1) (Write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Write (D_2) (Write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Terminate (D_3) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Channel Bank Select Register [1:0] (D_[5:4]) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . .17
Channel Bank Select Register Enable (D_6) (Write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Reset (D_7) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Channel Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Time-Slot Select [6:0] (Read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Port Select [3:0] (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Parallel Access Enable (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Switch Output Enable (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Time-Slot/Channel Select [6:0] (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . .20
Port Select [3:0] (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Local Connect Enable (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Switch Output Enable (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Parallel Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Serial Data [1:8] (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Source Parallel Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Serial Data [1:8] (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2000 Sep 07
2
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SCbus Clock Master (C_0) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SCbus Clock Master Arm (C_1) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SCbus Primary/Alternate Select (C_2) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . . . . .21
Diagnostic Mode Enable (C_3) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SCbus Framing Mode [1:0](C_[5:4]) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . .21
Local bus Framing Mode [1:0](C_[7:6]) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . .21
Master Clock Input Frequency Select [2:0] (C_[10:8]) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Direct R/W to Parallel Access Registers Enable (C_11) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Message Channel Registered TXD Enable (C_12) (Read/Write) . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . .21
Message Channel TXD_0 or TXD_1 Select (C_13) (Read/Write) . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . .22
Message Channel Clock Duty Cycle Select (C_14) (Read/Write) . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . .22
Message Channel Output Disable (W/ loopback) (C_15) (Read/Write) . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . .22
SCbus SD Sample Position (C_16) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Local Bus SI Sample Position (C_17) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
SCbus SD Output Delay Enable (C_18) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . . .22
Local bus SO Output Delay Enable (C_19) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . . .22
SCbus FSYNCN Sample Position (C_20) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . .22
SCbus FSYNCN Rate (C_21) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . . . . . .22
SCbus SCLKX2N, SCLKX2NA Output Disable(C_22) (Read/Write) . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . .22
SCbus Alternate (“A”) Signals Output Enable (C_23) (Read/Write) . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . .23
Local bus L_CLK Polarity (C_24) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . .23
Local bus L_FS Polarity (C_25) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . .23
Local bus L_FS Position (C_[27:26]) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . .23
Local bus L_CLK & L_FS Rate (C_28) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Local bus L_CLK DPLL Enable (C_29) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . . .23
Local bus L_CLK 8.192 MHz 62.5% Duty Cycle (C_30) (Read/Write) . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . .23
Version/Revision Status (C_[39:32]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . . . . .23
Master PLL Reference Select [2:0] (C_[42:40]) (Read/Write) . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . . .23
Internal/External Master PLL Select (C_43) (Read/Write) . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . . . .24
SCbus SREF_8K Source Select [1:0] (C_[45:44]) (Read/Write) . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . .24
SCbus SREF_8K Output Enable (C_46) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . .24
SCbus SCLK 8.192 MHz 62.5% Duty Cycle (C_47) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Clock Watchdog Enable (C_48) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . . . . . .24
Microprocessor Watchdog Enable (C_49) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SCbus CLKFAIL Latch Set Polarity Select (C_50) (Read/Write) . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . .24
SCbus CLKFAIL Latch Debounce Enable (C_51) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Frame Boundary Latch Set Delay Enable (C_52) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
INT_0 Mask_N (C_53) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . . . .25
INT_0 Output Polarity (C_54) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . .25
INT_0 Output Driver (C_55) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
SCbus CLKFAIL Latch (C_56) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . . . . . .25
Frame Boundary Latch (C_57) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . . . . . . . . .25
2000 Sep 07
3
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Internal Master PLL Error Latch (C_58) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
SCbus Error Indicator (C_59) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . . . .25
SCbus CLKFAIL Latch Clear_N (C_60) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . .25
Frame Boundary Latch Clear_N (C_61) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Internal Master PLL Error Latch Clear_N (C_62) (Read/Write) . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . .25
SCbus SCLKX2N Error Latch (C_64) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
SCbus SCLKX2NA Error Latch (C_65) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SCbus SCLK Error Latch (C_66) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . .26
SCbus SCLKA Error Latch (C_67) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . .26
SCbus SCLKX2N Error Latch Clear_N (C_68) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SCbus SCLKX2NA Error Latch Clear_N (C_69) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SCbus SCLK Error Latch Clear_N (C_70) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SCbus SCLKA Error Latch Clear_N(C_71) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SCbus FSYNCN Error Latch (C_72) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SCbus FSYNCNA Error Latch (C_73) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SCbus Clock Master Error Latch (C_74) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . .26
SCbus FSYNCN Error Latch Clear_N (C_76) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SCbus FSYNCNA Error Latch Clear_N (C_77) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SCbus Clock Master Error Latch Clear_N (C_78) (Read/Write) . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . .26
SCbus SREF_8K NE SREF_8KA Error Latch (C_80) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SCbus CLKFAIL NE CLKFAILA Error Latch (C_81) (Read only) . . . . . . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . . . .27
SCbus MC NE MCA Error Latch (C_82) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . .27
SCbus SD Error Indicator (C_83) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . .27
SCbus SREF_8K NE SREF_8KA Error Latch Clear_N (C_84) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SCbus CLKFAIL NE CLKFAILA Error Latch Clear_N (C_85) (Read/write) . . . . . . . . . . . . . . . .............................. . . . . . . . . . . .27
SCbus MC NE MCA Error Latch Clear_N (C_86) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . .27
SCbus SD Error Latch Clear_N (C_87) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . .27
SCbus SD_[15:0] Error Latch (C_[103:88]) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Summary of SC4000 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7.
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Master Clock/PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SCbus (MVIP Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Message Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Reserved Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Typical Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... . . . . . . . . .28
Typical Write Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . . . . . .28
Typical Read Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................... . . . . . . . . . . . . . . . .30
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2000 Sep 07
4
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Table 1. Configuration Register Setup for SCbus Clock Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . . . . . . . 11
Table 2. Configuration Register Setup for SCbus Clock Master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . . . . . . 12
Table 3. Configuration Register Setup for SCbus Armed Clock Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . . . 13
Table 4. Configuration Register Setup for MVIP Clock Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . . . . . . 14
Table 5. Configuration Register Setup for MVIP Clock Slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . . . . . . . 14
Table 6. SCbus/MVIP Signals Cross Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . . . . . . . . . 15
Table 7. Microprocessor Interface Timing - Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. Microprocessor Interface Timing - Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9. Microprocessor Interface Timing - Multiplexed Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10. Local Bus Timing, 1X L_CLK Mode (C_28=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11. Local Bus Timing, 2X L_CLK Mode (C_28=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12. SCbus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13. SCbus Clock Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. SCbus Clock Fail Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. REF_8K_[3:0] and SREF_8K Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . . . . . . . . . . 40
2000 Sep 07
5
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 1. Destination and Source Switch Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................ . . . . . . . . . . . . . . . .7
Figure 2. Internal Master PLL (C_43 = 0) Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................ . . . . . . . . . . . . . . . .8
Figure 3. External Master PLL (C_43 = 1) Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................ . . . . . . . . . . . . . . . .9
Figure 4. Internal PLL and Local Bus PLL Timing Function Block . . . . . . . . . . . . . . . . . . . . . . . . . ........................ . . . . . . . . . . . .10
Figure 5. Using Two Pins A_[1:0] for Address Bus Interface Scheme (C_11 = 0) . . . . . . . . . . . . . . . . . . ........................ . . . . . . .16
Figure 6. Using Nine Pins A_[8:0] for Address Bus Interface Scheme (C_11 = 1) . . . . . . . . . . . . . . . . . ........................ . . . . . . . .16
Figure 7. Microprocessor Interface Timing - Intel Bus Mode (Pin I_N = 0), Non-Multiplexed Address . . . . . . . . . . . . . . . . . . . . . .31
Figure 8. Microprocessor Interface Timing - Motorola Bus Mode (Pin I_N = 1), Non-multiplexed Address . . . . . . . . . . . . . . . . . . .32
Figure 9. Microprocessor Interface Timing - Multiplexed Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 10. Local Bus Timing, 1XL_CLK Mode (C_28=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 11. Local Bus Timing, 2X L_CLK Mode (C_28=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 12. SCbus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 13. SCbus Clock Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................ . . . . . . . . . . . . . . . . . . . .38
Figure 14. SCbus Clock Fail Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 15. REF_8K_[3:0] and SREF_8K input mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................ . . . . . . . . . . . .40
2000 Sep 07
6
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
•
•
Supports both Intel® and Motorola®
processor interfaces
•
•
5V CMOS technology
100-pin TQFP package
FEATURES
•
Timeslot interchange between local
and expansion buses
Serial or parallel access to expansion
bus
APPLICATIONS
•
Architecture optimized for call pro-
cessing environments: SCbus™,
MVIP® and ST-BUS Compatible
•
PC-based switching
•
•
•
Enhanced input hysteresis threshold
Internal phased lock loop
•
Small to medium size digital switch
matrices
•
•
Full switching between any of:
Fast response and support for SCbus
clock fallback
•
•
SCbus/MVIP interface functions
– 128 local bus input SI timeslots
– 128 local bus output SO timeslots
Digital centralized voice processing
system
•
•
Flexible local frame sync interface
– up to 2048 expansion bus SD
timeslots
Supports hyper channel capability
(bundling)
•
•
Voice/Data multiplexer and exchange
Computer telephony interface
Multiple local bus speeds and
formats:
•
•
SCbus message bus interface and local
loopback control
– 2.048, 4.096 or 8.192 Mb/s
– PEB®, STbus or GCI
High availability and self-diagnostic
features
Logic Pin Organization
44
43
42
40
39
38
36
35
15
D_7
D_6
INT_1
INT_0
14
D_5
D_4
D_3
D_2
D_1
D_0
99
100
(TEST_OUT_0)DRQ_R
(TEST_OUT_1)DRQ_T
46
47
49
50
51
52
54
55
56
58
59
60
62
63
64
66
67
68
70
71
72
74
75
76
77
79
80
81
SCLKX2N
SCLKX2NA
SCLK
34
32
31
30
28
27
26
25
24
A_8
A_7
A_6
A_5
A_4
A_3
A_2
A_1
A_0
SCLKA
SREF_8K
SREF_8KA
FSYNCN
FSYNCNA
CLKFAIL
CLKFAILA
SD_0
SD_1
SD_2
SD_3
SD_4
22
ALE
17
16
19
20
21
96
12
CS_1_N
SC4000
CS_0_N
SD_5
RD_N(STRB_N)
WR_N(R/W_N)
DACK_N
RESET
SD_6
SD_7
SD_8
SD_9
I_N(M)
SD_10
SD_11
SD_12
SD_13
2
1
X_IN
X_OUT
SD_14
SD_15
MC
7
6
5
4
REF_8K_3(REF_8K_OUT)
REF_8K_2(CLK_IN)
REF_8K_1
MCA
REF_8K_0
83
84
L_CLK
L_FS
95
94
92
91
SI_3
SI_2
SI_1
SI_0
90
88
87
86
SO_3
SO_2
SO_1
SO_0
9
TXD_0
TEST
11
10
98
MC_CLK
RXD
2000 Sep 07
7
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Block Diagram
SI_[3:0]
SD_[15:0]
128 x 2048
Destination
Switch
Local
Connect
SO_[3:0]
128 x 2176
Source
Switch
Local Bus Timing
SCbus Timing
Timing
DPLL
CLK_IN
REF_8K_[3:0]
A_[8:0]
Control
Bus
Micro
Processor
D_[7:0]
Control
Interface
SC4000 100-Pin TQFP (top view)
SCLKA
SCLK
VDD
SCLKX2NA
SCLKX2N
VSS
D_7
50
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SD_13
SD_14
VDD
SD_15
MC
MCA
VSS
L_CLK
L_FS
VDD
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
D_6
D_5
VSS
D_4
D_3
D_2
VDD
D_1
D_0
A_8
VSS
A_7
A_6
A_5
VDD
A_4
SC4000
100-PIN TQFP
SO_0
SO_1
SO_2
VDD
(TOP VIEW)
SO_3
SI_0
SI_1
VSS
SI_2
SI_3
RESET
VSS
TEST
DRQ_R
A_3
A_2
DRQ_T
1 2
3
4
5
6
7
8
9 10 11121314 15 16 17 1819 20 2122 23 24 25
2000 Sep 07
8
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
SC4000 Physical Dimensions (all dimensions in millimeters)
+
_
16.00 0.40
+
_
14.00 0.20
1.00 REF
+
_
0.22 0.05
o
12 REF
+
_
0.04
0.14
0.25
+
_
1.40 0.05
0.15 MAX
0
0
0 -10
Typ
0.50
+
_
o
0.60 0.15
12 REF
0.20 MIN
2000 Sep 07
9
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
PIN DESCRIPTION
Pin Name
Input/Output
Pin Number
Pin Description
D_[7:0]
I/O
44,43,42,40,
39,38,36,35
(TTL Bi-directional) Microprocessor Data Bus. These bi-directional, tri-state lines allow the microprocessor to
access SC4000 internal registers as well as the source/destination routing memory and parallel access registers.
A_[8:0]
ALE
I
I
I
I
I
34,32,31,30,
28,27,26,25,24
(TTL Input) Microprocessor Address Bus. These inputs select the internal registers used by a read or write opera-
tion. Normally these inputs are connected to Microprocessor address lines A[8:0].
22
17
16
12
(TTL Input) Address Latch Enable. This input pin is tied to high in non-multiplexed mode. Otherwise, in multi-
plexed mode, the Microprocessor Address Bus is latched internally on the falling edge of this signal.
CS_1_N
CS_0_N
(TTL Input) Chip Select 1. Reserved for future internal HDLC controller. If unused, this pin should be connected to
high.
(TTL Input) Chip Select 0. This active low signal selects the SC4000
for a microprocessor read or write operation.
I_N
or
M
(TTL Input) Microprocessor Bus Interface Mode Select.
When this input is low, Intel Bus Mode (I_N) is selected.
When this input is high, Motorola Bus (M) Mode is selected.
RD_N
or
STRB_N
I
I
19
20
(TTL Input) In Intel Bus Mode (RD_N), this active low input operates with CS_0_N to configure the data bus lines
D_[7:0] as output. In Motorola Bus Mode (STRB_N), this active low input operates with CS_0_N to enable a read
or write operation.
WR_N
or
R/W_N
(TTL Input) In Intel Bus Mode (WR_N), when CS_0_N is active, the rising edge of WR_N is used to latch an inter-
nal data register with data provided via the data bus lines D_[7:0]. In Motorola Bus Mode (R/W_N), this R/W_N
input is used to distinguish between read or write during a microprocessor access.
DACK_N
RESET
X_IN
I
I
21
96
2
(TTL Input, Pull up) DMA Acknowledge Reserved for future internal HDLC controller. If unused, this pin should be
left unconnected
(TTL Input) Reset. This active high signal initializes the microprocessor interface, configuration, routing and paral-
lel access registers.
I
(CMOS Input) Crystal Clock Input. This pin is a CMOS level input of either 2.048, 4.096, 8.192, 16.384, 32.768 or
65.536 MHz. A crystal of 16.384 MHz from X_IN to X_OUT may also be used.
X_OUT
O
I
1
7
(CMOS Output) Crystal Clock Output.
REF_8K_3
or
(TTL Bi-Directional) Internal Master PLL (REF_8K_3). If configuration register bit C_43=0, this pin is a Local 8
KHz Reference 3 Input.
REF_8K_OUT
O
I
External Master PLL (REF_8K_OUT). If configuration register bit C_43=1, this pin is an 8 KHz Reference Output.
REF_8K_2
or
CLK_IN
6
5
(TTL Input) Internal Master PLL (REF_8K_2). If configuration register bit C_43=0, this pin is a Local 8 KHz Refer-
ence 2 Input.
External Master PLL (CLK_IN). If configuration register bit C_43=1, this is a clock input from external master PLL.
REF_8K_1
I
(TTL Input) Local 8 KHz Reference 1 Input.
REF_8K_0
SI_[3:0]
I
I
4
(TTL Input) Local 8 KHz Reference 0 Input.
95,94,92,91
(TTL Input, Pull Up) Local Bus Serial Input Data Streams. This pin can be programmed to 2.048, 4.096 or 8.192
Mb/s data rates.
TXD_0
TEST
INT_1
INT_0
I
9
(TTL Input, Pull Up) Message Channel Transmit Data. This pin is for the SCbus Message channel transmit data
input line.
I
98
15
14
(TTL Input) NAND Gate Test Mode Enable. When in test mode (TEST=1) each pin except VDD/VSS/X_OUT is
nanded with the preceding pin and output at both DRQ_R and DRQ_T pins.
I/O
I/O
(TTL Bi-directional) Interrupt Request 1. Reserved for future internal HDLC controller. If unused, this pin should be
left unconnected.
(TTL Bi-directional) Interrupt Request 0. This pin will be asserted (controlled by C_[55:53]) if either SCbus Error,
SCbus CLKFAIL, Frame Boundary or Internal Master PLL Error and INT_0 unmasked (C_53 = 1).
2000 Sep 07
10
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Pin Description (continued)
Pin Name
Input/Output
Pin Number
Pin Description
DRQ_R
or
O
99
(TTL Output) Receive DMA Request. This pin is reserved for a future internal HDLC controller. Otherwise, in Test
Mode (TEST=1), this is a NANDed gate test chain 0 output.
TEST_OUT_0
DRQ_T
or
O
100
(TTL Output) Transmit DMA Request. This pin is reserved for a future internal HDLC controller. Otherwise, in Test
Mode (TEST=1), this is a NANDed gate test chain 1 output.
TEST_OUT_1
SCLKX2N
SCLKX2NA
SCLK
I/O
I/O
I/O
46
47
49
(SCbus Bi-directional) SCbus System clock x 2.
(SCbus Bi-directional) SCbus Alternate System clock x 2.
(SCbus Bi-directional) SCbus System clock. This can be programmed to either 2.048, 4.096 or 8.192 MHz.
Set C_0 = 1 to enable the SCLK output driver as master mode.
Set C_0 = 0 to disable the SCLK output driver as slave mode.
SCLKA
I/O
I/O
50
51
(SCbus Bi-directional) SCbus Alternate System clock.
SREF_8K
(SCbus Bi-directional) SCbus 8 KHz Reference.
If C_46 = 1, the SREF_8K output is enabled at SCbus
If C_46 = 0, the SREF_8K output is disabled at SCbus
SREF_8KA
FSYNCN
I/O
I/O
52
54
(SCbus Bi-directional) SCbus 8 KHz Alternate Reference.
(SCbus Bi-directional) SCbus 8 KHz Frame Synchronization signal.
Set C_0 = 1 to enable the FSYNCN output driver as master mode.
Set C_0 = 0 to disable the FSYNCN output driver as slave mode.
FSYNCNA
CLKFAIL
I/O
I/O
I/O
55
56
58
(SCbus Bi-directional) SCbus 8 KHz Alternate Frame Synchronization signal.
(SCbus Bi-directional) SCbus System Clock Fail signal.
CLKFAILA
(SCbus Bi-directional) SCbus Alternate System Clock Fail signal.
SD_[0:15]
I/O
59,60,62,63,
64,66,67,68,
70,71,72,74,
75,76,77,79
(SCbus Bi-directional) These are SCbus Serial Data Streams can be programmed to 2.048, 4.096 or 8.192 Mb/s
data rates.
MC
I/O
I/O
I/O
80
81
83
(SCbus Bi-directional Open Collector) SCbus Message Channel.
MCA
L_CLK
(SCbus Bi-directional Open Collector) SCbus Alternate Message Channel.
(TTL Bi-directional) Local bus Clock Output. It can be programmed to: 2.048, 4.096 or 8.192 MHz if set C_28 = 0.
4.096, 8.192 or 16.384 MHz if set C_28 = 1.
L_FS
I/O
I/O
84
(TTL Bi-directional) Local bus 8 KHz Frame Synchronization Output.
S0_[3:0]
90,88,87,86
(TTL Bi-directional) Local Bus Serial Output Data Streams. It can be programmed to 2.048, 4.096 or 8.192Mb/s
data rates.
MC_CLK
RXD
I/O
11
10
(TTL Bi-directional) Message Channel Data Clock. This pin is a 2.048 MHz output. The clock duty cycle can be
programmed by C_14 bit.
I/O
(TTL Bi-directional) Message Channel Receive Data. This pin is for the SCbus message channel receive data output
line.
VDD
Power
Power
8,13,29,37,48,
61,65,78,85,89
+5 Volt Power Supply.
VSS
3,18,23,33,41,
45,53,57,69,73,
82,93,97
Ground.
Note: In Test mode (TEST=1), every pin except VDD/VSS/X_OUT/DRQ_R/DRQ_T is configured as input.
2000 Sep 07
11
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
As shown in Figure 1 , the destination
The data stored in the source routing
DEVICE OVERVIEW
routing memory defines the Local Bus to
SCbus switch connection. There are 128
destination routing memory locations
— one for each Local Bus input channel.
The data stored in the destination rout-
ing memory selects the timeslot and
SCbus serial port connection for the
Local Bus input channel. The source
routing memory defines the SCbus to
Local Bus switch connection. There are
128 source routing memory locations —
one for each Local Bus output channel.
memory selects the time slot and SCbus
serial port connection for the Local Bus
output channel.
The SC4000 Universal Timeslot Inter-
change is designed to provide the hard-
ware interface to the SCbus. Its primary
function is exchanging digital data be-
tween the Local bus serial port and the
SCbus serial port. A microprocessor
interface allows the host controller to
specify the timeslots and serial lines for
this exchange. Both the SCbus and the
Local bus can be programmed to oper-
ate at either 2.048 Mb/s, 4.096 Mb/s or
8.192 Mb/s.
Local Bus Channels to Serial Ports SI and SO Time Slot Assignments
Framing mode
SI_0 and SO_0
SI_1 and SO_1
SI_2 and SO_2
SI_3 and SO_3
2.048 Mb/s
4.096Mb/s
8.192 Mb/s
ch[0:31] -> ts[0:31]
ch[0:63] -> ts[0:63]
ch[0:127] -> ts[0:127]
ch[32:63] -> ts[0:31]
ch[64:127] -> ts[0:63]
ch[64:95] -> ts[0:31]
ch[96:127] -> ts[0:31]
2000 Sep 07
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Writing to the routing memory is syn-
chronized with SCbus timing. So rout-
ing information can be changed only on
time slot boundaries. All input data is
buffered in holding registers. The entire
holding register is transferred to the out-
put registers on a frame boundary basis.
All frame-bounded time slots incur a
one frame delay as they pass through the
switch. Switching data in this fashion
supports time slot bundling.
In addition to switching local bus serial
any source channel without SCbus
data to and from the SCbus, the SC4000
provides a means of switching parallel
data through the microprocessor inter-
face to the SCbus. A frame boundary in-
terrupt helps control the timing of
parallel data accesses. Direct reading and
writing of parallel access register con-
tents makes for an efficient data transfer.
When using direct access, the control-
ling processor places the address of the
target channel on the address bus. In
this way, data can be read or written in a
single cycle. To avoid data corruption,
the application should not access the
channel for a time period defined as four
clocks before and four clocks after the
frame boundary.
intervention. This mode accommodates
either serial or parallel data transfer.
Since data passes through the switch
twice in this mode, there is a two-frame
delay from input to output.
Diagnostic mode electrically disconnects
the SC4000 from the SCbus but allows
access through the local bus. This mode
is particularly useful for running board
diagnostics without upsetting the
SCbus. A Master Clock source is
required to run this mode.
The SO outputs are tri-state controlled
on time slot boundaries by the Source
Routing Memory Switch Output Enable
Bit. This allows SO outputs from multi-
ple devices to be connected to a com-
mon line. The data sample position of
both the SCbus and the Local bus can be
selected for either 50% or 75% of the bit
cell.
The SC4000 pinout anticipates a future
version of the chip that includes an in-
ternal HDLC controller for the message
channel. To remain compatible with this
and other subsequent versions of the
SC4000, applications must write 0 to
all “Reserved (read only)” configuration
registers.
The Source Routing Memory Local
Connect Enable mode allows the switch-
ing of any destination channel to
Figure 1. Destination and Source Switch Function Block
1 OF 128 DESTINATION SWITCH
INPUT
SI_[3:0]
HOLDING
REGISTER
O
I
SD_[15:0]
OUTPUT
HOLDING REGISTER
TIMESLOT & PORT
OUTPUT ENABLE
D_[7:0]
W/R_N
PARALLEL
ACCESS
PARALLEL
ACCESS
ENABLE
REGISTER
DESTINATION
ROUTING MEMORY
1 OF 128 SOURCE SWITCH
SOURCE
ROUTING MEMORY
INTERNAL PARALLEL
ACCESS
READ
TIMESLOT,
INPUT
OUTPUT
PORT AND LOCAL
CONNECT ENABLE
HOLDING
HOLDING
REGISTER
REGISTER
OUTPUT
ENABLE
SO_[3:0]
2000 Sep 07
13
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
128 unique locations in the destination
SCLK, SCLKX2N and a “free-running”
FUNCTION DESCRIPTION
routing memory and source routing
FSYNCN signal based on the speed of
the SCbus and the clock frequency. The
internal master PLL runs free when:
Switching
memory, respectively. So data stored in
the destination or source routing mem-
ory selects the timeslot and serial port of
the SCbus. All data is buffered through
the input holding register, output hold-
ing register or parallel access register for
a switching matrix with one frame delay.
The SC4000 allows data switching
through the microprocessor interface in
any of the following three directions:
•
Put into free run mode (ignoring
reference input changes) by control
C_[42:40]
•
From any local bus serial channel (SI)
or parallel data bus D_[7:0] input to
any SCbus channel (SD) output
•
•
The 8 KHz reference input is static
“1” or “0”
•
From any SCbus channel (SD) input
to any output of the local bus serial
channel (SO) or parallel data bus
D_[7:0]
PLL Timing and Clock Control
The input of X_IN is less than 65.536
MHz.
The SC4000 provides the option of us-
ing the internal master PLL (C_43 = 0)
or an external master PLL (C_43 = 1).
As shown in Figure 2, the internal
master PLL generates a clock that is fre-
quency-locked to an 8 KHz reference in-
put of either SREF_8K or REF_8K[3:0].
When the SC4000 is enabled as SCbus
master (C_0 =1), a state machine inside
the SC4000 uses this clock to generate
The internal master PLL can also gener-
ate an interrupt if it cannot lock the
selected 8 KHz reference input.
•
From any of local bus serial channel
(SI) or parallel data bus D_[7:0] input
directly through an internal local
connect bus to any local bus serial
channel (SO) output
As shown in Figure 1, each input SI and
output SO channel is mapped to one of
Figure 2. Internal Master PLL (C_43 = 0) Function Block
C_0, C_3, C_[23:22]
EXTERNAL
CRYSTAL or OSC
SCLKX2N
SCLKX2NA
C_[10:8], C_[5:4]
46, 47
C_[42:40]
FSYNCN
FSYNCNA
Programmable
Divider
54, 55
SCbus
65.536 MHz
REF_8K_[3:0]
Clock
Master PLL
SCLK
SCLKA
Master PLL
Reference
8 K Select
4, 5, 6, 7
49, 50
To Internal Watchdogs and
SCbus Error Detectors
C_2
Primary
or
Alternate
Select
C_[45:44]
SREF_8K
SCbus
SREF_8KA
SREF_8K
Source
Select
51, 52
C_3, C_23, C_46
2000 Sep 07
14
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 3 shows an external master PLL
implementation. The SC4000 provides
the 8 KHz reference output signal
REF_8K_OUT (pin 7) to the external
PLL. This 8 KHz reference signal is
sourced from either REF_8K[1:0] or
SREF_8K. The output of the external
PLL is then routed back to the SC4000
via CLK_IN (pin 6). The master clock
input (CLK_IN) frequency select at
C_[10:8] would then be programmed
for the external PLL frequency.
then the SCbus clocks serve as the inter-
nal clock and use to create the local bus
clocks as well as message channel clock.
(pin 14). This signal is configured and
unmasked by configuration register bits
C_55, C_54 and C_53. The interrupt
sources are:
The local bus clock PLL is used to create
a 2.048 MHz L_CLK when:
•
•
•
•
C_56 SCbus CLKFAIL
•
•
•
Local bus framing mode C_[7:6] is set
to 2.048 Mb/s
C_57 Frame Boundary
C_58 Internal Master PLL Error
A 65.536 MHz clock is supplied on
X_IN
C_59 SCbus Error Indicator (logical
“OR” of C_[67:64], C_[74:72], and
C_[83:80])
The C_29 bit is set to one.
If SCLK stops transitionally such as
during a clock fail condition (CLKFAIL
= 1), then the local bus clock PLL runs
free to generate L_CLK clock. In addi-
tion, the local bus SO lines are tri-stated
so that the network interface can con-
tinue to run.
The interrupts are structured this way to
improve performance by allowing a sin-
gle read operation (of configuration reg-
ister byte 7) to determine whether the
SC4000 is the source of the interrupt.
Each of the SC4000 interrupt sources
can be individually masked.
As shown in Figure 4, the SC4000 also
provides an internal clock PLL and local
bus PLL timing control circuitry for
both SCbus master and slave operations.
The internal clock PLL is used to create
the 4.096 or 8.192 MHz timing slaved to
the SCbus when the local bus is running
faster than the SCbus (i.e., 2.048 MHz at
SCbus, 8.096 MHz at local bus). If the
SCbus is faster or equal to the local bus,
Interrupts Control
The SC4000 can interrupt the host CPU
with the interrupt request signal INT_0
Figure 3. External Master PLL (C_43 = 1) Function Block
C_0, C_3, C_[23:22]
SCLKX2N
SCLKX2NA
External
C_[10:8], C_[5:4]
46, 47
PLL
C_[42:40]
FSYNCN
FSYNCNA
Programmable
Divider
54, 55
REF_8K_[1:0]
SCLK
SCLKA
Master PLL
4, 5
49, 50
Reference
8 K Select
To Internal Watchdogs and
SCbus Error Detectors
C_2
Primary
or
Alternate
Select
C_[45:44]
SREF_8K
SCbus
SREF_8KA
SREF_8K
Source
Select
51, 52
C_3, C_23, C_46
2000 Sep 07
15
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 4. Internal PLL and Local Bus PLL Timing Function Block
X_IN
65.536 MHz
Local
Bus
Internal
2
Clock
1
0
Clock
PLL
L_CLK
PLL
Internal
Timing
Control
State
SCLK
83
Primary
or
Alternate
Select
49
SCLKA
C_[7:6]=0X (2.048 Mb/s)
C_29=1
50
Machine
SCLKX2N
Primary
or
L_FS
46
Alternate
Select
84
SCLKX2NA
47
MC_CLK
2.048 MHz
11
FSYNCN
Primary
or
54
Alternate
Select
FSYNCNA
55
C_[7:6], C_[5:4]
C_2
2000 Sep 07
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
CLKFAIL Timing and Control
using the clock and frame sync signals
Channel is Disabled (C_15 = 1), TXD_0
When an SC4000 is enabled to be clock
master (C_0 = 1), the chip drives clock
and frame sync signals to the SCbus and
pulls the CLKFAIL line low. If the
driven by the previous master, the new
master takes over without any framing
error. It is as if one clock period had
been stretched, as shown in Figure 14.
is looped back to the RXD to allow
diagnostics to be run on the HDLC
controller.
Operation Mode and Configuration
Register Setup
The SC4000 can be configured to func-
tion in five different modes shown in the
tables below:
SC4000 is then disabled as clock master,
the internal state machine waits for the
next frame boundary and then stops
driving clock and frame sync signals.
Instead, it drives the CLKFAIL line high
for one clock before tri-stating it (CLK-
FAIL is pulled up with 4.7K on every
board). An “armed” clock master (C_1
= 1) contains logic that monitors the
CLKFAIL line (C_51 must be set). If
CLKFAIL is sampled high for two con-
secutive clock periods, then the C_0 bit
is automatically set; the armed master
then begins driving clock and frame
sync signals and pulls CLKFAIL low.
Since the internal state machine was
Message Channel Interface
The SC4000 is designed for use with an
HDLC controller to implement the mes-
sage channel interface. The interface be-
tween an HDLC controller and SC4000
consists of the 2.048 MHz MC_CLK
(pin 11), TXD_0 (pin 9) and RXD (pin
10) lines. Data read from the SCbus MC
(pin 80) line is passed straight through
the SC4000 to the RXD output. Data
read from TXD_0 can be passed straight
through the SC4000 to the MC output,
or be buffered internally through a
•
•
•
•
•
SCbus Clock Slave (Table 1)
SCbus Clock Master (Table 2)
SCbus Armed Clock Master (Table 3)
MVIP Clock Master (Table 4)
MVIP Clock Slave (Table 5)
Table 6 shows signals that are cross
referenced by SCbus and MVIP.
clocked register. Buffering output data is
controlled by C_12. When the Message
Table 1. Configuration Register Setup for SCbus Clock Slave
Operation Mode
Conguration Register Bits Setup
Function Description
SCbus Slave
C_0 = 0
C_1 = 0
C_2
SCbus clock master disabled (Default)
SCbus clock master disarmed (Default)
SCbus Primary or Alternate Select
0: Primary SCbus signals selected (Default)
1: Alternate SCbus signals selected
C_3 = 0
C_[5:4]
Diagnostic mode disabled (Note)
SCbus Framing mode to select one of the following rate:
0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)
10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame
11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame
C_[7:6]
Local bus Framing mode to select one of the following rate:
0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)
10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame
11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame
Note: Default of all configuration register bits except C_3 are 0
2000 Sep 07
17
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Table 2. Configuration Register Setup for SCbus Clock Master
Operation Mode
Conguration Register Bits Setup
Function Description
SCbus Master
C_0 = 1
C_1 = 0
C_2
SCbus clock master enabled
SCbus clock master disarmed (Default)
SCbus Primary or Alternate Select
0: Primary SCbus signals selected (Default)
1: Alternate SCbus signals selected
C_3 = 0
C_[5:4]
Diagnostic mode disabled
SCbus Framing mode to select one of the following rate:
0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)
10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame
11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame
C_[7:6]
Local bus Framing mode to select one of the following rate:
0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)
10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame
11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame
C_[10:8]
Master clock input frequency select:
000 = 2.048 MHz (Default), 001 = 4.096 MHz, 010 = 8.192 MHz,
011 = 16.384 MHz, 100 = 32.768 MHz, 101= 65.536 MHz,
11X =Reserved
C_21 = 0
C_22
SCbus FSYNCN rate to select one SCLK period (Default)
SCbus SCLKX2N and SCLKX2NA output enable control
0: SCbus SCLKX2N and SCLKX2NA output enabled (Default)
1: SCbus SCLKX2N and SCLKX2NA output disabled
C_23
SCbus Alternate signals output enable control
0: SCbus Alternate signals output disabled (Default)
1: SCbus Alternate signals output enabled
C_[43:40] (Internal/External
Internal/External Master PLL reference select:
Master PLL reference 8K select)
If C_43 = 0 select the reference for the internal master PLL from C_[42:40]: 000 = Free-run (Default),
001/010 = Free-run,
011 = SREF_8K/SREF_8KA, 100 = REF_8K_0, 101 = REF_8K_1,
110 = REF_8K_2, 111 = REF_8K_3
(see Figure 2)
If C_43 = 1 select the reference for the external master PLL (output on REF_8K_OUT pin 7) from
C_[42:40]: 000 = Free-run (driven high) (Default), 001/010 = Free-run (driven high), 011 =
SREF_8K/SREF_8KA,
100 = REF_8K_0, 101 = REF_8K_1, 110/111 = Tri-state (Z)
(see Figure 3)
C_51 = 1
SCbus CLKFAIL latch debounce enabled
2000 Sep 07
18
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Table 3. Configuration Register Setup for SCbus Armed Clock Master
Operation Mode
Conguration Register Bits Setup
Function Description
SCbus Armed Master
C_0 = 0
C_1 = 1
SCbus clock master disabled initially
SCbus clock master armed. When CLKFAIL goes high, C_0 bit will be automatically set and SC4000
becomes clock master
C_2
SCbus Primary or Alternate Select
0: Primary SCbus signals selected (Default)
1: Alternate SCbus signals selected
C_3 = 0
C_[5:4]
Diagnostic mode disabled
SCbus Framing mode to select one of the following rate:
0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)
10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame
11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame
C_[7:6]
Local bus Framing mode to select one of the following rate:
0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)
10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame
11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame
C_[10:8]
Master clock input frequency select:
000 = 2.048 MHz (Default), 001 = 4.096 MHz, 010 = 8.192 MHz,
011 = 16.384 MHz, 100 = 32.768 MHz, 101= 65.536 MHz,
11X =Reserved
C_21 = 0
C_22
SCbus FSYNCN rate to select one SCLK period (Default)
SCbus SCLKX2N and SCLKX2NA output enable control
0: SCbus SCLKX2N and SCLKX2NA output enabled (Default)
1: SCbus SCLKX2N and SCLKX2NA output disabled
C_23
SCbus Alternate signals output enable control
0: SCbus Alternate signals output disabled (Default)
1: SCbus Alternate signals output enabled
C_[43:40] (Internal/External
Master PLL reference 8K select)
Internal/External Master PLL reference select:
If C_43 = 0 select the reference for the internal master PLL from C_[42:40]: 000 = Free-run (Default),
001/010 = Free-run,
011 = SREF_8K/SREF_8KA, 100 = REF_8K_0, 101 = REF_8K_1,
110 = REF_8K_2, 111 = REF_8K_3
(see Figure 2)
If C_43 = 1 select the reference for the external master PLL (output on REF_8K_OUT pin 7) from
C_[42:40]: 000 = Free-run (driven high) (Default), 001/010 = Free-run (driven high), 011 =
SREF_8K/SREF_8KA,
100 = REF_8K_0, 101 = REF_8K_1, 110/111 = Tri-state (Z)
(see Figure 3)
C_51 = 1
SCbus CLKFAIL latch debounce enabled
2000 Sep 07
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Table 4. Configuration Register Setup for MVIP Clock Master
Operation Mode
Conguration Register Bits Setup
Function Description
MVIP Master
C_0 = 1
C_1 = 0
C_2 = 0
C_3 = 0
C_[5:4] =00
MVIP clock master enabled
MVIP clock master disarmed (Default)
Primary SCbus signals selected (Default)
Diagnostic mode disabled (Note 1)
MVIP Framing mode to select only one rate:
0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)
C_[7:6]
Local bus Framing mode to select one of the following rate:
0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)
10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame
11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame
C_[10:8]
Master clock input frequency select:
000 = 2.048 MHz (Default), 001 = 4.096 MHz, 010 = 8.192 MHz,
011 = 16.384 MHz, 100 = 32.768 MHz, 101= 65.536 MHz,
11X =Reserved
C_21 = 1
C_22 = 0
C_23 =0
MVIP F0/ rate to select one C4/ period
MVIP C4/ output enabled (Default)
SCbus Alternate signals output disabled (Default)
C_[43:40] (Internal/External
Internal/External Master PLL reference select:
Master PLL reference 8K select)
If C_43 = 0 select the reference for the internal master PLL from C_[42:40]: 000 = Free-run (Default),
001/010 = Free-run,
011 = SEC_8K, 100 = REF_8K_0, 101 = REF_8K_1,
110 = REF_8K_2, 111 = REF_8K_3
(see Figure 2)
If C_43 = 1 select the reference for the external master PLL (output on REF_8K_OUT pin 7) from
C_[42:40]: 000 = Free-run (driven high) (Default), 001/010 = Free-run (driven high), 011 = SEC_8K,
100 = REF_8K_0, 101 = REF_8K_1, 110/111 = Tri-state (Z)
(see Figure 3)
Table 5. Configuration Register Setup for MVIP Clock Slave
Operation Mode
Conguration Register Bits Setup
Function Description
MVIP Slave
C_0 = 0
MVIP clock master disabled (Default)
MVIP clock master disarmed (Default)
Primary SCbus signals selected (Default)
Diagnostic mode disabled
C_1 = 0
C_2 = 0
C_3 = 0
C_[5:4] = 00
MVIP Framing mode to select only one rate:
0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)
C_[7:6]
Local bus Framing mode to select one of the following rate:
0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default)
10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame
11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame
2000 Sep 07
20
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Table 6. SCbus/MVIP Signals Cross Reference
SCbus 26-Pin Connector
SCbus Signal
MVIP Signal
MVIP 40-Pin Connector
1
SCLKX2N
GND
C4/
31
30, 32
35
37
33
N/A
8
2
GND
C2
3
SCLK
SREF_8K
FSYNCN
CLKFAIL
SD_0
4
SEC_8K
F0/
5
6
N/A
7
DSi0
GND
DSo0
DSi1
DSo1
DSi2
DSo2
DSi3
GND
DSo3
DSi4
DSo4
DSi5
DSo5
GND
DSi6
DSo6
DSi7
DSo7
N/A
8
GND
34
7
9
SD_1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SD_2
10
9
SD_3
SD_4
12
11
14
36
13
16
15
18
17
38
20
19
22
21
N/A
SD_5
SD_6
GND
SD_7
SD_8
SD_9
SD_10
SD_11
GND
SD_12
SD_13
SD_14
SD_15
MC
2000 Sep 07
21
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Register Access Schemes
cessor address bus interface from nine to
that all nine microprocessor address
The SC4000 features two address access two (A_[1:0]), as shown in Figure 5. The
pins (A_[8:0]) be used, as shown in
Figure 6.
schemes. One is an indirect access
scheme (C_11 = 0) to reduce the num-
ber of pins required for the micropro-
other is a combination of both indirect
and direct parallel access schemes (C_11
= 1). Using the combination requires
Figure 5. Using Two Pins A_[1:0] for Address Bus Interface Scheme (C_11 = 0)
Address
Data
FFh - E0h
DFh - C0h
BFh - A0h
9Fh - 80h
7Fh - 0Dh
0Ch - 00h
Source Parallel Access (31 - 0)
Destination Parallel Access (31 - 0)
Source Routing Memory (31 - 0)
Destination Routing Memory (31 - 0)
Reserved
03h
02h
01h
00h
High Byte Data Register (HBDR)
Low Byte Data Register (LBDR)
Internal Address Register (IAR)
Command/Status Register (CSR)
Configuration Register (12 - 0)
Note:See bit 5 and 4 of CSR to select
A_[1:0]
D_[7:0]
the bank of channels
Microprocessor
Figure 6. Using Nine Pins A_[8:0] for Address Bus Interface Scheme (C_11 = 1)
Address
Data
1FFh - 180h
17Fh - 100h
FFh - 04h
03h
Source Parallel Access (127 - 0)
Destination Parallel Access (127 - 0)
Reserved
FF - E0
DF - C0
BF - A0
9F - 80
7F - 0D
0C - 00
Source Parallel Access (31 - 0)
Destination Parallel Access (31 - 0)
Source Routing Memory (31 - 0)
Destination Routing Memory (31 - 0)
Reserved
High Byte Data Register (HBDR)
Low Byte Data Register (LBDR)
Internal Address Register (IAR)
Command/Status Register (CSR)
02h
01h
00h
Configuration Register (12 - 0)
Note:See bit 5 and 4 of CSR to select
the bank of channels
A_[8:0]
D_[7:0]
Microprocessor
2000 Sep 07
22
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Busy (D_0) (Read Only)
state machine has stopped running (no
MICROPROCESSOR INTERFACE
This bit is set (“1”) when a command
that requires synchronization with the
SC4000’s internal state machine has
been initiated. This bit clears (“0”)
when the command is completed.
SCLK). The command in process is
completed asynchronously and the
Busy bit is cleared. It is necessary to clear
(“0”) this bit after it has been set (“1”).
I/O Address Map
With Direct R/W to Parallel Access
Registers Disabled (C_11=0) (default)
A_[1:0]
REGISTER
Note: A new command (Read or Write)
should not be issued until after the
Terminate bit is cleared (“0”).
The following commands require
synchronization:
3h
2h
1h
0h
High Byte Data Register (HBDR)
Low Byte Data Register (LBDR)
Internal Address Register (IAR)
Command / Status Register
•
•
•
•
Destination Routing Memory
Write command
Channel Bank Select Register
[1:0] (D_[5:4]) (Read/Write)
This field determines the bank of chan-
nels that a command will affect. The
Channel Bank Select Register field is
combined with the Internal
Address Register to provide access to the
channel specific registers (routing and
parallel access). D_[5:4]) selects the
bank of channels to be accessed. This
field is cleared (“00”) on reset.
Source Routing Memory Write
command
With direct R/W to Parallel Access
Register Enable (C_11=1)
Indirect Parallel Access Destination
Write command
A_[8:0]
REGISTER
Indirect Parallel Access Source
Read command
1FFh:180h
Source Parallel Access Register
Ch. 127:0
Read (D_1) (Write only)
17Fh:100h
Destination Parallel Access Register
Ch. 127:0
Setting this bit (“1”) initiates a read of
the register pointed to by the Internal
Address Register. When the Busy bit is
clear (“0”), the contents of the register
to be read are available by reading the
Low byte & HighByte Data register. It is
not necessary to clear (“0”) this bit after
it has been set (“1”).
D_[5:4] = 00 -> Ch. 0 - 31
D_[5:4] = 01 -> Ch.32 - 63
D_[5:4] = 10 -> Ch.64 - 95
D_[5:4] = 11 -> Ch.96 - 127
0FFh:004h
003h
Reserved
High Byte Data Register (HBDR)
Low Byte Data Register (LBDR)
Internal Address Register (IAR)
Command / Status Register
002h
001h
Channel Bank Select Register Enable
(D_6) (Write only)
000h
Note: Set this bit for an Indirect Parallel
Access Source Read (this is the only
“READ” requiring synchronization).
For reads which do not require synchro-
nization, the data registers can be read
immediately after writing the internal
address register.
Writing to the command register with
this bit set (“1”) enables the Channel
bank select field to be changed. Writing
to the command register with this bit
cleared (“0”) causes the Channel Bank
Select Register field to retain its previous
value.
Command / Status Register (Address = 0h)
D_[7:0]
Definition
0
Busy (Read only)
1
Read Command (Write only)
Write Command (Write only)
Terminate Command (Read/Write)
2
3
Write (D_2) (Write only)
Note 1:The Channel Bank Select Regis-
ter may be changed during a write cycle
which also initiates a Read or Write
command. The Read or Write com-
mand affects the register pointed to by
the new value written into the Channel
Bank Select Register.
[5:4]
Channel Bank Select Register [1:0]
(Read/Write)
Setting this bit (“1”) initiates a write
to the register selected by the Internal
Address Register. When the Busy bit is
clear (“0”), the contents of the target
register have been updated using the
data stored in the Low Byte & High Byte
Data Register. It is not necessary to clear
(“0”) this bit after it has been set (“1”).
6
7
Channel Bank Select Register Enable
(Write only)
Reset (Read/Write)
Note:Setting more than one command
(Read, Write, Terminate or Reset) dur-
ing an access to the Command/Status
register is not recommended.
Note 2:The Channel Bank Select Regis-
ter should not be changed if the micro-
processor interface is busy.
Terminate (D_3) (Read/Write)
Setting this bit (“1”) terminates a com-
mand that requires synchronization
with the SC4000’s internal state ma-
chine. This is necessary to complete a
command when the SC4000’s internal
Note 3:The Channel Bank Select Regis-
ter should not be changed during a write
cycle that either sets (0->1) or clears
(1->0) the Terminate command.
2000 Sep 07
23
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Reset (D_7) (Read/Write)
Internal Address Register Map
Low Byte Data Register (Address = 02h)
D_[7:0] Definition
Setting this bit (“1”) puts the SC4000 in
reset and initializes the Configuration,
Routing and Parallel Access Registers.
This command is analogous to the func-
tion of the RESET pin. Clearing this bit
(“0”) returns the SC4000 to normal op-
eration, ready for configuration.
IAR_
[7:0]
Register
IAR_
[7:0]
Register
7:0
Low byte Data Register (LBDR_[7:0])
FFh:80h Channel Spe- FFh:E0h Source
cific Registers
Parallel
Access
High Byte Data Register (Address = 03h)
D_[7:0] Definition
DFh:C0h Destination
Parallel
7:0
High byte Data Register (HBDR_[7:0])
Internal Address Registerr (Address = 01h)
D_[7:0] Definition
Access
BFh:A0h Source
Routing
Memory
7:0
Internal Address Register (IAR_[7:0])
9Fh:80h Destination
Routing
Memory
7Fh:0Dh Reserved
0Ch:00h Configuration
Registers
2000 Sep 07
24
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Channel Specific Registers
The Channel Specific Registers are
divided into four groups. A group is se-
lected by bits 5 through 7 of theinternal
address register.
IAR_[7:5]
Channels within these groups are se-
lected by bits 4 through 0 (IAR_[4:0]) of
the Internal Address Register and bits 1
and 0 (D_[5:4] Command/Status Regis-
ter) of the Channel Bank Select Register
(CBSR)
100 -> Destination Routing Memory
101 -> Source Routing Memory
110 -> Destination Parallel Access
111 -> Source Parallel Access
Channel Specific Registers Map
D_[5:4] of Command/Status Register (D_6 = 1)
IAR[7:0]
CBSR_[1:0] = 00
CBSR_[1:0] = 01
CBSR_[1:0] = 10
CBSR_[1:0] = 11
IAR_[7:5]
FFh - E0h
IAR_[4:0] = 1Fh
Ch. 31
Ch. 30
.
Ch. 63
Ch. 62
.
Ch. 95
Ch. 94
.
Ch. 127
Ch. 126
.
IAR_[4:0] = 1Eh
Source
Parallel
Access
.
.
.
.
.
.
IAR_[4:0] = 01h
IAR_[4:0] = 00h
IAR_[4:0] = 1Fh
IAR_[4:0] = 1Eh
.
Ch. 1
Ch. 0
Ch. 31
Ch. 30
.
Ch. 33
Ch. 32
Ch. 63
Ch. 62
.
Ch. 65
Ch. 64
Ch. 95
Ch. 94
.
Ch. 97
Ch. 96
Ch. 127
Ch. 126
.
IAR_[7:5]
DFh - C0h
Destination
Parallel
Access
.
.
.
.
.
IAR_[4:0] = 01h
IAR_[4:0] = 00h
IAR_[4:0] = 1Fh
IAR_[4:0] = 1Eh
.
Ch. 1
Ch. 0
Ch. 31
Ch. 30
.
Ch. 33
Ch. 32
Ch. 63
Ch. 62
.
Ch. 65
Ch. 64
Ch. 95
Ch. 94
.
Ch. 97
Ch. 96
Ch. 127
Ch. 126
.
IAR_[7:5]
BFh - A0h
Source
Routing
Memory
.
.
.
.
.
IAR_[4:0] = 01h
IAR_[4:0] = 00h
IAR_[4:0] = 1Fh
IAR_[4:0] = 1Eh
.
Ch. 1
Ch. 0
Ch. 31
Ch. 30
.
Ch. 33
Ch. 32
Ch. 63
Ch. 62
.
Ch. 65
Ch. 64
Ch. 95
Ch. 94
.
Ch. 97
Ch. 96
Ch. 127
Ch. 126
.
IAR_[7:5]
9Fh - 80h
Destination
Routing
Memory
.
.
.
.
.
IAR_[4:0] = 01h
IAR_[4:0] = 00h
Ch. 1
Ch. 0
Ch. 33
Ch. 32
Ch. 65
Ch. 64
Ch. 97
Ch. 96
2000 Sep 07
25
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Destination Routing Memory—Low Byte
0 -> Output Disabled (Default)
2h -> SCbus SD_2
1 -> Output Enabled
.
LBDR_[7:0]
Definition
.
Source Routing Memory— Low Byte
[6:0]
7
Time-slot Select [6:0]
Reserved
Eh -> SCbus SD_14
Fh -> SCbus SD_15
LBDR_[7:0]
Definition
[6:0]
7
Time-Slot/Channel Select [6:0]
Reserved
Time-Slot Select [6:0] (Read/write)
If Local Connect is enabled this field is
don’t care.
This field selects the SCbus Time-Slot
that a Destination Channel is routed to.
Local Connect Enable (Read/Write)
This bit enables the Local Connection
of a Destination Channel to a Source
Channel.
Time-Slot/Channel Select [6:0] (Read/Write)
If Local Connect is disabled (default)
this field selects the SCbus Time-Slot
that is routed to a Source Channel.
00h -> SCbus Time-Slot 0 (Default)
01h -> SCbus Time-Slot 1
02h -> SCbus Time-Slot 2
.
0 -> Local Connect Disabled (Default)
1 -> Local Connect Enabled
00h -> SCbus Time-Slot 0 (Default)
01h -> SCbus Time-Slot 1
02h -> SCbus Time-Slot 2
.
.
Switch Output Enable (Read/Write)
This bit enables the Switch Output to
the Local Bus.
7Eh -> SCbus Time-Slot 126
7Fh -> SCbus Time-Slot 127
.
Destination Routing Memory— High Byte
0 -> Output Disabled (Default)
1 -> Output Enabled
7Eh -> SCbus Time-Slot 126
7Fh -> SCbus Time-Slot 127
HBDR_[7:0]
Definition
[3:0]
[5:4]
6
Port Select [3:0]
Reserved
Parallel Access
The parallel access channels can be ac-
cessed two ways: Indirect and Direct.
If Local Connect is enabled this field
selects the Destination Channel that
is routed to a Source Channel.
Parallel Access Enable
Switch Output Enable
7
Destination Parallel Access
LBDR_[7:0] Definition
00h -> Destination Channel 0 (Default)
01h -> Destination Channel 1
02h -> Destination Channel 2
.
Port Select [3:0] (Read/Write)
This field selects the SCbus Port that a
Destination Channel is routed to.
[7:0]
Serial Data Bit [1:8]
Serial Data [1:8] (Read/Write)
0h -> SCbus SD_0 (Default)
1h -> SCbus SD_1
2h -> SCbus SD_2
.
.
This register contains the byte to be
transmitted when Destination Routing
Memory Parallel Access is enabled
7Eh -> Destination Channel 126
7Fh -> Destination Channel 127
Note:When converted from parallel
to serial, bit 1 is transmitted first.
Source Routing Memory—High byte
HDBR_[7:0] Definition
.
Note: This register is cleared (“00”)
on Reset.
Eh -> SCbus SD_14
Fh -> SCbus SD_15
[3:0]
[5:4]
6
Port Select [3:0]
Reserved
Source Parallel Access
Parallel Access Enable (Read/Write)
Local Connect Enable
Switch Output Enable
LBDR_[7:0] Definition
This bit enables the Destination Parallel
Access channel to be output in place of
the SI Local Bus serial stream.
7
[7:0]
Serial Data Bit [1:8]
Port Select [3:0] (Read/Write)
This field selects the SCbus Port that is
routed to a Source Channel.
Serial Data [1:8] (Read Only)
0 -> Parallel Access Disabled (Default)
1 -> Parallel Access Enabled
This register contains the byte received
from the Source Channel selected by the
Source Routing Memory.
0h -> SCbus SD_0 (Default)
1h -> SCbus SD_1
Switch Output Enable (Read/Write)
This bit enables the Switch Output to
the SCbus.
Note: When converted from serial to
parallel, bit 1 is received first.
2000 Sep 07
26
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
SCbus Primary/Alternate Select (C_2)
Configuration Register Byte 1, IAR = 01H
CONFIGURATION REGISTERS
(Read/Write)
LBDR_[7:0]
C_[15:8]
Definition
Configuration Register Byte 0, IAR = 00H
The SC4000 provides Alternate SCbus
signals for fault tolerance. This bit con-
trols internal signal selection.
[2:0]
[10:8]
Master Clock Input
Frequency Select [2:0]
LBDR_[7:0]
C_[7:0]
Definition
0
1
0
1
SCbus Clock Master
3
11
Direct R/W to Parallel
Access Registers
Enable
0->Primary SCbus signals selected
(Default)
SCbus Clock Master
Arm
1->Alternate SCbus Signals selected
2
2
SCbus Primary/
Alternate Select
4
5
12
13
Message Channel
Registered TXD Enable
Diagnostic Mode Enable (C_3) (Read/Write)
In Diagnostic Mode the SC4000’s SCbus
output drivers and receivers are electri-
cally disconnected from the SCbus. In-
ternally, the SCbus outputs are looped
back to their corresponding inputs. This
creates a virtual SCbus within the
SC4000 that can be used to test thor-
oughly the SC4000 without disrupting
normal SCbus traffic.
3
3
Diagnostic Mode
Enable
Message Channel
TXD_0 or TXD_1
(internal HDLC) Select
[5:4]
[7:6]
[5:4]
[7:6]
SCbus Framing Mode
[1:0]
6
7
14
15
Message Channel
Clock Duty Cycle
Select
Local Bus Framing
Mode [1:0]
Message Channel
Output Disable
(w/Loopback)
SCbus Clock Master (C_0) (Read/Write)
This bit is synchronized with the Master
Clock Input enables the SC4000 to start
and stop being SCbus Clock Master.
0->Diagnostic Mode Disabled
Master Clock Input Frequency Select
[2:0] (C_[10:8]) (Read/Write)
000-> 2.048 MHz (Default)
1->Diagnostic Mode Enabled (default)
0-> SCbus Clock Master Disabled
(Default)
Note 1: Diagnostic Mode is Enabled
when the SC4000 is reset.
001-> 4.096 MHz
010-> 8.192 MHz
011->16.384 MHz
100-> 32.768 MHz
101-> 65.536 MHz
110-> Reserved
111-> Reserved
1-> SCbus Clock Master Enabled
Note 2: A clock must be present at the
Master Clock input to use this mode.
Note: With IAR=00H and LBDR D_0=0
issue Terminate command to asynchro-
nously stop being SCbus Clock Master
when no Master Clock Input is present
(i.e dead clock)
SCbus Framing Mode [1:0](C_[5:4])
(Read/Write)
0x -> 2.048 Mb/s, 256 Bits/Frame, 32
Timeslots/Frame (Default)
SCbus Clock Master Arm (C_1) (Read/Write)
The process of becoming SCbus Clock
Master can be sped up by arming the
SC4000 which is intended to become
clock master in the event of a clock fail-
ure. When a SC4000 is armed and CLK-
FAIL=1 the C_0 bit is automatically set.
The SC4000 begins driving the SCbus
within 4 clocks of CLKFAIL going high.
10 -> 4.096 Mb/s, 512 Bits/Frame, 64
Timeslots/frame
Note: The Master Clock Input may be
sourced from either X_IN or CLK_IN
(see C_43).
11 -> 8.192 Mb/s, 1024 Bits/Frame, 128
Timeslots/Frame
Direct R/W to Parallel Access Registers
Enable (C_11) (Read/Write)
0-> Direct R/W Disabled (Default)
Local bus Framing Mode [1:0](C_[7:6])
(Read/Write)
0x -> 2.048 Mb/s, 256 Bits/Frame, 32
Timeslots/Frame (Default)
1-> Direct R/W Enabled
0-> SCbus Clock Master Disarmed
(Default)
10 -> 4.096 Mb/s, 512 Bits/Frame, 64
Timeslots/frame
Note: When Disabled A_[8:2] is don’t
care. When Enabled address setup to
falling edge of WR_N or STRB_N is
required.
1-> SCbus Clock Master Armed
11 -> 8.192 Mb/s, 1024 Bits/Frame,
128 Timeslots/Frame
Note: C_51 SCbus CLKFAIL Debounce
Enable must be set to use this feature.
Message Channel Registered TXD Enable
(C_12) (Read/Write)
0-> TXD Passed Through onto MC
(Default)
Note: If the Local Bus framing mode
selection is for a higher data rate than
that of the SCbus framing mode, then a
65.536 MHz clock must be provided on
X_IN.
1-> TXD Registered onto MC
2000 Sep 07
27
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Note:When C_12=0 the HDLC Con-
troller must be programmed to output
TXD on the Rising edge of MC_CLK.
When C_12=1 the HDLC controller
must be programmed to output TXD on
the falling edge of MC_CLK.
Configuration Register Byte 2, IAR = 02H
LBDR_[7:0] C_[23:16] Definition
SCbus SD Output Delay Enable (C_18)
(Read/Write)
To avoid bus contention, enabled SCbus
SD outputs are delayed when coming
out of tri-state.
0
1
2
3
4
16
17
18
19
20
SCbus SD Sample
Position
Local bus SI Sample
Position
0-> SCbus SD Output Delay Disabled
(Default)
Message Channel TXD_0 or TXD_1 Select
(C_13) (Read/Write)
0-> TXD_0 External HDLC Controller
(Default)
SCbus SD Output
Delay Enable
1-> SCbus SD Output Delay Enabled
Local bus SO Output Delay Enable (C_19)
(Read/Write)
To avoid bus contention, enabled local
bus SO outputs are delayed when com-
ing out of tri-state.
Local bus SO Output
Delay Enable
1-> TXD_1 Future Internal HDLC
Controller
SCbus FSYNCN
Sample position
Note:If TXD_1 is selected on an SC4000
without an Internal HDLC Controller
all 1’s will be output on MC (idle).
5
6
21
22
SCbus FSYNCN Rate
0-> Local bus SO Output Delay Dis-
abled (Default)
SCbus SCLKX2N,
SCLKX2NA Output
Disable
Message Channel Clock Duty Cycle Select
(C_14) (Read/Write)
0-> 50% (Default)
1-> Local bus SO Output Delay Enabled
7
23
SCbus Alternate (A)
SCbus FSYNCN Sample Position (C_20)
(Read/Write)
0-> Sample at rising edge of SCLK
(Default)
Signals Output Enable
1-> 75% (2 &4 Mb/s SCbus modes),
62.5% (8 Mb/s SCbus)
SCbus SD Sample Position (C_16)
(Read/Write)
Note: SCLKX2N must be present to
select 75% when SCbus is 2 Mb/s.
0-> Sample at 50% of Bit Cell (Default)
1-> Sample at rising edge of SCLKX2N
with SCLK high.
1-> Sample at 75% of Bit Cell
Message Channel Output Disable
(W/ loopback) (C_15) (Read/Write)
0-> Message Channel Output Enabled
(Default)
SCbus FSYNCN Rate (C_21) (Read/Write)
This bit determines the clock by which
the FSYNCN signal is generated.
Note: SCLKX2N must be present to
select 75% sample.
Local Bus SI Sample Position (C_17)
(Read/Write)
0-> Sample at 50% of Bit Cell (Default)
0 -> 1 SCLK period (Default)
1 -> 1 SCLKX2N period
1-> Message Channel Output Disabled
Note:When the Message Channel is Dis-
abled, TXD is looped back to the RXD to
allow diagnostics runs on the HDLC
Controller.
1-> Sample at 75% of Bit Cell
Note: This mode is provided for MVIP
compatibility.
Note 1:To select 75% sample,SCLKX2N
must be present or the local bus framing
mode must be set to a data rate that is ei-
ther higher or lower than the SCbus
framing mode.
SCbus SCLKX2N, SCLKX2NA Output
Disable(C_22) (Read/Write)
This bit disables the SCLKX2N and
SCLKX2NA outputs when they are not
required. When disabled, the outputs
are tri-stated.
Note 2:To select 75% sample (C_17=1),
it is not necessary to select the L_CLK
rate equal to 2X (C_28=1)
0-> SCLKX2N and SCLKX2NA Outputs
Enabled (Default)
1-> SCLKX2N and SCLKX2NA Outputs
Disabled
2000 Sep 07
28
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
SCbus Alternate (A) Signals Output Enable
(C_23) (Read/Write)
This bit enables the SCbus Alternate
(“A”) Signals Output (when required).
When disabled, the outputs are
tri-stated.
Local bus L_CLK & L_FS Rate (C_28)
(Read/Write)
0 -> L_CLK & L_FS equal to the Local
bus data rate (Default)
Configuration Register Byte 4, IAR = 04H
LBDR_[7:0] C_[39:32]
Definition
[3:0]
[7:4]
[35:32]
[39:36]
Revision field (read
only)
1 -> L_CLK & L_FS equal to 2 times
the Local bus data rate
Version field (SC4000
= 1H, SC2000 = 0H)
(Read only)
0-> SCbus Alternate (“A”) Signals
Output Disabled (Default)
Note:To select the 2x rate, SCLKX2N
must be present or the Local bus fram-
ing mode must be set to a data rate that
is either higher or lower than the SCbus
framing mode.
1-> SCbus Alternate (“A”) Signals
Output Enabled
Version/Revision Status (C_[39:32])
The Version/Revision Register is a read
only register. It is intended for use to
identify SCxxxx devices.
Configuration Register Byte 3, IAR = 03H
Local bus L_CLK DPLL Enable (C_29)
(Read/Write)
This mode is provided to maintain a
continuous L_CLK for network inter-
faces during a Clock Fail condition.
LBDR_[7:0] C_[31:24]
Definition
This field may be changed in future
SCxxxx designs. It is recommended that
a test of this field be included in all ver-
sions of firmware interface code.
0
24
Local bus L_CLK
Polarity
1
25
Local bus L_FS
Polarity
0->L_CLK DPLL Disabled (Default)
1->L_CLK DPLL Enabled
The initial release of the SC4000 will be
Version/Revision = 10H
[3:2]
4
[27:26]
28
Local bus L_FS
Position [1:0]
Configuration Register 5,IAR = 05H
Note 1: The Local bus Framing Mode
(C_[7:6]) must be set to 2.048 Mb/s and
a 65.536MHz Clock must be supplied on
X_IN.
Local bus L_CLK
and L_FS Rate
LBDR_[7:0]
C_[47:40]
Definition
5
29
Local bus L_CLK
DPLL Enable
[2:0]
[42:40]
Master PLL Reference
Select [2:0]
Note 2:When Enabled L_CLK will run
free during an SCbus Clock Fail
condition.
6
30
Local bus L_CLK
8.192 MHz 62.5%
duty cycle Enable
3
43
Internal/External
Master PLL Select
[5:4]
6
[45:44]
46
SCbus SREF_8K
Source Select [1:0]
7
31
Reserved (0)
(Read only)
Note 3:When the DPLL enters the free-
run, the Local bus SO lines are tri-stated.
SCbus SREF_8K
Output Enable
Local bus L_CLK 8.192 MHz 62.5% Duty
Cycle (C_30) (Read/Write)
0 -> L_CLK 8.192 MHz 62.5% Duty
Cycle Disabled (Default)
Local bus L_CLK Polarity (C_24)
(Read/Write)
0- > L_CLK Non-Inverted (Default)
7
47
SCbus SCLK 8.192
MHz 62.5% duty
cycle enable
1- > L_CLK Inverted
1 -> L_CLK 8.192 MHz 62.5% Duty
Cycle Enabled
Master PLL Reference Select [2:0]
(C_[42:40]) (Read/Write)
Local bus L_FS Polarity (C_25) (Read/Write)
0- > L_FS Non-Inverted (Default)
Note: To enable L_CLK 8.192 MHz
62.5% Duty Cycle, the Local bus Fram-
ing Mode (C_[7:6]) must be set to 8.192
Mb/s and the SCbus Framing Mode
(C_[5:4]) must be set to 4.096 Mb/s or
2.048 Mb/s. C_28 must be set to 0.
When C_43=0 this field selects the refer-
ence for the Internal Master PLL.
1- > L_FS Inverted
Local bus L_FS Position (C_[27:26])
(Read/Write)
00 -> L_FS occurs during the last clock
period of the frame (Default)
000 -> Free-run (Default)
001 -> Free-run
010 -> Free-run
01 -> L_FS straddles the frame
boundary
011 -> SREF_8K
100 -> REF_8K_0
101 -> REF_8K_1
110 -> REF_8K_2
111 -> REF_8K_3
10 -> L_FS occurs during the first clock
period of the frame
11 -> Reserved
2000 Sep 07
29
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
When C_43=1 this field selects the refer-
ence for the External Master PLL which
is output on REF_8K_OUT pin7.
Configuration Register Byte 6, IAR = 06H
This mode is provided to force an
SC4000 off the SCbus when it’s control-
ling microprocessor fail to reset the
watchdog. Each time C_49 is cleared
“0” and the set “1” the watchdog count
is reset.
LBDR_[7:0] C_[55:48]
Definition
0
1
2
48
49
50
Clock Watchdog
Enable
000 ->Free-run (driven high) (Default)
001 ->Free-run (driven high)
010 ->Free-run (driven high)
011 -> SREF_8K
Microprocessor
Watchdog Enable
SCbus CLKFAIL Latch Set Polarity Select
(C_50) (Read/Write)
This bit selects the polarity of the SCbus
CLKFAIL signal that will set the
CLKFAIL latch.
SCbus CLKFAIL
Latch Set Polarity
Select
100 -> REF_8K_0
101 -> REF_8K_1
3
4
51
52
SCbus CLKFAIL
Latch Debounce
Enable
110 -> tri-state (Z)
0 -> CLKFAIL latch set when
CLKFAIL = 0 (Default)
111 -> tri-state (Z)
Frame Boundary
Latch Set Delay Enable
1 -> CLKFAIL latch set when
CLKFAIL = 1
Internal/External Master PLL Select (C_43)
(Read/Write)
This bit selects the Master PLL to be
either Internal or External.
5
6
7
53
54
55
INT_0 Mask_n
INT_0 Polarity
Note 1:The CLKFAIL polarity bit can be
used to generate interrupts on both ends
of a CLKFAIL transition. The CLKFAIL
= 0 interrupt is used by the new primary
clock source to determine that the tran-
sition from secondary to primary has
been made. The CLKFAIL = 1 interrupt
is used by a secondary clock source to
determine that the primary clock source
has given up the bus. A third module
(neither primary or secondary) could
use this interrupt to monitor the CLK-
FAIL transition and act as a system
watchdog.
INT_0 Output Driver
Configuration
0 -> Internal Master PLL (Default)
1 -> External Master PLL
Clock Watchdog Enable (C_48) (Read/Write)
This bit enables the Clock Watchdog.
SCbus SREF_8K Source Select [1:0]
(C_[45:44]) (Read/Write)
00 -> REF_8K_0 (Default)
0 -> Clock Watchdog Disabled (Default)
1 -> Clock Watchdog Enabled
01 -> REF_8K_1
10 -> REF_8K_2
11 -> REF_8K_3
Note: When enabled, C_48 is read back a
1 until the Master PLL clocks for 125us
(+/- 50%); then it reads back a 0. This
mode is provided to allow detection of a
missing PLL clock. This information can
then be used to take a master off the bus
or to remove a secondary clock master
from the fallback list. The Clock Watch-
dog must be re-armed after each test. To
re-arm, the Clock Watchdog C_48 must
be cleared to “0” and then set to “1”.
SCbus SREF_8K Output Enable (C_46)
(Read/Write)
0 -> SCbus SREF_8K Disabled (Z)
(Default)
Note 2:Only change CLKFAIL polarity
when CLKFAIL Latch Clear_N
(C_60) = 0.
1 -> SCbus SREF_8K Enabled
SCbus CLKFAIL Latch Debounce Enable (C_51)
(Read/Write)
0 -> CLKFAIL Latch Debounce Disabled
(Default)
SCbus SCLK 8.192 MHz 62.5% Duty Cycle
(C_47) (Read/Write)
0 -> SCLK 8.192 MHz 62.5% Duty
Cycle Disabled (Default)
Microprocessor Watchdog Enable (C_49)
(Read/Write)
This bit enables the Microprocessor
Watchdog.
1 -> CLKFAIL Latch Debounce Enabled
1 -> SCLK 8.192 MHz 62.5% Duty
Cycle Enabled
Note 1: A clock must be present from the
Master PLL to enable this feature.
Note:The SCbus Framing Mode
(C_[5:4]) must be set to 8.192 Mb/s to
enable SCLK 8.192 MHz 62.5% duty
cycle. If Enable (C_22=0) SCLKX2N
will be driven high.
0 -> Microprocessor Watchdog Dis-
abled (Default)
Note 2: The debounce logic requires that
the CLKFAIL signal be sampled with the
same value for two consecutive Master
PLL clocks before it can set the CLK-
FAIL Latch.
1 -> Microprocessor Watchdog Enabled
Note:When enabled the SC4000 will be
put into reset after the Master PLL
clocks for 256 ms (+/-50%).
2000 Sep 07
30
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Frame Boundary Latch Set Delay Enable
(C_52) (Read/Write)
0 -> Frame Boundary Latch Set at frame
boundary - no delay (Default)
Configuration Register Byte 7, IAR = 07H
SCbus CLKFAIL Latch Clear_N (C_60)
(Read/Write)
0 -> SCbus CLKFAIL Latch held clear
(Default)
LBDR_[7:0] C_[63:56]
Definition
0
1
2
56
57
58
SCbus CLKFAIL Latch
(Read only)
1 -> Frame Boundary Latch Set is
delayed until after the input buffer to
output buffer transfer is complete (4
internal clocks after frame boundary).
1 -> SCbus CLKFAIL Latch enabled
Frame Boundary
Latch (Read only)
Frame Boundary Latch Clear_N (C_61)
(Read/Write)
0 -> Frame Boundary Latch held clear
(Default)
Internal Master PLL
Error Latch
Note 1: With direct W/R to Parallel Ac-
cess Register Enabled (C_11=1), using
the delayed frame boundary interrupt
indicates that it is now safe to read from
and write to the Parallel Access Regis-
ters. To avoid data corruption, all access
must be completed 8 internal clocks
prior to the next delayed frame bound-
ary interrupt.
(Read only)
3
4
5
6
7
59
60
61
62
63
SCbus Error Indicator
(Read only)
1 -> Frame Boundary Latch enabled
Internal Master PLL Error Latch Clear_N
(C_62) (Read/Write)
0 -> Internal Master PLL Error Latch
held clear (Default)
SCbus CLKFAIL Latch
Clear_n
Frame Boundary
Latch Clear_n
1 -> Internal Master PLL Error Latch
enabled
Internal Master PLL
Error Latch Clear_n
Note 2:The internal clock is equal to
either the SCbus data rate or the Local
bus data rate whichever is faster.
Reserved (0)
(Read only)
Configuration Register Byte 8, IAR = 08H
LBDR_[7:0] C_[71:64]
Definition
SCbus CLKFAIL Latch (C_56) (Read Only)
0 -> SCbus CLKFAIL Latch Clear
INT_0 Mask_N (C_53) (Read/Write)
0
1
64
65
SCbus SCLKX2N
Error Latch
(Read only)
Clearing this bit(“0”) masks INT_0.
INT_0 is the logical OR of CLKFAIL
(C_56), Frame Boundary (C_57), Inter-
nal Master PLL Error (C_58) Latches
and SCbus Error (C_59) Indicator.
1 -> SCbus CLKFAIL Latch Set
SCbus SCLKX2NA
Error Latch
(Read only)
Frame Boundary Latch (C_57) (Read only)
0 -> Frame Boundary Latch Clear
2
3
4
5
6
7
66
67
68
69
70
71
SCbus SCLK Error
Latch (Read only)
1 -> Frame Boundary Latch Set
0 -> INT_0 Masked (Default)
1 -> INT_0 Enabled
Internal Master PLL Error Latch (C_58)
(Read Only)
This latch is set when the Internal Mas-
ter PLL is not “locked” to its selected ref-
erence.
SCbus SCLKA Error
Latch (Read only)
Note: The INT_0 Mask bit can be used
to globally disable interrupt generation
while the state of the latches can con-
tinue to be polled through the micro-
processor interface. This bit can also be
used to create edge-triggered interrupts.
SCbus SCLKX2N
Error Latch Clear_n
SCbus SCLKX2NA
Error Latch Clear_n
0 -> Internal Master PLL Error Latch
Clear
SCbus SCLK Error
Latch Clear_n
1 -> Internal Master PLL Error Latch Set
INT_0 Output Polarity (C_54) (Read/Write)
0 -> INT_0 Active Low (Default)
SCbus SCLKA Error
Latch Clear_n
SCbus Error Indicator (C_59) (Read Only)
C_59 is the logical OR of C_[67:64],
C_[74:72] and C_[83:80].
1 -> INT_0 Active High
SCbus SCLKX2N Error Latch (C_64)
(Read Only)
The SCbus SCLKX2N Error Latch is
set when SCLKX2N does not transition
during the equivalent Master PLL clock
period.
INT_0 Output Driver (C_55) (Read/Write)
0 -> Open Collector INT_0 Output
Driver (Default)
0 -> All SCbus Error Latches Clear
1 -> one or more SCbus Error Latches
Set
1 -> Totem-Pole INT_0 Output Driver
0 -> SCbus SCLKX2N Error Latch Clear
1 -> SCbus SCLKX2N Error Latch Set
2000 Sep 07
31
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
SCbus SCLKX2NA Error Latch (C_65)
(Read only)
The SCbus SCLKX2NA Error Latch is
set when SCLKX2NA does not transi-
tion during the equivalent Master PLL
clock period.
Configuration Register Byte 9, IAR = 09H
(i.e. two device driving FSYNCN).
0 ->SCbus Clock Master Error Latch
Clear
LBDR_[7:0] C_[79:72]
Definition
0
1
2
72
73
74
SCbus FSYNCN
Error Latch
(Read Only)
1 ->SCbus Clock Master Error Latch Set
SCbus FSYNCN Error Latch Clear_N (C_76)
(Read/Write)
0 ->SCbus FSYNCN Error Latch held
clear (Default)
SCbus FSYNCNA
Error Latch
(Read Only)
0 -> SCbus SCLKX2NA Error Latch
Clear
1 -> SCbus SCLKX2NA Error Latch Set
SCbus Clock Mas-
ter Error Latch (Read
Only)
1 ->SCbus FSYNCN Error Latch
enabled
SCbus SCLK Error Latch (C_66) (Read only)
The SCbus SCLK Error Latch is set when
SCLK does not transition during the
equivalent Master PLL clock period.
3
4
5
6
75
76
77
78
Reserved (0)
(Read Only)
SCbus FSYNCNA Error Latch Clear_N (C_77)
(Read/Write)
0 ->SCbus FSYNCNA Error Latch held
clear
SCbus FSYNCN
Error Latch Clear_n
0 -> SCbus SCLK Error Latch Clear
1 -> SCbus SCLK Error Latch Set
SCbus FSYNCNA
Error Latch Clear_n
1 ->SCbus FSYNCNA Error Latch
enabled
SCbus SCLKA Error Latch (C_67) (Read only)
The SCbus SCLKA Error Latch is set
when SCLKA does not transition during
the equivalent Master PLL clock period.
SCbus Clock
Master Error Latch
Clear_n
SCbus Clock Master Error Latch Clear_N
(C_78) (Read/Write)
0 ->SCbus Clock Master Error Latch
held clear (Default)
7
79
Reserved (0)
(Read Only)
0 -> SCbus SCLKA Error Latch Clear
1 -> SCbus SCLKA Error Latch Set
1 ->SCbus Clock Master Error Latch
enabled
SCbus FSYNCN Error Latch (C_72)
(Read Only)
The SCbus FSYNCN Error Latch is set
when FSYNCN does not transition
during the equivalent Master PLL clock
period.
SCbus SCLKX2N Error Latch Clear_N (C_68)
(Read/Write)
0 ->SCbus SCLKX2N Error Latch held
clear (Default)
Configuration Register Byte 10, IAR = 0AH
LBDR_[7:0] C_[87:80]
Definition
0
1
2
80
81
82
SCbus SREF_8K NE
SREF_8KA Error
Latch (Read only)
1 ->SCbus SCLKX2N Error Latch
enabled
0 ->SCbus FSYNCN Error Latch Clear
1 ->SCbus FSYNCN Error Latch Set
SCbus SCLKX2NA Error Latch Clear_N
(C_69) (Read/Write)
0 ->SCbus SCLKX2NA Error Latch held
clear (Default)
SCbus CLKFAIL NE
CLKFAILA Error
Latch (Read only)
SCbus FSYNCNA Error Latch (C_73)
(Read Only)
The SCbus FSYNCNA Error Latch is set
when FSYNCNA does not transition
during the equivalent Master PLL clock
period.
SCbus MC NE MCA
Error Latch
1 ->SCbus SCLKX2NA Error Latch
enabled
(Read only)
3
4
83
84
SCbus SD Error Indi-
cator (Read only)
SCbus SCLK Error Latch Clear_N (C_70)
(Read/Write)
0 ->SCbus SCLK Error Latch held clear
(Default)
0 ->SCbus FSYNCNA Error Latch Clear
1 ->SCbus FSYNCNA Error Latch Set
SCbus SREF_8K NE
SREF_8KA Error
Latch Clear_n
SCbus Clock Master Error Latch (C_74)
(Read Only)
5
85
SCbus CLKFAIL NE
CLKFAILA Error
Latch Clear_n
1 ->SCbus SCLK Error Latch enabled
SCbus SCLKA Error Latch Clear_N(C_71)
(Read/Write)
0 ->SCbus SCLKA Error Latch held
clear (Default)
The SCbus Clock Master Error Latch is
set when the SC4000 is configured to be
Clock Master and the internally gener-
ated frame sync signal and SCbus
FSYNCN are not equal. This feature is
provided to detect when more than one
SCbus device is enabled as Clock Master
6
7
86
87
SCbus MC NE MCA
Error Latch Clear_n
SCbus SD Error Latch
Clear_n
1 ->SCbus SCLKA Error Latch enabled
NE:Not Equal
2000 Sep 07
32
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
SCbus SREF_8K NE SREF_8KA Error Latch
(C_80)(Read only)
The SCbus SREF_8K NE SREF_8KA
Error Latch is set when SREF_8K and
SREF_8KA are not equal for three
consecutive Master PLL clocks.
SCbus MC NE MCA Error Latch Clear_N
(C_86)(Read/Write)
0 ->SCbus MC NE MCA Error Latch
held clear (Default)
SUMMARY OF SC4000
CONFIGURATION REGISTERS
Miscellaneous
Diagnostic Mode Enable (C_3)
(Read/Write)
1 ->SCbus MC NE MCA Error Latch
enabled
Direct R/W to Parallel Access Registers
Enable (C_11) (Read/Write)
0 ->SCbus SREF_8K NE SREF_8KA
Error Latch Clear
SCbus SD Error Latch Clear_N
(C_87)(Read/Write)
0 ->SCbus SD Error Latch held clear
(Default)
SC4000 Revision/Version Register
(C_[39:32]) (Read only)
1 ->SCbus SREF_8K NE SREF_8KA
Error Latch Set
Master Clock/PLL
Master Clock Input Frequency Select
[2:0] (C_[10:8]) (Read/Write)
SCbus CLKFAIL NE CLKFAILA Error Latch
(C_81)(Read only)
The SCbus CLKFAIL NE CLKFAILA
Error Latch is set when CLKFAIL and
CLKFAILA are not equal for three
consecutive Master PLL clocks.
1 ->SCbus SD Error Latch enabled
Note: C_87 controls all 16 SD Error
latches.
Master PLL Reference Select [2:0]
(C_[42:40]) (Read/Write)
Configuration Register Byte 11, IAR = 0BH
LBDR_[7:0]
C_[95:88]
Definition
Internal/External Master PLL Select
(C_43) (Read/Write)
0 ->SCbus CLKFAIL NE CLKFAILA
Error Latch Clear
[7:0]
[95:88]
SCbus SD_[7:0]
Error Latch (Read
only)
SCbus (MVIP Bus)
SCbus Clock Master (C_0)
(Read/Write)
1 ->SCbus CLKFAIL NE CLKFAILA
Error Latch Set
Configuration Register Byte 12, IAR = 0CH
SCbus MC NE MCA Error Latch (C_82)
(Read only)
Scbus Clock Master Arm (C_1)
(Read/Write)
LBDR_[7:0]
C_[103:96]
Definition
The SCbus MC NE MCA Error Latch
is set when MC and MCA are not
equal. MC_CLK is used to sample
the comparison.
[7:0]
[103:96]
SCbus SD_[15:8]
Error Latch
(Read only)
SCbus Primary/Alternate Select (C_2)
(Read/Write
SCbus Framing Mode [1:0](C_[5:4])
(Read/Write)
SCbus SD_[15:0] Error Latch (C_[103:88])
(Read only)
0 ->SCbus MC NE MCA Error Latch
Clear
SCbus SD Sample Position (C_16)
(Read/Write)
An SCbus SD Error Latch is set when an
SD output timeslot is enabled and the
internally generated SD signal and
SCbus are not equal. This feature is
provided to detect when more than one
SCbus device is enabled on the same
timeslot. All SCbus SD Error Latches
are enabled and cleared by C_87.
1 ->SCbus MC NE MCA Error Latch Set
SCbus SD Output Delay Enable (C_18)
(Read/Write)
SCbus SD Error Indicator (C_83) (Read only)
C_83 is the logical OR of C_[103:88]
SCbus FSYNCN Sample Position
(C_20) (Read/Write)
0 -> All SCbus SD Error Latches Clear
1 -> One or more SCbus SD Error Latch
Set
SCbus FSYNCN Rate (C_21)
(Read/Write)
SCbus SREF_8K NE SREF_8KA Error Latch
Clear_N (C_84)(Read/Write)
0 ->SCbus SREF_8K NE SREF_8KA
Error Latch held clear (Default)
SCbus SCLKX2N, SCLKX2NA Output
Disable (C_22) (Read/Write)
Note:If multiple destination channels
within the same SC4000 are enabled
onto the same timeslot anerror will not
occur. Bus contention is prevented by
logically “ANDing” the internal SD
signals before they are output onto the
SCbus SD.
SCbus Alternate (“A”) Signals Output
Enable (C_23) (Read/Write)
1 ->SCbus SREF_8K NE SREF_8KA
Error Latch enabled
SCbus SREF_8K Source Select [1:0]
(C_[45:44]) (Read/Write
SCbus CLKFAIL NE CLKFAILA Error Latch
Clear_N (C_85)(Read/write)
0 ->SCbus CLKFAIL NE CLKFAILA
Error Latch held clear (Default)
SCbus SREF_8K Output Enable (C_46)
(Read/Write)
SCbus SCLK 8.192 MHz 62.5% Duty
Cycle (C_47) (Read/Write)
1 ->SCbus CLKFAIL NE CLKFAILA
Error Latch enabled
2000 Sep 07
33
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Local Bus
INT_0 Output Driver (C_55)
SCbus SREF_8K NE SREF_8KA Error
Local bus Framing Mode [1:0] (C_[7:6])
(Read/Write)
(Read/Write)
Latch (C_80)(Read only)
SCbus CLKFAIL Latch (C_56)
(Read Only)
SCbus CLKFAIL NE CLKFAILA Error
Latch (C_81)(Read only)
Local Bus SI Sample Position (C_17)
(Read/Write)
Frame Boundary Latch (C_57)
(Read only)
SCbus MC NE MCA Error Latch
(C_82)(Read only)
Local bus SO Output Delay Enable
(C_19) (Read/Write)
Internal Master PLL Error Latch (C_58)
(Read Only)
SCbus SD Error Indicator (C_83)
(Read only)
Local bus L_CLK Polarity (C_24)
(Read/Write)
SCbus Error Indicator (C_59)
(Read Only)
SCbus SREF_8K NE SREF_8KA Error
Latch Clear_N (C_84)(Read/Write)
Local bus L_FS Polarity (C_25)
(Read/Write)
SCbus CLKFAIL Latch Clear_N (C_60)
(Read/Write)
SCbus CLKFAIL NE CLKFAILA Error
Latch Clear_N (C_85)(Read/write)
Local bus L_FS Position (C_[27:26])
(Read/Write)
Frame Boundary Latch Clear_N (C_61)
(Read/Write)
SCbus MC NE MCA Error Latch
Clear_N (C_86)(Read/Write)
Local bus L_CLK & L_FS Rate (C_28)
(Read/Write)
Internal Master PLL Error Latch
Clear_N (C_62) (Read/Write)
SCbus SD Error Latch Clear_N
(C_87)(Read/Write)
Local bus L_CLK DPLL Enable (C_29)
(Read/Write)
SCbus SCLKX2N Error Latch (C_64)
(Read Only)
SCbus SD_[15:0] Error Latch
(C_[103:88]) (Read only)
Local bus L_CLK 8.192 MHz 62.5%
Duty Cycle (C_30) (Read/Write)
SCbus SCLKX2NA Error Latch (C_65)
(Read only)
Reserved Bit
No use Bit (C_31) (Read only)
Message Channel
Message Channel Registered TXD
Enable (C_12) (Read/Write)
SCbus SCLK Error Latch (C_66)
(Read only)
No use Bit (C_63) (Read only)
No use Bit (C_75) (Read only)
No use Bit (C_79) (Read only)
Message Channel TXD_0 or TXD_1
Select (C_13) (Read/Write)
SCbus SCLKA Error Latch (C_67)
(Read only)
Message Channel Clock Duty Cycle
Select (C_14) (Read/Write)
TYPICAL INTERNAL REGISTER ACCESS
SCbus SCLKX2N Error Latch Clear_N
(C_68) (Read/Write)
Typical Write Internal Register Access
1. Read Command/Status register and
test for NOT BUSY. (Note1)
Message Channel Output Disable
(W/ loopback) (C_15) (Read/Write)
SCbus SCLKX2NA Error Latch Clear_N
(C_69) (Read/Write)
Watchdog
Clock Watchdog Enable (C_48)
(Read/Write)
SCbus SCLK Error Latch Clear_N
(C_70) (Read/Write)
2. Write Data into Internal Address reg-
ister, Low Byte Data register, and
High Byte Data register as required.
SCbus SCLKA Error Latch
Clear_N(C_71) (Read/Write
Microprocessor Watchdog Enable
(C_49) (Read/Write)
3. Write a “1” to the WRITE Command
bit in the Command/Status register.
(Note 4)
SCbus FSYNCN Error Latch (C_72)
(Read Only)
Interrupt
SCbus CLKFAIL Latch Set Polarity
Select (C_50) (Read/Write)
4. Read Command/Status register and
test for NOT BUSY. (Note 2)
SCbus FSYNCNA Error Latch (C_73)
(Read Only)
SCbus CLKFAIL Latch Debounce
Enable (C_51) (Read/Write)
SCbus Clock Master Error Latch (C_74)
(Read Only)
Typical Read Internal Register Access
1. Read Command/Status register and
test for NOT BUSY. (Note 1)
Frame Boundary Latch Set Delay Enable
(C_52) (Read/Write)
SCbus FSYNCN Error Latch Clear_N
(C_76) (Read/Write)
2. Write Data into Internal Address
register.
INT_0 Mask_N (C_53) (Read/Write)
SCbus FSYNCNA Error Latch Clear_N
(C_77) (Read/Write)
3. Write a “1” to the READ Command
bit in the Command/Status register.
(Note 3 & 4)
INT_0 Output Polarity (C_54)
(Read/Write)
SCbus Clock Master Error Latch
Clear_N (C_78) (Read/Write)
2000 Sep 07
34
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
4. Read Command/Status register and
test for NOT BUSY. (Note2)
Test
A_5
A_6
A_7
A_8
↓
SD_4
The Nand gate test chain is enabled by
forcing the TEST pin “high”. When in
test mode each pin is “nanded” with the
preceding pin and output at the end of
chain.
SD_5
SD_6
SD_7
SD_8
SD_9
SD_10
SD_11
SD_12
SD_13
SD_14
SD_15
MC
5. Read contents of Low Byte Data regis-
ter and High Byte Data register as
required.
Note 1:It is not necessary to test for
NOT BUSY in this step if the protocol
X_IN
D_0
DRQ_R
used to access the SC4000 does not allow REF_8K_0
D_1
the previous command to be completed
until the Command/Status register indi-
cates NOT BUSY.
REF_8K_1
D_2
REF_8K_2
D_3
REF_8K_3
D_4
Note 2:It is not necessary to test for
NOT BUSY in this step if the Command
given does not require synchronization
or if the protocol used to access the
SC4000 allows a command to be com-
pleted while the Command/Status regis-
ter indicates BUSY.
TXD_0
RXD
D_5
D_6
MC_CLK
I_N
D_7
SCLKX2N
SCLKX2NA
SCLK
MCA
INT_0
INT_1
CS_0_N
CS_1_N
RD_N
WR_N
DACK_N
ALE
L_CLK
L_FS
SO_0
SO_1
SO_2
SO_3
SI_0
Note 3:It is not necessary to execute this
step if the Command given does not re-
quire synchronization.
SCLKA
SREF_8K
SREF_8KA
FSYNCN
FSYNCNA
CLKFAIL
CLKFAILA
SD_0
Note 4:The Channel Bank Select field
may be changed during the same write
cycle which issues a command. The
command will effect the register pointed
to by the new value in the Channel Bank
Select Field.
SI_1
A_0
SI_2
A_1
SI_3
A_2
SD_1
RESET
↓
A_3
SD_2
A_4
SD_3
DRQ_T
2000 Sep 07
35
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Symbol
Parameter
Test Condition
Min
-65
Max
150
7
Unit
o
T
s
Storage Temperature
Input Voltage
C
V
i
-0.5
V
P
Package Power Dissipation
1
W
D
Recommended Operating Conditions
Symbol
Parameter
Test Condition
Min
0
Max
70
Unit
o
T
Ambient Temperature
Supply Voltage
C
A
V
4.75
5.25
V
DD
DC Electrical Characteristic
Symbol
Parameter
Test Condition
Min
Max
Unit
I
Supply Current
100
mA
DD
V
Input High Voltage - SCbus
Input Low Voltage - SCbus
Input Hysteresis Voltage-SCbus
Input High Voltage -TTL
Input Low Voltage -TTL
Input High Voltage -CMOS
Input Low Voltage -CMOS
Output High Voltage -SCbus
Output Low Voltage -SCbus
Output High Voltage-TTL
Output Low Voltage-TTL
Output High Voltage-CMOS
Output Low Voltage-CMOS
Pull-up Current - SCbus
Pull-up Current - TTL
2.6
V
+0.5
V
IH-SCbus
DD
V
-0.5
1.65
V
IL-SCbus
V
+/- 0.3
2.0
V
HYS-SCbus
V
V
+0.5
+0.5
V
IH-TTL
DD
V
-0.5
0.8
V
IL-TTL
V
V
0.7 x V
V
DD
IH-CMOS
DD
V
-0.5
3
0.3 x V
DD
V
IL-CMOS
I
= -24mA
= 24mA
= -8mA
= 8mA
V
V
OH
OH-SCbus
I
V
0.4
0.4
V
V
OL
OL-SCbus
I
V
2.4
V
V
OH
OH-TTL
I
V
V
OL
OL-TTL
I
= -0.8mA
= 0.8mA
V
V
- 0.1V
OH
OH-CMOS
DD
I
V
V
+ 0.1 V
OL
OL-CMOS
SS
I
µA
µA
µA
pF
-20
-50
V
V
= 0V
P-SCbus
PAD
I
-130
-400
= 0V
P-TTL
PAD
I
I/O Leakage Current
+/- 10
6
V
= V or V
LI/O
I/O DD
SS
C
Input Capacitance-TTL
Input Capacitance-CMOS
I/O Capacitance-SCbus
Output or I/O Capacitance - TT
Output Capacitance - CMOS
I-TTL
C
7
pF
pF
pF
I-CMOS
C
12
7
IO-SCbus
C
IO-TTL
CO-CMOS
6
pF
2000 Sep 07
36
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
AC ELECTRICAL CHARACTERISTICS
Figure 7. Microprocessor Interface Timing - Intel Bus Mode (Pin I_N = 0), Non-Multiplexed Address
t1
CS_0_N
RD_N
t2
WR_N
A_[8:0]
D_[7:0]
t3
t4
t5
t7
t6
t8
t9
Table 7. Microprocessor Interface Timing - Intel Bus Mode
Symbol
Parameter
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
t8
CS_0_N setup to WR_N ↑
WR_N pulse width
40
40
5
A_[8:0] setup to WR_N ↓ (C_11 = 1)
A_[1:0] setup to WR_N ↑ (C_11 = 0)
A_[8:0] hold from WR_N ↑
D_[7:0] setup to WR_N ↑
40
5
40
5
D_[7:0] hold from WR_N ↑
50
20
D_[7:0] float to valid delay from CS_0_N, RD_N
and A_[8:0]
0
ns
0
t9
D_[7:0] valid to float delay from CS_0_N or RD_N
Notes
1. Timing measured with 100 pF load on D_[7:0].
2. Write cycle may be controlled by CS_0_N or WR_N.
3. ALE = 1.
2000 Sep 07
37
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 8. Microprocessor Interface Timing - Motorola Bus Mode (Pin I_N = 1), Non-multiplexed Address
t1
CS_0_N
t2
STRB_N
t4
t4
t3
t3
R/W_N
t5
t7
t6
A_[8:0]
D_[7:0]
t8
t9
t10
t11
Table 8. Microprocessor Interface Timing - Intel Bus Mode
Symbol
Parameter
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
CS_0_N setup to STRB_N ↑
STRB_N pulse width
40
40
5
R/W_N setup to STRB_N ↓
R/W_N hold from STRB_N ↑
A_[8:0] setup to STRB_N ↓ (C_11 = 1)
A_[1:0] setup to STRB_N ↑ (C_11 = 0)
A_[8:0] hold from STRB_N ↑
D_[7:0] setup to STRB_N ↑
D_[7:0] hold from STRB_N ↑
5
5
40
5
40
5
D_[7:0] float to valid delay from CS_0_N,
STRB_N and A_[8:0]
50
20
0
ns
0
t11
D_[7:0] valid to float delay from CS_0_N or STRB_N
1. Timing measured with 100 pF load on D_[7:0].
Notes
2. Write cycle may be controlled by CS_0_N or STRB_N.
3. ALE = 1.
2000 Sep 07
38
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 9. MicroprocessorInterface Timing-MultiplexedAddress
t1
ALE
t2
t3
A_[8:0]
Table 9. Microprocessor Interface Timing - Multiplexed Address
Symbol
Parameter
Min
Typ
Max
Unit
t1
t2
t3
ALE pulse width
20
5
ns
ns
ns
A_[8:0] setup to ALE ↓
A_[8:0] hold from ALE ↓
5
2000 Sep 07
39
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 10. Local Bus Timing, 1XL_CLK Mode (C_28 = 0)
Frame Boundary
t1
L_CLK
t2
t2
L_FS
(C_[27:26]=00)
t2
t2
L_FS
(C_[27:26]=01)
t2
t3
t2
t4
L_FS
(C_[27:26]=10)
t5
SO
SI
t6 t7
Table 10. Local Bus Timing, 1X L_CLK Mode (C_28 = 0)
Symbol
Parameter
Min
Typ
Max
Unit
488
244
122
ns
ns
ns
t1a
t1b
t1c
t2a
t2b
t3a
t3b
t3c
t3d
t3e
t3f
L_CLK Period (C_[7:6] = 0X)
L_CLK Period (C_[7:6] = 10)
L_CLK Period (C_[7:6] = 11)
L_FS delay from L_CLK (C_29 = 0)
L_FS delay from L_CLK (C_[7:6] = 0X, C_29 = 1)
0
10
25
10
25
60
75
60
30
10
25
10
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-15
0
SO_[3:0] float to valid delay from L_CLK ↑ (C_19 = 0, C_29 = 0)
SO_[3:0] float to valid delay from L_CLK ↑ (C_19 = 0, C_[7:6] = 0X, C_29 = 1)
SO_[3:0] float to valid delay from L_CLK ↑ (C_19 = 1, C_[7:6] = 0X, C_29 = 0)
SO_[3:0] float to valid delay from L_CLK ↑ (C_19 = 1, C_[7:6] = 0X, C_29 = 1)
SO_[3:0] float to valid delay from L_CLK ↑ (C_19 = 1, C_[7:6] = 10)
SO_[3:0] float to valid delay from L_CLK ↑ (C_19 = 1, C_[7:6] = 11)
SO_[3:0] valid to valid delay from L_CLK ↑ (C_29 = 0)
-15
25
10
25
10
0
t4a
t4b
t5a
t5b
t6a
t6b
t7a
t7b
Notes
SO_[3:0] valid to valid delay from L_CLK ↑ (C_[7:6] = 0X, C_29 = 1)
SO_[3:0] valid to float delay from L_CLK ↑ (C_29 = 0)
-15
0
SO_[3:0] valid to float delay from L_CLK ↑ (C_[7:6] = 0X, C_29 = 1)
SI_[3:0] setup to L_CLK ↓ (C_17 = 0, C_29 = 0)
-15
10
25
10
25
SI_[3:0] setup to L_CLK ↓ (C_17 = 0, C_[7:6] = 0X, C_29 = 1)
SI_[3:0] hold from L_CLK ↓ (C_17 = 0, C_29 = 0)
SI_[3:0] hold from L_CLK ↓ (C_17 = 0, C_[7:6] = 0X, C_29 = 1)
1. Timing measured with 100 pF load on all Local Bus outputs.
2. L_CLK and L_FS shown with positive polarity, timing is equivalent when signals are inverted.
2000 Sep 07
40
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 11. Local Bus Timing, 2X L_CLK Mode (C_28=1)
Frame Boundary
t1
L_CLK
t2
t2
L_FS
(C_[27:26]=00)
t2
t2
L_FS
(C_[27:26]=01)
t2
t3
t2
L_FS
(C_[27:26]=10)
t4
t5
SO
SI
t6
t7
t9
t8
Table 11. Local Bus Timing, 2X L_CLK Mode (C_28 = 1)
Symbol
Parameter
Min
Typ
Max
Unit
t1a
t1b
t1c
t2a
t2b
t3a
t3b
t3c
t3d
t3e
t3f
L_CLK Period (C_[7:6] = 0X)
244
122
61
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
L_CLK Period (C_[7:6] = 10)
L_CLK Period (C_[7:6] = 11)
L_FS delay from L_CLK ↑(C_29 = 0)
L_FS delay from L_CLK ↑(C_[7:6] = 0X, C_29 = 1)
0
10
25
10
25
60
75
60
30
10
25
10
25
-15
0
SO_[3:0] float to valid delay from L_CLK ↑(C_19 = 0, C_29 = 0)
SO_[3:0] float to valid delay from L_CLK ↑(C_19 = 0, C_[7:6] = 0X, C_29 = 1)
SO_[3:0] float to valid delay from L_CLK ↑(C_19 = 1, C_[7:6] = 0X, C_29 = 0)
SO_[3:0] float to valid delay from L_CLK ↑(C_19 = 1, C_[7:6] = 0X, C_29 = 1)
SO_[3:0] float to valid delay from L_CLK ↑(C_19 = 1, C_[7:6] = 10)
SO_[3:0] float to valid delay from L_CLK ↑(C_19 = 1, C_[7:6] = 11)
SO_[3:0] valid to valid delay from L_CLK ↑(C_29 = 0)
-15
25
10
25
10
0
t4a
t4b
t5a
t5b
t6a
t6b
t7a
t7b
t8a
t8b
t9a
t9b
Notes
SO_[3:0] valid to valid delay from L_CLK ↑(C_[7:6] = 0X, C_29 = 1)
SO_[3:0] valid to float delay from L_CLK ↑(C_29 = 0)
-15
0
SO_[3:0] valid to float delay from L_CLK ↑(C_[7:6] = 0X, C_29 = 1)
SI_[3:0] setup to L_CLK ↑(C_17 = 0, C_29 = 0)
-15
10
25
10
25
10
25
10
25
SI_[3:0] setup to L_CLK ↑(C_17 = 0, C_[7:6] = 0X, C_29 = 1)
SI_[3:0] hold from L_CLK ↑ (C_17 = 0,C_29 = 0)
SI_[3:0] hold from L_CLK ↑ (C_17 = 0, C_[7:6] = 0X, C_29 = 1)
SI_[3:0] setup to L_CLK ↓(C_17 = 1, C_29 = 0)
SI_[3:0] setup to L_CLK ↓ (C_17 = 1, C_[7:6] = 0X, C_29 = 1)
SI_[3:0] hold from L_CLK ↓ (C_17 = 1, C_29 = 0)
SI_[3:0] hold from L_CLK ↓ (C_17 = 1, C_[7:6] = 0X, C_29 = 1)
1. Timing measured with 100 pF load on all Local Bus outputs.
2. L_CLK and L_FS shown with positive polarity, timing is equivalent when signals are inverted.
2000 Sep 07
41
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 12. SCbus Timing
Frame Boundary
t1
SCLKX2N
t2
SCLK
t5
t3
t6
t4
FSYNCN
t9
t7
t8
SD_[15:0]
(Output)
t10
t14
t11
t12 t13
SD_[15:0]
(Input)
MC_CLK
t15
t16
TXD
MC
t17
t18
t19
RXD
Table 12. SCbus Timing
Symbol
Parameter
Min
Typ
Max
Unit
t1a
t1b
t1c
t2a
t2b
t2c
t3
SCLKX2N Period (C_[5:4] = 0X)
244
122
61
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLKX2N Period (C_[5:4] = 10)
SCLKX2N Period (C_[5:4] = 11)
SCLK Period (C_[5:4] = 0X)
488
244
122
SCLK Period (C_[5:4] = 10)
SCLK Period (C_[5:4] = 11)
FSYNCN setup to SCLK ↑ (C_20 = 0)
FSYNCN hold from SCLK ↑ (C_20 = 0)
FSYNCN setup to SCLKX2N ↑ (C_20 = 1)
FSYNCN hold from SCLKX2N ↑ (C_20 = 1)
SD_[15:0] float to valid delay from SCLK ↑ (C_18 = 0)
10
10
10
10
0
t4
t5
t6
t7a
t7b
t7c
t7d
t8
15
60
60
30
15
15
SD_[15:0] float to valid delay from SCLK ↑ (C_18 = 1, C_[5:4] = 0X)
SD_[15:0] float to valid delay from SCLK ↑ (C_18 = 1, C_[5:4] = 10)
SD_[15:0] float to valid delay from SCLK ↑ (C_18 = 1, C_[5:4] = 11)
SD_[15:0] valid to valid delay from SCLK ↑
25
25
10
0
0
t9
SD_[15:0] valid to float delay from SCLK ↑
2000 Sep 07
42
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Symbol
Parameter
Min
Typ
Max
Unit
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
Notes
SD_[15:0] setup to SCLK ↓ (C_16 = 0)
SD_[15:0] hold from SCLK ↓ (C_16 = 0)
SD_[15:0] setup to SCLKX2N ↑ (C_16 = 1)
SD_[15:0] hold from to SCLKX2N ↑ (C_16 = 1)
MC_CLK delay from SCLK
10
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
TXD setup to MC_CLK ↑ (C_12 = 1)
TXD hold from MC_CLK ↑ (C_12 = 1)
MC delay from MC_CLK ↑ (C_12 = 1)
MC delay from TXD (C_12 = 0)
10
10
0
75
75
15
0
RXD delay from MC
0
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF load on all SCbus outputs.
2. MC timing measured with 200 pF, 470 Ω pull-up (4.7 kΩ/10). Open collector low to high transitions include 15 ns + 60 ns delay from hi-Z to 3 V.
3. Timing is equivalent when Alternate SCbus signals are selected (C_2=1).
2000 Sep 07
43
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 13. SCbus Clock Master Timing
Frame Boundary
t1
t1
SCLKX2N
SCLK
t2
t3
t3
t2
FSYNCN
Table 13. SCbus Clock Master Timing
Symbol
Parameter
Min
Typ
Max
Unit
-5
0
5
ns
ns
ns
t1
SCLK to SCLKX2N Skew
t2
FSYNCN delay from SCLK ↓ (C_21 = 0)
FSYNCN delay from SCLKX2N ↑ (C_21 = 1)
1. Timing measured with 200 pF load on all SCbus outputs.
10
10
t3
0
Note
2000 Sep 07
44
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 14. SCbus Clock Fail Timing
Frame Boundary
t3
t3
t3
t4
SCLKX2N
SCLK
t4
t4
FSYNCN
t1
t2
CLKFAIL
SD_[15:0]
Bit 8
Bit 2
Bit 1
MC
Table 14. SCbus Clock Fail Timing
Symbol
Parameter
Min
Typ
Max
Unit
t1
CLKFAIL delay from SCLK ↑
-5
5
ns
ns
ns
ns
ns
ns
t2a
t2b
t2c
t3
CLKFAIL period (C_[5:4] = 0X)
CLKFAIL period (C_[5:4] = 10)
CLKFAIL period (C_[5:4] = 11)
488
244
122
SCLKX2N, SCLK, FSYNCN float delay from CLKFAIL float
SCLKX2N, SCLK, FSYNCN valid delay from CLKFAIL ↓
1. Timing measured with 200 pF load on all SCbus outputs.
15
10
t4
Note
2000 Sep 07
45
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 15. REF_8K_[3:0] and SREF_8K input mode Timing
t1
t2
t3
REF_8K_[3:0]
SREF_8K
Table 15. REF_8K_[3:0] and SREF_8K Timing
Symbol
Parameter
Min
Typ
Max
Unit
t1
REF_8K_[3:0] or SREF_8K period
REF_8K_[3:0] or SREF_8K high time
REF_8K_[3:0] or SREF_8K low time
125
µs
ns
ns
t2
100
100
t3
Note
1. Timing measured with 200 pF load on all SCbus outputs.
2000 Sep 07
46
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2000 Sep 07
47
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Sep 07
48
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS
STATUS
DEFINITIONS (1)
Objective specification
Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2000 Sep 07
49
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
NOTES
2000 Sep 07
50
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
NOTES
2000 Sep 07
51
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. +66 2 361 7910, Fax. +66 2 398 3447
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
70
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
02/pp52
Date of release: 2000 Sep 07
Document order number: 9397 750 07434
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