SC68C562C1N_技术文档

INTEGRATED CIRCUITS

SC68C562

CMOS dual universal serial

communications controller (CDUSCC)

Product specification

1998 Sep 04

Supersedes data of 1994 Apr 27

IC19 Data Handbook

Philips

Semiconductors

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

DESCRIPTION

• 0 to 10MHz data rate

The Philips Semiconductors SC68C562 Dual Universal Serial

• Programmable bit rate for each receiver and transmitter selectable

Communications Controller (CDUSCC) is a single-chip CMOS-LSI

communications device that provides two independent,

from:

– 19 fixed rates: 50 to 64k baud

multi-protocol, full-duplex receiver/transmitter channels in a single

package. It supports bit-oriented and character-oriented (byte count

and byte control) synchronous data link controls as well as

asynchronous protocols. The SC68C562 interfaces to the 68000

MPUs via asynchronous bus control signals and is capable of

program-polled, interrupt driven, block-move or DMA data transfers.

– One user-defined rate derived from programmable

counter/timer

– External 1X or 16X clock

– Digital phase-locked loop

• Parity and FCS (frame check sequence LRC or CRC) generation

The SC68C562 is hardware (pin) and software (Register)

compatible with SCN68562 (NMOS version). It will automatically

configure to NMOS DUSCC register map on power-up or reset.

and checking

• Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,

Manchester

The operating mode and data format of each channel can be

programmed independently. Each channel consists of a receiver, a

transmitter, a 16-bit multifunction counter/timer, a digital

• Programmable channel mode: full- and half-duplex, auto-echo, or

local loopback

phase-locked loop (DPLL), a parity/CRC generator and checker, and

associated control circuits. The two channels share a common bit

rate generator (BRG), operating directly from a crystal or an external

clock, which provides 16 common bit rates simultaneously. The

operating rate for the receiver and transmitter of each channel can

be independently selected from the BRG, the DPLL, the

• Programmable data transfer mode: polled, interrupt, DMA, wait

• DMA interface

– Compatible with the Philips Semiconductors SCB68430 Direct

Memory Access Interface (DMAI) and other DMA controllers

– Single- or dual-address dual transfers

– Half- or full-duplex operation

counter/timer, or from an external 1X or 16X clock.

This makes the CDUSCC well suited for dual speed channel

applications. Data rates up to 10Mb/s are supported.

– Automatic frame termination on counter/timer terminal count or

DMA DONE

Each transmitter and each receiver is serviced by a 16 byte FIFO.

The receiver FIFO also stores 9 status bits for each character

received; the transmit FIFO is able to store transmitter commands

with each byte. This permits reading and writing of up to 16 bytes at

a time, thus minimizing the

• Transmit path clear status

• Interrupt capabilities

– Daisy chain option

– Vector output (fixed or modified by status)

– Programmable internal priorities

– Interrupt at any FIFO fill level

– Maskable interrupt conditions

potential for transmitter underrun, receiver overrun and reducing

interrupt or DMA overhead.

In addition, a flow control capability is provided to disable a remote

transmitter when the FIFO of the local receiving device is full. Two

modem control inputs (DCD and CTS) and three modem control

outputs (RTS and two general purpose) are provided. Because the

modem control inputs are general purpose in nature, they can be

optionally programmed for other functions. This document contains

the electrical specifications for the SC68C562. Refer to the CMOS

Dual Universal Serial Communications Controller (CDUSCC) User

Manual for a complete operational description of this product.

• FIFO’d status bits

• Watchdog timer

• Multi-function programmable 16-bit counter/timer

– Bit rate generator

– Event counter

– Count received or transmitted characters

– Delay generator

– Automatic bit length measurement

FEATURES

• Modem controls

– RTS, CTS, DCD, and up to four general I/O pins per channel

– CTS and DCD programmable auto-enables for Tx and Rx

– Programmable interrupt on change of CTS or DCD

• Full hardware and software upward compatibility with previous

NMOS device

General Features

• Dual full-duplex synchronous/ asynchronous receiver and

• On-chip oscillator for crystal

• TTL compatible

transmitter

• Low power CMOS process

• Multiprotocol operation

– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,

etc.

• Single +5V power supply

Asynchronous Mode Features

• Character length: 5 to 8 bits

– COP: BISYNC, DDCMP

• Odd or even parity, no parity, or force parity

– ASYNC: 5–8 bits plus optional parity

• Sixteen character receiver and transmitter FIFOs

• Up to two stop bits programmable in 1/16-bit increments

2

1998 Sep 04

853-1682 19973

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

• 1X or 16X Rx and Tx clock factors

• Auto transparent mode switching

• Parity, overrun, and framing error detection

• False start bit detection

• Auto hunt after receipt of EOM sequence (with closing PAD check

after EOT or NAK)

• Control character sequence detection for both transparent and

• Start bit search 1/2-bit time after framing error detection

• Break generation with handshake for counting break characters

• Detection of start and end of received break

• Character compare with optional interrupt on match

normal text

Bit-Oriented Protocol Features

• Character length: 5 to 8 bits

• Detection and transmission of residual character: 0–7 bits

• Automatic switch to programmed character length for I field

• Zero insertion and deletion

• Transmits up to 10Mb/s at 1X and receive up to 1Mb/s at 16X

data rates

Character-Oriented Protocol Features

• Optional opening PAD transmission

• Character length: 5 to 8 bits

• Detection and generation of FLAG, ABORT, and IDLE bit patterns

• Odd or even parity, no parity, or force parity

• LRC or CRC generation and checking

• Optional opening PAD transmission

• One or two SYN characters

• Detection and generation of shared (single) FLAG between

frames

• Detection of overlapping (shared zero) FLAGs

• ABORT, ABORT-FLAGs, or FCS FLAGs line fill on underrun

• Idle in MARK or FLAGs

• External sync capability

• SYN detection and optional stripping

• SYN or MARK line fill on underrun

• Idle in MARK or SYNs

• Secondary address recognition including group and global

address

• Single- or dual-octet secondary address

• Extended address and control fields

• Short frame rejection for receiver

• Parity, FCS, overrun, and underrun error detection

BISYNC Features

• Detection and notification of received end of message

• CRC generation and checking

• EBCDIC or ASCII header, text and control messages

• SYN, DLE stripping

• SDLC loop mode capability

• EOM (end of message) detection and transmission

ORDERING INFORMATION

V

T

= +5V ±10%,

= 0 to +70°C

V

= +5V ±10%,

CC

A

CC

T = –40 to +85°C

A

DESCRIPTION

DWG #

Serial Data Rate =

10Mbps Maximum

Serial Data Rate =

8Mbps Maximum

48-Pin Plastic Dual In-Line Package (DIP)

SC68C562C1N

SC68C562C1A

Not available

SOT240-1

SOT238-3

52-Pin Plastic Leaded Chip Carrier (PLCC) Package

SC68C562A8A

1

ABSOLUTE MAXIMUM RATINGS

RATING

SYMBOL

PARAMETER

UNIT

COMMERCIAL

0 to +70

INDUSTRIAL

-40 to +85

2

T

Operating ambient temperature

°C

V

A

T

Storage temperature

-65 to +150

–0.5 to +7.0

-65 to +150

–0.5 to +7.0

STG

3

V

Voltage from V to GND

CC

S

CC

3

Voltage from any pin to ground

–0.5 to V +0.5

V

CC

3

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

PIN CONFIGURATIONS

A PACKAGE

INDEX

CORNER

N PACKAGE

7

47

1

8

46

34

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

V

IACKN

A3

DD

A4

A5

A6

PLCC

A2

A1

RTxDAKBN/

GPI1BN

RTxDAKAN/

GPI1AN

20

IRQN

X1/CLK

21

33

TOP VIEW

RESETN

X2/IDCN

Pin Function

RTSBN/

SYNOUTBN

RTSAN/

SYNOUTAN

1

2

3

4

5

IACKN

A3

A2

27 CSN

28 R/WN

29 DONEN

30 D3

9

TRxCA

TRxCB

RTxCB

10

11

12

13

14

RTxCA

A1

RTxDAKBN/

GPI1BN

IRQN

31 D2

32 D1

33 D0

34 NC

DCDBN/

SYNIBN

DCDAN/

SYNIAN

DIP

6

7

8

9

RxDB

Rxda

TxDA

NC

RESETN

RTSBN/

SYNOUTBN

35 CTSAN/LCAN

36 TxDRQAN/

GPO2AN/RTSAN

37 RTxDRQAN/

GPO1AN

TxDB

TxDAKAN/

GPI2AN

RTxDRQAN/

GPO1AN

TxDRQAN/

GPO2AN/RTSAN

TxDAKBN/

GPI2BN

10 TRxCB

11 RTxCB

12 DCDBN/

SYNIBN

13 NC

14 RxDB

15 TxDB

16 TxDAKBN/

GPI2BN

17 RTxDRQBN/

GPO1BN

18 TxDRQBN/

GPO2BN/RTSBN

19 CTSBN/LCBN

20 D7

21 D6

22 D5

23 D4

24 DTACKN

25 DTCN

RTxDRQBN/ 15

38 TxDAKAN/

GPI2AN

GPO1BN

TxDRQBN/

GPO2BN/RTSBN

16

17

18

39 TxDA

40 RxDA

41 NC

CTSBN/LCBN

CTSAN/LCAN

42 DCDAN/

SYNIAN

D7

D6

D0

D1

43 RTxCA

44 TRxCA

45 RTSAN/

SYNOUTAN

46 X2/IDCN

47 X1/CLK

48 RTxDAKAN/

GPI1AN

19

20

21

22

D5

D2

D4

D3

DONEN

R/WN

CSN

DTACKN

DTCN

GND

23

24

49 A6

50 A5

51 A4

SD00222

26 GND

52 V

DD

4

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

BLOCK DIAGRAM

CHANNEL MODE

AND TIMING A/B

D0-D7

BUS

BUFFER

DPLL CLK

MUX A/B

DPLL A/B

BRG

INTERFACE/

OPERATION

CONTROL

ADDRESS

DECODE

A7 CONTROL

LOGIC

COUNTER/

TIMER A/B

DTACKN

RWN

R/W

DECODE

C/T CLK

MUX A/B

MPU

INTERFACE

A1-A6

CSN

CTCRA/B

CTPRHA/B

CTPRLA/B

CTHA/B

DMA

CONTROL

RESETN

CCRA/B

PCRA/B

RSRA/B

RTxDRQAN/GPO1AN

RTxDRQBN/GPO1BN

TxDRQAN/GPO2AN

TxDRQBN/GPO2BN

RTxDAKAN/GPI1AN

RTxDAKBN/GPI1BN

TxDAKAN/GPI2AN

TxDAKBN/GPI2BN

DTCN

CTLA/B

TRSRA/B

ICTSRA/B

TRANSMIT A/B

GSR

TRANS CLK

MUX

DMA INTERFACE

CMR1A/B

CMR2A/B

OMRA/B

TPRA/B

TTRA/B

TRCR A/B

FTLR A/B

DONEN

TX SHIFT

REG

TxD A/B

TRMR A/B

CID

TRANSMIT

16 DEEP

FIFO

TRxCA/B

RTxCA/B

RTSBN/SYNOUTBN

RTSAN/SYNOUTAN

CTSA/BN

SPECIAL

FUNCTION

PINS

TELRA/B

CONTROL

CRC

GEN

DCDBN/SYNIBN

DCDAN/SYNIAN

SPEC CHAR

GEN LOGIC

RECEIVER A/B

RCVR CLK

MUX

INTERRRUPT

CONTROL

ICRA/B

RPRA/B

RTRA/B

S1RA/B

S2RA/B

IRQN

IERA/B

IVR

IACKN

RxD A/B

IVRM

IER1

RCVR

SHIFT REG

IER2

IER3

RECEIVER

16 DEEP

FIFO

RFLRA/B

DUSCC

LOGIC

CRC

ACCUM

BISYNC

COMPARE

LOGIC

X1/CLK

OSCILLATOR

X2/IDCN

SD00253

5

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

PIN DESCRIPTION

PIN NO.

MNEMONIC

A1–A6

TYPE

NAME AND FUNCTION

DIP

PLCC

4-2,

I

Address Lines: Active-high. Address inputs which specify which of the internal registers

47-45

51-49

is accessed for read/write operation.

D0–D7

31-28,

21-18

33-30,

23-20

I/O

Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All

data, command and status transfers between the CPU and the CDUSCC take place over

this bus. The data bus is enabled when CSN and R/WN or during interrupt acknowledge

cycles and single address DMA acknowledge cycles.

R/WN

CSN

26

25

28

27

I

Read/Write: A high input indicates a read cycle and a low indicates a write cycle when

CEN is active.

Chip Select: Active-low input. When active, data transfers between the CPU and the

CDUSCC are enabled on D0–D7 as controlled by R/WN and A1–A6 inputs. When CSN is

high, the data lines are placed in the 3-State condition (except during interrupt

acknowledge cycles and single address DMA transfers).

IRQN

6

1

6

1

O

I

Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of

any enabled interrupting condition. The CPU can read the general status register to

determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle

to cause the CDUSCC to output an interrupt vector on the data bus.

IACKN

X1/CLK

Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds

by either forcing the bus into high-impedance, placing a vector number, call instruction or

zero on the data bus. The vector number can be modified or unmodified by the status. If

no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.

43

47

I

Crystal or External Clock: When using the crystal oscillator, the crystal is connected

between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input.

This clock is used to drive the internal bit rate generator, as an optional input to the

counter/timer or DPLL, and to provide other required clocking signals. When a crystal is

used, a capacitor must be connected from this pin to ground.

X2/IDCN

42

46

O

Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal

is connected between pins X1 and X2. This pin can be programmed to provide an

interrupt daisy chain active-low output which propagates the IACKN signal to lower priority

devices, if no active interrupt is pending. This pin should be left floating when an external

clock is used on X1 and X2 is not used as an interrupt daisy chain output. When a crystal

is used, a capacitor must be connected from this pin to ground.

RESETN

7

8

I

Master Reset: Active-low. A low on this pin resets the transmitters and receivers and

resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is

asynchronous, i.e., no clock is required.

RxDA, RxDB

TxDA, TxDB

37, 12

36, 13

40, 14

39, 15

Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If

external receiver clock is specified for the channel, the input is sampled on the rising edge

of the clock.

O

Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted

first. This output is in the marking (high) condition when the transmitter is disabled or when

the channel is operating in local loopback mode. If external transmitter clock is specified

for the channel, the data is shifted on the falling edge of the clock.

RTxCA, RTxCB

TRxCA, TRxCB

39, 10

40, 9

43, 11

44, 10

I/O

Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to

supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply

the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock

(1X).

Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,

transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer

output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),

the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system

clock (X1 ÷ 2).

CTSA/BN,

LCA/BN

32, 17

35, 19

I/O

Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal

can be programmed to act as an enable for the transmitter when not in loop mode. The

CDUSCC detects logic level transitions on this input and can be programmed to generate

an interrupt when a transition occurs. When operating in the BOP loop mode, this pin be-

comes a loop control output which is asserted and negated by CDUSCC commands. This

output provides the means of controlling external loop interface hardware to go on-line and

off-line without disturbing operation of the loop.

6

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

PIN DESCRIPTION (Continued)

PIN NO.

MNEMONIC

TYPE

NAME AND FUNCTION

DIP

PLCC

DCDA/BN,

SYNIA/BN

38, 11

42, 12

I

Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is

programmable. As a DCD active-low input, it acts as an enable for the receiver or can be

used as a general purpose input. For the DCD function, the CDUSCC detects logic level

transitions on this pin and can be programmed to generate an interrupt when a transition

occurs. As an active-low external sync input, it is used in COP mode to obtain character

synchronization for the receiver without receipt of a SYN character. This mode can be

used in disc or tape controller applications or for the optional byte timing lead in X.21.

RTxDRQA/BN,

GPO1A/BN

34, 15

37, 17

O

Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose

Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA

controller that one or more characters are available in the receiver FIFO (when the

receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).

For full-duplex DMA operation, this output indicates to the DMA controller that data is

available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that

can be asserted and negated under program control.

TxDRQA/BN,

GPO2A/BN,

RTSA/BN

33, 16

44, 5

36, 18

48, 5

O

I

Channel A (B) Transmitter DMA Service Request, General Purpose Output, or

Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the

DMA controller that the transmit FIFO is not full and can accept more data. When not in

full-duplex DMA mode, this pin can be programmed as a general purpose or a

Request-to-Send output, which can be asserted and negated under program control.

RTxDAKA/BN,

GPI1A/BN

Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:

Active-low. For half-duplex single address operation, this input indicates to the CDUSCC

that the DMA controller has acquired the bus and that the requested bus cycle (read

receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter

is enabled) is beginning. For full-duplex single address DMA operation, this input indicates

to the CDUSCC that the DMA controller has acquired the bus and that the requested read

receiver FIFO bus cycle is beginning. Because the state of this input can be read under

program control, it can be used as a general purpose input when not in single address

DMA mode.

TxDAKA/BN,

GPI2A/BN

35, 14

38, 16

I

Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low.

When the channel is programmed for full-duplex single address DMA operation, this input

is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and

that the requested load transmitter FIFO bus cycle is beginning. Because the state of this

input can be read under program control, it can be used as a general purpose input when

not in full-duplex single address DMA mode.

DONEN

27

41, 8

22

29

45, 9

24

I/O

O

Done: Active-low, open-drain. DONEN can be used and is active in both DMA and

non-DMA modes. As an input, DONEN indicates the last DMA transfer cycle to the

TxFIFO. As an output, DONEN indicates either the last DMA transfer from the RxFIFO or

that the transmitted character count has reached terminal count.

RTSA/BN,

SYNOUTA/BN

Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync

output, it is asserted one bit time after the specified sync character (COP or BISYNC

modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send

modem control signal, it functions as described previously for the TxDRQN/RTSN pin.

DTACKN

O

Data Transfer Acknowledge: Active-low, 3-state. DTACKN is asserted on a write cycle to

indicate that the data on the bus has been latched, and on a read cycle or interrupt

acknowledge cycle to indicate valid data is on the bus. In a write bus cycle, input data is

latched by the assertion (falling edge) of DTACKN or by the negation (rising edge) of CSN,

whichever occurs first. The signal is negated when completion of the cycle is indicated by

negation of CSN or IACKN input, and returns to the inactive state (3-state) a short period

after it is negated. In single address DMA mode, input data is latched by the assertion

(falling edge) of DTCN or by the negation (rising edge) of the DMA acknowledge input,

whichever occurs first. DTACK is negated when completion of the cycle is indicated by the

assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first), and

returns to the inactive state (3-state) a short period after it is negated. When inactive,

DTACKN requires an external pull-up resistor.

DTC

23

25

I

Device Transfer Complete: Active-low. DTCN is asserted by the DMA controller to

indicate that the requested data transfer is complete.

V

48

24

34, 52

I

+5V Power Input

CC

GND

26, 13,

41, 7

Signal and Power Ground Input

7

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

4, 5

DC ELECTRICAL CHARACTERISTICS

T = 0 to +70°C, –40 to +85_C, V = 5.0V " 10%

A

CC

LIMITS

Typ

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

Max

Min

V

Input low voltage:

All except X1/CLK

X1/CLK

Input high voltage:

All except X1/CLK

X1/CLK

IL

0.8

V

IH

0 to 70_C

2.0

2.3

–40 to 85_C

0.8xV

V

CC

14

V

OL

Output low voltage:

All except IRQN

I

= 5.3mA (Comm), 4.8mA

(Indus)

= 8.8mA (Comm), 7.8mA

(Indus)

0.5

V

OL

7

IRQN

14

OL

Output high voltage:

V

OH

(Except open drain outputs)

V

CC

–0.5

V

I

= -400µA

OH

10

I

X1/CLK input low current

V

= 0, X2 = GND

–150

-15

0.0

150

µA

ILX1

IHX1

IN

10

X1/CLK input high current

V

IN

= V , X2 = GND

CC

I

X2 short circuit current (X2 mode)

X1 open V = 0

–15

+15

mA

SCX2

IN

CC

V

IN

= V

I

IL

Input low current

RESETN, DTCN, TxDAKA/BN,

RTxDAKA/BN

V

IN

= 0

–0.5

µA

I

Input leakage current

V

= 0 to V

CC,

0 to 70_C

-1

–10

+1

+10

L

IN

–40 to 85_C

Output off current high, 3-State data bus

Output off current low, 3-State data bus

Open drain output low current in off

V

IN

= V

CC,

0 to 70_C

+1

+10

µA

OZH

OZL

ODL

–40 to 85_C

V

= 0 0 to 70_C

-1

–10

µA

IN

,

–40 to 85_C

V

IN

= 0

state:

DONEN, DTACKN (3-state)

IRQN

-15

-1

-0.5

+1

µA

6

I

Open drain output high current in off state:

DONEN, IRQN, DTACKN (3-state)

V = V

IN CC

ODH

–1

µA

16

Power supply current

0 to 70_C

25

80

95

mA

CC

(See Figure 17 for graphs)

–40 to 85_C

9

C

Input capacitance

V

= GND = 0

10

15

20

pF

IN

OUT

I/O

CC

9

Output capacitance

9

Input/output capacitance

NOTES:

1. Stresses above those listed under Abs. Max Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.

2. Clock may be stopped (DC) for testing purposes or when the CDUSCC is in non-operational modes. Operation down to 0 rate clocks is

implied by a full static CMOS design, but is not verified in testing or characterization.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over specified temperature and voltage range.

5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transi-

tion time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V. All time measurements are referenced at input voltages of

0.2V and 3.0V and output voltages of 0.8V and 2.0V, as appropriate.

6. See Figure 18 for test conditions for outputs.

7. Tests for open drain outputs are intended to guarantee switching of the output transistor. To include noise margin this response is measured

from the switching signal midpoint to 0.2 V above the required output level.

8. Execution of the valid command (after it is latched) requires a minimum of three rising edges of X1 (see Figure 19).

9. These values were no explicitly tested; they are guaranteed by design and characterization data.

10.X1/CLK and X2 are not tested with a crystal installed.

11. X1/CLK frequency must be at least as fast as the faster of the receiver or transmitter data rate.

12.The X1 clock drives DTACKN, Baud Rate Generator, command register and the update of the FIFO fill level encoders. The Command

Register requires three X1 clocks between two commands; FIFO fill level encoding requires 2.5 to 3.5 X1 cycles.

13.The 68562 bus interface may be operated in two modes; a 68000 compatible mode with automatic DTACK generation and a short chip

select mode. DTACKN should not be used externally in the short chip select mode. The DTACKN signal is generated by the assertion of

the chip select, and data is latched by assertion of DTACKN or by de-assertion of the chip select, whichever comes first. In single address

DMA, the DTACK signal will be de-asserted by the assertion of the DTCN or from the de-assertion of the TxDAKN, whichever occurs first.

14.Also includes X2/IDCN pin in IDC mode.

15.In case of 3-state output, output levels V + 0.2 are considered float or high impedance.

OL

16.V = 0 to V , Rx/Tx at 10MHz and X1 at 10MHz

O

CC

8

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

RESETN

t

RELREH

SD00205

Figure 1. Reset Timing

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

t

RESETN low to RESETN high

200

ns

RELREH

t

ADVCSL

A1–A6

t

RWHCSL

CSHRWL

R/WN

t

CSLADI

t

CSHCSL

t

CSLCSH

CSN

t

CSLDDV

CSHDDF

D0–D7

INVALID

DATA VALID

INVALID

t

CSHDDI

t

DDVDAL

CSLDDA

12

DTACKN

t

CSHDAH

t

CSLDAL

DALCSH

CSHDAZ

SD00254

Figure 2. Read Cycle Bus Timing

Times represent an X1 clock frequency of 14.745MHz

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

10

Max

Min

5

Max

t

A0-A6 valid to CSN low

ns

ADVCSL

RWHCSL

CSHRWL

CSHCSL

CSLDDV

CSHDDF

DDVDAL

DALCSH

RWN high to CSN low

CSN high to RWN low

10

5

20

10

30

8

CSN high to CSN low

50

CSN low to read data valid

CSN high to data bus float

Read data valid to DTACKN low

150

50

130

40

9

20

0

20

0

9

DTACKN low to CSN high

1.5

f_CL

1.5

f_CL

1

f_CL

1

f_CL

13

9

30 )

140 )

40 )

130 )

t

CSN low to DTACKN low

ns

CSLDAL

t

CSN high to DTACKN high

60

90

60

90

ns

CSHDAH

CSHDAZ

CSLADI

CSN high to DTACKN high impedance

CSN low to address invalid

CSN low to CSN high

60

150

5

50

130

10

5

CSLCSH

CSLDDA

CSHDDI

9

CSN low to data bus driver active

CSN high to data invalid

5

9

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

t

ADVCSL

A1–A6

t

CSHRWH

t

CSLADI

R/WN

t

CSLCSH

t

RWLCSL

CSHCSL

t

DALCSH

CSN

t

CSHWDI

D0–D7

12

t

DALWDI

CSLWDV

DTACKN

t

CSHDAH

t

CSLDAL

t

CSHDAZ

SD00255

Figure 3. Write Cycle Bus Timing

LIMITS

INDUSTRIAL SC68C562 COMMERCIAL SC68C562

SYMBOL

PARAMETER

UNIT

Min

10

60

0

Max

Min

5

Max

t

A0-A6 valid to CSN low

CSN low to A0-A6 invalid

RWN low to CSN low

CSN high to RWN high

ns

ADVCSL

50

0

CSLADI

RWLCSL

CSHRWH

CSHCSL

DALCSH

DALWDI

0

8

CSN high to CSN low

50

0

30

0

9

DTACKN low to CSN high

9

DTACKN low to write data invalid

0

1.5

f_CL

1.5

f_CL

1

f_CL

1

f_CL

13

9

30 )

140 )

40 )

130 )

t

CSN low to DTACKN low

ns

CSLDAL

t

CSN high to DTACKN high

60

90

60

90

ns

CSHDAH

CSHDAZ

CSLCSH

CSLWDV

CSHWDI

CSN high to DTACKN high impedance

CSN low to CSN high

150

30

130

35

5

CSN low to write data valid

CSN high to write data invalid

10

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

IRQN

t

IALIAH

t

IACKN

IAHDDF

t

IALDDV

IAHDDI

INVALID

DATA VALID

INVALID

D0-D7

t

IAHDAH

t

DDVDAL

IALDDA

12

DTACHN

t

IALDAL

t

IAHDAZ

t

DALIAH

SD00256

Figure 4. Interrupt Cycle Timing

LIMITS

INDUSTRIAL SC68C562 COMMERCIAL SC68C562

12

SYMBOL

PARAMETER

UNIT

Min

140

5

Max

Min

130

10

Max

t

IACKN low to IACKN high

ns

IALIAH

9

IACKN low to data bus drivers active

IACKN low to read data valid

IACKN high to data bus floating

IALDDA

IALDDV

IAHDDF

DDVDAL

IAHDAH

IAHDAZ

140

60

130

60

9

Read data valid to DTACKN low

20

IACKN high to DTACKN high

80

70

IACKN high to DTACKN high impedance

110

100

1.5

f_CL

1.5

f_CL

1

f_CL

1

f_CL

9

30 )

140 )

40 )

130 )

t

IACKN low to DTACKN low

ns

IALDAL

t

IACKN high to data bus invalid

5

0

5

0

ns

IAHDDI

9

DTACKN low to IACKN high

DALIAH

IACKN

IDCN

t

IALDCL

SD00257

Figure 5. Interrupt Daisy Chain Timing

LIMITS

COMMERCIAL SC68C562

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

UNIT

Min

Max

Min

Max

t

IACKN low to IDCN (daisy chain) low

70

60

ns

IALDCL

RWN

CSN

GPI1_N

AND/OR

GPI2_N

t

CSLGII

t

GIVCSL

SD00258

Figure 6. Input Port Timing

11

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

20

Max

Min

20

Max

t

GPI input valid to CSN low

ns

GIVCSL

CSN low to GPI input invalid

40

CSLGII

RWN

CSN

t

CSHGOV

t

DALGOV

GPO1_N

AND/OR

GPO2_N

OLD DATA

NEW DATA

12

DTACKN

t

CSLDAL

SD00259

Figure 7. Output Port Timing

LIMITS

INDUSTRIAL SC68C562 COMMERCIAL SC68C562

SYMBOL

PARAMETER

UNIT

Min

Max

Min

Max

9

t

DTACKN low to GPO output data valid

40

ns

DALGOV

1.5

1

f_CL

1

f_CL

13

9

30 )

140 )

40 )

130 )

CSN low to DTACKN low

CSLDAL

f_CL

CSN high to GPO output data valid

100

CSHGOV

12

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

CSN

t

CSHIRH

DTACKN

t

DALIRH

IRQN

SD00260

Figure 8. Interrupt Timing, Write Cycle

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

9

t

DTACKN low to IRQN high, write cycle

DALIRH

9

Write TxFIFO (TxRDY interrupt)

40

ns

9

Write RSR (Rx condition interrupt)

9

Write TRSR (Rx/Tx interrupt)

9

Write ICTSR (port change and CT interrupt)

9

Write TRMSR (Tx Path, Patt recognition)

CSN high to IRQN high, write cycle

Write TxFIFO (TxRDY interrupt)

Write RSR (Rx condition interrupt)

Write TRSR (Rx/Tx interrupt)

CSHIRH

100

90

ns

Write ICTSR (port change and CT interrupt)

9

Write TRMSR (Tx Path, Patt recognition)

CSN

t

CSHIRH

IRQN

V

+.5V

OL

SD00261

Figure 9. Interrupt Timing, Read Cycle

INDUSTRIAL SC68C562

LIMITS

COMMERCIAL SC68C562

SYMBOL

PARAMETER

UNIT

Min

Max

Min

Max

t

CSN high to IRQN high, read cycle

Read RxFIFO (RxRDY interrupt)

CSHIRH

100

90

ns

13

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

t

CLHCLL

*PULL-UP RESISTOR IS NOT REQUIRED

WHEN USING CMOS LEVELS

t

+5V

CCHCCL

RCHRCL

TCHTCL

TTL

470Ω

X1

*

X1/CLK

CTCLK

RxC

CLK

t

CLLCLH

CCLCCH

RCLRCH

TCLTCH

TxC

OPEN X2

a. Driving X1 from an External Source

CRYSTAL SERIES RESISTANCE SHOULD

BE LESS THAN 180Ω

X1

CP1

C1

TO DTACKN

BLOCK

360k

TO

1.5M

Y1

÷2

C2

ALL OTHER BLOCKS

CDUSCC

X2

CP2

SD00262

Figure 10. Receive, Dual Address DMA

LIMITS

INDUSTRIAL SC68C562 COMMERCIAL SC68C562

SYMBOL

PARAMETER

UNIT

Min

25

50

55

0

Typ

Max

Min

25

45

50

0

Typ

Max

t

f

X1/CLK high to low time

X1/CLK low to high time

CT and DPLL CLK high to low time

CT and DPLL CLK low to high time

RxC high to low time

ns

CLHCLL

CLLCLH

CCHCCL

CCLCCH

RCHRCL

RCLRCH

TCHTCL

TCLTCH

CL

ns

RxC low to high time

ns

TxC high to low time

ns

TxC low to high time

ns

11, 2

X1/CLK frequency

14.7456

16.0

14.7456

16.0

10

5

MHz

CT CLK frequency

0

8

4

0

CC

RxC frequency (16X or 1X)

TxC frequency (16X or 1X)

0

RC

0

TC

Tx/Rx frequency for FM/Manchester encoding

RTC

14

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

1 BIT TIME

(1 OR 16 CLOCKS)

TxC

(INPUT)

TxC

(INPUT)

t

CILTXV

t

CILTXV

t

CILTXV

TxD

t

COLTXV

t

COLTXV

TxC

(1X OUTPUT)

t

COLTXV

TxC

(1X OUTPUT)

a. Transmit Timing NRZ

b. Transmit Timing FM0/1, Manchester Encoding

SD00263

Figure 11.

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

120

125

25

Min

Max

120

20

t

TxC input low (1X) to TxD output

ns

CILTXV

TxC input low (16X) to TxD output

TxC output low to TxD output (NRZ, NRZI)

9

t

*

COLTXV

9

(FM, Manchester)

35

30

NOTE: Characterized with no loads on TxD and TxC outputs.* Tester load approximately 50pF.

t

RCHSOL

RXC

(INPUT)

SYNOUTN

SYNIN

t

RCHRXI

t

SILRCH

t

RXVRCH

t

RXVRCH

RCHSIH

RxD

RXC (1X)

INPUT

t

RCHRXI

RXVRCH

RxD

a. Receive Timing NRZ

b. Receive Timing FM0/1, Manchester Encoding

SD00264

Figure 12.

LIMITS

INDUSTRIAL SC68C562 COMMERCIAL SC68C562

SYMBOL

PARAMETER

UNIT

Min

Max

Min

Max

t

RxD data valid to RxC high:

For NRZ data

RXVRCH

25

30

20

30

ns

For NRZI, Manchester, FM0, FM1 data

RxC high to RxD data invalid:

For NRZ data

RCHRXI

25

30

50

20

30

50

20

ns

For NRZI, Manchester, FM0, FM1 data

SYNIN low to RxC high

t

SILRCH

RCHSIH

RCHSOL

RxC high to SYNIN high

RxC high to SYNOUT low

110

100

15

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

t

CSLDAL

CSN

t

ROLDAL

12

DTACKN

t

CSLROL

t

CSHROH

DONEN (OUTPUT)

(EOM)

t

RRHDAL

t

CSLRRH

RTxDRQ_N

SD00265

Figure 13. Receive, Dual Address DMA

INDUSTRIAL SC68C562

LIMITS

COMMERCIAL SC68C562

SYMBOL

PARAMETER

UNIT

Min

Max

110

70

Min

Max

100

60

t

CSN low to Rx DONEN output low

CSN low to Rx DMA REQN high

CSN high to Rx DONEN output high

Rx DONEN output low to DTACKN low

ns

CSLROL

CSLRRH

CSHROH

ROLDAL

RRHDAL

9

40

9

Rx DMA REQN high to DTACKN low

1.5

f_CL

1.5

f_CL

1

f_CL

1

f_CL

30 )

140 )

40 )

130 )

13

9

t

CSN low to DTACKN low

ns

CSLDAL

16

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

t

TOLDAL

t

DALTOH

DONEN

(OUTPUT)

t

CSHTOH

t

CSLTOL

CSN

t

CSLDAL

12

t

DTACKN

CSHDIH

t

CSLDIL

t

DALDIH

DONEN

(INPUT)

t

CSLTRH

TxDRQ_N OR

RTxDRQ_N

t

TRHDAL

SD00266

Figure 14. Transmit, Dual Address DMA

LIMITS

COMMERCIAL SC68C562

INDUSTRIAL SC68C562

SYMBOL

PARAMETER

UNIT

Min

Max

110

Min

Max

100

t

CSN low to Tx DONEN output low

CSN low to Tx DMA REQN high

DTACKN low to Tx DONEN input high

ns

CSLTOL

CSLTRH

DALDIH

DALTOH

TOLDAL

TRHDAL

9

0

9

DTACKN low to Tx DONEN output high

20

9

Tx DONEN output low to DTACKN low

40

9

Tx DMA REQN high to DTACKN low

1.5

f_CL

1.5

f_CL

1

f_CL

1

f_CL

30 )

140 )

40 )

130 )

13

9

t

CSN low to DTACKN low

ns

CSLDAL

t

CSN low to Tx DONEN input low

CSN high to Tx DONEN output high

CSN high to Tx DONEN input high

35

40

ns

CSLDIL

CSHTOH

CSHDIH

70

60

30

25

17

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

SD00267

Figure 15. DMA Rx Read Timing—Single Address DMA

18

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

DMA Rx Read Timing — Single Address DMA

LIMITS

INDUSTRIAL SC68C562 COMMERCIAL SC68C562

SYMBOL

PARAMETER

UNIT

Min

Max

Min

Max

t

Receive DMA ACKN low to read data valid

DTCN low to DTCN high

140

130

ns

RALDDV

DTLDTH

DALDTL

DTLDDF

50

0

40

0

9

DTACKN low to DTCN low

DTCN low to data bus float

70

60

1.5

f_CL

1.5

f_CL

1

f_CL

9

1

f_CL

140 )

40 )

130 )

t

Rx DMA ACK low to DTACKN low

ns

RALDAL

30 )

9

t

Read data valid to DTACKN low

20

ns

DDVDAL

DTLDAH

DTLDAZ

RRHDAL

ROLDAL

RALRRH

RAHRAL

RALROL

DTLROH

RALRAH

RAHDDF

RALDDA

RAHDDI

DTLDDI

DTCN low to DTACKN high

80

DTCN low to DTACKN high impedance

110

9

Rx DMA REQN high to DTACKN low

40

9

Rx DONEN output low to DTACKN low

Rx DMA ACKN low to receive DMA REQN high

Receive DMA ACKN high to low time

Rx DMA ACK low to Rx DONEN output low

DTCN low to Rx DONEN output high

100

50

30

100

80

100

70

Rx DMA ACKN low to Rx DMA ACKN high

Rx DMA ACKN high to data bus float

140

130

60

9

Rx DMA ACKN low to data bus drivers active

5

10

5

Rx DMA ACKN high to data bus invalid

DTCN low to data bus invalid

5

Rx DMA ACKN low to DTCN low

140

130

RALDTL

RAHDAH

RAHDAZ

RAHROH

Rx DMA ACKN high to DTACKN high

Rx DMA ACKN high to DTACKN high impedance

Rx DMA ACKN high to DONEN output high

80

110

70

100

60

19

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

DMA Tx Write Timing — Single Address DMA

LIMITS

INDUSTRIAL SC68C562 COMMERCIAL SC68C562

SYMBOL

PARAMETER

UNIT

Min

50

0

Max

Min

40

0

Max

t

DTCN low to DTCN high

ns

DTLDTH

9

DTACKN low to DTCN low

DALDTL

1.5

f_CL

1.5

f_CL

1

f_CL

1

f_CL

9

30 )

140 )

40 )

130 )

t

Tx DMA ACK low to DTACKN low

ns

TALDAL

t

DTCN low to DTACKN high

80

ns

DTLDAH

DTLDAZ

TRHDAL

TOLDAL

DTLTOH

WDVDTL

DTLWDI

TALTRH

TAHTAL

TALTOL

DILDTL

DTCN low to DTACKN high impedance

110

80

110

70

9

Tx DMA REQN high to DTACKN low

40

9

Tx DONEN output low to DTACKN low

DTCN low to Tx DONEN output high

Write data valid to DTCN low

40

30

40

20

DTCN low to write data invalid

Tx DMA ACKN low to transmit DMA REQN high

Transmit DMA ACKN high to low time

Tx DMA ACKN low to Tx DONEN output low

Transmit DONEN input low to DTCN low

DTCN low to transmit DONEN input high

Tx ACKN low to Tx ACKN high

110

100

90

40

30

40

30

DTLDIH

TALTAH

TAHWDI

WDVTAH

TAHDAH

TAHDAZ

TAHTOH

DILTAH

110

15

100

10

Tx ACKN high to write data invalid

Write data valid to Tx DAKN high

60

40

Tx DAKN high to DTACKN high

80

110

70

100

60

Tx DAKN high to DTACKN high impedance

Tx DAKN high to DONEN output high

DONEN input low to Tx DAKN high

Tx DAKN high to DONEN input high

Tx DAKN low to DTCN low

40

30

25

TAHDIH

TALDTL

110

100

20

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

SD00269

Figure 16. DMA Tx Write Timing—SIngle Address DMA

21

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

50

40

30

50

40

30

20

10

0

0°C

25°C

I

CC

70°C

20

10

0

4

4.5

5

5.5

6

4

6

8

10

Tx/Rx Clk and X1 Frequency

V

CC

Test Condition: Tx/Rx and X1 Frequency @ 10MHz

Test Condition: V = 5V @ 25°C

CC

SD00250

Figure 17.

2.7k

TRxC

RTxC

V

IRQN

CC

50pF

820Ω

DTACKN

+5.0V

150pF

1k

DONEN

V

CC

50pF

710

ALL OTHER

OUTPUTS

+5.0V

150pF

6.0k

NOTE:

All C includes 50pF stray capacitance, i.e., C = 150pF = (100pF discrete + 50pF stray).

L

SD00270

Figure 18. Test Conditions for Outputs

X1/CLK

WRN

COMMAND

VALID

SD00219

Figure 19. Command Timing

22

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

RxC

1

2

3

4

5

6

7

8

RxD

LCN

a. Loop Control Output Assertion

RxC

RxD

1

2

3

4

5

6

7

8

9

LCN

b. Loop Control Output Negation

SD00220

Figure 20. Relationship Between Received Data and the Loop Control Output

23

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

DIP48: plastic dual in-line package; 48 leads (600 mil)

SOT240-1

24

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

PLCC52: plastic leaded chip carrier; 52 leads; pedestal

SOT238-3

25

1998 Sep 04

Philips Semiconductors

Product specification

CMOS Dual universal serial communications controller

(CDUSCC)

SC68C562

Data sheet status

[1]

Data sheet

status

Product

status

Definition

Objective

specification

Development

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

Preliminary

specification

Qualification

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make chages at any time without notice in order to

improve design and supply the best possible product.

Product

specification

Production

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 1998

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Date of release: 08-98

Document order number:

9397 750 04356

Philips

Semiconductors

26

1998 Sep 04


型号：	SC68C562C1N
厂家：	NXP
描述：	CMOS dual universal serial communications controller CDUSCC CMOS双通用串行通信控制器CDUSCC 微控制器和处理器串行IO控制器通信控制器外围集成电路光电二极管数据传输 CD 时钟
文件：	总26页 (文件大小：167K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC68C562C1N [NXP]

相关型号：

SC68C652B

SC68C652BIB48

SC68C652BIB48,128

SC68C652BIB48,151

SC68C652BIB48,157

SC68C752B

SC68C752BIB48

SC68C752BIB48,128

SC68C752BIB48,157

SC68C752BIBS

SC68C752BIBS,128

SC68C752BIBS,157