SC87C51APN40_技术文档

INTEGRATED CIRCUITS

80C31/80C51/87C51

CMOS single-chip 8-bit microcontrollers

Product specification

IC20 Data Handbook

1996 Aug 16

Philips

Semiconductors

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

DESCRIPTION

PIN CONFIGURATIONS

The Philips 80C31/80C51/87C51 is a high-performance

microcontroller fabricated with Philips high-density CMOS

technology. The CMOS 8XC51 is functionally compatible with the

NMOS 8031/8051 microcontrollers. The Philips CMOS technology

combines the high speed and density characteristics of HMOS with

the low power attributes of CMOS. Philips epitaxial substrate

minimizes latch-up sensitivity.

P1.0

P1.1

40

V

1

2

3

CC

P0.0/AD0

P0.1/AD1

39

38

P1.2

37 P0.2/AD2

36

P1.3

P1.4

4

5

P0.3/AD3

35 P0.4/AD4

34

The 8XC51 contains a 4k × 8 ROM (80C51) EPROM (87C51), a 128

× 8 RAM, 32 I/O lines, two 16-bit counter/timers, a five-source,

two-priority level nested interrupt structure, a serial I/O port for either

multi-processor communications, I/O expansion or full duplex UART,

and on-chip oscillator and clock circuits.

P1.5

P1.6

P1.7

RST

6

7

8

9

P0.5/AD5

33 P0.6/AD6

32

31

30

P0.7/AD7

CERAMIC

AND

PLASTIC

DUAL

IN-LINE

PACKAGE

In addition, the device has two software selectable modes of power

reduction—idle mode and power-down mode. The idle mode freezes

the CPU while allowing the RAM, timers, serial port, and interrupt

system to continue functioning. The power-down mode saves the

RAM contents but freezes the oscillator, causing all other chip

functions to be inoperative.

EA/V

PP

RxD/P3.0 10

TxD/P3.1 11

INT0/P3.2 12

ALE/PROG

29 PSEN

13

28 P2.7/A15

27 P2.6/A14

INT1/P3.3

T0/P3.4 14

T1/P3.5 15

WR/P3.6 16

RD/P3.7 17

XTAL2 18

XTAL1 19

26

P2.5/A13

FEATURES

25 P2.4/A12

24 P2.3/A11

• 8031/8051 compatible

– 4k × 8 ROM (80C51)

– 4k × 8 EPROM (87C51)

– ROMless (80C31)

23

22

21

P2.2/A10

P2.1/A9

P2.0/A8

– 128 × 8 RAM

20

V

SS

– Two 16-bit counter/timers

– Full duplex serial channel

– Boolean processor

6

1

40

• Memory addressing capability

– 64k ROM and 64k RAM

7

39

29

CERAMIC

AND

PLASTIC

LEAD

CHIP

CARRIER

• Power control modes:

– Idle mode

17

– Power-down mode

• CMOS and TTL compatible

18

28

34

• Five speed ranges at V = 5V

CC

– 12MHz

– 16MHz

– 24MHz

– 33MHz

44

1

33

23

PLASTIC

QUAD

FLAT

• Five package styles

PACK

• Extended temperature ranges

• OTP package available

11

12

22

SU00001

SEE PAGE 3 FOR QFP AND LCC PIN FUNCTIONS.

2

1996 Aug 16

853–0169 17187

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

CERAMIC AND PLASTIC LEADED CHIP CARRIER

PIN FUNCTIONS

PLASTIC QUAD FLAT PACK

PIN FUNCTIONS

44

34

6

1

40

7

39

1

33

23

LCC

PQFP

11

17

29

18

28

12

22

1

Function

NC*

Function

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

Function

P2.7/A15

PSEN

1

Function

P1.5

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Function

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

V

31

32

33

34

35

36

37

38

39

40

41

42

43

44

SS

2

P1.0

2

P1.6

NC*

3

P1.1

ALE/PROG

NC*

3

P1.7

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

4

P1.2

4

RST

5

P1.3

EA/V

PP

5

P3.0/RxD

NC*

6

P1.4

XTAL1

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

6

7

P1.5

V

7

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

SS

8

P1.6

NC*

8

V

CC

9

P1.7

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

9

NC*

P1.0

P1.1

P1.2

P.13

P1.4

10

11

12

13

14

15

RST

10

11

12

13

14

15

P3.0/RxD

NC*

ALE/PROG

NC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

V

EA/V

PP

CC

P0.7/AD7

* DO NOT CONNECT

SU00003

SU00002

LOGIC SYMBOL

V

SS

CC

XTAL1

ADDRESS AND

DATA BUS

XTAL2

RST

EA/V

PP

PSEN

ALE/PROG

RxD

TxD

INT0

INT1

T0

ADDRESS BUS

T1

WR

RD

SU00004

3

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

ORDERING INFORMATION

PHILIPS NORTH AMERICA

DRAWING

o

TEMPERATURE RANGE C

Freq

MHz

DRAWING

1

EPROM

ROMless

ROM

NUMBER

0590B

1472A

NUMBER

AND PACKAGE

SC87C51CCF40

SC87C51CCK44

0 to +70, Ceramic Dual In-line Package, UV

0 to +70, Ceramic Leaded Chip Carrier, UV

3.5 to 12

SC87C51CCN40 SOT129-1 SC80C31BCCN40 SC80C51BCCN40 SOT129-1 0 to +70, Plastic Dual In-line Package, OTP

SC87C51CCA44 SOT187-2 SC80C31BCCA44 SC80C51BCCA44 SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP

SC87C51CCB44 SOT307-2 SC80C31BCCB44 SC80C51BCCB44 SOT307-2 0 to +70, Plastic Quad Flat Pack, OTP

SC87C51ACF40

0590B

–40 to +85, Ceramic Dual In-line Package, UV 3.5 to 12

SC87C51ACN40 SOT129-1 SC80C31BACN40 SC80C51BACN40 SOT129-1 –40 to +85, Plastic Dual In-line Package, OTP 3.5 to 12

SC87C51ACA44 SOT187-2 SC80C31BACA44 SC80C51BACA44 SOT187-2 –40 to +85, Plastic Leaded Chip Carrier, OTP

SC87C51ACB44 SOT307-2 SC80C31BACB44 SC80C51BACB44 SOT307-2 –40 to +85, Plastic Quad Flat Pack, OTP

3.5 to 12

3.5 to 16

SC87C51CGF40

SC87C51CGK44

0590B

1472A

0 to +70, Ceramic Dual In-line Package, UV

0 to +70, Ceramic Leaded Chip Carrier, UV

SC87C51CGN40 SOT129-1 SC80C31BCGN40 SC80C51BCGN40 SOT129-1 0 to +70, Plastic Dual In-line Package, OTP

SC87C51CGA44 SOT187-2 SC80C31BCGA44 SC80C51BCGA44 SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP

SC87C51CGB44 SOT307-2 SC80C31BCGB44 SC80C51BCGB44 SOT307-2 0 to +70, Plastic Quad Flat Pack, OTP

SC87C51AGF40

0590B

–40 to +85, Ceramic Dual In-line Package, UV 3.5 to 16

SC87C51AGN40 SOT129-1 SC80C31BAGN40 SC80C51BAGN40 SOT129-1 –40 to +85, Plastic Dual In-line Package, OTP 3.5 to 16

SC87C51AGA44 SOT187-2 SC80C31BAGA44 SC80C51BAGA44 SOT187-2 –40 to +85, Plastic Leaded Chip Carrier, OTP

SC87C51AGB44 SOT307-2 SC80C31BAGB44 SC80C51BAGB44 SOT307-2 –40 to +85, Plastic Quad Flat Pack, OTP

3.5 to 16

SC87C51CPF40

SC87C51CPK44

0590B

1472A

0 to +70, Ceramic Dual In-line Package, UV

0 to +70, Ceramic Leaded Chip Carrier, UV

3.5 to 24

SC87C51CPN40 SOT129-1 SC80C31BCPN40 SC80C51BCPN40 SOT129-1 0 to +70, Plastic Dual In-line Package, OTP

SC87C51CPA44 SOT187-2 SC80C31BCPA44 SC80C51BCPA44 SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP

SC87C51APF40

0590B

–40 to +85, Ceramic Dual In-line Package, UV

SC87C51APN40 SOT129-1 SC80C31BAPN40 SC80C51BAPN40 SOT129-1 –40 to +85, Plastic Dual In-line Package, OTP 3.5 to 24

SC87C51APA44

SOT187-2 SC80C31BAPA44 SC80C51BAPA44

SOT187-2 –40 to +85, Plastic Leaded Chip Carrier, OTP

3.5 to 24

SC87C51CYF40

SC87C51CYK44

0590B

1472A

0 to +70, Ceramic Dual In-line Package, UV

0 to +70, Ceramic Leaded Chip Carrier, UV

3.5 to 33

SC87C51CYN40 SOT129-1 SC80C31BCYN40 SC80C51BCYN40 SOT129-1 0 to +70, Plastic Dual In-line Package, OTP

SC87C51CYA44 SOT187-2 SC80C31BCYA44 SC80C51BCYA44 SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP

1. OTP = One Time Programmable EPROM. UV = UV Erasable EPROM

2. SOT311 replaced by SOT307-2.

4

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

ORDERING INFORMATION (Continued)

PHILIPS

DRAWING

o

ROMless

(ORDER NUMBER)

ROMless

(MARKING NUMBER)

TEMPERATURE RANGE C

Freq

MHz

1

ROM

NUMBER

AND PACKAGE

PCB80C31-2 N

PCB80C31-2 A

PCB80C31BH2-12P

PCB80C51BH-2P

SOT129-1 0 to +70, Plastic Dual In-line Package, OTP

0.5 to 12

PCB80C31BH2-12WP PCB80C51BH-2WP SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP

2

PCB80C31BH2-12H

PCB80C51BH-2H

SOT307-2 0 to +70, Plastic Quad Flat Pack, OTP

PCB80C31-3 N

PCB80C31-3 A

PCB80C31BH3-16P

PCB80C51BH-3P

SOT129-1 0 to +70, Plastic Dual In-line Package, OTP

1.2 to 16

PCB80C31BH3-16WP PCB80C51BH-3WP SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP

2

PCB80C31BH3-16H

PCB80C51BH-3H

SOT307-2 0 to +70, Plastic Quad Flat Pack, OTP

PCF80C31-3 N

PCF80C31-3 A

PCF80C31BH3-16P

PCF80C51BH-3P

SOT129-1 –40 to +85, Plastic Dual In-line Package, OTP 1.2 to 16

PCF80C31BH3-16WP PCF80C51BH-3WP SOT187-2 –40 to +85, Plastic Leaded Chip Carrier, OTP

1.2 to 16

2

PCF80C31BH3-16H

PCA80C31BH3-16P

PCF80C51BH-3H

PCA80C51BH-3P

SOT307-2 –40 to +85, Plastic Quad Flat Pack, OTP

SOT129-1 –40 to +125, Plastic Dual In-line Package

PCA80C31BH3-16WP PCA80C51BH-3WP SOT187-2 –40 to +125, Plastic Leaded Chip Carrier

PCB80C31-4 N

PCB80C31-4 A

PCB80C31BH4-24P

PCB80C51BH-4P

SOT129-1 0 to +70, Plastic Dual In-line Package, OTP

1.2 to 24

PCB80C31BH4-24WP PCB80C51BH-4WP SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP

2

PCB80C31BH4-24H

PCB80C51BH-4H

SOT307-2 0 to +70, Plastic Quad Flat Pack, OTP

PCF80C31-4 N

PCF80C31-4 A

PCF80C31BH4-24P

PCF80C51BH-4P

SOT129-1 –40 to +85, Plastic Dual In-line Package, OTP 1.2 to 24

PCF80C31BH4-24WP PCF80C51BH-4WP SOT187-2 –40 to +85, Plastic Leaded Chip Carrier, OTP

1.2 to 24

2

PCF80C31BH4-24H

PCF80C51BH-4H

SOT307-2 –40 to +85, Plastic Leaded Chip Carrier, OTP

PCB80C31-5 N

PCB80C31-5 A

PCB80C31-5 B

PCB80C31BH5-30P

PCB80C51BH-5P

SOT129-1 0 to +70, Plastic Dual In-line Package

1.2 to 33

PCB80C31BH5-30WP PCB80C51BH-5WP SOT187-2 0 to +70, Plastic Leaded Chip Carrier

2

PCB80C31BH5-30H

PCB80C51BH-5H

SOT307-2 0 to +70, Plastic Quad Flat Pack

5

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

BLOCK DIAGRAM

P0.0–P0.7

P2.0–P2.7

PORT 0

DRIVERS

PORT 2

DRIVERS

V

CC

V

SS

RAM ADDR

REGISTER

PORT 0

LATCH

PORT 2

LATCH

ROM/EPROM

RAM

B

STACK

POINTER

ACC

REGISTER

PROGRAM

ADDRESS

REGISTER

TMP1

TMP2

BUFFER

PCON SCON TMOD TCON

ALU

TH0

TL0

TH1

TL1

PC

INCRE-

MENTER

SBUF

IE

IP

PSW

INTERRUPT, SERIAL

PORT AND TIMER BLOCKS

PROGRAM

COUNTER

PSEN

ALE/PROG

TIMING

AND

CONTROL

DPTR

EA/V

PP

RST

PORT 1

LATCH

PORT 3

LATCH

PD

OSCILLATOR

PORT 1

DRIVERS

PORT 3

DRIVERS

XTAL1

XTAL2

P1.0–P1.7

P3.0–P3.7

SU00005

6

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

PIN DESCRIPTION

PIN NO.

MNEMONIC

DIP

20

LCC

22

QFP TYPE

NAME AND FUNCTION

V

16

38

I

Ground: 0V reference.

SS

40

44

Power Supply: This is the power supply voltage for normal, idle, and power-down

CC

operation.

P0.0–0.7

39–32 43–36 37–30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to

them float and can be used as high-impedance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external program and data memory. In

this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the

code bytes during program verification in the 87C51. External pull-ups are required during

program verification.

P1.0–P1.7

P2.0–P2.7

1–8

2–9

40-44,

1–3

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, port 1 pins that are externally pulled low will source current because of the internal

pull-ups. (See DC Electrical Characteristics: I ). Port 1 also receives the low-order address

IL

byte during program memory verification.

21–28 24–31 18–25

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, port 2 pins that are externally being pulled low will source current because of the

internal pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order

IL

address byte during fetches from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it

uses strong internal pull-ups when emitting 1s. During accesses to external data memory

that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function

register.

P3.0–P3.7

10–17

11,

5,

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, port 3 pins that are externally being pulled low will source current because of the

13–19 7–13

pull-ups. (See DC Electrical Characteristics: I ). Port 3 also serves the special features of

IL

the 80C51 family, as listed below:

10

11

12

13

14

15

16

17

11

13

14

15

16

17

18

19

5

7

8

I

O

I

O

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

INT0 (P3.2): External interrupt

INT1 (P3.3): External interrupt

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

9

10

11

12

13

RST

9

10

4

I

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

device. An internal diffused resistor to V permits a power-on reset using only an external

SS

capacitor to V

.

CC

ALE/PROG

30

33

27

I/O

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.

Note that one ALE pulse is skipped during each access to external data memory. This pin is

also the program pulse input (PROG) during EPROM programming.

PSEN

29

31

32

35

26

29

O

I

Program Store Enable: The read strobe to external program memory. When the device is

executing code from the external program memory, PSEN is activated twice each machine

cycle, except that two PSEN activations are skipped during each access to external data

memory. PSEN is not activated during fetches from internal program memory.

EA/V

External Access Enable/Programming Supply Voltage: EA must be externally held low

to enable the device to fetch code from external program memory locations 0000H to

0FFFH. If EA is held high, the device executes from internal program memory unless the

program counter contains an address greater than 0FFFH. This pin also receives the

PP

12.75V programming supply voltage (V ) during EPROM programming.

PP

XTAL1

XTAL2

19

18

21

20

15

14

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

O

Crystal 2: Output from the inverting oscillator amplifier.

7

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

Table 1.

80C52/80C54/80C58 Special Function Registers

DIRECT

DESCRIPTION

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

VALUE

SYMBOL

ADDRESS MSB

LSB

ACC*

AUXR#

AUXR1#

B*

Accumulator

Auxiliary

E0H

8EH

A2H

F0H

E7

–

E6

–

E5

–

E4

–

E3

–

E2

–

E1

–

E0

00H

AO

DPS

F0

xxxxxxx0B

xxxx00x0B

00H

Auxiliary 1 (Note 2)

B register

–

WUPD

F3

0

–

F7

F6

F5

F4

F2

F1

DPTR:

DPH

DPL

Data Pointer (2 bytes)

Data Pointer High

Data Pointer Low

83H

82H

00H

AF

EA

BF

–

AE

EC

BE

–

AD

ET2

BD

AC

ES

BC

PS

B4

AB

ET1

BB

AA

EX1

BA

A9

ET0

B9

A8

EX0

B8

IE*

Interrupt Enable

Interrupt Priority

Interrupt Priority High

Port 0

A8H

B8H

B7H

80H

90H

A0H

00H

IP*

PT2

B5

PT1

B3

PX1

B2

PT0

B1

PX0

B0

x0000000B

FFH

B7

–

B6

–

IPH#

P0*

P1*

P2*

P3*

PT2H

85

PSH

84

PT1H

83

PX1H PT0H

PX0H

80

87

86

82

AD2

92

81

AD1

91

AD7

97

AD6

96

AD5

95

AD4

94

AD3

93

AD0

90

Port 1

–

T2EX

A1

T2

FFH

A7

AD15

B7

RD

A6

AD14

B6

WR

A5

A4

A3

A2

A0

Port 2

AD13

B5

AD12

B4

AD11

B3

AD10

B2

AD9

B1

AD8

B0

FFH

Port 3

B0H

87H

T1

T0

INT1

INT0

TxD

RxD

FFH

1

PCON#

Power Control

SMOD1

D7

SMOD0

D6

–

GF1

D3

GF0

D2

PD

D1

–

IDL

D0

P

00xx0000B

D5

F0

D4

PSW*

Program Status Word

D0H

CY

AC

RS1

RS0

OV

00H

SADDR#

SADEN#

Slave Address

Slave Address Mask

A9H

B9H

00H

SBUF

Serial Data Buffer

99H

xxxxxxxxB

9F

9E

9D

9C

9B

9A

99

TI

98

RI

SM0/FE

SCON*

SP

Serial Control

Stack Pointer

98H

81H

SM1

SM2

REN

TB8

RB8

00H

07H

8F

TF1

CF

–

8E

TR1

CE

–

8D

TF0

CD

–

8C

TR0

CC

–

8B

IE1

CB

–

8A

IT1

CA

–

89

IE0

88

IT0

TCON*

Timer Control

88H

00H

C9

C8

T2MOD#

TH0

TH1

TL0

TL1

Timer 2 Mode Control

Timer High 0

Timer High 1

Timer Low 0

Timer Low 1

C9H

8CH

8DH

8AH

8BH

T2OE

DCEN

xxxxxx00B

00H

TMOD

Timer Mode

89H

GATE

C/T

M1

M0

GATE

C/T

M1

M0

00H

*

SFRs are bit addressable.

#

–

SFRs are modified from or added to the 80C51 SFRs.

Reserved bits.

1. Reset value depends on reset source.

2. Available only on SC80C51.

8

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

OSCILLATOR CHARACTERISTICS

IDLE MODE

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an on-chip

oscillator, as shown in the logic symbol.

In idle mode, the CPU puts itself to sleep while all of the on-chip

peripherals stay active. The instruction to invoke the idle mode is the

last instruction executed in the normal operating mode before the

idle mode is activated. The CPU contents, the on-chip RAM, and all

of the special function registers remain intact during this mode. The

idle mode can be terminated either by any enabled interrupt (at

which time the process is picked up at the interrupt service routine

and continued), or by a hardware reset which starts the processor in

the same manner as a power-on reset.

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. There are no requirements

on the duty cycle of the external clock signal, because the input to

the internal clock circuitry is through a divide-by-two flip-flop.

However, minimum and maximum high and low times specified in

the data sheet must be observed.

POWER-DOWN MODE

RESET

In the power-down mode, the oscillator is stopped and the

instruction to invoke power-down is the last instruction executed.

Only the contents of the on-chip RAM are preserved. A hardware

reset is the only way to terminate the power-down mode. the control

bits for the reduced power modes are in the special function register

PCON.

A reset is accomplished by holding the RST pin high for at least two

machine cycles (24 oscillator periods), while the oscillator is running.

To insure a good power-up reset, the RST pin must be high long

enough to allow the oscillator time to start up (normally a few

milliseconds) plus two machine cycles.

Table 2 shows the state of I/O ports during low current operating

modes.

Table 2. External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM MEMORY

Internal

ALE

PSEN

PORT 0

Data

PORT 1

Data

PORT 2

Data

PORT 3

Data

Idle

1

0

1

0

External

Float

Data

Address

Data

Power-down

Internal

Data

External

Float

Data

ROM CODE SUBMISSION

When submitting ROM code for the 80C51, the following must be specified:

1. 4k byte user ROM data

2. 64 byte ROM encryption key (SC80C51 only)

3. ROM security bits (SC80C51 only).

ADDRESS

0000H to 0FFFH

1000H to 101FH

1020H

CONTENT

DATA

KEY

BIT(S)

7:0

0

COMMENT

User ROM Data

ROM Encryption Key

ROM Security Bit 1

ROM Security Bit 2

SEC

1020H

SEC

1

Security Bit 1: When programmed, this bit has two effects on masked ROM parts:

1. External MOVC is disabled, and

2. EA# is latched on Reset.

Security Bit 2: When programmed, this bit inhibits Verify User ROM.

9

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

Electrical Deviations from Commercial Specifications for Extended Temperature Range (87C51)

DC and AC parameters not included here are the same as in the commercial temperature range table.

DC ELECTRICAL CHARACTERISTICS

T

amb

= –40°C to +85°C, V = 5V ±10%, V = 0V (Philips North America SC87C51);

CC SS

For SC87C51 (33MHz only), T

= 0°C to +70°C, V = 5V ±5%

CC

amb

T

amb

= –40°C to +85°C, V = 5V ±10%, V = 0V (PCB80C31/51 and PCF80C31/51 Philips Parts Only)

CC SS

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

–0.5

MAX

0.2V –0.15

UNIT

V

Input low voltage, except EA (Philips North America)

Input low voltage, except EA (Philips)

Input low voltage to EA

IL

CC

0.2V –0.25

V

IL

CC

0.2V –0.45

V

IL1

IH

CC

Input high voltage, except XTAL1, RST

Input high voltage to XTAL1, RST

Logical 0 input current, ports 1, 2, 3

Logical 1-to-0 transition current, ports 1, 2, 3

Power supply current:

0.2V +1

V

CC

V

CC

+0.5

V

CC

0.7V +0.1

V

IH1

CC

I

V

= 0.45V

= 2.0V

IN

–75

µA

IL

IN

V

–750

TL

V

CC

= 4.5–5.5V

CC

1

Active mode @ 16MHz (Philips PCB80C31/51, PCF80C31/51)

Active mode @ 12MHz (Philips North America SC87C51)

Idle mode @ 16MHz (Philips PCB80C31/51, PCF80C31/51)

Idle mode @ 12MHz (Philips North America SC87C51)

Power-down mode (Philips PCB80C31/51, PCF80C31/51)

Power-down mode (Philips North America SC87C51)

25

20

6.5

5

75

50

mA

µA

2

3

µA

NOTES:

1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V + 0.5V;

r

f

IL

SS

V

IH

= V – 0.5V; XTAL2 not connected; EA = RST = Port 0 = V

.

CC

2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V + 0.5V;

r

f

IL

SS

V

IH

= V – 0.5V; XTAL2 not connected; EA = Port 0 = V ; RST = V

CC CC SS.

3. The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port 0 = V ; RST = V

CC

SS.

ABSOLUTE MAXIMUM RATINGS^{1, 2, 3}

PARAMETER

RATING

0 to +70 or –40 to +85

–65 to +150

0 to +13.0

–0.5 to +6.5

15

UNIT

Operating temperature under bias

Storage temperature range

°C

V

Voltage on EA/V pin to V

PP

SS

Voltage on any other pin to V

V

SS

Maximum I per I/O pin

mA

W

OL

Power dissipation (based on package heat transfer limitations, not device power consumption)

1.5

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise

SS

noted.

10

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

DC ELECTRICAL CHARACTERISTICS

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±20%, V = 0V (PCB80C31/51 and PCF80C31/51) (12, 16, and 24MHz versions)

CC SS

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V (87C51 12, 16, and 24MHz versions) (PCB80C31/51 33MHz version);

CC SS

For SC87C51 (33MHz only) T

= 0°C to +70°C, V = 5V ±5%

amb

CC

TEST

LIMITS

1

SYMBOL

PARAMETER

CONDITIONS

MIN

–0.5

0

TYPICAL

MAX

0.2V –0.1

UNIT

V

7

V

Input low voltage, except EA

IL

CC

7

Input low voltage to EA

0.2V –0.3

V

IL1

IH

CC

7

Input high voltage, except XTAL1, RST

0.2V +0.9

V

+0.5

V

CC

7

Input high voltage, XTAL1, RST

0.7V

V

IH1

OL

OL1

OH

CC

11

2

Output low voltage, ports 1, 2, 3

I

= 1.6mA

0.45

V

OL

OH

11

2

Output low voltage, port 0, ALE, PSEN

= 3.2mA

V

3

Output high voltage, ports 1, 2, 3, ALE, PSEN

= –60µA,

= –25µA

= –10µA

2.4

V

I

0.75V

OH

CC

0.9V

V

OH1

Output high voltage (port 0 in external bus mode)

I

= –800µA,

= –300µA

2.4

V

OH

I

0.75V

CC

= –80µA

0.9V

OH

7

I

Logical 0 input current, ports 1, 2, 3

V

= 0.45V

–50

–650

±10

µA

IL

IN

7

Logical 1-to-0 transition current, ports 1, 2, 3

See note 4

= V or V

IH

TL

LI

Input leakage current, port 0

V

IN

IL

7

Power supply current:

See note 6

CC

8

5

Active mode @ 12MHz (Philips)

Active mode @ 12MHz (Philips North America)

18

19

4.4

4

mA

µA

11.5

9

Idle mode @ 12MHz (Philips)

Idle mode @ 12MHz (Philips North America)

Power-down mode (Philips and

1.3

3

10

50

Philips North America)

R

C

Internal reset pull-down resistor

(Philips North America)

RST

IO

50

300

150

kΩ

(Philips)

12

Pin capacitance

10

pF

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due

OL

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no

OL

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the

OH

CC

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V is approximately 2V.

IN

5. I

at other frequencies (for Philips North America parts) is given by: Active mode: I

= 1.43 X FREQ + 1.90;

CCMAX

Idle mode: I

= 0.14 X FREQ +2.31, where FREQ is the external oscillator frequency in MHz. I

is given in mA. See Figure 8.

CCMAX

6. See Figures 9 through 12 for I test conditions.

CC

7. For Philips North America parts when T

= –40°C to +85°C or Philips parts when T

= –40°C to +125°C, see DC Electrical

amb

Characteristics table on previous page.

8. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V + 0.5V;

r

f

IL

SS

V

IH

= V – 0.5V; XTAL2 not connected; EA = RST = Port 0 = V

.

CC

9. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V + 0.5V;

r

f

IL

SS

V

IH

= V – 0.5V; XTAL2 not connected; EA = Port 0 = V ; RST = V

CC CC SS.

10.The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port 0 = V ; RST = V

CC

SS.

11. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

15mA

26mA

67mA

OL

Maximum I per 8-bit port:

Maximum I total for all outputs:

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

OL

test conditions.

12.Pin capacitance for the ceramic DIP package is 15pF maximum.

1996 Aug 16

11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

DC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%; V = 0V

CC SS

LIMITS

TEST

CONDITIONS

SYMBOL

PARAMETER

UNIT

1

MIN

TYP

MAX

0.2V –0.1

V

Input low voltage

4.5V < V < 5.5V

–0.5

V

IL

CC

Input high voltage (ports 0, 1, 2, 3, EA)

Input high voltage, XTAL1, RST

0.2V +0.9

V

CC

V

CC

+0.5

IH

CC

0.7V

IH1

CC

V

OL

= 4.5V

= 1.6mA

CC

8

V

Output low voltage, ports 1, 2, 3

0.4

V

OL

2

I

V

CC

= 4.5V

8, 7

Output low voltage, port 0, ALE, PSEN

0.4

OL1

OH

2

= 3.2mA

OL

V

CC

= 4.5V

= –30µA

3

Output high voltage, ports 1, 2, 3

V

– 0.7

CC

I

OH

Output high voltage (port 0 in external bus mode),

V

CC

= 4.5V

= –3.2mA

V

OH1

CC

9

3

ALE , PSEN

I

OH

I

Logical 0 input current, ports 1, 2, 3

V

= 0.4V

= 2.0V

–1

–50

–650

±10

µA

IL

IN

6

Logical 1-to-0 transition current, ports 1, 2, 3

TL

See note 4

I

Input leakage current, port 0

0.45 < V < V – 0.3

LI

IN

CC

Power supply current (see Figure 8):

See note 5

CC

5

Active mode @ 16MHz

Idle mode @ 16MHz

11.5

1.3

3

32

5

50

µA

5

Power-down mode

T

amb

= 0 to +70°C

amb

= –40 to +85°C

75

R

C

Internal reset pull-down resistor

40

225

15

kΩ

RST

IO

10

Pin capacitance (except EA)

pF

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due

OL

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no

OL

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the (V –0.7) specification when the

OH

CC

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V is approximately 2V.

IN

5. See Figures 9 through 12 for I test conditions.

CC

Active Mode:

Idle Mode:

I

= 1.5 × FREQ + 8.0;

= 0.14 × FREQ +2.31; See Figure 8.

CC

6. This value applies to T

= 0°C to +70°C. For T = –40°C to +85°C, I = –750µA.

amb TL

amb

7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

8. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

15mA (*NOTE: This is 85°C specification.)

OL

Maximum I per 8-bit port:

26mA

71mA

OL

Maximum total I for all outputs:

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

OL

test conditions.

9. ALE is tested to V

, except when ALE is off then V is the voltage specification.

OH

OH1

10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF

(except EA it is 25pF).

12

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

AC ELECTRICAL CHARACTERISTICS FOR SC87C51 12–33MHz PHILIPS NORTH AMERICA DEVICES

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V (SC87C51 12, 16 and 24MHz versions);

CC SS

For SC87C51 (33MHz only) T

= = 0°C to +70°C, V = 5V ±5%

amb

CC

3

VARIABLE CLOCK

SYMBOL

1/t

FIGURE

PARAMETER

MIN

MAX

UNIT

Oscillator frequency: Speed Versions

CLCL

SC87C51

C

G

P

Y

3.5

12

16

24

33

MHz

t

1

ALE pulse width

2t

–40

ns

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

PSEN pulse width

t

–13

AVLL

LLAX

LLIV

CLCL

t

–20

4t

3t

–65

CLCL

t

–13

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

3t

CLCL

–20

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

–45

CLCL

0

t

–10

CLCL

5t

CLCL

–55

10

Data Memory

t

2, 3

RD pulse width

6t

–100

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

5t

2t

–90

–28

CLCL

0

Data float after RD

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

8t

–150

–165

CLCL

9t

AVDV

LLWL

AVWL

QVWX

WHQX

RLAZ

WHLH

3t

–50

–75

3t

CLCL

+50

CLCL

4t

CLCL

t

–20

CLCL

t

RD low to address float

RD or WR high to ALE high

0

t

–20

t

+25

CLCL

External Clock

t

5

High time

Low time

Rise time

Fall time

12

ns

CHCX

CLCX

CLCH

CHCL

20

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

3. For all Philips North America speed versions only.

4. Interfacing the 87C51 to devices with float times up to 50ns is permitted. This limited bus contention will not cause damage to port 0 drivers.

13

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

AC ELECTRICAL CHARACTERISTICS FOR PHILIPS DEVICES

1, 2, 4, 5

T

amb

= 0°C to +70°C, V = 5V ±20%, V = 0V (PCB80C31/51, PCF80C31/51)

CC SS

3

VARIABLE CLOCK

SYMBOL

1/t

FIGURE

PARAMETER

Oscillator frequency: Speed Versions

MIN

MAX

UNIT

CLCL

PCB8031/51

–2

–3

–4

–5

0.5

1.2

12

16

24

33

MHz

PCA/PCB/PCF80C31/51

PCB/PCF80C31/51

PCB/FB80C31/51

t

1

ALE pulse width

2t

–40

ns

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

PSEN pulse width

t

–25

AVLL

LLAX

LLIV

CLCL

–25

4t

3t

–65

CLCL

t

–25

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

3t

CLCL

–45

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

–60

CLCL

0

t

–25

CLCL

5t

CLCL

–80

10

Data Memory

t

2, 3

RD pulse width

6t

–100

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

5t

2t

–90

–28

CLCL

0

Data float after RD

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

8t

–150

–165

CLCL

9t

AVDV

LLWL

AVWL

QVWX

WHQX

RLAZ

WHLH

3t

–50

–75

3t

CLCL

+50

CLCL

4t

CLCL

t

–30

–25

CLCL

RD low to address float

RD or WR high to ALE high

0

t

–25

t

+25

CLCL

External Clock

t

5

High time

Low time

Rise time

Fall time

15

ns

CHCX

CLCX

CLCH

CHCL

20

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

3. For all Philips speed versions only.

4. Interfacing the 80C31/51 to devices with float times up to 30ns is permitted. This limited bus contention will not cause damage to port 0

drivers.

5. V = 5V ±10% for 33MHz.

CC

14

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)

1, 2, 3

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V

CC SS

16MHz CLOCK

VARIABLE CLOCK

MIN MAX

SYMBOL

1/t

FIGURE

PARAMETER

Oscillator frequency

MIN

MAX

UNIT

1

CLCL

Speed versions : C, G

3.5

16

MHz

ns

t

1

ALE pulse width

85

22

32

2t

–40

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

t

–40

–30

AVLL

LLAX

LLIV

CLCL

t

150

82

4t

3t

–100

CLCL

32

t

–30

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

PSEN pulse width

142

3t

–45

CLCL

4

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

–105

CLCL

0

37

207

10

t

–25

CLCL

4

Address to valid instruction in

5t

–105

CLCL

PSEN low to address float

10

Data Memory

t

2, 3

3

RD pulse width

275

6t

–100

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

147

5t

–165

CLCL

0

Data float after RD

65

2t

–60

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

350

397

239

8t

CLCL

9t

CLCL

–150

–165

AVDV

LLWL

137

122

13

3t

–50

3t

+50

CLCL

4t

–130

–50

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

CLCL

t

13

t

–50

Data valid to WR high

RD low to address float

RD or WR high to ALE high

287

7t

–150

2, 3

0

23

103

t

–40

t

+40

CLCL

External Clock

t

5

High time

Low time

Rise time

Fall time

20

t

–t

ns

CHCX

CLCX

CLCH

CHCL

CLCL CLCX

t

–t

CLCL CHCX

20

Shift Register

t

4

Serial port clock cycle time

750

492

8

12t

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

10t

–133

QVXH

XHQX

XHDX

XHDV

CLCL

2t

CLCL

–117

0

492

10t

–133

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

3. Interfacing the 80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0

drivers.

4. See application note AN457 for external memory interfacing.

15

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)

1, 2, 3

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V

CC SS

4

24MHz CLOCK

VARIABLE CLOCK

33MHz CLOCK

SYMBOL FIGURE

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

1

Oscillator frequency

3.5

33

Speed versions : P (24MHz)

: Y (33MHz)

3.5

24

MHz

3.5

21

5

33

t

1

ALE pulse width

43

17

2t

–40

ns

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

t

–25

AVLL

LLAX

LLIV

CLCL

–25

102

65

4t

3t

–65

–60

55

30

CLCL

17

80

t

–25

5

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

PSEN pulse width

3t

CLCL

–45

45

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

CLCL

0

17

128

10

t

–25

5

CLCL

5t

CLCL

–80

70

10

Data Memory

t

2, 3

3

RD pulse width

150

6t

–100

82

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

118

5t

2t

–90

–28

60

CLCL

0

Data float after RD

55

32

90

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

183

210

175

8t

–150

–165

CLCL

9t

105

140

AVDV

LLWL

75

92

3t

–50

–75

3t

CLCL

+50

40

45

0

CLCL

4t

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

CLCL

12

t

–30

CLCL

17

t

–25

5

Data valid to WR high

RD low to address float

RD or WR high to ALE high

162

7t

–130

80

2, 3

0

17

67

t

–25

t

+25

5

55

CLCL

External Clock

t

5

High time

Low time

Rise time

Fall time

17

t

–t

ns

CHCX

CLCX

CLCH

CHCL

CLCL CLCX

t

–t

CLCL CHCX

5

Shift Register

t

4

Serial port clock cycle time

505

283

3

12t

360

167

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

10t –133

CLCL

QVXH

XHQX

XHDX

XHDV

2t

CLCL

–80

0

283

10t

–133

167

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

3. Interfacing the SC80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0

drivers.

4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz

“AC Electrial Characteristics”, page 15.

16

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always

‘t’ (= time). The other characters, depending on their positions,

indicate the name of a signal or the logical status of that signal. The

designations are:

P – PSEN

Q – Output data

R – RD signal

t – Time

A – Address

V – Valid

C – Clock

W– WR signal

D – Input data

H – Logic level high

X – No longer a valid logic level

Z – Float

I – Instruction (program memory contents)

L – Logic level low, or ALE

Examples: t

= Time for address valid to ALE low.

= Time for ALE low to PSEN low.

AVLL

t

LLPL

t

LHLL

ALE

t

LLPL

AVLL

t

PLPH

t

LLIV

t

PLIV

PSEN

t

LLAX

t

PXIZ

t

PLAZ

t

PXIX

A0–A7

INSTR IN

A0–A7

PORT 0

PORT 2

t

AVIV

A0–A15

A8–A15

SU00006

Figure 1. External Program Memory Read Cycle

ALE

PSEN

RD

t

WHLH

t

LLDV

t

LLWL

RLRH

t

RHDZ

t

LLAX

t

RLDV

AVLL

t

RLAZ

t

RHDX

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA IN

A0–A7 FROM PCL

INSTR IN

t

AVWL

t

AVDV

P2.0–P2.7 OR A8–A15 FROM DPH

A0–A15 FROM PCH

SU00007

Figure 2. External Data Memory Read Cycle

17

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

ALE

t

WHLH

PSEN

t

WLWH

LLWL

WR

t

LLAX

t

WHQX

t

AVLL

QVWX

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA OUT

A0–A7 FROM PCL

INSTR IN

t

AVWL

P2.0–P2.7 OR A8–A15 FROM DPH

A0–A15 FROM PCH

SU00008

Figure 3. External Data Memory Write Cycle

INSTRUCTION

ALE

0

1

2

3

4

5

6

7

8

t

XLXL

CLOCK

t

XHQX

t

QVXH

OUTPUT DATA

0

1

2

3

4

5

6

7

WRITE TO SBUF

t

XHDX

t

SET TI

VALID

XHDV

INPUT DATA

CLEAR RI

VALID

SET RI

SU00027

Figure 4. Shift Register Mode Timing

V

–0.5

CC

0.7V

CC

0.45V

0.2V

–0.1

t

CHCX

t

CHCL

CLCX

CLCH

t

CLCL

SU00009

Figure 5. External Clock Drive

18

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

V

–0.5

CC

0.2V

+0.9

–0.1

CC

0.45V

NOTE:

AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.

CC

Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.

IH

IL

SU00010

Figure 6. AC Testing Input/Output

V

+0.1V

V

–0.1V

TIMING

REFERENCE

POINTS

LOAD

OH

+0.1V

OL

V

LOAD

–0.1V

LOAD

NOTE:

For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,

and begins to float when a 100mV change from the loaded V /V level occurs. I /I ≥ ±20mA.

OH OL

SU00011

Figure 7. Float Waveform

MAX ACTIVE MODE

(I = 1.43 freq + 1.9)

CCMAX

45

40

35

30

TYP ACTIVE MODE

25

20

I

mA

CC

15

10

5

MAX IDLE MODE

TYP IDLE MODE

4MHz

8MHz

12MHz

16MHz

20MHz

24MHz

30MHz 33MHz

FREQ AT XTAL1

SU00012

Figure 8. I vs. FREQ

CC

Valid only within frequency specifications of the device under test

19

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

V

CC

I

CC

V

CC

V

RST

V

CC

P0

EA

P0

EA

RST

(NC)

XTAL2

XTAL1

(NC)

XTAL2

XTAL1

CLOCK SIGNAL

V

SS

SU00719

SU00720

Figure 9. I Test Condition, Active Mode

Figure 10. I Test Condition, Idle Mode

CC

All other pins are disconnected

V

–0.5

CC

0.7V

CC

0.45V

0.2V

–0.1

CC

t

CHCX

t

CHCL

t

CLCX

CLCH

t

CLCL

SU00015

Figure 11. Clock Signal Waveform for I Tests in Active and Idle Modes

CC

t

= t

CHCL

= 5ns

CLCH

V

CC

I

CC

V

CC

V

RST

P0

EA

(NC)

XTAL2

XTAL1

V

SS

SU00016

Figure 12. I Test Condition, Power Down Mode

CC

All other pins are disconnected. V = 2V to 5.5V

CC

20

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

EPROM CHARACTERISTICS

The 87C51 is programmed by using a modified Quick-Pulse

Programming algorithm. It differs from older methods in the value

Program Verification

If security bit 2 has not been programmed, the on-chip program

memory can be read out for program verification. The address of the

program memory locations to be read is applied to ports 1 and 2 as

shown in Figure 15. The other pins are held at the ‘Verify Code Data’

levels indicated in Table 3. The contents of the address location will

be emitted on port 0. External pull-ups are required on port 0 for this

operation.

used for V (programming supply voltage) and in the width and

PP

number of the ALE/PROG pulses.

The 87C51 contains two signature bytes that can be read and used

by an EPROM programming system to identify the device. The

signature bytes identify the device as an 87C51 manufactured by

Philips Corporation.

If the encryption table has been programmed, the data presented at

port 0 will be the exclusive NOR of the program byte with one of the

encryption bytes. The user will have to know the encryption table

contents in order to correctly decode the verification data. The

encryption table itself cannot be read out.

Table 3 shows the logic levels for reading the signature bytes, and

for programming the program memory, the encryption table, and the

security bits. The circuit configuration and waveforms for quick-pulse

programming are shown in Figures 13 and 14. Figure 15 shows the

circuit configuration for normal program memory verification.

Reading the Signature Bytes

The signature bytes are read by the same procedure as a normal

verification of locations 030H and 031H, except that P3.6 and P3.7

need to be pulled to a logic low. The values are:

(030H) = 15H indicates manufactured by Philips

(031H) = 92H indicates 87C51

Quick-Pulse Programming

The setup for microcontroller quick-pulse programming is shown in

Figure 13. Note that the 87C51 is running with a 4 to 6MHz

oscillator. The reason the oscillator needs to be running is that the

device is executing internal address and program data transfers.

Program/Verify Algorithms

Any algorithm in agreement with the conditions listed in Table 3, and

which satisfies the timing specifications, is suitable.

The address of the EPROM location to be programmed is applied to

ports 1 and 2, as shown in Figure 13. The code byte to be

programmed into that location is applied to port 0. RST, PSEN and

pins of ports 2 and 3 specified in Table 3 are held at the ‘Program

Code Data’ levels indicated in Table 3. The ALE/PROG is pulsed

low 25 times as shown in Figure 14.

Erasure Characteristics

Erasure of the EPROM begins to occur when the chip is exposed to

light with wavelengths shorter than approximately 4,000 angstroms.

Since sunlight and fluorescent lighting have wavelengths in this

range, exposure to these light sources over an extended time (about

1 week in sunlight, or 3 years in room level fluorescent lighting)

could cause inadvertent erasure. For this and secondary effects,

it is recommended that an opaque label be placed over the

window. For elevated temperature or environments where solvents

are being used, apply Kapton tape Fluorglas part number 2345–5, or

equivalent.

To program the encryption table, repeat the 25 pulse programming

sequence for addresses 0 through 1FH, using the ‘Pgm Encryption

Table’ levels. Do not forget that after the encryption table is

programmed, verification cycles will produce only encrypted data.

To program the security bits, repeat the 25 pulse programming

sequence using the ‘Pgm Security Bit’ levels. After one security bit is

programmed, further programming of the code memory and

encryption table is disabled. However, the other security bit can still

be programmed.

The recommended erasure procedure is exposure to ultraviolet light

(at 2537 angstroms) to an integrated dose of at least 15W-sec/cm .

Exposing the EPROM to an ultraviolet lamp of 12,000µW/cm rating

for 20 to 39 minutes, at a distance of about 1 inch, should be

sufficient.

2

Note that the EA/V pin must not be allowed to go above the

PP

2

maximum specified V level for any amount of time. Even a narrow

PP

glitch above that voltage can cause permanent damage to the

device. The V source should be well regulated and free of glitches

PP

and overshoot.

Erasure leaves the array in an all 1s state.

Table 3. EPROM Programming Modes

MODE

Read signature

RST

PSEN

ALE/PROG

EA/V

P2.7

P2.6

P3.7

P3.6

PP

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Program code data

Verify code data

Pgm encryption table

Pgm security bit 1

0*

1

V

PP

1

0*

V

PP

V

Pgm security bit 2

NOTES:

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.

2. V = 12.75V +0.25V.

PP

3. V = 5V±10% during programming and verification.

CC

4. *ALE/PROG receives 25 programming pulses while V is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a

PP

minimum of 10µs.

Trademark phrase of Intel Corporation.

21

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

+5V

V

CC

P0

A0–A7

PGM DATA

P1

1

RST

P3.6

+12.75V

EA/V

PP

25 100µs PULSES TO GROUND

ALE/PROG

PSEN

0

1

87C51

P3.7

XTAL2

P2.7

0

P2.6

4–6MHz

XTAL1

A8–A11

P2.0–P2.3

V

SS

SU00017

Figure 13. Programming Configuration

25 PULSES

1

0

ALE/PROG:

10µs MIN

100µs+10

1

0

SU00018

Figure 14. PROG Waveform

+5V

V

CC

P0

A0–A7

PGM DATA

P1

1

RST

P3.6

1

EA/V

PP

ALE/PROG

PSEN

0

87C51

P3.7

0 ENABLE

XTAL2

P2.7

0

P2.6

4–6MHz

XTAL1

A8–A11

P2.0–P2.3

V

SS

SU00019

Figure 15. Program Verification

22

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

T

amb

= 21°C to +27°C, V = 5V±10%, V = 0V (See Figure 16)

CC SS

SYMBOL

PARAMETER

MIN

MAX

13.0

50

UNIT

V

PP

Programming supply voltage

Programming supply current

Oscillator frequency

12.5

I

PP

mA

MHz

1/t

CLCL

4

6

t

Address setup to PROG low

Address hold after PROG

Data setup to PROG low

Data hold after PROG

48t

AVGL

CLCL

48t

GHAX

DVGL

GHDX

EHSH

SHGL

GHSL

GLGH

AVQV

ELQZ

EHQZ

GHGL

P2.7 (ENABLE) high to V

PP

V

PP

V

PP

setup to PROG low

hold after PROG

10

90

µs

PROG width

110

Address to data valid

48t

CLCL

ENABLE low to data valid

Data float after ENABLE

PROG high to PROG low

48t

0

10

µs

PROGRAMMING*

ADDRESS

VERIFICATION*

ADDRESS

P1.0–P1.7

P2.0–P2.4

t

AVQV

PORT 0

DATA IN

DATA OUT

t

DVGL

GHDX

GHAX

t

AVGL

ALE/PROG

t

GLGH

GHGL

t

SHGL

GHSL

LOGIC 1

EA/V

PP

LOGIC 0

t

EHSH

ELQV

EHQZ

P2.7

ENABLE

SU00020

NOTE:

*

FOR PROGRAMMING VERIFICATION SEE FIGURE 13.

FOR VERIFICATION CONDITIONS SEE FIGURE 15.

Figure 16. EPROM Programming and Verification

23

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

0590B

40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)

853–0590B 06688

24

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

1472A

44-PIN CERQUAD J-BEND (K) PACKAGE

853-1472A 05854

25

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

DIP40: plastic dual in-line package; 40 leads (600 mil)

SOT129-1

26

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

27

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

28

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

NOTES

29

1996 Aug 16

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontrollers

80C31/80C51/87C51

DEFINITIONS

Data Sheet Identification

Product Status

Definition

This data sheet contains the design target or goal specifications for product development. Specifications

may change in any manner without notice.

Objective Specification

Formative or in Design

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips

Semiconductors reserves the right to make changes at any time without notice in order to improve design

and supply the best possible product.

Preliminary Specification

Product Specification

Preproduction Product

Full Production

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes

at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,

including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,

or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work

right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only.

Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

LIFE SUPPORT APPLICATIONS

Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,

or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips

Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully

indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Sunnyvale, California 94088–3409

Philips Semiconductors and Philips Electronics North America Corporation register

eligible circuits under the Semiconductor Chip Protection Act.

Copyright Philips Electronics North America Corporation 1996

Telephone 800-234-7381


型号：	SC87C51APN40
厂家：	NXP
描述：	CMOS single-chip 8-bit microcontrollers CMOS单芯片8位微控制器微控制器
文件：	总30页 (文件大小：414K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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